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URL https://opencores.org/ocsvn/mjpeg-decoder/mjpeg-decoder/trunk

Subversion Repositories mjpeg-decoder

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    /mjpeg-decoder/trunk/mjpeg/data
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Rev 2 → Rev 4

/herkules.avi Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/herkules.avi
herkules.avi Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: system.ucf =================================================================== --- system.ucf (nonexistent) +++ system.ucf (revision 4) @@ -0,0 +1,396 @@ +############################################################################ +## This system.ucf file is generated by Base System Builder based on the +## settings in the selected Xilinx Board Definition file. Please add other +## user constraints to this file based on customer design specifications. +############################################################################ + +Net sys_clk_pin LOC=AJ15; +Net sys_clk_pin IOSTANDARD = LVCMOS25; +Net sys_rst_pin LOC=AH5; +Net sys_rst_pin IOSTANDARD = LVTTL; +## System level constraints +Net sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; +Net sys_rst_pin TIG; +NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP"; +NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP"; +NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP"; +TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; +Net fpga_0_DDR_CLK_FB LOC=C16; +Net fpga_0_DDR_CLK_FB IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_CLK_FB_OUT LOC=G23; +Net fpga_0_DDR_CLK_FB_OUT IOSTANDARD = SSTL2_II; + +## IO Devices constraints + +#### Module RS232_Uart_1 constraints + +Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8; +Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25; +Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7; +Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25; +Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW; +Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12; + +#### Module DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 constraints + +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<0> LOC=M25; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<0> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<1> LOC=N25; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<1> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<2> LOC=L26; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<2> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<3> LOC=M29; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<3> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<4> LOC=K30; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<4> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<5> LOC=G25; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<5> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<6> LOC=G26; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<6> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<7> LOC=D26; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<7> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<8> LOC=J24; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<8> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<9> LOC=K24; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<9> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<10> LOC=F28; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<10> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<11> LOC=F30; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<11> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<12> LOC=M24; +#Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<12> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<12> LOC=M25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<12> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<11> LOC=N25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<11> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<10> LOC=L26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<10> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<9> LOC=M29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<9> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<8> LOC=K30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<8> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<7> LOC=G25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<7> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<6> LOC=G26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<6> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<5> LOC=D26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<5> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<4> LOC=J24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<4> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<3> LOC=K24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<3> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<2> LOC=F28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<1> LOC=F30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<0> LOC=M24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin<1> LOC=M26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin<0> LOC=K26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin LOC=L27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<1> LOC=R26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<0> LOC=R25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<1> LOC=R24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<0> LOC=R23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin LOC=N29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin LOC=N26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<7> LOC=U26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<7> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<6> LOC=V29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<6> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<5> LOC=W29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<5> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<4> LOC=T22; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<4> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<3> LOC=W28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<3> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<2> LOC=W27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<1> LOC=W26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<0> LOC=W25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<7> LOC=E30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<7> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<6> LOC=J29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<6> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<5> LOC=M30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<5> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<4> LOC=P29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<4> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<3> LOC=V23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<2> LOC=AA25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<1> LOC=AC25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<0> LOC=AH26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<63> LOC=C27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<63> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<62> LOC=D28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<62> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<61> LOC=D29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<61> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<60> LOC=D30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<60> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<59> LOC=H25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<59> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<58> LOC=H26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<58> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<57> LOC=E27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<57> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<56> LOC=E28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<56> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<55> LOC=J26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<55> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<54> LOC=G27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<54> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<53> LOC=G28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<53> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<52> LOC=G30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<52> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<51> LOC=L23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<51> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<50> LOC=L24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<50> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<49> LOC=H27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<49> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<48> LOC=H28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<48> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<47> LOC=J27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<47> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<46> LOC=J28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<46> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<45> LOC=K29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<45> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<44> LOC=L29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<44> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<43> LOC=N23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<43> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<42> LOC=N24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<42> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<41> LOC=K27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<41> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<40> LOC=K28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<40> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<39> LOC=R22; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<39> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<38> LOC=M27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<38> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<37> LOC=M28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<37> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<36> LOC=P30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<36> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<35> LOC=P23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<35> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<34> LOC=P24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<34> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<33> LOC=N27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<33> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<32> LOC=N28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<32> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<31> LOC=V27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<30> LOC=Y30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<29> LOC=U24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<28> LOC=U23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<27> LOC=V26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<26> LOC=V25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<25> LOC=Y29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<24> LOC=AA29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<23> LOC=Y26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<22> LOC=AA28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<21> LOC=AA27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<20> LOC=W24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<19> LOC=W23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<18> LOC=AB28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<17> LOC=AB27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<16> LOC=AC29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<15> LOC=AB25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<14> LOC=AE29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<13> LOC=AA24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<12> LOC=AA23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<11> LOC=AD28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<10> LOC=AD27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<9> LOC=AF30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<8> LOC=AF29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<7> LOC=AF25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<6> LOC=AG30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<5> LOC=AG29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<4> LOC=AD26; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<3> LOC=AD25; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<2> LOC=AG28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<1> LOC=AH27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<0> LOC=AH29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<2> LOC=AC27; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<1> LOC=AD29; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<0> LOC=AB23; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<2> LOC=AC28; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<1> LOC=AD30; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<0> LOC=AB24; +Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin<0> IOSTANDARD = SSTL2_II; + +#Net fpga_0_net_gnd_pin LOC=G12; +#Net fpga_0_net_gnd_pin IOSTANDARD = LVTTL; +#Net fpga_0_net_gnd_pin SLEW = SLOW; +#Net fpga_0_net_gnd_pin DRIVE = 6; +#Net fpga_0_net_gnd_1_pin LOC=D15; +#Net fpga_0_net_gnd_1_pin IOSTANDARD = LVTTL; +#Net fpga_0_net_gnd_1_pin SLEW = SLOW; +#Net fpga_0_net_gnd_1_pin DRIVE = 6; +#Net fpga_0_net_gnd_2_pin LOC=E15; +#Net fpga_0_net_gnd_2_pin IOSTANDARD = LVTTL; +#Net fpga_0_net_gnd_2_pin SLEW = SLOW; +#Net fpga_0_net_gnd_2_pin DRIVE = 6; +#Net fpga_0_net_gnd_3_pin LOC=G10; +#Net fpga_0_net_gnd_3_pin IOSTANDARD = LVTTL; +#Net fpga_0_net_gnd_3_pin SLEW = SLOW; +#Net fpga_0_net_gnd_3_pin DRIVE = 6; +#Net fpga_0_net_gnd_4_pin LOC=E10; +#Net fpga_0_net_gnd_4_pin IOSTANDARD = LVTTL; +#Net fpga_0_net_gnd_4_pin SLEW = SLOW; +#Net fpga_0_net_gnd_4_pin DRIVE = 6; +#Net fpga_0_net_gnd_5_pin LOC=G8; +#Net fpga_0_net_gnd_5_pin IOSTANDARD = LVTTL; +#Net fpga_0_net_gnd_5_pin SLEW = SLOW; +#Net fpga_0_net_gnd_5_pin DRIVE = 6; +#Net fpga_0_net_gnd_6_pin LOC=H9; +#Net fpga_0_net_gnd_6_pin IOSTANDARD = LVTTL; +#Net fpga_0_net_gnd_6_pin SLEW = SLOW; +#Net fpga_0_net_gnd_6_pin DRIVE = 6; +Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB; +TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps; + +########################################################################## +# Manually added +########################################################################## + +NET myipif_0_LEDs_pin<0> LOC = "AC4" | IOSTANDARD = LVTTL ; # Led 0 +NET myipif_0_LEDs_pin<1> LOC = "AC3" | IOSTANDARD = LVTTL ; # Led 1 +NET myipif_0_LEDs_pin<2> LOC = "AA6" | IOSTANDARD = LVTTL ; # Led 2 +NET myipif_0_LEDs_pin<3> LOC = "AA5" | IOSTANDARD = LVTTL ; # Led 3 + +NET "myipif_0_SWITCHEs_pin<0>" LOC = "AC11" | IOSTANDARD = LVCMOS25 ; # Switch 0 +NET "myipif_0_SWITCHEs_pin<1>" LOC = "AD11" | IOSTANDARD = LVCMOS25 ; # Switch 1 +NET "myipif_0_SWITCHEs_pin<2>" LOC = "AF8" | IOSTANDARD = LVCMOS25 ; # Switch 2 +NET "myipif_0_SWITCHEs_pin<3>" LOC = "AF9" | IOSTANDARD = LVCMOS25 ; # Switch 3 + +NET "myipif_0_BUTTONs_pin<0>" LOC = "AH1" | IOSTANDARD = LVTTL ; # Button LEFT +NET "myipif_0_BUTTONs_pin<1>" LOC = "AH2" | IOSTANDARD = LVTTL ; # Button RIGHT +NET "myipif_0_BUTTONs_pin<2>" LOC = "AH4" | IOSTANDARD = LVTTL ; # Button UP +NET "myipif_0_BUTTONs_pin<3>" LOC = "AG3" | IOSTANDARD = LVTTL ; # Button DOWN +NET "myipif_0_BUTTONs_pin<4>" LOC = "AG5" | IOSTANDARD = LVTTL ; # Button CENTER + +## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE XSGA +## VIDEO OUTPUT OF THE XUP-V2PRO DEVELOPMENT SYSTEM +## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 +NET "myipif_0_VGA_VSYNCH_pin" LOC = "D11"; +NET "myipif_0_VGA_HSYNCH_pin" LOC = "B8"; +NET "myipif_0_VGA_OUT_BLANK_Z_pin" LOC = "A8"; +NET "myipif_0_VGA_COMP_SYNCH_pin" LOC = "G12"; +NET "myipif_0_VGA_OUT_PIXEL_CLOCK_pin" LOC = "H12"; + +NET "myipif_0_VGA_OUT_RED_pin[7]" LOC = "H10"; +NET "myipif_0_VGA_OUT_RED_pin[6]" LOC = "C7"; +NET "myipif_0_VGA_OUT_RED_pin[5]" LOC = "D7"; +NET "myipif_0_VGA_OUT_RED_pin[4]" LOC = "F10"; +NET "myipif_0_VGA_OUT_RED_pin[3]" LOC = "F9"; +NET "myipif_0_VGA_OUT_RED_pin[2]" LOC = "G9"; +NET "myipif_0_VGA_OUT_RED_pin[1]" LOC = "H9"; +NET "myipif_0_VGA_OUT_RED_pin[0]" LOC = "G8"; + +NET "myipif_0_VGA_OUT_GREEN_pin[7]" LOC = "E11"; +NET "myipif_0_VGA_OUT_GREEN_pin[6]" LOC = "G11"; +NET "myipif_0_VGA_OUT_GREEN_pin[5]" LOC = "H11"; +NET "myipif_0_VGA_OUT_GREEN_pin[4]" LOC = "C8"; +NET "myipif_0_VGA_OUT_GREEN_pin[3]" LOC = "D8"; +NET "myipif_0_VGA_OUT_GREEN_pin[2]" LOC = "D10"; +NET "myipif_0_VGA_OUT_GREEN_pin[1]" LOC = "E10"; +NET "myipif_0_VGA_OUT_GREEN_pin[0]" LOC = "G10"; + +NET "myipif_0_VGA_OUT_BLUE_pin[7]" LOC = "E14"; +NET "myipif_0_VGA_OUT_BLUE_pin[6]" LOC = "D14"; +NET "myipif_0_VGA_OUT_BLUE_pin[5]" LOC = "D13"; +NET "myipif_0_VGA_OUT_BLUE_pin[4]" LOC = "C13"; +NET "myipif_0_VGA_OUT_BLUE_pin[3]" LOC = "J15"; +NET "myipif_0_VGA_OUT_BLUE_pin[2]" LOC = "H15"; +NET "myipif_0_VGA_OUT_BLUE_pin[1]" LOC = "E15"; +NET "myipif_0_VGA_OUT_BLUE_pin[0]" LOC = "D15"; + +NET "myipif_0_VGA_OUT_BLUE_pin[*]" IOSTANDARD = LVTTL; +NET "myipif_0_VGA_OUT_GREEN_pin[*]" IOSTANDARD = LVTTL; +NET "myipif_0_VGA_OUT_RED_pin[*]" IOSTANDARD = LVTTL; + +NET "myipif_0_VGA_OUT_BLUE_pin[*]" SLEW = SLOW; +NET "myipif_0_VGA_OUT_GREEN_pin[*]" SLEW = SLOW; +NET "myipif_0_VGA_OUT_RED_pin[*]" SLEW = SLOW; + +NET "myipif_0_VGA_OUT_BLUE_pin[*]" DRIVE = 8; +NET "myipif_0_VGA_OUT_GREEN_pin[*]" DRIVE = 8; +NET "myipif_0_VGA_OUT_RED_pin[*]" DRIVE = 8; + +NET "myipif_0_VGA_VSYNCH_pin" IOSTANDARD = LVTTL; +NET "myipif_0_VGA_OUT_PIXEL_CLOCK_pin" IOSTANDARD = LVTTL; +NET "myipif_0_VGA_HSYNCH_pin" IOSTANDARD = LVTTL; +NET "myipif_0_VGA_OUT_BLANK_Z_pin" IOSTANDARD = LVTTL; +NET "myipif_0_VGA_COMP_SYNCH_pin" IOSTANDARD = LVTTL; +NET "myipif_0_VGA_VSYNCH_pin" DRIVE = 12; +NET "myipif_0_VGA_OUT_PIXEL_CLOCK_pin" DRIVE = 12; +NET "myipif_0_VGA_HSYNCH_pin" DRIVE = 12; +NET "myipif_0_VGA_OUT_BLANK_Z_pin" DRIVE = 12; +NET "myipif_0_VGA_COMP_SYNCH_pin" DRIVE = 12; + +NET "myipif_0_VGA_VSYNCH_pin" SLEW = SLOW; +NET "myipif_0_VGA_OUT_PIXEL_CLOCK_pin" SLEW = SLOW; +NET "myipif_0_VGA_HSYNCH_pin" SLEW = SLOW; +NET "myipif_0_VGA_OUT_BLANK_Z_pin" SLEW = SLOW; +NET "myipif_0_VGA_COMP_SYNCH_pin" SLEW = SLOW; +########################################################################## + Index: lena.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: lena.jpg =================================================================== --- lena.jpg (nonexistent) +++ lena.jpg (revision 4)
lena.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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