URL
https://opencores.org/ocsvn/mjpeg-decoder/mjpeg-decoder/trunk
Subversion Repositories mjpeg-decoder
Compare Revisions
- This comparison shows the changes necessary to convert path
/mjpeg-decoder/trunk/mjpeg/pcores/myipif/data
- from Rev 2 to Rev 4
- ↔ Reverse comparison
Rev 2 → Rev 4
/myipif_v2_1_0.pao
0,0 → 1,26
############################################################################## |
## Filename: /home/smanz/Diplomarbeit/learn_vhdl/trunk/EDK-pong-uart/pcores/myipif/data/myipif_v2_1_0.pao |
## Description: Peripheral Analysis Order |
## Date: Tue Jul 3 11:09:07 2007 (by Create and Import Peripheral Wizard) |
############################################################################## |
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lib myipif jpeg_checkff_fifo vhdl |
lib myipif jpeg_check_FF vhdl |
lib myipif jpeg_dequant_multiplier vhdl |
lib myipif jpeg_dequantize vhdl |
lib myipif jpeg_dezigzag vhdl |
lib myipif jpeg_header vhdl |
lib myipif jpeg_ht_nr_of_symbols vhdl |
lib myipif jpeg_ht_tables vhdl |
lib myipif jpeg_huffman vhdl |
lib myipif jpeg_idct_core_12 vhdl |
lib myipif jpeg_idct vhdl |
lib myipif jpeg_input_fifo vhdl |
lib myipif jpeg_qt_sr vhdl |
lib myipif jpeg_upsampling vhdl |
lib myipif jpeg vhdl |
lib myipif jpeg_YCbCr2RGB vhdl |
lib myipif vga_memory vhdl |
lib myipif vga_signals vhdl |
lib myipif vga vhdl |
lib myipif myipif vhdl |
/myipif_v2_1_0.mpd
0,0 → 1,70
################################################################### |
## |
## Name : myipif |
## Desc : Microprocessor Peripheral Description |
## : Automatically generated by PsfUtility |
## |
################################################################### |
|
BEGIN myipif |
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## Peripheral Options |
OPTION IPTYPE = PERIPHERAL |
OPTION IMP_NETLIST = TRUE |
OPTION HDL = MIXED |
OPTION CORE_STATE = DEVELOPMENT |
OPTION IP_GROUP = MICROBLAZE:PPC:USER |
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## Bus Interfaces |
BUS_INTERFACE BUS = MSOPB, BUS_TYPE = MASTER_SLAVE, BUS_STD = OPB |
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## Generics for VHDL or Parameters for Verilog |
PARAMETER C_BASEADDR = 0x50000000, DT = std_logic_vector, BUS = MSOPB, ADDRESS = BASE, PAIR = C_HIGHADDR |
PARAMETER C_HIGHADDR = 0x5000ffff, DT = std_logic_vector, BUS = MSOPB, ADDRESS = HIGH, PAIR = C_BASEADDR |
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = MSOPB |
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = MSOPB |
PARAMETER C_FAMILY = virtex2p, DT = STRING |
PARAMETER C_SDRAM_ADDR = 0x00000000, DT = std_logic_vector |
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## Ports |
PORT OPB_Clk = "", DIR = I, BUS = MSOPB, SIGIS = CLK |
PORT OPB_Rst = OPB_Rst, DIR = I, BUS = MSOPB, SIGIS = RST |
PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB |
PORT Sl_errAck = Sl_errAck, DIR = O, BUS = MSOPB |
PORT Sl_retry = Sl_retry, DIR = O, BUS = MSOPB |
PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = MSOPB |
PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = MSOPB |
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB |
PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB |
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB |
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = MSOPB |
PORT OPB_select = OPB_select, DIR = I, BUS = MSOPB |
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = MSOPB |
PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB |
PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB |
PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB |
PORT M_request = M_request, DIR = O, BUS = MSOPB |
PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB |
PORT M_select = M_select, DIR = O, BUS = MSOPB |
PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB |
PORT OPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB |
PORT OPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB |
PORT OPB_retry = OPB_retry, DIR = I, BUS = MSOPB |
PORT OPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB |
PORT OPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB |
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PORT LEDs = "", DIR = O, VEC = [3:0] |
PORT BUTTONs = "", DIR = I, VEC = [4:0] |
PORT SWITCHEs = "", DIR = I, VEC = [3:0] |
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PORT VGA_OUT_PIXEL_CLOCK = "", DIR = O |
PORT VGA_COMP_SYNCH = "", DIR = O |
PORT VGA_OUT_BLANK_Z = "", DIR = O |
PORT VGA_HSYNCH = "", DIR = O |
PORT VGA_VSYNCH = "", DIR = O |
PORT VGA_OUT_RED = "", DIR = O, VEC = [7:0] |
PORT VGA_OUT_GREEN = "", DIR = O, VEC = [7:0] |
PORT VGA_OUT_BLUE = "", DIR = O, VEC = [7:0] |
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END |