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    /mjpeg-decoder/trunk/mjpeg/pcores
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Rev 2 → Rev 4

/myipif/hdl/vhdl/fifo_sim32.vhd
0,0 → 1,95
library ieee, std, unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use unisim.vcomponents.all;
 
 
entity fifo_sim32 is
generic
(
filename : string := "fifo32.log";
log_time : integer := 1
);
port
(
rst : in std_logic;
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
we : in std_logic;
full : out std_logic
);
end fifo_sim32;
 
 
architecture default of fifo_sim32 is
 
file log_file : text open write_mode is filename;
 
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(127 downto 0) := (others => '0');
variable hex : string(1 to 32);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'a';
when "1011" => hex(hexlen -I) := 'b';
when "1100" => hex(hexlen -I) := 'c';
when "1101" => hex(hexlen -I) := 'd';
when "1110" => hex(hexlen -I) := 'e';
when "1111" => hex(hexlen -I) := 'f';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
 
 
begin
 
full <= '0';
 
process(clk)
variable TheLine : line;
begin
if rising_edge(clk) then
if we = '1' then
 
if log_time = 1 then
write(TheLine, now);
while (TheLine'length < 13) loop
write(TheLine, string'(" "));
end loop;
end if;
 
write(TheLine, string'("0x" & hstr(din)));
writeline(log_file, TheLine);
 
end if;
end if;
end process;
 
end default;
/myipif/hdl/vhdl/jpeg_checkff_fifo.vhd
0,0 → 1,149
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_checkff_fifo.vhd when simulating
-- the core, jpeg_checkff_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_checkff_fifo IS
port (
din: IN std_logic_VECTOR(11 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(11 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
END jpeg_checkff_fifo;
 
ARCHITECTURE jpeg_checkff_fifo_a OF jpeg_checkff_fifo IS
-- synopsys translate_off
component wrapped_jpeg_checkff_fifo
port (
din: IN std_logic_VECTOR(11 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(11 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
end component;
 
-- Configuration specification
for all : wrapped_jpeg_checkff_fifo use entity XilinxCoreLib.fifo_generator_v2_3(behavioral)
generic map(
c_wr_response_latency => 1,
c_has_rd_data_count => 0,
c_din_width => 12,
c_has_wr_data_count => 0,
c_implementation_type => 2,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 12,
c_rd_depth => 2048,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 1,
c_has_rst => 1,
c_data_count_width => 2,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 11,
c_has_almost_empty => 1,
c_rd_data_count_width => 2,
c_enable_rlocs => 0,
c_wr_pntr_width => 11,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 2,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 2046,
c_wr_depth => 2048,
c_prog_empty_thresh_negate_val => 2046,
c_prog_empty_thresh_assert_val => 2046,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 2046,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => 1024,
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_checkff_fifo
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
almost_empty => almost_empty,
almost_full => almost_full,
dout => dout,
empty => empty,
full => full,
valid => valid);
-- synopsys translate_on
 
END jpeg_checkff_fifo_a;
 
/myipif/hdl/vhdl/jpeg_idct_core_12.vhd
0,0 → 1,101
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_idct_core_12.vhd when simulating
-- the core, jpeg_idct_core_12. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_idct_core_12 IS
port (
ND: IN std_logic;
RDY: OUT std_logic;
RFD: OUT std_logic;
CLK: IN std_logic;
RST: IN std_logic;
DIN: IN std_logic_VECTOR(11 downto 0);
DOUT: OUT std_logic_VECTOR(8 downto 0));
END jpeg_idct_core_12;
 
ARCHITECTURE jpeg_idct_core_12_a OF jpeg_idct_core_12 IS
-- synopsys translate_off
component wrapped_jpeg_idct_core_12
port (
ND: IN std_logic;
RDY: OUT std_logic;
RFD: OUT std_logic;
CLK: IN std_logic;
RST: IN std_logic;
DIN: IN std_logic_VECTOR(11 downto 0);
DOUT: OUT std_logic_VECTOR(8 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_jpeg_idct_core_12 use entity XilinxCoreLib.C_DA_2D_DCT_V2_0(behavioral)
generic map(
c_clks_per_sample => 12,
c_result_width => 9,
c_internal_width => 15,
c_data_type => 0,
c_precision_control => 2,
c_data_width => 12,
c_operation => 2,
c_enable_rlocs => 0,
c_latency => 99,
c_enable_symmetry => 0,
c_coeff_width => 15,
c_shape => 0,
c_mem_type => 0,
c_col_latency => 15,
c_row_latency => 18,
c_has_reset => 1);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_idct_core_12
port map (
ND => ND,
RDY => RDY,
RFD => RFD,
CLK => CLK,
RST => RST,
DIN => DIN,
DOUT => DOUT);
-- synopsys translate_on
 
END jpeg_idct_core_12_a;
 
/myipif/hdl/vhdl/vga_memory.vhd
0,0 → 1,124
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file vga_memory.vhd when simulating
-- the core, vga_memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY vga_memory IS
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(14 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(14 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
END vga_memory;
 
ARCHITECTURE vga_memory_a OF vga_memory IS
-- synopsys translate_off
component wrapped_vga_memory
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(14 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(14 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_vga_memory use entity XilinxCoreLib.blk_mem_gen_v1_1(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 1,
c_has_mux_output_regs => 0,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "virtex2p",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 1,
c_init_file_name => "no_coe_file_loaded",
c_write_mode_b => "WRITE_FIRST",
c_write_mode_a => "WRITE_FIRST",
c_load_init_file => 0,
c_write_depth_b => 32768,
c_write_depth_a => 32768,
c_has_ssrb => 0,
c_has_ssra => 0,
c_addra_width => 15,
c_addrb_width => 15,
c_default_data => "0",
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_has_mem_output_regs => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 32768,
c_read_depth_a => 32768,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 0);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_vga_memory
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
clkb => clkb,
addrb => addrb,
doutb => doutb);
-- synopsys translate_on
 
END vga_memory_a;
 
/myipif/hdl/vhdl/jpeg_input_fifo.vhd
0,0 → 1,147
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_input_fifo.vhd when simulating
-- the core, jpeg_input_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_input_fifo IS
port (
din: IN std_logic_VECTOR(31 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
END jpeg_input_fifo;
 
ARCHITECTURE jpeg_input_fifo_a OF jpeg_input_fifo IS
-- synopsys translate_off
component wrapped_jpeg_input_fifo
port (
din: IN std_logic_VECTOR(31 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
end component;
 
-- Configuration specification
for all : wrapped_jpeg_input_fifo use entity XilinxCoreLib.fifo_generator_v2_3(behavioral)
generic map(
c_wr_response_latency => 1,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_implementation_type => 2,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 8,
c_rd_depth => 2048,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 1,
c_has_rst => 1,
c_data_count_width => 2,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 11,
c_has_almost_empty => 0,
c_rd_data_count_width => 2,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 2,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 510,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 2046,
c_prog_empty_thresh_assert_val => 2046,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => 512,
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_input_fifo
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
almost_full => almost_full,
dout => dout,
empty => empty,
full => full,
valid => valid);
-- synopsys translate_on
 
END jpeg_input_fifo_a;
 
/myipif/hdl/vhdl/jpeg_dezigzag.vhd
0,0 → 1,419
------------------------------------------------------------------------------
-- Two shift registers are used, when nr1 is full and nr2 is empty
-- they are nr1 is mapped on nr2 in a reverse-zigzag order. Additionally
-- the "matrix" is transposed to compensate transponation of successional
-- the idct-core.
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg_dezigzag is
port(
Clk : in std_logic;
context_i: in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(11 downto 0);
reset_i : in std_logic;
context_o: out std_logic_vector(3 downto 0);
data_o : out std_logic_vector(11 downto 0);
 
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end entity jpeg_dezigzag;
 
 
 
 
 
architecture IMP of jpeg_dezigzag is
type sr is array (0 to 63) of std_logic_vector(11 downto 0);
signal sr_in, sr_out : sr := (others=>X"000");
signal ce_in, ce_out : std_logic :='0';
signal counter_in : std_logic_vector(5 downto 0) :=(others=>'0');
signal counter_out : std_logic_vector(5 downto 0) :=(others=>'0');
signal do_copy, do_copy_D : std_logic :='0';
signal stop_in, stop_in_D : std_logic :='0';
signal stop_out, stop_out_D : std_logic :='1';
signal stop_eoi_out, stop_eoi_out_D : std_logic := '1';
signal context, context_D : std_logic_vector(3 downto 0) :=(others=>'0');
signal eoi, eoi_D : std_logic :='0';
signal eoi_hold, eoi_hold_D : std_logic :='0';
signal ready, ready_D : std_logic :='1';
 
 
 
 
 
 
 
begin
 
 
 
ready_o <= ready;
datavalid_o <= (ce_out and not do_copy);
data_o <= sr_out(0);
context_o <= context;
 
process(ready, counter_in, do_copy)
begin
ready_D <= ready;
if (counter_in=63) then
ready_D <='0';
elsif(do_copy='1') then
ready_D<='1';
end if;
end process;
process(Clk)
begin
if rising_edge(Clk) then
if(reset_i='1') then
ready <='1';
elsif ce_in='1' then
ready <= ready_D;
end if;
end if;
end process;
 
 
process(stop_eoi_out, counter_in, do_copy)
begin
stop_eoi_out_D <= stop_eoi_out;
if (counter_in=1) then
stop_eoi_out_D <='1';
elsif(do_copy='1') then
stop_eoi_out_D<='0';
end if;
end process;
process(Clk)
begin
if rising_edge(Clk) then
if(reset_i='1') then
stop_eoi_out <='1';
elsif ce_in='1' then
stop_eoi_out <= stop_eoi_out_D;
end if;
end if;
end process;
 
 
 
-- handle the context
process(eoi, eoi_hold, context_i, counter_out, do_copy, stop_eoi_out)
begin
eoi_D <= eoi;
eoi_hold_D <= eoi_hold;
if (context_i(3)='1' and do_copy='0' and stop_eoi_out='1') then
eoi_hold_D <= '1';
elsif(context_i(3)='1' and (do_copy='1' and stop_eoi_out='1')) then
eoi_D <= '1';
eoi_hold_D <= '0';
elsif(context_i(3)='1' and stop_eoi_out='0') then
eoi_D <= '1';
eoi_hold_D <= '0';
elsif(eoi_hold='1' and do_copy='1') then
eoi_D <= '1';
eoi_hold_D <= '0';
end if;
if (counter_out=63 and eoi='1') then
eoi_D <= '0';
eoi_hold_D <= '0';
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
eoi <= eoi_D;
eoi_hold <= eoi_hold_D;
context <= '0' & '0' & context(1 downto 0);
if counter_in=60 then
context_D <= context_i;
end if;
if do_copy='1' then
context <= context_D;
end if;
 
if reset_i='1' then
context <= (others=>'0');
eoi <='0';
eoi_hold <='0';
elsif counter_out=63 and ce_out='1' then
context(3) <= eoi;
end if;
 
end if;
end process;
 
 
 
 
 
-- SHIFT_IN
process(Clk)
begin
if rising_edge(Clk) then
if reset_i='1' then
sr_in <= (others=>X"000");
counter_in <= (others=>'0');
elsif ce_in='1' and do_copy='0' then
sr_in <= sr_in(1 to 63) & data_i;
counter_in <= counter_in+1;
end if;
end if;
end process;
 
process(datavalid_i, stop_in, do_copy)
begin
if datavalid_i='1' and stop_in='0' then
ce_in <='1';
elsif(do_copy='1') then
ce_in <= '1';
else
ce_in <='0';
end if;
end process;
 
process(counter_in, do_copy, ce_in)
begin
stop_in_D <= stop_in;
if(do_copy='1') then
stop_in_D <= '0';
elsif counter_in="111111" and ce_in='1' then
stop_in_D <= '1';
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
if reset_i='1' then
stop_in <= '0';
else
stop_in <= stop_in_D;
end if;
end if;
end process;
 
 
 
 
 
-- DO_COPY
process(stop_in, stop_out)
begin
if stop_in ='1' and stop_out='1' then
do_copy_D <= '1';
else
do_copy_D <= '0';
end if;
end process;
process(Clk)
begin
if rising_edge(Clk) then
if(reset_i='1') then
do_copy <='0';
else
do_copy <= do_copy_D;
end if;
end if;
end process;
 
 
 
 
-- SHIFT_OUT
process(Clk)
begin
if rising_edge(Clk) then
if reset_i='1' then
sr_out <= (others=>X"000");
counter_out <= (others=>'0');
elsif do_copy='1' then
-- -- do the Zig-Zag Mapping
-- sr_out(00) <= sr_in(00);
-- sr_out(01) <= sr_in(01);
-- sr_out(02) <= sr_in(05);
-- sr_out(03) <= sr_in(06);
-- sr_out(04) <= sr_in(14);
-- sr_out(05) <= sr_in(17);
-- sr_out(06) <= sr_in(27);
-- sr_out(07) <= sr_in(28);
-- sr_out(08) <= sr_in(02);
-- sr_out(09) <= sr_in(04);
-- sr_out(10) <= sr_in(07);
-- sr_out(11) <= sr_in(13);
-- sr_out(12) <= sr_in(16);
-- sr_out(13) <= sr_in(26);
-- sr_out(14) <= sr_in(29);
-- sr_out(15) <= sr_in(42);
-- sr_out(16) <= sr_in(03);
-- sr_out(17) <= sr_in(08);
-- sr_out(18) <= sr_in(12);
-- sr_out(19) <= sr_in(17);
-- sr_out(20) <= sr_in(25);
-- sr_out(21) <= sr_in(30);
-- sr_out(22) <= sr_in(41);
-- sr_out(23) <= sr_in(43);
-- sr_out(24) <= sr_in(09);
-- sr_out(25) <= sr_in(11);
-- sr_out(26) <= sr_in(18);
-- sr_out(27) <= sr_in(24);
-- sr_out(28) <= sr_in(31);
-- sr_out(29) <= sr_in(40);
-- sr_out(30) <= sr_in(44);
-- sr_out(31) <= sr_in(53);
-- sr_out(32) <= sr_in(10);
-- sr_out(33) <= sr_in(19);
-- sr_out(34) <= sr_in(23);
-- sr_out(35) <= sr_in(32);
-- sr_out(36) <= sr_in(39);
-- sr_out(37) <= sr_in(45);
-- sr_out(38) <= sr_in(52);
-- sr_out(39) <= sr_in(54);
-- sr_out(40) <= sr_in(20);
-- sr_out(41) <= sr_in(22);
-- sr_out(42) <= sr_in(33);
-- sr_out(43) <= sr_in(38);
-- sr_out(44) <= sr_in(46);
-- sr_out(45) <= sr_in(51);
-- sr_out(46) <= sr_in(55);
-- sr_out(47) <= sr_in(60);
-- sr_out(48) <= sr_in(21);
-- sr_out(49) <= sr_in(34);
-- sr_out(50) <= sr_in(37);
-- sr_out(51) <= sr_in(47);
-- sr_out(52) <= sr_in(50);
-- sr_out(53) <= sr_in(56);
-- sr_out(54) <= sr_in(59);
-- sr_out(55) <= sr_in(61);
-- sr_out(56) <= sr_in(35);
-- sr_out(57) <= sr_in(36);
-- sr_out(58) <= sr_in(48);
-- sr_out(59) <= sr_in(49);
-- sr_out(60) <= sr_in(57);
-- sr_out(61) <= sr_in(58);
-- sr_out(62) <= sr_in(62);
-- sr_out(63) <= sr_in(63);
-- additionally transpose the inputx matrix
-- to compensate the column-wise output of the successional idct-entity
sr_out(00) <= sr_in(00);
sr_out(08) <= sr_in(01);
sr_out(16) <= sr_in(05);
sr_out(24) <= sr_in(06);
sr_out(32) <= sr_in(14);
sr_out(40) <= sr_in(17);
sr_out(48) <= sr_in(27);
sr_out(56) <= sr_in(28);
sr_out(01) <= sr_in(02);
sr_out(09) <= sr_in(04);
sr_out(17) <= sr_in(07);
sr_out(25) <= sr_in(13);
sr_out(33) <= sr_in(16);
sr_out(41) <= sr_in(26);
sr_out(49) <= sr_in(29);
sr_out(57) <= sr_in(42);
sr_out(02) <= sr_in(03);
sr_out(10) <= sr_in(08);
sr_out(18) <= sr_in(12);
sr_out(26) <= sr_in(17);
sr_out(34) <= sr_in(25);
sr_out(42) <= sr_in(30);
sr_out(50) <= sr_in(41);
sr_out(58) <= sr_in(43);
sr_out(03) <= sr_in(09);
sr_out(11) <= sr_in(11);
sr_out(19) <= sr_in(18);
sr_out(27) <= sr_in(24);
sr_out(35) <= sr_in(31);
sr_out(43) <= sr_in(40);
sr_out(51) <= sr_in(44);
sr_out(59) <= sr_in(53);
sr_out(04) <= sr_in(10);
sr_out(12) <= sr_in(19);
sr_out(20) <= sr_in(23);
sr_out(28) <= sr_in(32);
sr_out(36) <= sr_in(39);
sr_out(44) <= sr_in(45);
sr_out(51) <= sr_in(52);
sr_out(60) <= sr_in(54);
sr_out(05) <= sr_in(20);
sr_out(13) <= sr_in(22);
sr_out(21) <= sr_in(33);
sr_out(29) <= sr_in(38);
sr_out(37) <= sr_in(46);
sr_out(45) <= sr_in(51);
sr_out(53) <= sr_in(55);
sr_out(61) <= sr_in(60);
sr_out(06) <= sr_in(21);
sr_out(14) <= sr_in(34);
sr_out(22) <= sr_in(37);
sr_out(30) <= sr_in(47);
sr_out(38) <= sr_in(50);
sr_out(46) <= sr_in(56);
sr_out(54) <= sr_in(59);
sr_out(62) <= sr_in(61);
sr_out(07) <= sr_in(35);
sr_out(15) <= sr_in(36);
sr_out(23) <= sr_in(48);
sr_out(31) <= sr_in(49);
sr_out(39) <= sr_in(57);
sr_out(47) <= sr_in(58);
sr_out(55) <= sr_in(62);
sr_out(63) <= sr_in(63);
elsif ce_out='1' and do_copy='0' then
sr_out <= sr_out(1 to 63) & X"000";
counter_out <= counter_out+1;
end if;
end if;
end process;
 
 
process(ready_i, stop_out, do_copy)
begin
if ready_i='1' and stop_out='0' then
ce_out <='1';
elsif(do_copy='1') then
ce_out <= '1';
else
ce_out <='0';
end if;
end process;
 
 
process(counter_out, do_copy, ce_out)
begin
stop_out_D <= stop_out;
if(do_copy='1') then
stop_out_D <= '0';
elsif counter_out="111111" and ce_out='1' then
stop_out_D <= '1';
end if;
end process;
 
 
process(Clk)
begin
if rising_edge(Clk) then
if reset_i='1' then
stop_out <= '1';
else
stop_out <= stop_out_D;
end if;
end if;
end process;
 
 
end IMP;
/myipif/hdl/vhdl/jpeg_ht_tables.vhd
0,0 → 1,125
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_ht_tables.vhd when simulating
-- the core, jpeg_ht_tables. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_ht_tables IS
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(11 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(11 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
END jpeg_ht_tables;
 
ARCHITECTURE jpeg_ht_tables_a OF jpeg_ht_tables IS
-- synopsys translate_off
component wrapped_jpeg_ht_tables
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(11 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(11 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_jpeg_ht_tables use entity XilinxCoreLib.blk_mem_gen_v1_1(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 1,
c_has_mux_output_regs => 0,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "virtex2p",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 1,
c_init_file_name => "no_coe_file_loaded",
c_write_mode_b => "WRITE_FIRST",
c_write_mode_a => "WRITE_FIRST",
c_load_init_file => 0,
c_write_depth_b => 4096,
c_write_depth_a => 4096,
c_has_ssrb => 0,
c_has_ssra => 0,
c_addra_width => 12,
c_addrb_width => 12,
c_default_data => "0",
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_has_mem_output_regs => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 4096,
c_read_depth_a => 4096,
c_byte_size => 9,
c_sim_collision_check => "NONE",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 0,
C_CORENAME => "blk_mem_gen_v1_1");
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_ht_tables
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
clkb => clkb,
addrb => addrb,
doutb => doutb);
-- synopsys translate_on
 
END jpeg_ht_tables_a;
 
/myipif/hdl/vhdl/jpeg_ht_nr_of_symbols.vhd
0,0 → 1,120
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_ht_nr_of_symbols.vhd when simulating
-- the core, jpeg_ht_nr_of_symbols. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_ht_nr_of_symbols IS
port (
A: IN std_logic_VECTOR(7 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(7 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(7 downto 0);
DPO: OUT std_logic_VECTOR(7 downto 0);
SPO: OUT std_logic_VECTOR(7 downto 0));
END jpeg_ht_nr_of_symbols;
 
ARCHITECTURE jpeg_ht_nr_of_symbols_a OF jpeg_ht_nr_of_symbols IS
-- synopsys translate_off
component wrapped_jpeg_ht_nr_of_symbols
port (
A: IN std_logic_VECTOR(7 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(7 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(7 downto 0);
DPO: OUT std_logic_VECTOR(7 downto 0);
SPO: OUT std_logic_VECTOR(7 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_jpeg_ht_nr_of_symbols use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
generic map(
c_qualify_we => 0,
c_mem_type => 2,
c_has_qdpo_rst => 0,
c_has_qspo => 0,
c_has_qspo_rst => 0,
c_has_dpo => 1,
c_has_qdpo_clk => 0,
c_has_d => 1,
c_qce_joined => 0,
c_width => 8,
c_reg_a_d_inputs => 0,
c_latency => 0,
c_has_spo => 1,
c_has_we => 1,
c_depth => 256,
c_has_i_ce => 0,
c_default_data_radix => 1,
c_default_data => "0",
c_has_dpra => 1,
c_has_clk => 1,
c_enable_rlocs => 1,
c_generate_mif => 1,
c_has_qspo_ce => 0,
c_addr_width => 8,
c_has_qdpo_srst => 0,
c_mux_type => 0,
c_has_spra => 0,
c_has_qdpo => 0,
c_reg_dpra_input => 0,
c_mem_init_file => "jpeg_ht_nr_of_symbols.mif",
c_has_qspo_srst => 0,
c_has_rd_en => 0,
c_read_mif => 0,
c_sync_enable => 0,
c_has_qdpo_ce => 0);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_ht_nr_of_symbols
port map (
A => A,
CLK => CLK,
D => D,
WE => WE,
DPRA => DPRA,
DPO => DPO,
SPO => SPO);
-- synopsys translate_on
 
END jpeg_ht_nr_of_symbols_a;
 
/myipif/hdl/vhdl/jpeg_dequant_multiplier.vhd
0,0 → 1,113
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_dequant_multiplier.vhd when simulating
-- the core, jpeg_dequant_multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_dequant_multiplier IS
port (
a: IN std_logic_VECTOR(11 downto 0);
b: IN std_logic_VECTOR(7 downto 0);
o: OUT std_logic_VECTOR(19 downto 0));
END jpeg_dequant_multiplier;
 
ARCHITECTURE jpeg_dequant_multiplier_a OF jpeg_dequant_multiplier IS
-- synopsys translate_off
component wrapped_jpeg_dequant_multiplier
port (
a: IN std_logic_VECTOR(11 downto 0);
b: IN std_logic_VECTOR(7 downto 0);
o: OUT std_logic_VECTOR(19 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_jpeg_dequant_multiplier use entity XilinxCoreLib.mult_gen_v8_0(behavioral)
generic map(
c_a_type => 0,
c_mem_type => 0,
c_has_sclr => 0,
c_has_q => 0,
c_reg_a_b_inputs => 0,
c_has_o => 1,
c_family => "virtex2p",
bram_addr_width => 0,
c_v2_speed => 0,
c_baat => 0,
c_output_hold => 0,
c_b_constant => 0,
c_has_loadb => 0,
c_has_b => 0,
c_use_luts => 0,
c_has_rdy => 0,
c_has_nd => 0,
c_pipeline => 0,
c_has_a_signed => 0,
c_b_type => 1,
c_standalone => 0,
c_sqm_type => 0,
c_b_value => "1010",
c_enable_rlocs => 0,
c_mult_type => 6,
c_has_aclr => 0,
c_mem_init_prefix => "mgv8",
c_has_load_done => 0,
c_has_swapb => 0,
c_out_width => 20,
c_b_width => 8,
c_a_width => 12,
c_has_rfd => 0,
c_sync_enable => 0,
c_has_ce => 0,
c_stack_adders => 0,
-- manually added:
c_elaboration_dir => "./",
c_xdevicefamily => "virtex2p"
);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_dequant_multiplier
port map (
a => a,
b => b,
o => o);
-- synopsys translate_on
 
END jpeg_dequant_multiplier_a;
 
/myipif/hdl/vhdl/jpeg_huffman_input_sr.vhd
0,0 → 1,102
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_huffman_input_sr.vhd when simulating
-- the core, jpeg_huffman_input_sr. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_huffman_input_sr IS
port (
CLK: IN std_logic;
SDOUT: OUT std_logic;
P_LOAD: IN std_logic;
D: IN std_logic_VECTOR(7 downto 0);
CE: IN std_logic;
SCLR: IN std_logic);
END jpeg_huffman_input_sr;
 
ARCHITECTURE jpeg_huffman_input_sr_a OF jpeg_huffman_input_sr IS
-- synopsys translate_off
component wrapped_jpeg_huffman_input_sr
port (
CLK: IN std_logic;
SDOUT: OUT std_logic;
P_LOAD: IN std_logic;
D: IN std_logic_VECTOR(7 downto 0);
CE: IN std_logic;
SCLR: IN std_logic);
end component;
 
-- Configuration specification
for all : wrapped_jpeg_huffman_input_sr use entity XilinxCoreLib.C_SHIFT_FD_V7_0(behavioral)
generic map(
c_has_aset => 0,
c_has_d => 1,
c_sync_priority => 1,
c_has_sclr => 1,
c_fill_data => 0,
c_width => 8,
c_enable_rlocs => 1,
c_ainit_val => "00000000",
c_has_ce => 1,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "00000000",
c_has_sdout => 1,
c_has_sset => 0,
c_has_sinit => 0,
c_has_q => 0,
c_shift_type => 0,
c_has_sdin => 0,
c_has_lsb_2_msb => 0);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_huffman_input_sr
port map (
CLK => CLK,
SDOUT => SDOUT,
P_LOAD => P_LOAD,
D => D,
CE => CE,
SCLR => SCLR);
-- synopsys translate_on
 
END jpeg_huffman_input_sr_a;
 
/myipif/hdl/vhdl/vga.vhd
0,0 → 1,520
---------------------------------------------------------------
-- This code is a simplified port from the Verilog sources that can be found here:
-- http://embedded.olin.edu/xilinx_docs/projects/bitvga-v2p.php
-- The Verilog sources are based on code from Xilinx and released under
-- "Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License"
-- with the note, that Xilinx claims the following copyright:
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
---------------------------------------------------------------
 
 
 
------------------------------
-- Suffix vga for 25MHz-clock-domain
------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
 
entity vga is
generic(
MAX_LINE_COUNT : integer := 479
);
port(
Clk : in std_logic;
reset_i : in std_logic;
eoi_i : in std_logic;
red_i : in STD_LOGIC_VECTOR (7 downto 0);
green_i : in STD_LOGIC_VECTOR (7 downto 0);
blue_i : in STD_LOGIC_VECTOR (7 downto 0);
width_i : in std_logic_vector(15 downto 0);
height_i : in std_logic_vector(15 downto 0);
sampling_i : in std_logic_vector( 1 downto 0);
 
VGA_OUT_PIXEL_CLOCK: out STD_LOGIC;
VGA_COMP_SYNCH: out STD_LOGIC;
VGA_OUT_BLANK_Z: out STD_LOGIC;
VGA_HSYNCH: out STD_LOGIC;
VGA_VSYNCH: out STD_LOGIC;
VGA_OUT_RED: out STD_LOGIC_VECTOR (7 downto 0);
VGA_OUT_GREEN: out STD_LOGIC_VECTOR (7 downto 0);
VGA_OUT_BLUE: out STD_LOGIC_VECTOR (7 downto 0);
 
-- -- chipscope-debugging
-- chipscope_o : out std_logic_vector(127 downto 0);
 
-- flow controll
datavalid_i : in std_logic;
ready_o : out std_logic
);
end entity vga;
 
 
 
 
 
architecture IMP of vga is
 
 
------------------------------------------------------------
-- VGA output
------------------------------------------------------------
component vga_signals is
port (
SYSTEM_CLOCK: in STD_LOGIC;
VGA_OUT_PIXEL_CLOCK: out STD_LOGIC;
VGA_COMP_SYNCH: out STD_LOGIC;
VGA_OUT_BLANK_Z: out STD_LOGIC;
VGA_HSYNCH: out STD_LOGIC;
VGA_VSYNCH: out STD_LOGIC;
o_pixel_clock: out STD_LOGIC;
o_pixel_count: out STD_LOGIC_VECTOR (10 downto 0);
o_line_count: out STD_LOGIC_VECTOR (9 downto 0)
);
end component vga_signals;
------------------------------------------------------------
 
 
 
 
 
------------------------------------------------------------
-- VGA Memory Buffer
------------------------------------------------------------
component vga_memory
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(14 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(14 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
end component;
------------------------------------------------------------
 
 
 
 
 
-- Clock domain crossing
signal eoi, vga_eoi, vga_eoi_D : std_logic :='0'; -- opb-Clk -> vga-clk
signal reset, vga_reset, vga_reset_D : std_logic :='0'; -- opb-Clk -> vga-clk
signal reset_hold, reset_hold_D : std_logic_vector(3 downto 0) :=(others=>'0');
signal width, vga_width, vga_width_D : std_logic_vector(15 downto 0) :=(others=>'0'); -- opb-Clk -> vga-clk
signal height, vga_height, vga_height_D : std_logic_vector(15 downto 0) :=(others=>'0'); -- opb-Clk -> vga-clk
signal sampling, vga_sampling, vga_sampling_D : std_logic_vector(1 downto 0) := (others=>'0'); -- opb-Clk -> vga-clk
signal vga_pixel_count : std_logic_vector(10 downto 0) := (others=>'0'); -- vga-clk -> OPB-clk
signal line_count, line_count_D, vga_line_count : std_logic_vector(9 downto 0) := (others=>'0'); -- vga-clk -> OPB-clk
 
signal memory_select, memory_select_D : std_logic :='0'; -- vga-clk -> OPB-clk
signal vga_memory_select, vga_memory_select_D : std_logic :='0';
signal vga_out_of_picture, vga_out_of_picture_D : std_logic :='0';
 
signal blocks_per_line, blocks_per_line_D : std_logic_vector(7 downto 0); -- opb-Clk -> vga-clk
signal vga_blocks_per_line, vga_blocks_per_line_D : std_logic_vector(7 downto 0);
 
-- OPB-Clk
signal stop_writing, stop_writing_D : std_logic :='1';
signal ready, ready_D : std_logic :='0';
signal last_memory_select, last_memory_select_D : std_logic :='0';
signal memory_addra, memory_addra_D : std_logic_vector(13 downto 0) :=(others=>'0');
signal memory_addra_final : std_logic_vector(14 downto 0) :=(others=>'0');
 
-- vga-clk
signal vga_pixel_clock : std_logic :='0';
signal vga_out_blank_z_intern : std_logic :='0';
signal vga_memory_red, vga_memory_green, vga_memory_blue : std_logic_vector(7 downto 0) :=(others=>'0');
signal vga_memory_addrb, vga_memory_addrb_D : std_logic_vector(13 downto 0) :=(others=>'0');
signal vga_memory_addrb_final : std_logic_vector(14 downto 0) :=(others=>'0');
signal vga_last_line_count, vga_last_line_count_D : std_logic :='0';
 
 
 
begin
 
 
 
-- **********************************************************************************************
-- * Wires
-- **********************************************************************************************
--chipscope_o <= red_i & green_i & blue_i & sampling_i & eoi_i & reset_i & datavalid_i & '0' & ready & vga_out_of_picture &
-- vga_memory_red & vga_memory_green & vga_memory_blue & vga_out_blank_z_intern & (vga_out_blank_z_intern and not vga_out_of_picture and not vga_reset) & "000000" &
-- X"0" & blocks_per_line & memory_addra_final & vga_memory_addrb_final &
-- "0" & vga_pixel_count & vga_line_count;
 
--VGA_OUT_RED <= vga_memory_red;
--VGA_OUT_GREEN <= memory_addra_final(14 downto 7);
--VGA_OUT_BLUE <= vga_memory_addrb(7 downto 0);
VGA_OUT_RED <= vga_memory_red;
VGA_OUT_GREEN <= vga_memory_green;
VGA_OUT_BLUE <= vga_memory_blue;
 
VGA_OUT_BLANK_Z <= vga_out_blank_z_intern and not vga_out_of_picture and not vga_reset;
 
eoi <= eoi_i;
width <= width_i;
height <= height_i;
sampling <= sampling_i;
ready_o <= ready;
reset <= reset_i;
 
 
 
 
 
-- **********************************************************************************************
-- * OPB-Clk domain (100 MHz)
-- **********************************************************************************************
-- to control writing
process(line_count, eoi, stop_writing, height)
begin
stop_writing_D <= stop_writing;
if (line_count=0) then
stop_writing_D <= '0';
end if;
if (line_count= MAX_LINE_COUNT or line_count=height-1) then -- maybe height-1
stop_writing_D <='1';
end if;
end process;
process(Clk)
begin
if rising_edge(Clk) then
if (reset='1' or eoi='1') then
stop_writing <= '1';
else
stop_writing <= stop_writing_D;
end if;
end if;
end process;
 
 
--------------------------------------------------------------
-- Calc blocks per line - this is necessary because jpeg fills
-- the picture on the right (and bottom) side to have a width
-- (and height) that is a multiple of 8
--------------------------------------------------------------
process(width, sampling)
begin
case sampling is
 
when "01" | "10" => -- 4:2:2 and 4:2:0
if width(3 downto 0)="0000" then
blocks_per_line_D <= width(11 downto 4);
else
blocks_per_line_D <= width(11 downto 4) + 1;
end if;
 
when others => -- 4:4:4 and gray
if width(2 downto 0)="000" then
blocks_per_line_D <= width(10 downto 3);
else
blocks_per_line_D <= width(10 downto 3) + 1;
end if;
 
end case;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
blocks_per_line <= blocks_per_line_D;
end if;
end process;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Calc the write-address for vga_memory
--------------------------------------------------------------
 
process(memory_addra, datavalid_i, ready, memory_select, last_memory_select)
begin
last_memory_select_D <= memory_select;
memory_addra_D <= memory_addra;
if(memory_select /= last_memory_select) then
memory_addra_D <= (others=>'0');
elsif (datavalid_i='1' and ready='1') then
memory_addra_D <= memory_addra + 1;
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
last_memory_select <= last_memory_select_D;
if reset='1' or eoi='1' then
memory_addra <= (others=>'0');
else
memory_addra <= memory_addra_D;
end if;
end if;
end process;
--------------------------------------------------------------
 
--------------------------------------------------------------
-- calc vga-ready
--------------------------------------------------------------
process(memory_addra, ready, blocks_per_line, sampling, stop_writing)
begin
ready_D <= ready;
case sampling is
when "01" =>
if( (memory_addra = (blocks_per_line & "00000000") ) or
(stop_writing='1') ) then
ready_D <= '0';
end if;
when "10" =>
if( (memory_addra = (blocks_per_line & "0000000") ) or
(stop_writing='1') ) then
ready_D <= '0';
end if;
when others =>
if( (memory_addra = (blocks_per_line & "000000") ) or
(stop_writing='1') ) then
ready_D <= '0';
end if;
end case;
if(memory_addra = 0 and stop_writing='0') then
ready_D <= '1';
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
if reset='1' or eoi='1'then
ready <= '0';
else
ready <= ready_D;
end if;
end if;
end process;
--------------------------------------------------------------
 
 
 
 
 
 
 
-- **********************************************************************************************
-- * Clock Domain Crossing
-- **********************************************************************************************
 
------------------------------------------------------------
-- Dual port bram for data (opb-clk -> vga-clk)
------------------------------------------------------------
vga_memory_red_p:vga_memory
port map (
clka => Clk,
dina => red_i,
addra => memory_addra_final,
wea(0)=> datavalid_i,
clkb => vga_pixel_clock,
addrb => vga_memory_addrb_final,
doutb => vga_memory_red
);
vga_memory_green_p:vga_memory
port map (
clka => Clk,
dina => green_i,
addra => memory_addra_final,
wea(0)=> datavalid_i,
clkb => vga_pixel_clock,
addrb => vga_memory_addrb_final,
doutb => vga_memory_green
);
vga_memory_blue_p:vga_memory
port map (
clka => Clk,
dina => blue_i,
addra => memory_addra_final,
wea(0)=> datavalid_i,
clkb => vga_pixel_clock,
addrb => vga_memory_addrb_final,
doutb => vga_memory_blue
);
 
memory_addra_final <= memory_select & (memory_addra);
vga_memory_addrb_final <= not vga_memory_select & vga_memory_addrb;
------------------------------------------------------------
 
 
 
------------------------------------------------------------
-- vga-clk -> opb-clk
------------------------------------------------------------
process(Clk)
begin
if rising_edge(Clk) then
 
line_count_D <= vga_line_count;
line_count <= line_count_D;
 
memory_select_D <= vga_memory_select;
memory_select <= memory_select_D;
 
end if;
end process;
------------------------------------------------------------
 
 
 
------------------------------------------------------------
-- opb-clk -> vga-clk
------------------------------------------------------------
process(vga_pixel_clock)
begin
if rising_edge(Clk) then
 
vga_sampling_D <= sampling;
vga_sampling <= vga_sampling_D;
 
vga_width_D <= width;
vga_width <= vga_width_D;
 
vga_height_D<= height;
vga_height <= vga_height_D;
 
end if;
end process;
------------------------------------------------------------
 
 
 
 
 
 
 
 
-- **********************************************************************************************
-- * VGA-Clock-Domain (25 MHz)
-- **********************************************************************************************
 
------------------------------------------------------------
-- Generate VGA-Signals and VGA-Clock
------------------------------------------------------------
vgacard:vga_signals
Port map (
SYSTEM_CLOCK => Clk,
VGA_OUT_PIXEL_CLOCK => VGA_OUT_PIXEL_CLOCK,
VGA_COMP_SYNCH => VGA_COMP_SYNCH,
VGA_OUT_BLANK_Z => vga_out_blank_z_intern,
VGA_HSYNCH => VGA_HSYNCH,
VGA_VSYNCH => VGA_VSYNCH,
o_pixel_clock => vga_pixel_clock,
o_pixel_count => vga_pixel_count,
o_line_count => vga_line_count
);
------------------------------------------------------------
 
--------------------------------------------------------------
-- is VGA-Coordinate "outside of the picture"?
--------------------------------------------------------------
process(vga_pixel_count, vga_line_count, vga_height, vga_width)
begin
if( (vga_pixel_count-1 >= vga_width) or (vga_line_count-16 >= vga_height) ) then -- TODO
vga_out_of_picture_D <= '1';
else
vga_out_of_picture_D <= '0';
end if;
end process;
 
process(vga_pixel_clock)
begin
if rising_edge(vga_pixel_clock) then
vga_out_of_picture <= vga_out_of_picture_D;
end if;
end process;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Calc the read-address for vga_memory
--------------------------------------------------------------
process(vga_memory_addrb, vga_memory_select, vga_pixel_count, vga_line_count, vga_sampling)
begin
 
vga_last_line_count_D <= vga_line_count(0);
vga_memory_select_D <= vga_memory_select;
vga_memory_addrb_D <= vga_memory_addrb;
case vga_sampling is
when "01" => -- 4:2:0
if ( vga_line_count(3 downto 0) = "0000" and vga_last_line_count /= vga_line_count(0)) then
vga_memory_select_D <= not vga_memory_select;
vga_memory_addrb_D <= (others=>'0');
elsif (vga_last_line_count /= vga_line_count(0)) then
vga_memory_addrb_D <= "000000" & (vga_line_count(3 downto 0)) & "0000";
elsif ( vga_pixel_count(3 downto 0)="0000" ) then
vga_memory_addrb_D <= vga_memory_addrb + 241;
else
vga_memory_addrb_D <= vga_memory_addrb + 1;
end if;
when "10" => -- 4:2:2
if ( vga_line_count(2 downto 0) = "000" and vga_last_line_count /= vga_line_count(0)) then
vga_memory_select_D <= not vga_memory_select;
vga_memory_addrb_D <= (others=>'0');
elsif (vga_last_line_count /= vga_line_count(0)) then
vga_memory_addrb_D <= "0000000" & (vga_line_count(2 downto 0)) & "0000";
elsif ( vga_pixel_count(3 downto 0)="0000" ) then
vga_memory_addrb_D <= vga_memory_addrb + 113;
else
vga_memory_addrb_D <= vga_memory_addrb + 1;
end if;
when others=> -- gray or 4:4:4
if ( vga_line_count(2 downto 0) = "000" and vga_last_line_count /= vga_line_count(0)) then
vga_memory_select_D <= not vga_memory_select;
vga_memory_addrb_D <= (others=>'0');
elsif (vga_last_line_count /= vga_line_count(0)) then
vga_memory_addrb_D <= "00000000" & (vga_line_count(2 downto 0)) & "000";
elsif ( vga_pixel_count(2 downto 0)="000" ) then
vga_memory_addrb_D <= vga_memory_addrb + 57;
else
vga_memory_addrb_D <= vga_memory_addrb + 1;
end if;
end case;
 
end process;
 
process(vga_pixel_clock)
begin
if rising_edge(vga_pixel_clock) then
vga_last_line_count <= vga_last_line_count_D;
vga_memory_select <= vga_memory_select_D;
vga_memory_addrb <= vga_memory_addrb_D;
end if;
end process;
--------------------------------------------------------------
 
 
 
end IMP;
/myipif/hdl/vhdl/jpeg_upsampling_buffer.vhd
0,0 → 1,126
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_upsampling_buffer.vhd when simulating
-- the core, jpeg_upsampling_buffer. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_upsampling_buffer IS
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(8 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(10 downto 0);
doutb: OUT std_logic_VECTOR(8 downto 0));
END jpeg_upsampling_buffer;
 
ARCHITECTURE jpeg_upsampling_buffer_a OF jpeg_upsampling_buffer IS
-- synopsys translate_off
component wrapped_jpeg_upsampling_buffer
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(8 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(10 downto 0);
doutb: OUT std_logic_VECTOR(8 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_jpeg_upsampling_buffer use entity XilinxCoreLib.blk_mem_gen_v1_1(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 1,
c_has_mux_output_regs => 0,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 9,
c_family => "virtex2p",
c_read_width_a => 9,
c_disable_warn_bhv_coll => 0,
c_init_file_name => "no_coe_file_loaded",
c_write_mode_b => "WRITE_FIRST",
c_write_mode_a => "WRITE_FIRST",
c_load_init_file => 0,
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_ssrb => 0,
c_has_ssra => 0,
c_addra_width => 11,
c_addrb_width => 11,
c_default_data => "0",
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_has_mem_output_regs => 0,
c_write_width_b => 9,
c_write_width_a => 9,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 0,
C_CORENAME => "blk_mem_gen_v1_1"
);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_upsampling_buffer
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
clkb => clkb,
addrb => addrb,
doutb => doutb);
-- synopsys translate_on
 
END jpeg_upsampling_buffer_a;
 
/myipif/hdl/vhdl/jpeg_dequantize.vhd
0,0 → 1,396
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg_dequantize is
port
( Clk : in std_logic;
reset_i : in std_logic;
 
-- storing the tables
header_select_i: in std_logic;
qt_wea_i : in std_logic;
qt_select_i : in std_logic_vector(1 downto 0); -- bit 1 and 0: table-nr. (at the moment only two QTs supported)
qt_data_i : in std_logic_vector(7 downto 0);
 
sampling_i : in std_logic_vector(3 downto 0);
context_i : in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(11 downto 0);
context_o : out std_logic_vector(3 downto 0) :=(others=>'0');
data_o : out std_logic_vector(11 downto 0) :=(others=>'0');
comp1_qt_number_i : in std_logic_vector(1 downto 0);
comp2_qt_number_i : in std_logic_vector(1 downto 0);
comp3_qt_number_i : in std_logic_vector(1 downto 0);
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end entity jpeg_dequantize;
 
 
 
 
 
 
 
 
 
architecture IMP of jpeg_dequantize is
 
component jpeg_dequant_multiplier
port (
a: IN std_logic_VECTOR(11 downto 0);
b: IN std_logic_VECTOR(7 downto 0);
o: OUT std_logic_VECTOR(19 downto 0));
end component;
 
-- store the tables in shift registers
component jpeg_qt_sr IS
port (
d: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
ce: IN std_logic;
q: OUT std_logic_VECTOR(7 downto 0));
end component;
 
 
 
signal qt0_0_data_in, qt1_0_data_in, qt0_1_data_in, qt1_1_data_in : std_logic_vector(7 downto 0) := (others=>'0');
signal qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out : std_logic_vector(7 downto 0) := (others=>'0');
signal qt0_0_ce, qt1_0_ce, qt0_1_ce, qt1_1_ce : std_logic :='0';
signal qt_out : std_logic_vector(7 downto 0) :=(others=>'0');
signal data : std_logic_vector(19 downto 0):=(others=>'0');
signal context : std_logic_vector(3 downto 0) :=(others =>'0');
signal select_qt, select_qt_D : std_logic_vector( 1 downto 0) :=(others=>'0');
signal counter : std_logic_vector(5 downto 0) :=(others=>'0');
signal sampling_counter, sampling_counter_D : std_logic_vector(2 downto 0) :=(others=>'0');
signal sampling : std_logic_vector(1 downto 0) :=(others=>'0');
signal comp1_qt_number : std_logic_vector(0 downto 0) :="0";
signal comp2_qt_number : std_logic_vector(0 downto 0) :="0";
signal comp3_qt_number : std_logic_vector(0 downto 0) :="0";
 
-- flowcontroll
signal datavalid : std_logic := '0';
signal ce : std_logic :='0';
signal reset : std_logic :='1';
 
 
 
 
 
begin
 
ce <= datavalid_i and ready_i;
datavalid <= ce;
ready_o <= ready_i;
reset <= reset_i;
 
process(Clk)
begin
if rising_edge(Clk) then
 
datavalid_o <= datavalid;
data_o <= data(19) & data(10 downto 0);
context <= context_i;
context_o <= context;
 
if reset='1' then
datavalid_o <= '0';
context_o <= "0000";
context <= "0000";
end if;
end if;
end process;
 
 
 
process(Clk)
begin
if rising_edge(Clk) then
if reset='1' then
counter <= (others=>'0');
elsif(ce='1') then
counter <= counter + 1;
end if;
end if;
end process;
 
 
 
 
-------------------------------------------------------------------------
-- store the context
-------------------------------------------------------------------------
process(sampling_i, context(1))
begin
if (context(1)='0') then
sampling <= sampling_i(1 downto 0);
comp1_qt_number <= comp1_qt_number_i(0 downto 0);
comp2_qt_number <= comp2_qt_number_i(0 downto 0);
comp3_qt_number <= comp3_qt_number_i(0 downto 0);
else
sampling <= sampling_i(3 downto 2);
comp1_qt_number <= comp1_qt_number_i(1 downto 1);
comp2_qt_number <= comp2_qt_number_i(1 downto 1);
comp3_qt_number <= comp3_qt_number_i(1 downto 1);
end if;
end process;
-------------------------------------------------------------------------
 
 
 
 
-------------------------------------------------------------------------
-- count the data processed
-------------------------------------------------------------------------
process(sampling_counter, sampling, counter)
begin
sampling_counter_D <= sampling_counter;
 
case sampling is
---------------------------------------
-- gray Y -> Y -> Y ...
---------------------------------------
when "00" =>
sampling_counter_D <= "000";
---------------------------------------
-- 4:2:0 Y -> Y -> Y -> Y -> Cb -> Cr -> Y -> Y ...
---------------------------------------
when "01" =>
if (counter=63) then
sampling_counter_D <= sampling_counter + 1;
if (sampling_counter="101") then
sampling_counter_D <= "000";
end if;
end if;
---------------------------------------
-- 4:2:2 Y -> Y -> Cb -> Cr -> Y -> Y ...
---------------------------------------
when "10" =>
if (counter=63) then
sampling_counter_D <= sampling_counter + 1;
if (sampling_counter="011") then
sampling_counter_D <= "000";
end if;
end if;
---------------------------------------
-- 4:4:4 Y -> Cb -> Cr -> Y -> Cb ...
---------------------------------------
when others =>
if (counter=63) then
sampling_counter_D <= sampling_counter + 1;
if (sampling_counter="010") then
sampling_counter_D <= "000";
end if;
end if;
end case;
end process;
 
 
process(Clk)
begin
if (rising_edge(Clk)) then
if (reset='1') then
sampling_counter <= (others=>'0');
elsif ce='1' then
sampling_counter <= sampling_counter_D;
end if;
end if;
end process;
-------------------------------------------------------------------------
 
 
 
-------------------------------------------------------------------------
-- decide which table to use
-------------------------------------------------------------------------
process(select_qt, sampling_counter, sampling)
begin
select_qt_D <= select_qt;
case sampling is
---------------------------------------
-- gray
---------------------------------------
when "00" =>
select_qt_D <= context(1) & comp1_qt_number;
---------------------------------------
-- 4:2:0
---------------------------------------
when "01" =>
case sampling_counter is
when "000"|"001"|"010"|"011" =>
select_qt_D <= context(1) & comp1_qt_number;
when "100" =>
select_qt_D <= context(1) & comp2_qt_number;
when "101" =>
select_qt_D <= context(1) & comp3_qt_number;
when others =>
end case;
---------------------------------------
-- 4:2:2
---------------------------------------
when "10" =>
case sampling_counter is
when "000"|"001" =>
select_qt_D <= context(1) & comp1_qt_number;
when "010" =>
select_qt_D <= context(1) & comp2_qt_number;
when "011" =>
select_qt_D <= context(1) & comp3_qt_number;
when others =>
end case;
---------------------------------------
-- 4:4:4
---------------------------------------
when others =>
case sampling_counter is
when "000" =>
select_qt_D <= context(1) & comp1_qt_number;
when "001" =>
select_qt_D <= context(1) & comp2_qt_number;
when "010" =>
select_qt_D <= context(1) & comp3_qt_number;
when others =>
end case;
end case;
end process;
 
 
process(Clk)
begin
if rising_edge(Clk) then
select_qt <= select_qt_D;
end if;
end process;
-------------------------------------------------------------------------
 
 
 
 
-------------------------------------------------------------------------
-- process the right table
-------------------------------------------------------------------------
process( qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out,
ce, context, select_qt, qt_wea_i, header_select_i, qt_select_i, qt_data_i)
begin
 
qt0_0_ce <= '0';
qt1_0_ce <= '0';
qt0_1_ce <= '0';
qt1_1_ce <= '0';
qt0_0_data_in <= qt0_0_data_out;
qt1_0_data_in <= qt1_0_data_out;
qt0_1_data_in <= qt0_1_data_out;
qt1_1_data_in <= qt1_1_data_out;
 
if ce='1' and context(1)='0' and select_qt(0)='0' then
qt0_0_ce <= '1';
elsif ce='1' and context(1)='0' and select_qt(0)='1' then
qt1_0_ce <= '1';
elsif ce='1' and context(1)='1' and select_qt(0)='0' then
qt0_1_ce <= '1';
elsif ce='1' and context(1)='1' and select_qt(0)='1' then
qt1_1_ce <= '1';
end if;
 
-- fill the tables
if qt_wea_i='1' and header_select_i='0' and qt_select_i="00" then
qt0_0_ce <= '1';
qt0_0_data_in <= qt_data_i;
elsif qt_wea_i='1' and header_select_i='0' and qt_select_i="01" then
qt1_0_ce <= '1';
qt1_0_data_in <= qt_data_i;
elsif qt_wea_i='1' and header_select_i='1' and qt_select_i="00" then
qt0_1_ce <= '1';
qt0_1_data_in <= qt_data_i;
elsif qt_wea_i='1' and header_select_i='1' and qt_select_i="01" then
qt1_1_ce <= '1';
qt1_1_data_in <= qt_data_i;
end if;
 
-- end if;
end process;
-------------------------------------------------------------------------
 
-------------------------------------------------------------------------
-- select the right table for the multiplication
-------------------------------------------------------------------------
process(qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out, select_qt)
begin
if select_qt="00" then
qt_out <= qt0_0_data_out;
elsif select_qt="01" then
qt_out <= qt1_0_data_out;
elsif select_qt="10" then
qt_out <= qt0_1_data_out;
elsif select_qt="11" then
qt_out <= qt1_1_data_out;
end if;
end process;
-------------------------------------------------------------------------
 
 
-------------------------------------------------------------------------
-- Multiply
-------------------------------------------------------------------------
jpeg_dequant_multiplier_p : jpeg_dequant_multiplier
port map (
a => data_i,
b => qt_out,
o => data
);
-------------------------------------------------------------------------
 
-------------------------------------------------------------------------
-- circular shift registers for the tables
-------------------------------------------------------------------------
jpeg_qt_sr_0_0_p : jpeg_qt_sr
port map(
d => qt0_0_data_in,
clk => Clk,
ce => qt0_0_ce,
q => qt0_0_data_out
);
 
jpeg_qt_sr_1_0_p : jpeg_qt_sr
port map(
d => qt1_0_data_in,
clk => Clk,
ce => qt1_0_ce,
q => qt1_0_data_out
);
 
jpeg_qt_sr_0_1_p : jpeg_qt_sr
port map(
d => qt0_1_data_in,
clk => Clk,
ce => qt0_1_ce,
q => qt0_1_data_out
);
 
jpeg_qt_sr_1_1_p : jpeg_qt_sr
port map(
d => qt1_1_data_in,
clk => Clk,
ce => qt1_1_ce,
q => qt1_1_data_out
);
-------------------------------------------------------------------------
 
 
end IMP;
/myipif/hdl/vhdl/jpeg_qt_tables.vhd
0,0 → 1,119
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_qt_tables.vhd when simulating
-- the core, jpeg_qt_tables. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_qt_tables IS
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
END jpeg_qt_tables;
 
ARCHITECTURE jpeg_qt_tables_a OF jpeg_qt_tables IS
-- synopsys translate_off
component wrapped_jpeg_qt_tables
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_jpeg_qt_tables use entity XilinxCoreLib.blk_mem_gen_v1_1(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_has_mux_output_regs => 0,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "virtex2p",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 1,
c_init_file_name => "no_coe_file_loaded",
c_write_mode_b => "WRITE_FIRST",
c_write_mode_a => "WRITE_FIRST",
c_load_init_file => 0,
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_ssrb => 0,
c_has_ssra => 0,
c_addra_width => 11,
c_addrb_width => 11,
c_default_data => "0",
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_has_mem_output_regs => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 0,
C_CORENAME => "blk_mem_gen_v1_1");
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_qt_tables
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
douta => douta);
-- synopsys translate_on
 
END jpeg_qt_tables_a;
 
/myipif/hdl/vhdl/jpeg_testbench.vhd
0,0 → 1,271
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
use std.textio.all;
 
 
entity jpeg_testbench is
generic (
jpeg_file_name: string := "data/lena.jpg";
log_file_name : string := "data/lena.log"
);
end entity jpeg_testbench;
 
 
architecture test of jpeg_testbench is
 
 
component jpeg is
port (
Clk : in std_logic;
data_i : in std_logic_vector(31 downto 0);
reset_i : in std_logic;
eoi_o : out std_logic;
error_o : out std_logic;
context_o : out std_logic_vector (3 downto 0);
red_o : out STD_LOGIC_VECTOR (7 downto 0);
green_o : out STD_LOGIC_VECTOR (7 downto 0);
blue_o : out STD_LOGIC_VECTOR (7 downto 0);
width_o : out std_logic_vector(15 downto 0);
height_o : out std_logic_vector(15 downto 0);
-- -- debug
-- LEDs : out std_logic_vector(3 downto 0);
-- BUTTONs : in std_logic_vector(4 downto 0); -- 0:left, 1:right, 2:up, 3:down, 4:center
-- SWITCHEs : in std_logic_vector(3 downto 0);
 
-- flow controll
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg;
 
 
 
 
component fifo_sim32 is
generic
(
filename : string := "out.log";
log_time : integer := 1
);
port
(
rst : in std_logic;
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
we : in std_logic;
full : out std_logic
);
end component fifo_sim32;
 
 
 
signal data : std_logic_vector(31 downto 0) :=(others=>'0');
signal ddr_address : std_logic_vector(31 downto 0) :=(others=>'0');
signal wea : std_logic :='0';
signal Clk, reset : std_logic :='1';
signal ready : std_logic :='0';
signal counter : std_logic_vector(31 downto 0) := (others=>'0');
signal jpeg_ready, jpeg_eoi, jpeg_error : std_logic :='0';
 
signal fifo_sim32_data : std_logic_vector(31 downto 0) :=(others=>'0');
signal fifo_sim32_wea, fifo_sim32_full, fifo_sim32_notfull : std_logic :='0';
type ByteT is (c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30,c31,c32,c33,c34,c35,c36,c37,c38,c39,c40,c41,c42,c43,c44,c45,c46,c47,c48,c49,c50,c51,c52,c53,c54,c55,c56,c57,c58,c59,c60,c61,c62,c63,c64,c65,c66,c67,c68,c69,c70,c71,c72,c73,c74,c75,c76,c77,c78,c79,c80,c81,c82,c83,c84,c85,c86,c87,c88,c89,c90,c91,c92,c93,c94,c95,c96,c97,c98,c99,c100,c101,c102,c103,c104,c105,c106,c107,c108,c109,c110,c111,c112,c113,c114,c115,c116,c117,c118,c119,c120,c121,c122,c123,c124,c125,c126,c127,c128,c129,c130,c131,c132,c133,c134,c135,c136,c137,c138,c139,c140,c141,c142,c143,c144,c145,c146,c147,c148,c149,c150,c151,c152,c153,c154,c155,c156,c157,c158,c159,c160,c161,c162,c163,c164,c165,c166,c167,c168,c169,c170,c171,c172,c173,c174,c175,c176,c177,c178,c179,c180,c181,c182,c183,c184,c185,c186,c187,c188,c189,c190,c191,c192,c193,c194,c195,c196,c197,c198,c199,c200,c201,c202,c203,c204,c205,c206,c207,c208,c209,c210,c211,c212,c213,c214,c215,c216,c217,c218,c219,c220,c221,c222,c223,c224,c225,c226,c227,c228,c229,c230,c231,c232,c233,c234,c235,c236,c237,c238,c239,c240,c241,c242,c243,c244,c245,c246,c247,c248,c249,c250,c251,c252,c253,c254,c255);
subtype Byte is ByteT;
type ByteFileType is file of Byte;
file jpeg_file : ByteFileType;
 
 
-- integer to bit_vector conversion
function int2bit_vec(A: integer; SIZE: integer) return BIT_VECTOR is
variable RESULT: BIT_VECTOR(SIZE-1 downto 0);
variable TMP: integer;
begin
TMP:=A;
for i in 0 to SIZE-1 loop
if TMP mod 2 = 1 then RESULT(i):='1';
else RESULT(i):='0';
end if;
TMP:=TMP / 2;
end loop;
return RESULT;
end;
 
 
 
begin
 
 
 
 
------------------------------------------------------------
-- JPEG - Decoder
--------------------------------------------------------------
jpeg_decoder:jpeg
port map
( Clk => Clk,
data_i => data,
reset_i => reset,
eoi_o => jpeg_eoi,
error_o => jpeg_error,
-- context_o =>
red_o => fifo_sim32_data(23 downto 16),
green_o => fifo_sim32_data(15 downto 8),
blue_o => fifo_sim32_data(7 downto 0),
-- width_o => ,
-- height_o => ,
 
-- debug
-- LEDs => ,
-- BUTTONs => "11111",
-- SWITCHEs => "1111",
 
datavalid_i => wea,
datavalid_o => fifo_sim32_wea,
ready_i => ready,
ready_o => jpeg_ready
);
--------------------------------------------------------------
 
 
 
--------------------------------------------------------------
-- Output into file
--------------------------------------------------------------
fifo32_p : fifo_sim32
generic map(
filename => log_file_name
-- log_time => 0
)
port map(
rst => reset,
clk => Clk,
din => fifo_sim32_data,
we => fifo_sim32_wea,
full => fifo_sim32_full
);
fifo_sim32_data(31 downto 24) <= (others=>'0');
fifo_sim32_notfull <= not fifo_sim32_full;
--------------------------------------------------------------
 
 
 
-- **********************************************************************************************
-- * Wires
-- **********************************************************************************************
 
--wea <= '0', '1' after 58 ns;
reset <= '1', '0' after 13 ns; --, '1' after 50 us, '0' after 51 us;
 
 
 
-- **********************************************************************************************
-- * Processes
-- **********************************************************************************************
 
 
-- simulate a clock
clock_p: process
begin
Clk <= '1';
wait for 5 ns;
Clk <= '0';
wait for 5 ns;
end process;
 
ready <= '1';
 
 
---- counter
--counter_p: process
--begin
-- while true loop
-- wait until CLK='1';
-- counter <= counter +1;
-- end loop;
--end process;
 
 
 
 
 
 
file_input: process
variable l: line;
variable b1: Byte;
variable b2: Byte;
variable b3: Byte;
variable b4: Byte;
begin
wea <= '0';
wait for 20 ns;
-- read from file
file_open(jpeg_file, jpeg_file_name, read_mode);
-- while true loop
while not(endfile(jpeg_file)) loop
 
-- -- reload image on eoi
-- if(endfile(jpeg_file)) then
-- wait until CLK='1';
-- wea <= '0';
-- file_close(jpeg_file);
-- wait until jpeg_eoi='1';
-- file_open(jpeg_file, jpeg_file_name, read_mode);
-- wait for 20 ns;
-- end if;
 
-- reload image on reset
-- if(reset='1') then
-- wea <= '0';
-- file_close(jpeg_file);
-- wait until reset='0';
-- file_open(jpeg_file, jpeg_file_name, read_mode);
-- wait for 20 ns;
-- end if;
 
if (jpeg_ready='1') then
if not(endfile(jpeg_file)) then
read(jpeg_file,b1);
end if;
if not(endfile(jpeg_file)) then
read(jpeg_file,b2);
end if;
if not(endfile(jpeg_file)) then
read(jpeg_file,b3);
end if;
if not(endfile(jpeg_file)) then
read(jpeg_file,b4);
end if;
end if;
 
wait for 8 ns;
wea <= '1';
data(31 downto 24) <= to_stdlogicvector(int2bit_vec(ByteT'pos(b1),8));
data(23 downto 16) <= to_stdlogicvector(int2bit_vec(ByteT'pos(b2),8));
data(15 downto 8 ) <= to_stdlogicvector(int2bit_vec(ByteT'pos(b3),8));
data( 7 downto 0 ) <= to_stdlogicvector(int2bit_vec(ByteT'pos(b4),8));
 
wait until CLK='1';
 
end loop;
 
wait;
 
end process;
 
 
end test;
/myipif/hdl/vhdl/jpeg_YCbCr2RGB.vhd
0,0 → 1,144
------------------------------------------------------------------
-- Two clock cycles delay
--
-- TODO:
-- - remove reset ???
------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity jpeg_YCbCr2RGB is
port(
Clk : in std_logic;
reset_i : in std_logic;
context_i : in std_logic_vector(3 downto 0);
Y_i : in std_logic_vector(8 downto 0);
Cb_i : in std_logic_vector(8 downto 0);
Cr_i : in std_logic_vector(8 downto 0);
context_o : out std_logic_vector(3 downto 0);
R_o : out std_logic_vector(7 downto 0);
G_o : out std_logic_vector(7 downto 0);
B_o : out std_logic_vector(7 downto 0);
 
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end entity jpeg_YCbCr2RGB;
 
 
 
architecture IMP of jpeg_YCbCr2RGB is
 
signal datavalid, datavalid_D : std_logic := '0';
signal ready : std_logic := '0';
signal ce : std_logic :='1';
signal reset : std_logic :='1';
signal context, context_D : std_logic_vector(3 downto 0) := (others=>'0');
signal R, R_D, G, G_D, B, B_D : std_logic_vector(7 downto 0) := (others=>'0');
signal tmp_R, tmp_G, tmp_B : integer := 0;
signal tmp_R_D, tmp_G_D, tmp_B_D : integer := 0;
signal Y, Cb, Cr : std_logic_vector(7 downto 0) := (others=>'0');
 
begin
 
process(Y_i, Cb_i, Cr_i, R, G, B)
variable tmp_Y : integer := 0;
variable int_Y, int_Cb, int_Cr : integer := 0;
begin
 
-- level shift and convertion to integer
-- 8-bit may (intentionally) overflow here
int_Y := conv_integer(signed(Y_i));
int_Cb := conv_integer(signed(Cb_i));
int_Cr := conv_integer(signed(Cr_i));
-- to use integer arithmetic
tmp_Y := 1024*(int_Y+128);
 
-- YCbCr2RBG
tmp_R_D <= tmp_Y + 1436*(int_Cr);
tmp_G_D <= tmp_Y - 352*(int_Cb) - 731*(int_Cr);
tmp_B_D <= tmp_Y + 1815*(int_Cb);
 
end process;
 
 
-- one additional clock cycle to meet timing constraints on the xup board
process(Clk)
begin
if rising_edge(Clk) then
if ce='1' then
tmp_R <= tmp_R_D;
tmp_G <= tmp_G_D;
tmp_B <= tmp_B_D;
end if;
end if;
end process;
 
 
 
process(tmp_R, tmp_G, tmp_B)
variable tmp_R2, tmp_G2, tmp_B2 : integer := 0;
begin
tmp_R2 := tmp_R;
tmp_G2 := tmp_G;
tmp_B2 := tmp_B;
 
-- check boundaries
if(tmp_R<0) then
tmp_R2 := 0;
elsif(tmp_R>255*1024) then
tmp_R2 := 255*1024;
end if;
if(tmp_G<0) then
tmp_G2 := 0;
elsif(tmp_G>255*1024) then
tmp_G2 := 255*1024;
end if;
if(tmp_B<0) then
tmp_B2 := 0;
elsif(tmp_B>255*1024) then
tmp_B2 := 255*1024;
end if;
R_D <= conv_std_logic_vector(tmp_R2/1024, 8);
G_D <= conv_std_logic_vector(tmp_G2/1024, 8);
B_D <= conv_std_logic_vector(tmp_B2/1024, 8);
end process;
 
 
-- flowcontroll
ready_o <= ready_i;
ce <= ready_i;
 
process(Clk)
begin
if rising_edge(Clk) then
context <= context_i;
context_o <= context;
if reset_i ='1' then
context <= (others=>'0');
context_o <= (others=>'0');
datavalid <= '0';
datavalid_o <= '0';
elsif ce='1' then
datavalid <= datavalid_i;
datavalid_o <= datavalid;
R_o <= R_D;
G_o <= G_D;
B_o <= B_D;
end if;
end if;
end process;
 
end IMP;
/myipif/hdl/vhdl/jpeg_upsampling.vhd
0,0 → 1,461
-------------------------------------------------------------------------------------------------
-- Two address ranges (indicated by the address-MSB) are used alternately as input and output buffer.
-- When the input buffer is full and the output buffer is empty, 'do_copy' toggles the address-MSB.
-------------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity jpeg_upsampling is
port(
Clk : in std_logic;
reset_i : in std_logic;
context_i : in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(8 downto 0);
sampling_i : in std_logic_vector(3 downto 0);
context_o : out std_logic_vector(3 downto 0);
Y_o : out std_logic_vector(8 downto 0);
Cb_o : out std_logic_vector(8 downto 0);
Cr_o : out std_logic_vector(8 downto 0);
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end entity;
 
architecture IMP of jpeg_upsampling is
 
component jpeg_upsampling_buffer
port (
clka : IN std_logic;
dina : IN std_logic_VECTOR(8 downto 0);
addra : IN std_logic_VECTOR(10 downto 0);
wea : IN std_logic_VECTOR(0 downto 0);
clkb : IN std_logic;
addrb : IN std_logic_VECTOR(10 downto 0);
doutb : OUT std_logic_VECTOR(8 downto 0)
);
end component;
 
signal doutb_Y, doutb_Cb, doutb_Cr : std_logic_vector(8 downto 0) :=(others=>'0');
 
signal addra_Y, addra_Cb, addra_Cr : std_logic_vector(10 downto 0) :=(others=>'0');
signal addrb_Y, addrb_Cb, addrb_Cr : std_logic_vector(10 downto 0) :=(others=>'0');
signal addrb_Y_short, addrb_Y_short_D : std_logic_vector(7 downto 0) :=(others=>'0');
signal addrb_Cb_short, addrb_Cr_short, addrb_Cb_short_D, addrb_Cr_short_D : std_logic_vector(5 downto 0) :=(others=>'0');
signal address_msb, address_msb_D : std_logic :='0';
 
signal wea_Y : std_logic_vector(0 downto 0) :=(others=>'1');
signal wea_Y_D, wea_Y_rem : std_logic_vector(0 downto 0) :=(others=>'1');
signal wea_Cb, wea_Cr : std_logic_vector(0 downto 0) :=(others=>'0');
signal wea_Cb_D, wea_Cr_D, wea_Cb_rem, wea_Cr_rem : std_logic_vector(0 downto 0) :=(others=>'0');
signal ce_in : std_logic :='0';
signal ce_out : std_logic :='0';
signal counter_in, counter_in_D, counter_in_hold : std_logic_vector(8 downto 0) :=(others=>'0');
signal counter_out,counter_out_D, counter_out_hold : std_logic_vector(7 downto 0) :=(others=>'1');
signal counter_in_Y_max, counter_in_Y_D_max : std_logic_vector(8 downto 0) :=(others=>'0');
signal counter_in_Cb_max, counter_in_Cb_D_max : std_logic_vector(8 downto 0) :=(others=>'0');
signal counter_in_Cr_max, counter_in_Cr_D_max : std_logic_vector(8 downto 0) :=(others=>'0');
signal do_copy, do_copy_D, do_copy_delayed : std_logic :='0';
signal stop_in, stop_in_D : std_logic :='0';
signal stop_out, stop_out_D : std_logic :='1';
signal stop_eoi_out, stop_eoi_out_D : std_logic := '1';
signal context_in, context_in_D, context_out, context_out_D : std_logic_vector(3 downto 0) :=(others=>'0');
signal eoi, eoi_D : std_logic :='0';
signal eoi_hold, eoi_hold_D : std_logic :='0';
signal ready, ready_D : std_logic :='1';
signal datavalid : std_logic :='0';
-- "00"->gray, "01"->4:2:0, "10"->4:2:2, "11"->4:4:4
signal sampling_in, sampling_in_D, sampling_out, sampling_out_D : std_logic_vector(1 downto 0) :=(others=>'0');
 
 
begin
 
 
Y_buffer : jpeg_upsampling_buffer
port map (
clka => Clk,
dina => data_i,
addra => addra_Y,
wea => wea_Y,
clkb => Clk,
addrb => addrb_Y,
doutb => doutb_Y
);
Cb_buffer : jpeg_upsampling_buffer
port map (
clka => Clk,
dina => data_i,
addra => addra_Cb,
wea => wea_Cb,
clkb => Clk,
addrb => addrb_Cb,
doutb => doutb_Cb
);
Cr_buffer : jpeg_upsampling_buffer
port map (
clka => Clk,
dina => data_i,
addra => addra_Cr,
wea => wea_Cr,
clkb => Clk,
addrb => addrb_Cr,
doutb => doutb_Cr
);
addra_Y <= address_msb & "00" & counter_in(7 downto 0);
addra_Cb <= address_msb & "0000" & counter_in(5 downto 0);
addra_Cr <= address_msb & "0000" & counter_in(5 downto 0);
addrb_Y <= not address_msb & "00" & addrb_Y_short;
addrb_Cb <= not address_msb & "0000" & addrb_Cb_short;
addrb_Cr <= not address_msb & "0000" & addrb_Cr_short;
wea_Y(0) <= wea_Y_rem(0) and ce_in;
wea_Cb(0) <= wea_Cb_rem(0) and ce_in;
wea_Cr(0) <= wea_Cr_rem(0) and ce_in;
 
 
 
 
-- connect signals to the outside
process(Clk)
begin
if rising_edge(Clk) then
ready_o <= ready;
datavalid <= ce_out;
datavalid_o <= datavalid;
Y_o <= doutb_Y;
Cb_o <= doutb_Cb;
Cr_o <= doutb_Cr;
context_o <= context_out;
end if;
end process;
 
 
 
process(sampling_in, sampling_out)
begin
case sampling_in is
when "00" => -- gray 1 in (8x8 blocks)
counter_in_hold <= "000111111";
counter_in_Y_max <= "111111111";
counter_in_Cb_max <= "111111111";
counter_in_Cr_max <= "111111111";
when "01" => -- 4:2:0 6 in
counter_in_hold <= "101111111";
counter_in_Y_max <= "011111111";
counter_in_Cb_max <= "100111111";
counter_in_Cr_max <= "101111111";
when "10" => -- 4:2:2 4 in
counter_in_hold <= "011111111";
counter_in_Y_max <= "001111111";
counter_in_Cb_max <= "010111111";
counter_in_Cr_max <= "011111111";
when others => -- 4:4:4 3 in
counter_in_hold <= "010111111";
counter_in_Y_max <= "000111111";
counter_in_Cb_max <= "001111111";
counter_in_Cr_max <= "010111111";
end case;
case sampling_out is
when "00" => -- gray 1 out
counter_out_hold <= "00111111";
when "01" => -- 4:2:0 4 out
counter_out_hold <= "11111111";
when "10" => -- 4:2:2 2 out
counter_out_hold <= "01111111";
when others => -- 4:4:4 1 out
counter_out_hold <= "00111111";
end case;
end process;
 
 
 
 
 
 
 
 
 
----------------------------------------------------------
-- handle the write-enable
process(wea_Y_rem, wea_Cb_rem, wea_Cr_rem, counter_in, counter_in_Y_max, counter_in_Cb_max,
counter_in_Cr_max, reset_i, do_copy)
begin
wea_Y_D <= wea_Y_rem;
wea_Cb_D <= wea_Cb_rem;
wea_Cr_D <= wea_Cr_rem;
if (counter_in=counter_in_Y_max) then
wea_Y_D <= "0";
wea_Cb_D <= "1";
end if;
if (counter_in=counter_in_Cb_max) then
wea_Cb_D <= "0";
wea_Cr_D <= "1";
end if;
if (counter_in=counter_in_Cr_max) then
wea_Cr_D <= "0";
wea_Y_D <= "1";
end if;
if reset_i='1' or do_copy='1' then
wea_Y_D <= "1";
wea_Cb_D <= "0";
wea_Cr_D <= "0";
end if;
 
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
wea_Y_rem <= wea_Y_D;
wea_Cb_rem <= wea_Cb_D;
wea_Cr_rem <= wea_Cr_D;
end if;
end process;
----------------------------------------------------------
 
 
process(counter_out, addrb_Y_short, addrb_Cb_short, addrb_Cr_short, sampling_out)
begin
 
case sampling_out is
when "01" => -- 4:2:0
addrb_Y_short <= counter_out(7) & counter_out(3) & counter_out(6 downto 4) & counter_out(2 downto 0);
addrb_Cb_short <= counter_out(7 downto 5) & counter_out(3 downto 1);
addrb_Cr_short <= counter_out(7 downto 5) & counter_out(3 downto 1);
when "10" => -- 4:2:2
addrb_Y_short <= '0' & counter_out(3) & counter_out(6 downto 4) & counter_out(2 downto 0);
addrb_Cb_short <= counter_out(6 downto 1);
addrb_Cr_short <= counter_out(6 downto 1);
when others => -- gray and 4:4:4
addrb_Y_short <= "00" & counter_out(5 downto 0);
addrb_Cb_short <= counter_out(5 downto 0);
addrb_Cr_short <= counter_out(5 downto 0);
end case;
 
end process;
----------------------------------------------------------
 
 
 
 
----------------------------------------------------------
-- switch read and write memory
 
do_copy_D <= stop_in and stop_out;
 
process(do_copy, do_copy_delayed, address_msb)
begin
address_msb_D <= address_msb;
if do_copy='1' and do_copy_delayed='0' then
address_msb_D <= not address_msb;
end if;
end process;
 
 
process(ready, counter_in, counter_in_hold, do_copy)
begin
ready_D <= ready;
 
if counter_in=(counter_in_hold-62) then
ready_D <='0';
end if;
if do_copy='1' then
ready_D <='1';
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
if reset_i='1' then
ready <= '1';
do_copy <= '0';
do_copy_delayed <= '0';
address_msb <= '0';
else
ready <= ready_D;
do_copy <= do_copy_D;
do_copy_delayed <= do_copy;
address_msb <= address_msb_D;
end if;
end if;
end process;
----------------------------------------------------------
 
 
 
 
 
 
 
process(stop_eoi_out, counter_in, do_copy)
begin
stop_eoi_out_D <= stop_eoi_out;
if (counter_in=1) then
stop_eoi_out_D <='1';
elsif(do_copy='1') then
stop_eoi_out_D<='0';
end if;
end process;
process(Clk, reset_i)
begin
if rising_edge(Clk) then
if(reset_i='1') then
stop_eoi_out <='1';
elsif ce_in='1' then
stop_eoi_out <= stop_eoi_out_D;
end if;
end if;
end process;
 
 
 
-- handle the context
process(eoi, eoi_hold, context_i, counter_out, do_copy, stop_eoi_out)
begin
eoi_D <= eoi;
eoi_hold_D <= eoi_hold;
if (context_i(3)='1' and do_copy='0' and stop_eoi_out='1') then
eoi_hold_D <= '1';
elsif(context_i(3)='1' and (do_copy='1' and stop_eoi_out='1')) then
eoi_D <= '1';
eoi_hold_D <= '0';
elsif(context_i(3)='1' and stop_eoi_out='0') then
eoi_D <= '1';
eoi_hold_D <= '0';
elsif(eoi_hold='1' and do_copy='1') then
eoi_D <= '1';
eoi_hold_D <= '0';
end if;
if (counter_out=counter_out_hold and eoi='1') then
eoi_D <= '0';
end if;
end process;
 
process(context_i, sampling_i)
begin
context_in_D <= '0' & context_i(2 downto 0);
if context_i(1)='0' then
sampling_in_D <= sampling_i(1 downto 0);
else
sampling_in_D <= sampling_i(3 downto 2);
end if;
end process;
 
 
process(Clk)
begin
if rising_edge(Clk) then
eoi <= eoi_D;
eoi_hold <= eoi_hold_D;
context_out <= '0' & '0' & context_out(1 downto 0);
if counter_out=counter_out_hold and ce_out='1' then
context_out(3) <= eoi;
end if;
 
if(ce_in='1') then
sampling_in <= sampling_in_D;
context_in <= context_in_D;
end if;
if do_copy='1' then
sampling_out <= sampling_in;
context_out(2 downto 0) <= context_in(2 downto 0);
end if;
 
if reset_i='1' then
context_out <= (others=>'0');
context_in <= (others=>'0');
eoi <='0';
eoi_hold <='0';
sampling_out <= "00";
sampling_in <= "00";
end if;
 
end if;
end process;
 
 
 
 
 
-------------------------------------------------------------------------
-- shift in
 
ce_in <= datavalid_i and not stop_in;
 
process(counter_in_hold, stop_in, counter_in)
begin
if counter_in = counter_in_hold then
stop_in_D <= '1';
elsif do_copy ='1' then
stop_in_D <= '0';
else
stop_in_D <= stop_in;
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
if reset_i='1' or do_copy ='1' then
counter_in <= (others=>'0');
stop_in <= '0';
elsif ce_in='1' then
counter_in <= counter_in+1;
stop_in <= stop_in_D;
end if;
end if;
end process;
-------------------------------------------------------------------------
 
 
-------------------------------------------------------------------------
-- shift out
ce_out <= ready_i and not stop_out and not do_copy;
 
process(counter_out_hold, do_copy, stop_out, counter_out)
begin
if counter_out = counter_out_hold then
stop_out_D <= '1';
elsif do_copy ='1' then
stop_out_D <= '0';
else
stop_out_D <= stop_out;
end if;
end process;
 
process(counter_out, do_copy, ready_i, stop_out)
begin
counter_out_D <= counter_out;
if ready_i='1' and stop_out='0' then
counter_out_D <= counter_out+1;
end if;
 
if (do_copy='1') then
counter_out_D <=(others=>'0');
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
stop_out <= stop_out_D;
if reset_i='1' then
counter_out <= (others=>'1');
stop_out <= '1';
elsif ce_out='1' or do_copy='1' then
counter_out <= counter_out_D;
end if;
end if;
end process;
 
-------------------------------------------------------------------------
 
end IMP;
/myipif/hdl/vhdl/jpeg.vhd
0,0 → 1,846
--------------------------------------------------------------------------------
-- TODO
-- * register all output signals
-- * ??? delay input_fifo_valid by one cycle to match data
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg is
port(
Clk : in std_logic;
data_i : in std_logic_vector(31 downto 0);
reset_i : in std_logic;
-- Indicates the detection of an eoi marker at the input side
-- of the pipeline. This is used to handle the input stream.
eoi_o : out std_logic;
 
-- The Huffman- and the header-component may run in an error-state
-- on invalid input data.
error_o : out std_logic;
 
-- data and context at the output side of the pipeline
context_o : out std_logic_vector (3 downto 0);
red_o : out STD_LOGIC_VECTOR (7 downto 0);
green_o : out STD_LOGIC_VECTOR (7 downto 0);
blue_o : out STD_LOGIC_VECTOR (7 downto 0);
width_o : out std_logic_vector(15 downto 0);
height_o : out std_logic_vector(15 downto 0);
sampling_o : out std_logic_vector( 1 downto 0);
 
-- -- debug
-- LEDs : out std_logic_vector(3 downto 0);
-- BUTTONs : in std_logic_vector(4 downto 0); -- 0:left, 1:right, 2:up, 3:down, 4:center
-- SWITCHEs : in std_logic_vector(3 downto 0);
-- -- chipscope-debugging
-- chipscope_o : out std_logic_vector(127 downto 0);
 
-- flow controll
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end entity jpeg;
 
 
 
 
 
architecture IMP of jpeg is
 
-- **********************************************************************************************
-- * Components
-- **********************************************************************************************
 
------------------------------------------------------------
-- FIFO to buffer the input data
------------------------------------------------------------
component jpeg_input_fifo
port (
din: IN std_logic_VECTOR(31 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
end component;
------------------------------------------------------------
 
 
------------------------------------------------------------
-- Replaces "FF00" with "FF" and filters out other occurances
-- of "FF", detects eoi markers
------------------------------------------------------------
component jpeg_check_FF is
port(
Clk : in std_logic;
reset_i : in std_logic;
header_valid_i : in std_logic;
header_select_i: in std_logic;
eoi_o : out std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
-- bit occupancy
-- 0: header_valid
-- 1: header_select
-- 2: end of block
-- 3: end of image
context_o : out std_logic_vector(3 downto 0);
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg_check_FF;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Fifo between checkff and huffman
--------------------------------------------------------------
component jpeg_checkff_fifo
port (
din: IN std_logic_VECTOR(11 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(11 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic
);
end component;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Huffman decoder.
--------------------------------------------------------------
component jpeg_huffman is
port(
Clk : in std_logic;
reset_i : in std_logic;
error_o : out std_logic;
header_select_i : in std_logic;
ht_symbols_wea_i : in std_logic;
ht_tables_wea_i : in std_logic;
ht_select_i : in std_logic_vector(2 downto 0); -- bit 2: dc (low) or ac (high), bit 1 and 0: table-nr.
ht_tables_address_i : in std_logic_vector(7 downto 0); -- address in bram: ht_select_o & ht_tables_address_o
ht_nr_of_symbols_address_i : in std_logic_vector(3 downto 0); -- address in distrib-ram: ht_select_o & ht_nr_of_symbols_address_o
ht_data_i : in std_logic_vector(7 downto 0);
context_i : in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(7 downto 0);
context_o : out std_logic_vector(3 downto 0);
data_o : out std_logic_vector(15 downto 0);
 
-- header data
comp1_huff_dc_i : in std_logic_vector(3 downto 0);
comp2_huff_dc_i : in std_logic_vector(3 downto 0);
comp3_huff_dc_i : in std_logic_vector(3 downto 0);
comp1_huff_ac_i : in std_logic_vector(3 downto 0);
comp2_huff_ac_i : in std_logic_vector(3 downto 0);
comp3_huff_ac_i : in std_logic_vector(3 downto 0);
sampling_i : in std_logic_vector(3 downto 0); -- "00"->gray, "01"->4:2:0, "10"->4:2:2, "11"->4:4:4
 
-- flow control
-- datavalid signal valid data in this cycle
-- ready signals "I am ready in NEXT cycle"
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg_huffman;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Dequantization
--------------------------------------------------------------
component jpeg_dequantize is
port(
Clk : in std_logic;
reset_i : in std_logic;
 
context_i : in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(11 downto 0);
context_o : out std_logic_vector(3 downto 0);
data_o : out std_logic_vector(11 downto 0);
-- header data
header_select_i : in std_logic;
sampling_i : in std_logic_vector(3 downto 0);
qt_wea_i : in std_logic;
qt_select_i : in std_logic_vector(1 downto 0);
qt_data_i : in std_logic_vector(7 downto 0);
comp1_qt_number_i : in std_logic_vector(1 downto 0);
comp2_qt_number_i : in std_logic_vector(1 downto 0);
comp3_qt_number_i : in std_logic_vector(1 downto 0);
 
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg_dequantize;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Address-maping to revert the ZigZag-Order
--------------------------------------------------------------
component jpeg_dezigzag is
port(
Clk : in std_logic;
context_i: in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(11 downto 0);
reset_i : in std_logic;
context_o: out std_logic_vector(3 downto 0);
data_o : out std_logic_vector(11 downto 0);
 
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg_dezigzag;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Inverse Discrete Cosine Transformation
-- Core provided by Xilinx, with some additional logic
-- for reverse flow control
--------------------------------------------------------------
component jpeg_idct is
port(
Clk : in std_logic;
reset_i : in std_logic;
context_i : in std_logic_vector( 3 downto 0);
data_i : in std_logic_vector(11 downto 0);
context_o : out std_logic_vector( 3 downto 0);
data_o : out std_logic_vector( 8 downto 0);
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg_idct;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Upsampling
--------------------------------------------------------------
component jpeg_upsampling is
port(
Clk : in std_logic;
reset_i : in std_logic;
context_i : in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(8 downto 0);
sampling_i : in std_logic_vector(3 downto 0);
context_o : out std_logic_vector(3 downto 0);
Y_o : out std_logic_vector(8 downto 0);
Cb_o : out std_logic_vector(8 downto 0);
Cr_o : out std_logic_vector(8 downto 0);
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg_upsampling;
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Color Transformation
--------------------------------------------------------------
component jpeg_YCbCr2RGB is
port(
Clk : in std_logic;
reset_i : in std_logic;
context_i : in std_logic_vector(3 downto 0);
Y_i : in std_logic_vector(8 downto 0);
Cb_i : in std_logic_vector(8 downto 0);
Cr_i : in std_logic_vector(8 downto 0);
context_o : out std_logic_vector(3 downto 0);
R_o : out std_logic_vector(7 downto 0);
G_o : out std_logic_vector(7 downto 0);
B_o : out std_logic_vector(7 downto 0);
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg_YCbCr2RGB;
--------------------------------------------------------------
 
 
------------------------------------------------------------
-- This one first reads out header information,
-- then provides header information
------------------------------------------------------------
component jpeg_header is
port(
Clk : in std_logic;
data_i : in std_logic_vector(7 downto 0);
datavalid_i : in std_logic;
reset_i : in std_logic;
eoi_i : in std_logic;
header_valid_o : out std_logic;
header_select_o: out std_logic;
header_error_o : out std_logic;
-- initialize the huffmann tables located in the huffmann-decoder entity
ht_symbols_wea_o : out std_logic;
ht_tables_wea_o : out std_logic;
ht_select_o : out std_logic_vector(2 downto 0); -- bit 2: dc (low) or ac (high), bit 1 and 0: table-nr.
ht_tables_address_o : out std_logic_vector(7 downto 0); -- address in bram: ht_select_o & ht_tables_address_o
ht_nr_of_symbols_address_o : out std_logic_vector(3 downto 0); -- address in distrib-ram: ht_select_o & ht_nr_of_symbols_address_o
ht_data_o : out std_logic_vector(7 downto 0);
-- initialize the quantization tables located in the dequantize entity
qt_wea_o : out std_logic;
qt_select_o : out std_logic_vector(1 downto 0);
qt_data_o : out std_logic_vector(7 downto 0);
-- sos-field
comp1_huff_dc_o : out std_logic_vector(3 downto 0);
comp2_huff_dc_o : out std_logic_vector(3 downto 0);
comp3_huff_dc_o : out std_logic_vector(3 downto 0);
comp1_huff_ac_o : out std_logic_vector(3 downto 0);
comp2_huff_ac_o : out std_logic_vector(3 downto 0);
comp3_huff_ac_o : out std_logic_vector(3 downto 0);
--sof-field
height_o : out std_logic_vector(15 downto 0);
width_o : out std_logic_vector(15 downto 0);
sampling_o : out std_logic_vector(1 downto 0); -- "00"->gray, "01"->4:2:0, "10"->4:2:2, "11"->4:4:4
comp1_qt_number_o : out std_logic_vector(0 downto 0);
comp2_qt_number_o : out std_logic_vector(0 downto 0);
comp3_qt_number_o : out std_logic_vector(0 downto 0)
);
end component jpeg_header;
--------------------------------------------------------------
 
 
 
 
-- **********************************************************************************************
-- * Signals
-- **********************************************************************************************
signal ready, ready_D : std_logic :='0';
signal reset, error : std_logic :='0';
 
-- double width to have old and new values present in pipline in case of picture change
signal sampling, sampling_D : std_logic_vector(3 downto 0) :=(others=>'0');
signal width, width_D, height, height_D : std_logic_vector(31 downto 0) :=(others=>'0');
signal comp1_qt_number, comp1_qt_number_D : std_logic_vector(1 downto 0) := (others=>'0');
signal comp2_qt_number, comp2_qt_number_D : std_logic_vector(1 downto 0) := (others=>'0');
signal comp3_qt_number, comp3_qt_number_D : std_logic_vector(1 downto 0) := (others=>'0');
signal sampling_out : std_logic_vector(1 downto 0) :=(others=>'0');
signal width_out, height_out : std_logic_vector(15 downto 0) :=(others=>'0');
 
-- Signals to connect the pipeline components. The signals are named after the component
-- from which it originates.
signal check_FF_ready : std_logic :='0';
signal check_FF_data : std_logic_vector(7 downto 0) := (others=>'0');
signal check_FF_datavalid : std_logic :='0';
signal check_FF_eoi : std_logic :='0';
signal check_FF_context : std_logic_vector(3 downto 0) := (others=>'0');
 
signal input_fifo_data : std_logic_vector(7 downto 0) := (others=>'0');
signal input_fifo_datavalid, input_fifo_full, input_fifo_almost_full, input_fifo_empty, input_fifo_almost_empty : std_logic :='0';
signal input_fifo_rd_en, input_fifo_wr_en, input_fifo_reset : std_logic :='0';
 
signal checkff_fifo_data : std_logic_vector(11 downto 0) := (others=>'0');
signal checkff_fifo_datavalid, checkff_fifo_full, checkff_fifo_almost_full, checkff_fifo_empty, checkff_fifo_almost_empty : std_logic :='0';
signal checkff_fifo_ready : std_logic :='0';
signal huffman_error, huffman_ready, huffman_datavalid, huffman_eob : std_logic :='0';
signal huffman_address : std_logic_vector(5 downto 0) := (others=>'0');
signal huffman_data : std_logic_vector(15 downto 0) := (others=>'0');
signal huffman_context : std_logic_vector(3 downto 0) :=(others=>'0');
 
signal dezigzag_context : std_logic_vector(3 downto 0) :=(others=>'0');
signal dezigzag_data : std_logic_vector(11 downto 0) := (others=>'0');
signal dezigzag_datavalid, dezigzag_ready : std_logic :='0';
 
signal dequantize_datavalid, dequantize_ready : std_logic :='0';
signal dequantize_context : std_logic_vector(3 downto 0) :=(others=>'0');
signal dequantize_data : std_logic_vector(11 downto 0) := (others=>'0');
signal idct_datavalid, idct_ready : std_logic :='0';
signal idct_context : std_logic_vector(3 downto 0) :=(others=>'0');
signal idct_data : std_logic_vector(8 downto 0) := (others=>'0');
signal upsampling_datavalid, upsampling_ready : std_logic :='0';
signal upsampling_context : std_logic_vector(3 downto 0) :=(others=>'0');
signal upsampling_Y, upsampling_Cb, upsampling_Cr : std_logic_vector(8 downto 0) := (others=>'0');
signal YCbCr2RGB_datavalid, YCbCr2RGB_ready : std_logic :='0';
signal YCbCr2RGB_context : std_logic_vector(3 downto 0) :=(others=>'0');
signal YCbCr2RGB_R, YCbCr2RGB_G, YCbCr2RGB_B : std_logic_vector(7 downto 0) := (others=>'0');
 
signal vga_datavalid, vga_ready, vga_error : std_logic :='0';
 
-- header: info
signal header_select, header_valid, header_error : std_logic :='0';
-- huffman tables
signal header_ht_symbols_wea, header_ht_tables_wea :std_logic :='0';
signal header_ht_select : std_logic_vector(2 downto 0) := (others=>'0');
signal header_ht_tables_address : std_logic_vector(7 downto 0) := (others=>'0');
signal header_ht_nr_of_symbols_address : std_logic_vector(3 downto 0) := (others=>'0');
signal header_ht_data : std_logic_vector(7 downto 0) := (others=>'0');
-- quantization tables
signal header_qt_wea : std_logic := '0';
signal header_qt_select : std_logic_vector(1 downto 0) := (others=>'0');
signal header_qt_data : std_logic_vector(7 downto 0) := (others=>'0');
-- header: sos-field
signal header_comp1_huff_dc : std_logic_vector(3 downto 0) := (others=>'0');
signal header_comp2_huff_dc : std_logic_vector(3 downto 0) := (others=>'0');
signal header_comp3_huff_dc : std_logic_vector(3 downto 0) := (others=>'0');
signal header_comp1_huff_ac : std_logic_vector(3 downto 0) := (others=>'0');
signal header_comp2_huff_ac : std_logic_vector(3 downto 0) := (others=>'0');
signal header_comp3_huff_ac : std_logic_vector(3 downto 0) := (others=>'0');
--header: sof-field
signal header_height : std_logic_vector(15 downto 0) := (others=>'0');
signal header_width : std_logic_vector(15 downto 0) := (others=>'0');
signal header_sampling: std_logic_vector(1 downto 0) := (others=>'0');
signal header_comp1_qt_number : std_logic_vector(0 downto 0) := (others=>'0');
signal header_comp2_qt_number : std_logic_vector(0 downto 0) := (others=>'0');
signal header_comp3_qt_number : std_logic_vector(0 downto 0) := (others=>'0');
 
 
 
 
begin
 
 
 
-- **********************************************************************************************
-- * Debugging
-- **********************************************************************************************
--LEDs <= not header_error & not huffman_error & not vga_ready & not header_valid;
--chipscope_o <= data_i &
-- input_fifo_data & YCbCr2RGB_R & YCbCr2RGB_G & YCbCr2RGB_B &
-- datavalid_i & ready_i & YCbCr2RGB_datavalid & ready & header_sampling & check_FF_eoi &
-- (header_error or huffman_error) & check_FF_data & checkff_fifo_data(7 downto 0) &
-- huffman_data(7 downto 0) & header_width & header_height;
-- **********************************************************************************************
 
 
 
--------------------------------------------------------------
-- store some values from header
--------------------------------------------------------------
process( header_select, header_sampling, sampling, width, height, header_width, header_height,
header_comp1_qt_number, header_comp2_qt_number, header_comp3_qt_number,
comp1_qt_number, comp2_qt_number, comp3_qt_number)
begin
sampling_D <= sampling;
comp1_qt_number_D <= comp1_qt_number;
comp2_qt_number_D <= comp2_qt_number;
comp3_qt_number_D <= comp3_qt_number;
width_D <= width;
height_D <= height;
if(header_select='0') then
sampling_D(1 downto 0) <= header_sampling;
comp1_qt_number_D(0 downto 0) <= header_comp1_qt_number;
comp2_qt_number_D(0 downto 0) <= header_comp2_qt_number;
comp3_qt_number_D(0 downto 0) <= header_comp3_qt_number;
width_D(15 downto 0) <= header_width;
height_D(15 downto 0) <= header_height;
else
sampling_D(3 downto 2) <= header_sampling;
comp1_qt_number_D(1 downto 1) <= header_comp1_qt_number;
comp2_qt_number_D(1 downto 1) <= header_comp2_qt_number;
comp3_qt_number_D(1 downto 1) <= header_comp3_qt_number;
width_D(31 downto 16) <= header_width;
height_D(31 downto 16) <= header_height;
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
if reset='1' then
sampling <= (others=>'0');
comp1_qt_number <= (others=>'0');
comp2_qt_number <= (others=>'0');
comp3_qt_number <= (others=>'0');
width <= (others=>'0');
height <= (others=>'0');
else
sampling <= sampling_D;
comp1_qt_number <= comp1_qt_number_D;
comp2_qt_number <= comp2_qt_number_D;
comp3_qt_number <= comp3_qt_number_D;
width <= width_D;
height <= height_D;
end if;
end if;
end process;
--------------------------------------------------------------
 
 
 
 
-- **********************************************************************************************
-- * Port Maps
-- **********************************************************************************************
 
--------------------------------------------------------------
-- FIFO to buffer the input data
--------------------------------------------------------------
jpeg_input_fifo_p:jpeg_input_fifo
port map (
din => data_i,
rd_clk => Clk,
rd_en => input_fifo_rd_en,
rst => input_fifo_reset,
wr_clk => Clk,
wr_en => input_fifo_wr_en,
almost_full => input_fifo_almost_full,
dout => input_fifo_data,
empty => input_fifo_empty,
full => input_fifo_full,
valid => input_fifo_datavalid
);
input_fifo_reset <= reset or check_FF_eoi;
--------------------------------------------------------------
input_fifo_rd_en <= check_FF_ready;
input_fifo_wr_en <= datavalid_i and ready;
 
 
--------------------------------------------------------------
-- Replaces "FF00" with "FF" and filters out other occurances
-- of "FF"
--------------------------------------------------------------
jpeg_check_FF_p:jpeg_check_FF
port map(
Clk => Clk,
reset_i => reset,
eoi_o => check_FF_eoi,
header_valid_i => header_valid,
header_select_i=> header_select,
data_i => input_fifo_data,
data_o => check_FF_data,
context_o => check_FF_context,
datavalid_i => input_fifo_datavalid,
datavalid_o => check_FF_datavalid,
ready_i => checkff_fifo_ready,
ready_o => check_FF_ready
);
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Fifo between checkff and huffman
--------------------------------------------------------------
jpeg_checkff_fifo_p:jpeg_checkff_fifo
port map (
din(11 downto 8) => check_ff_context,
din(7 downto 0) => check_FF_data,
rd_clk => Clk,
rd_en => huffman_ready,
rst => reset,
wr_clk => Clk,
wr_en => check_FF_datavalid,
almost_empty => checkff_fifo_almost_empty,
almost_full => checkff_fifo_almost_full,
dout => checkff_fifo_data,
empty => checkff_fifo_empty,
full => checkff_fifo_full,
valid => checkff_fifo_datavalid
);
 
--------------------------------------------------------------
checkff_fifo_ready <= not (checkff_fifo_full);
 
 
--------------------------------------------------------------
-- Huffman decoder
--------------------------------------------------------------
jpeg_huffman_p:jpeg_huffman
port map (
Clk => Clk,
reset_i => reset,
header_select_i => header_select,
error_o => huffman_error,
ht_symbols_wea_i => header_ht_symbols_wea,
ht_tables_wea_i => header_ht_tables_wea,
ht_select_i => header_ht_select,
ht_tables_address_i => header_ht_tables_address,
ht_nr_of_symbols_address_i => header_ht_nr_of_symbols_address,
ht_data_i => header_ht_data,
context_i => checkff_fifo_data(11 downto 8),
data_i => checkff_fifo_data(7 downto 0),
context_o => huffman_context,
data_o => huffman_data,
comp1_huff_dc_i => header_comp1_huff_dc,
comp2_huff_dc_i => header_comp2_huff_dc,
comp3_huff_dc_i => header_comp3_huff_dc,
comp1_huff_ac_i => header_comp1_huff_ac,
comp2_huff_ac_i => header_comp2_huff_ac,
comp3_huff_ac_i => header_comp3_huff_ac,
sampling_i => sampling,
datavalid_i => checkff_fifo_datavalid,
datavalid_o => huffman_datavalid,
ready_i => dequantize_ready,
ready_o => huffman_ready
);
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Dequantization
--------------------------------------------------------------
jpeg_dequantize_p:jpeg_dequantize
port map (
Clk => Clk,
reset_i => reset,
header_select_i=> header_select,
qt_wea_i => header_qt_wea,
qt_select_i => header_qt_select,
qt_data_i => header_qt_data,
sampling_i => sampling,
comp1_qt_number_i => comp1_qt_number,
comp2_qt_number_i => comp2_qt_number,
comp3_qt_number_i => comp3_qt_number,
context_i => huffman_context,
data_i(11) => huffman_data(15), -- handle negative values (TODO better)
data_i(10 downto 0) => huffman_data(10 downto 0),
context_o => dequantize_context,
data_o => dequantize_data,
datavalid_i => huffman_datavalid, -- TODO
datavalid_o => dequantize_datavalid,
ready_i => dezigzag_ready,
ready_o => dequantize_ready -- TODO
);
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Address-maping to revert the ZigZag-Order
--------------------------------------------------------------
jpeg_dezigzag_p:jpeg_dezigzag
port map (
Clk => Clk,
context_i => dequantize_context,
data_i => dequantize_data,
reset_i => reset,
data_o => dezigzag_data,
context_o => dezigzag_context,
datavalid_i => dequantize_datavalid,
datavalid_o => dezigzag_datavalid,
ready_i => idct_ready,
ready_o => dezigzag_ready
);
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- IDCT
--------------------------------------------------------------
jpeg_idct_p:jpeg_idct
port map (
Clk => Clk,
reset_i => reset,
context_i => dezigzag_context,
data_i => dezigzag_data,
context_o => idct_context,
data_o => idct_data,
datavalid_i => dezigzag_datavalid,
datavalid_o => idct_datavalid,
ready_i => upsampling_ready,
ready_o => idct_ready
);
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- Upsampling
--------------------------------------------------------------
jpeg_upsampling_p:jpeg_upsampling
port map (
Clk => Clk,
reset_i => reset,
context_i => idct_context,
data_i => idct_data,
sampling_i => sampling,
context_o => upsampling_context,
Y_o => upsampling_Y,
Cb_o => upsampling_Cb,
Cr_o => upsampling_Cr,
datavalid_i => idct_datavalid,
datavalid_o => upsampling_datavalid,
ready_i => YCbCr2RGB_ready,
ready_o => upsampling_ready
);
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- YCbCr2RGB
--------------------------------------------------------------
jpeg_YCbCr2RGB_p:jpeg_YCbCr2RGB
port map (
Clk => Clk,
reset_i => reset,
context_i => upsampling_context,
Y_i => upsampling_Y,
Cb_i => upsampling_Cb,
Cr_i => upsampling_Cr,
context_o => YCbCr2RGB_context,
R_o => YCbCr2RGB_R,
G_o => YCbCr2RGB_G,
B_o => YCbCr2RGB_B,
datavalid_i => upsampling_datavalid,
datavalid_o => YCbCr2RGB_datavalid,
ready_i => vga_ready,
ready_o => YCbCr2RGB_ready
);
--------------------------------------------------------------
vga_ready <= ready_i;
 
 
------------------------------------------------------------
-- This one first reads out header information,
-- then provides header information
------------------------------------------------------------
jpeg_header_p:jpeg_header
port map (
Clk => Clk, -- 1 bit
data_i => input_fifo_data, -- 8 bit
datavalid_i => input_fifo_datavalid, -- 1 bit
reset_i => reset, -- 1 bit
eoi_i => check_FF_eoi, -- 1 ibt
 
header_valid_o => header_valid, -- 1 bit
header_select_o=> header_select, -- 1 bit
header_error_o => header_error, -- 1 bit
-- initialize the huffmann tables (located in the huffmann-decoder entity)
ht_symbols_wea_o => header_ht_symbols_wea,
ht_tables_wea_o => header_ht_tables_wea,
ht_select_o => header_ht_select,
ht_tables_address_o => header_ht_tables_address,
ht_nr_of_symbols_address_o => header_ht_nr_of_symbols_address,
ht_data_o => header_ht_data,
 
-- initialize the quantization tables (located in the dequantisation entity)
qt_wea_o => header_qt_wea,
qt_select_o => header_qt_select,
qt_data_o => header_qt_data,
 
-- sos-field
comp1_huff_dc_o => header_comp1_huff_dc,
comp2_huff_dc_o => header_comp2_huff_dc,
comp3_huff_dc_o => header_comp3_huff_dc,
comp1_huff_ac_o => header_comp1_huff_ac,
comp2_huff_ac_o => header_comp2_huff_ac,
comp3_huff_ac_o => header_comp3_huff_ac,
--sof-field
height_o => header_height,
width_o => header_width,
sampling_o => header_sampling,
comp1_qt_number_o => header_comp1_qt_number,
comp2_qt_number_o => header_comp2_qt_number,
comp3_qt_number_o => header_comp3_qt_number
);
------------------------------------------------------------
 
 
 
-- **********************************************************************************************
-- * Wires
-- **********************************************************************************************
eoi_o <= check_FF_eoi; -- for controlling input data (backwards in pipeline)
context_o<= YCbCr2RGB_context; -- context of output data
 
reset <= reset_i;
error_o <= error;
error <= header_error or huffman_error;
 
red_o <= YCbCr2RGB_R;
green_o <= YCbCr2RGB_G;
blue_o <= YCbCr2RGB_B;
 
-- connect the valid context set to the outside
sampling_o <= sampling_out;
width_o <= width_out;
height_o <= height_out;
process(YCbCr2RGB_context, sampling, width, height)
begin
if YCbCr2RGB_context(1) ='0' then
sampling_out <= sampling(1 downto 0);
width_out <= width(15 downto 0);
height_out <= height(15 downto 0);
else
sampling_out <= sampling(3 downto 2);
width_out <= width(31 downto 16);
height_out <= height(31 downto 16);
end if;
end process;
 
 
-- connect pipeline flowcontroll to the outside
datavalid_o <= YCbCr2RGB_datavalid;
ready_o <= ready and not error;
 
 
-- **********************************************************************************************
-- * Processes
-- **********************************************************************************************
 
-- refill the input-fifo only after it has run empty -> bus is free the most time
process(input_fifo_almost_full, input_fifo_empty)
begin
ready_D <= ready;
if input_fifo_almost_full='1' then
ready_D <= '0';
elsif input_fifo_empty ='1' then
ready_D <= '1';
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
if reset='1' or check_FF_eoi='1' then
ready <= '0';
else
ready <= ready_D;
end if;
end if;
end process;
 
end IMP;
/myipif/hdl/vhdl/jpeg_idct.vhd
0,0 → 1,214
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg_idct is
port
( Clk : in std_logic;
reset_i : in std_logic;
 
context_i : in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(11 downto 0);
context_o : out std_logic_vector(3 downto 0);
data_o : out std_logic_vector(8 downto 0);
 
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end entity jpeg_idct;
 
 
 
 
 
architecture IMP of jpeg_idct is
 
--------------------------------------------------------------
-- IDCT-Core
--------------------------------------------------------------
component jpeg_idct_core_12
port (
ND: IN std_logic;
RDY: OUT std_logic;
RFD: OUT std_logic;
CLK: IN std_logic;
RST: IN std_logic;
DIN: IN std_logic_VECTOR(11 downto 0);
DOUT: OUT std_logic_VECTOR(8 downto 0));
end component;
--------------------------------------------------------------
 
signal datavalid : std_logic :='0';
signal ready, last_ready : std_logic :='0';
signal block_counter : std_logic_vector(1 downto 0) :=(others=>'0');
signal out_counter, out_counter_D : std_logic_vector(7 downto 0) :=(others=>'0');
signal in_counter, in_counter_D : std_logic_vector(7 downto 0) :=(others=>'0');
signal eoi, eoi_D : std_logic_vector(3 downto 0) :=(others=>'0');
signal eoi_out, eoi_out_D : std_logic :='0';
signal header_select, header_select_D : std_logic_vector(3 downto 0) :=(others=>'0');
signal header_select_out, header_select_out_D : std_logic :='0';
signal context : std_logic_vector(3 downto 0) := (others=>'0');
 
begin
--------------------------------------------------------------
-- dataflow
--------------------------------------------------------------
datavalid_o <= datavalid;
ready_o <= ready and last_ready and ready_i;
process(Clk)
begin
if rising_edge(Clk) then
last_ready <= ready;
end if;
end process;
--------------------------------------------------------------
 
 
 
 
--------------------------------------------------------------
-- context (esp. eoi)
--------------------------------------------------------------
context_o <= context;
 
-- count to see when block is finished
out_counter_D <= out_counter +1;
in_counter_D <= in_counter +1;
process(Clk)
begin
if rising_edge(Clk) then
if reset_i='1' then
out_counter <= (others=>'0');
elsif(datavalid='1') then
out_counter <= out_counter_D;
end if;
if reset_i='1' then
in_counter <= (others=>'0');
elsif(datavalid_i='1' and ready='1') then
in_counter <= in_counter_D;
end if;
 
end if;
end process;
 
-- remember header_select to write while block is shifted out
process(context_i, in_counter, out_counter, header_select)
begin
header_select_D <= header_select;
 
if in_counter(5 downto 0) = "111101" then -- just a random counter_value less than "1111111" and greater than "000000"
case in_counter(7 downto 6) is
when "00" =>
header_select_D(0) <= context_i(1);
when "01" =>
header_select_D(1) <= context_i(1);
when "10" =>
header_select_D(2) <= context_i(1);
when others =>
header_select_D(3) <= context_i(1);
end case;
end if;
case out_counter(7 downto 6) is
when "00" =>
header_select_out_D <= header_select(0);
when "01" =>
header_select_out_D <= header_select(1);
when "10" =>
header_select_out_D <= header_select(2);
when others =>
header_select_out_D <= header_select(3);
end case;
 
end process;
-- remember received eoi to write after block is finished
process(eoi, context_i, in_counter, out_counter)
begin
eoi_D <= eoi;
eoi_out_D <='0';
if context_i(3)='1' then
case in_counter(7 downto 6) is
when "00" =>
eoi_D(0) <= '1';
when "01" =>
eoi_D(1) <= '1';
when "10" =>
eoi_D(2) <= '1';
when others =>
eoi_D(3) <= '1';
end case;
elsif(out_counter(5 downto 0)="000000") then
case out_counter(7 downto 6) is
when "00" =>
eoi_D(0) <= '0';
eoi_out_D <= eoi(0);
when "01" =>
eoi_D(1) <= '0';
eoi_out_D <= eoi(1);
when "10" =>
eoi_D(2) <= '0';
eoi_out_D <= eoi(2);
when others =>
eoi_D(3) <= '0';
eoi_out_D <= eoi(3);
end case;
end if;
 
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
 
eoi <= eoi_D;
eoi_out <= eoi_out_D;
header_select <= header_select_D;
header_select_out <= header_select_out_D;
context <= '0' & context(2 downto 0);
 
if reset_i='1' then
eoi <= "0000";
eoi_out <= '0';
context <= (others=>'0');
header_select <= (others=>'0');
header_select_out <= '0';
elsif(out_counter(5 downto 0)="000000") then
context <= eoi_out & '0' & header_select_out & '0';
end if;
 
end if;
end process;
 
--------------------------------------------------------------
 
 
--------------------------------------------------------------
-- IDCT-Core
--------------------------------------------------------------
jpeg_idct_core_12_p : jpeg_idct_core_12
port map (
ND => datavalid_i,
RDY => datavalid,
RFD => ready,
CLK => CLK,
RST => reset_i,
DIN => data_i,
DOUT => data_o);
--------------------------------------------------------------
end IMP;
/myipif/hdl/vhdl/jpeg_huffman.vhd
0,0 → 1,880
----------------------------------------------------------------
-- TODO:
-- * select right Huffman-table according to compX_huff_Xc
-- * store all tables in one bram (atm ht_nr_of_symbols are stored in distr.ram
-- * continue to decode while write zrl and eob zeroes are written
----------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg_huffman is
port
( Clk : in std_logic;
reset_i : in std_logic;
header_select_i: in std_logic;
error_o : out std_logic;
-- to initialize the bram
ht_symbols_wea_i : in std_logic;
ht_tables_wea_i : in std_logic;
ht_select_i : in std_logic_vector(2 downto 0); -- bit 2: dc (low) or ac (high), bit 1 and 0: table-nr.
ht_tables_address_i : in std_logic_vector(7 downto 0); -- address in bram: ht_select_i & ht_tables_address_i
ht_nr_of_symbols_address_i : in std_logic_vector(3 downto 0); -- address in distrib-ram: ht_select_i & ht_nr_of_symbols_address_i
ht_data_i : in std_logic_vector(7 downto 0);
context_i : in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(7 downto 0);
context_o : out std_logic_vector(3 downto 0);
data_o : out std_logic_vector(15 downto 0);
 
-- header data
comp1_huff_dc_i : in std_logic_vector(3 downto 0);
comp2_huff_dc_i : in std_logic_vector(3 downto 0);
comp3_huff_dc_i : in std_logic_vector(3 downto 0);
comp1_huff_ac_i : in std_logic_vector(3 downto 0);
comp2_huff_ac_i : in std_logic_vector(3 downto 0);
comp3_huff_ac_i : in std_logic_vector(3 downto 0);
sampling_i : in std_logic_vector(3 downto 0); -- "00"->gray, "01"->4:2:0, "10"->4:2:2, "11"->4:4:4
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end entity jpeg_huffman;
 
 
 
 
 
architecture IMP of jpeg_huffman is
 
 
-- store the number of huffman codes with length n (cf. jpeg-standard)
component jpeg_ht_nr_of_symbols
port (
A : IN std_logic_VECTOR(7 downto 0); -- n = A+1
CLK: IN std_logic;
D : IN std_logic_VECTOR(7 downto 0);
WE : IN std_logic;
DPRA: IN std_logic_VECTOR(7 downto 0);
DPO: OUT std_logic_VECTOR(7 downto 0);
SPO: OUT std_logic_VECTOR(7 downto 0));
end component;
 
 
-- store the values of the huffman codes
component jpeg_ht_tables
port (
clka : IN std_logic;
dina : IN std_logic_VECTOR(7 downto 0);
addra : IN std_logic_VECTOR(11 downto 0);
wea : IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(11 downto 0);
doutb : OUT std_logic_VECTOR(7 downto 0));
end component;
 
 
 
-- Shiftregister, used to read 8-bits from imput and
-- then provide it in the needed bit wise order
component jpeg_huffman_input_sr
port (
CLK : IN std_logic;
SDOUT : OUT std_logic;
P_LOAD: IN std_logic;
D : IN std_logic_VECTOR(7 downto 0);
CE : IN std_logic;
SCLR : IN std_logic);
end component;
 
 
 
 
 
signal err, err_D : std_logic :='0';
 
type states is (st_start1, st_start2, st_start3, st_get_code, st_check_code1, st_check_code2, st_write_zeros_zrl, st_write_zeros_eob, st_write_zeros, st_get_value1, st_get_value2);
signal state, state_D : states := st_start1;
 
-- flow controll
signal datavalid, datavalid_D : std_logic := '0';
signal ready, ready_D : std_logic := '0';
signal ce, ce_D : std_logic :='1';
signal reset_flowcontroll : std_logic :='1';
 
-- handle the "input shift register"
signal sr_load, sr_load_D, last_ready, last_ready_D, sr_ce, sr_init : std_logic :='0';
signal sr_empty : std_logic :='1';
signal sr_counter, sr_counter_D : std_logic_vector(2 downto 0) := (others=>'0');
 
-- final addresses
signal ht_tables_address_ram_rd : std_logic_vector(11 downto 0) := (others=>'0');
signal ht_tables_address_ram_wr : std_logic_vector(11 downto 0) := (others=>'0');
signal ht_nr_of_symbols_address_ram_rd : std_logic_vector(7 downto 0) := (others=>'0');
signal ht_nr_of_symbols_address_ram_wr : std_logic_vector(7 downto 0) := (others=>'0');
 
-- data from the RAM
signal data_symbols, data_tables : std_logic_vector(7 downto 0) := (others=>'0');
 
-- signals to work with
signal reset : std_logic :='0';
signal context, context_D : std_logic_vector(3 downto 0) :=(others=>'0');
signal data, data_D : std_logic_vector(15 downto 0) :=(others=>'0');
signal get_bit, get_bit_D : std_logic :='0';
signal dataready, dataready_D : std_logic :='0';
signal data_intern : std_logic_vector(0 downto 0) := (others=>'0');
signal code_read, code_read_D : std_logic_vector(15 downto 0) := (others=>'0');
signal code_build, code_build_D : std_logic_vector(15 downto 0) := (others=>'0');
signal symbols, symbols_D : std_logic_vector(7 downto 0) := (others=>'0');
signal zeros_counter, zeros_counter_D : std_logic_vector(5 downto 0) := (others=>'0');
 
-- internal address calculation
signal ht_select, ht_select_D : std_logic_vector(2 downto 0) := (others=>'0');
signal ht_tables_address, ht_tables_address_D : std_logic_vector(7 downto 0) := (others=>'0');
signal ht_nr_of_symbols_address, ht_nr_of_symbols_address_D : std_logic_vector(3 downto 0) := (others=>'0');
 
-- to choose between dc and ac table, also used as address to write data to -- TODO
signal ac_dc_counter, ac_dc_counter_D : std_logic_vector(5 downto 0) := (others=>'0');
 
-- to do the sampling
signal sampling_counter, sampling_counter_D : std_logic_vector(2 downto 0) := (others=>'0');
 
-- sign
signal is_negative, is_negative_D : std_logic := '0';
 
-- Context
signal eob, eob_D : std_logic :='0';
signal eoi, last_eoi : std_logic :='0';
signal header_valid_out : std_logic := '0';
signal header_select_out : std_logic := '0';
signal header_select : std_logic := '0';
signal sampling, sampling_D : std_logic_vector(1 downto 0) :=(others=>'0');
 
-- remember the dc-coeffizient
signal last_dc , last_dc_D, last_dc_reg : std_logic_vector(15 downto 0) := (others=>'0');
signal last_dc_Y , last_dc_Cb, last_dc_Cr : std_logic_vector(15 downto 0) := (others=>'0');
signal last_dc_Y_ce , last_dc_Cb_ce, last_dc_Cr_ce : std_logic := '0';
signal last_dc_select, last_dc_select_D : std_logic_vector(1 downto 0) := (others=>'0');
 
 
 
begin
 
 
 
--***********************************************************************
-- portmaps
--***********************************************************************
ht_nr_of_symbols : jpeg_ht_nr_of_symbols
port map (
A => ht_nr_of_symbols_address_ram_wr,
CLK => Clk,
D => ht_data_i,
WE => ht_symbols_wea_i,
DPRA => ht_nr_of_symbols_address_ram_rd,
DPO => data_symbols
);
ht_table : jpeg_ht_tables
port map (
clka => Clk,
dina => ht_data_i,
addra => ht_tables_address_ram_wr,
wea(0) => ht_tables_wea_i,
clkb => Clk,
addrb => ht_tables_address_ram_rd,
doutb => data_tables
);
 
jpeg_huffman_input_sr_p : jpeg_huffman_input_sr
port map (
CLK => Clk,
SDOUT => data_intern(0),
P_LOAD => sr_load,
D => data_i,
CE => sr_ce,
SCLR => reset); -- TODO: care about stuffed bits
sr_ce <= (get_bit and ce) or sr_init;
--***********************************************************************
 
 
 
 
 
 
 
 
 
--***********************************************************************
-- processes and wires
--***********************************************************************
 
 
-------------------------------------------------------------------------
-- connect signal to outside
-------------------------------------------------------------------------
ready_o <= ready;
error_o <= err;
data_o <= data;
 
reset <= reset_i or (eoi and not last_eoi);
process(Clk)
begin
if rising_edge(Clk) then
last_eoi <= eoi;
end if;
end process;
 
--------------------------------------------------
-- sampling
process(header_select, sampling_i)
begin
if (header_select='0') then
sampling_D <= sampling_i(1 downto 0);
else
sampling_D <= sampling_i(3 downto 2);
end if;
end process;
process(Clk)
begin
if(rising_edge(Clk)) then
if reset='1' then
sampling <= (others=>'0');
elsif(sr_ce='1') then
sampling <= sampling_D;
end if;
end if;
end process;
--------------------------------------------------
 
 
 
-- context_o <= eoi & eob & context_D(1 downto 0); -- This may cause problems :(
context_o <= eoi & eob & header_select_out & header_valid_out;
header_select <= context(1);
process(Clk)
begin
if rising_edge(Clk) then
if sr_ce = '1' then
eoi <= context(3);
header_select_out <= context(1);
header_valid_out <= context(0);
end if;
end if;
end process;
 
 
process(Clk)
begin
if rising_edge(Clk) then
if sr_ce = '1' and sr_load='1' then
context <= context_i;
end if;
end if;
end process;
 
process(code_read, last_dc, ac_dc_counter, is_negative, dataready)
begin
data_D <= (others=>'0');
last_dc_D <= last_dc;
if(ac_dc_counter = 1 and dataready ='1') then
if(is_negative='1') then
data_D <= last_dc - code_read;
last_dc_D <= last_dc - code_read;
else
data_D <= last_dc + code_read;
last_dc_D <= last_dc + code_read;
end if;
elsif(dataready='1') then
if(is_negative='1') then
data_D <= 0 - code_read;
else
data_D <= code_read;
end if;
end if;
end process;
 
-- last_dc_D handled later to do the right sampling-method
process(Clk)
begin
if rising_edge(Clk) then
if reset='1' then
data <= (others=>'0');
elsif ce='1' then
data <= data_D;
end if;
end if;
end process;
-------------------------------------------------------------------------
 
 
 
-------------------------------------------------------------------------
-- count the bits remaining in the shift register, refill it if neccessary
-------------------------------------------------------------------------
process(sr_ce, sr_counter, sr_load, datavalid_i)
begin
sr_counter_D <= sr_counter;
sr_load_D <= sr_load;
 
if (sr_ce='1') then
sr_counter_D <= sr_counter+1;
end if;
if (sr_counter="000" and sr_ce='1') then
sr_load_D <= '1';
end if;
if sr_load='1' and datavalid_i='1' and sr_ce='1' then
sr_load_D <='0';
end if;
 
ready_D <= sr_load and sr_ce and not last_ready;
last_ready_D <= (ready or last_ready) and sr_load; -- last_ready to prevent multiple loads on ce=0
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
sr_counter <= sr_counter;
sr_load <= sr_load;
sr_init <= '0';
ready <= ready_D;
last_ready <= last_ready_D;
sr_empty <= sr_empty;
 
if reset='1' then
sr_counter <= "000";
sr_load <= '0';
last_ready <= '0';
ready <= '0';
sr_empty <= '1';
elsif sr_empty='1' and datavalid_i='1' then
sr_counter <= "001";
sr_load <= '1';
sr_init <= '1';
sr_empty <= '0';
elsif ce='1' then
sr_load <= sr_load_D;
sr_counter <= sr_counter_D;
end if;
 
end if;
end process;
-------------------------------------------------------------------------
 
 
-------------------------------------------------------------------------
-- flowcontroll with reset
-------------------------------------------------------------------------
datavalid_o <= datavalid and not (reset_i or reset_flowcontroll);
ce <= datavalid_i and (ready_i or not datavalid) and not (reset_i or reset_flowcontroll);
datavalid_D <= (dataready or (datavalid and (not ready_i))) and not (reset_i or reset_flowcontroll);
 
process(Clk)
begin
if rising_edge(Clk) then
datavalid <= datavalid_D; -- or (eoi and not last_eoi);
reset_flowcontroll <= reset_i;
end if;
end process;
-------------------------------------------------------------------------
 
 
 
-------------------------------------------------------------------------
-- store and recall the right diff-value for the dc-components
-------------------------------------------------------------------------
process(last_dc_select, sampling_counter, sampling)
begin
last_dc_select_D <= last_dc_select;
 
case sampling is
 
---------------------------------------
-- gray
---------------------------------------
when "00" =>
last_dc_select_D <= "00";
 
---------------------------------------
-- 4:2:0
---------------------------------------
when "01" =>
case sampling_counter is
when "000"|"001"|"010"|"011" =>
last_dc_select_D <= "00";
when "100" =>
last_dc_select_D <= "01";
when "101" =>
last_dc_select_D <= "10";
when others =>
last_dc_select_D <= "11";
end case;
---------------------------------------
-- 4:2:2
---------------------------------------
when "10" =>
case sampling_counter is
when "000"|"001" =>
last_dc_select_D <= "00";
when "010" =>
last_dc_select_D <= "01";
when "011" =>
last_dc_select_D <= "10";
when others =>
last_dc_select_D <= "11";
end case;
---------------------------------------
-- 4:4:4
---------------------------------------
when others =>
case sampling_counter is
when "000" =>
last_dc_select_D <= "00";
when "001" =>
last_dc_select_D <= "01";
when "010" =>
last_dc_select_D <= "10";
when others =>
last_dc_select_D <= "11";
end case;
end case;
 
end process;
 
 
process(last_dc_select, last_dc_Y ,last_dc_Cr, last_dc_Cb)
begin
last_dc_Y_ce <= '0';
last_dc_Cb_ce <= '0';
last_dc_Cr_ce <= '0';
last_dc <= (others=>'0');
 
case last_dc_select is
when "00" =>
last_dc_Y_ce <= '1';
last_dc <= last_dc_Y;
when "01" =>
last_dc_Cb_ce <= '1';
last_dc <= last_dc_Cb;
when "10" =>
last_dc_Cr_ce <= '1';
last_dc <= last_dc_Cr;
when others =>
-- this should not happen, maybe put some errordetection here
end case;
end process;
 
 
process(Clk)
begin
if rising_edge(Clk) then
if (reset='1') then
last_dc_select <= (others=>'0');
elsif ce='1' then
last_dc_select <= last_dc_select_D;
end if;
 
if (reset='1') then
last_dc_Y <= (others=>'0');
elsif ce='1' and last_dc_Y_ce='1' then
last_dc_Y <= last_dc_D;
end if;
 
if (reset='1') then
last_dc_Cb <= (others=>'0');
elsif ce='1' and last_dc_Cb_ce='1' then
last_dc_Cb <= last_dc_D;
end if;
 
if (reset='1') then
last_dc_Cr <= (others=>'0');
elsif ce='1' and last_dc_Cr_ce='1' then
last_dc_Cr <= last_dc_D;
end if;
end if;
end process;
-------------------------------------------------------------------------
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------
-- choose right address for bram/distr-ram.
-------------------------------------------------------------------------
ht_tables_address_ram_wr <= header_select_i & ht_select_i & ht_tables_address_i;
ht_nr_of_symbols_address_ram_wr <= header_select_i & ht_select_i & ht_nr_of_symbols_address_i;
ht_tables_address_ram_rd <= header_select & ht_select & ht_tables_address;
ht_nr_of_symbols_address_ram_rd <= header_select & ht_select & ht_nr_of_symbols_address;
-------------------------------------------------------------------------
 
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------
-- switch between ac/dc and between Y/Cb/Cr decoding by choosing right huffman-table
-------------------------------------------------------------------------
process(dataready, eob, sampling_counter, ht_select, sampling, state)
begin
ht_select_D <= ht_select;
sampling_counter_D <= sampling_counter;
 
case sampling is
---------------------------------------
-- gray Y -> Y -> Y ...
---------------------------------------
when "00" =>
ht_select_D(1 downto 0) <= "00";
 
if (eob='1') then
ht_select_D(2) <= '0';
elsif(dataready='1' and state/=st_write_zeros_eob) then
ht_select_D(2) <= '1';
end if;
---------------------------------------
-- 4:2:0 Y -> Y -> Y -> Y -> Cb -> Cr -> Y -> Y ...
---------------------------------------
when "01" =>
if (sampling_counter < 4) then
ht_select_D(1 downto 0) <= "00";
elsif (sampling_counter="100") then
ht_select_D(1 downto 0) <= "01";
elsif (sampling_counter="101") then
ht_select_D(1 downto 0) <= "01";
end if;
 
if (eob='1') then
ht_select_D(2) <= '0';
sampling_counter_D <= sampling_counter + 1;
if (sampling_counter="101") then
sampling_counter_D <= "000";
end if;
elsif(dataready='1' and state/=st_write_zeros_eob) then
ht_select_D(2) <= '1';
end if;
---------------------------------------
-- 4:2:2 Y -> Y -> Cb -> Cr -> Y -> Y ...
---------------------------------------
when "10" =>
if (sampling_counter < 2) then
ht_select_D(1 downto 0) <= "00";
else
ht_select_D(1 downto 0) <= "01";
end if;
 
if (eob='1') then
ht_select_D(2) <= '0';
sampling_counter_D <= sampling_counter + 1;
if (sampling_counter="011") then
sampling_counter_D <= "000";
end if;
elsif(dataready='1' and state/=st_write_zeros_eob) then
ht_select_D(2) <= '1';
end if;
---------------------------------------
-- 4:4:4 Y -> Cb -> Cr -> Y -> Cb ...
---------------------------------------
when others =>
if (sampling_counter = 0) then
ht_select_D(1 downto 0) <= "00";
else
ht_select_D(1 downto 0) <= "01";
end if;
 
if (eob='1') then
ht_select_D(2) <= '0';
sampling_counter_D <= sampling_counter + 1;
if (sampling_counter="010") then
sampling_counter_D <= "000";
end if;
elsif(dataready='1' and state/=st_write_zeros_eob) then
ht_select_D(2) <= '1';
end if;
end case;
end process;
 
 
process(Clk)
begin
if (rising_edge(Clk)) then
if (reset='1') then
ht_select <= (others=>'0');
sampling_counter <= (others=>'0');
elsif ce='1' then
ht_select <= ht_select_D;
sampling_counter <= sampling_counter_D;
end if;
end if;
end process;
-------------------------------------------------------------------------
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------
-- the huffman decoding
-------------------------------------------------------------------------
process(data_intern, datavalid_i, ready_i, state, code_read, code_build,
symbols, data_symbols, data_tables, get_bit, err, ht_tables_address,
ht_nr_of_symbols_address, is_negative, ac_dc_counter, zeros_counter,
ht_select, dataready)
begin
err_D <= err;
state_D <= state;
dataready_D <= '0';
get_bit_D <= '0';
code_read_D <= code_read;
code_build_D <= code_build;
ht_tables_address_D <= ht_tables_address;
ht_nr_of_symbols_address_D <= ht_nr_of_symbols_address;
symbols_D <= symbols;
is_negative_D <= is_negative;
ac_dc_counter_D<= ac_dc_counter;
zeros_counter_D<= zeros_counter;
eob_D <= eob;
 
 
-- with the last of the 64 words signal eob as well
if ((ac_dc_counter = 0) and (dataready = '1')) then
eob_D <= '1';
else
eob_D <= '0';
end if;
 
 
 
case state is
when st_start1 =>
-- start reading a new huffman code
state_D <= st_start2;
ht_tables_address_D <= (others=>'0');
ht_nr_of_symbols_address_D <= (others=>'0');
code_build_D <= (others=>'0');
code_read_D <= (others=>'0');
-- important, do not remove
when st_start2 =>
state_D <= st_start3;
 
when st_start3 =>
state_D <= st_get_code;
get_bit_D <= '1';
-- append bit to existing code
when st_get_code =>
state_D <= st_check_code1;
code_read_D <= code_read(14 downto 0) & data_intern;
code_build_D <= code_build(14 downto 0) & '0';
ht_nr_of_symbols_address_D <= ht_nr_of_symbols_address + 1;
symbols_D <= data_symbols;
if (data_symbols=0) then
state_D <= st_get_code;
get_bit_D <= '1';
end if;
 
-- decode
when st_check_code1 =>
if (symbols = 0) then
state_D <= st_get_code;
get_bit_D <= '1';
elsif (code_build < code_read) then
code_build_D <= code_build + 1;
ht_tables_address_D <= ht_tables_address + 1;
symbols_D <= symbols - 1;
elsif (code_build = code_read) then
state_D <= st_check_code2;
code_read_D <= (others=>'0');
code_build_D <= (others=>'0');
else
state_D <= st_start1;
err_D <= '1';
end if;
 
 
-- check for EOB and ZRL, initialize value-readout otherwise
when st_check_code2 =>
if (data_tables = 0 and (ht_select(2) = '1')) then -- EOB
state_D <= st_write_zeros_eob;
dataready_D <='1';
zeros_counter_D <= 64 - ac_dc_counter;
ac_dc_counter_D <= ac_dc_counter + 1;
elsif (data_tables = 0 and (ht_select(2) = '0')) then -- to avoid overflow of code_build in next cycle
state_D <= st_start1;
ac_dc_counter_D <= ac_dc_counter + 1;
if (ac_dc_counter=0) then -- value 0 for dc component must be written (diff-value 0)
dataready_D <= '1';
end if;
 
elsif (data_tables = X"F0" and not (ht_select(2) = '0')) then -- ZRL
state_D <= st_write_zeros_zrl;
dataready_D<='1';
zeros_counter_D <= "010000";
ac_dc_counter_D <= ac_dc_counter + 1;
elsif(data_tables(7 downto 4)="0000") then
state_D <= st_get_value1;
code_build_D <= X"000" & data_tables(3 downto 0); -- in the next state this will be the counter
get_bit_D <= '1';
else
state_D <= st_write_zeros;
dataready_D<='1';
code_build_D <= X"000" & data_tables(3 downto 0); -- in the state st_get_valueX this will be the counter
zeros_counter_D <= "00" & data_tables(7 downto 4);
ac_dc_counter_D <= ac_dc_counter+1;
end if;
 
-- write zeroes and start with new code
when st_write_zeros_zrl | st_write_zeros_eob =>
dataready_D <='1';
ac_dc_counter_D <= ac_dc_counter+1;
zeros_counter_D <= zeros_counter-1;
if (zeros_counter=1) then
ac_dc_counter_D <= ac_dc_counter;
state_D <= st_start1;
dataready_D <='0';
end if;
-- write zeroes and read code
when st_write_zeros =>
dataready_D<='1';
ac_dc_counter_D <= ac_dc_counter+1;
zeros_counter_D <= zeros_counter-1;
if (zeros_counter=1) then
ac_dc_counter_D <= ac_dc_counter;
state_D <= st_get_value1;
dataready_D<='0';
get_bit_D <= '1';
end if;
 
 
-- read value
when st_get_value1 =>
if (data_intern = "1") then
code_read_D <= code_read(14 downto 0) & data_intern;
is_negative_D <= '0';
else
code_read_D <= code_read(14 downto 0) & (not data_intern);
is_negative_D <= '1';
end if;
 
if (code_build = 1) then
state_D <= st_start1;
dataready_D <='1';
ac_dc_counter_D <= ac_dc_counter + 1;
else
code_build_D <= code_build - 1;
get_bit_D <= '1';
state_D <= st_get_value2;
end if;
 
 
 
 
when st_get_value2 =>
if (is_negative='0') then
code_read_D <= code_read(14 downto 0) & data_intern;
else
code_read_D <= code_read(14 downto 0) & (not data_intern);
end if;
 
if (code_build = 1) then
state_D <= st_start1;
dataready_D <='1';
ac_dc_counter_D <= ac_dc_counter + 1;
else
code_build_D <= code_build - 1;
get_bit_D <= '1';
state_D <= st_get_value2;
end if;
 
end case;
 
 
end process;
-------------------------------------------------------------------------
 
 
 
 
-------------------------------------------------------------------------
-- Update registers on rising edge
-------------------------------------------------------------------------
process(Clk)
begin
if (rising_edge(Clk)) then
if(reset = '1') then
err <= '0';
state <= st_start1;
dataready <= '0';
get_bit <= '0';
code_read <= (others =>'0');
code_build <= (others =>'0');
ht_tables_address <= (others =>'0');
ht_nr_of_symbols_address <= (others =>'0');
symbols <= (others =>'0');
ac_dc_counter <= (others =>'0');
zeros_counter <= (others =>'0');
is_negative <= '0';
eob <= '0';
elsif ce='1' then
err <= err_D;
state <= state_D;
dataready <= dataready_D;
get_bit <= get_bit_D;
code_read <= code_read_D;
code_build <= code_build_D;
ht_tables_address <= ht_tables_address_D;
ht_nr_of_symbols_address <= ht_nr_of_symbols_address_D;
symbols <= symbols_D;
ac_dc_counter <= ac_dc_counter_D;
zeros_counter <= zeros_counter_D;
is_negative <= is_negative_D;
eob <= eob_D;
end if;
end if;
end process;
-------------------------------------------------------------------------
 
 
 
end IMP;
/myipif/hdl/vhdl/jpeg_header.vhd
0,0 → 1,1083
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg_header is
port
( Clk : in std_logic;
data_i : in std_logic_vector(7 downto 0);
datavalid_i : in std_logic;
reset_i : in std_logic;
eoi_i : in std_logic;
header_valid_o : out std_logic;
header_error_o : out std_logic;
header_select_o: out std_logic;
-- initialize the huffmann tables located in the huffmann-decoder entity
ht_symbols_wea_o : out std_logic;
ht_tables_wea_o : out std_logic;
ht_select_o : out std_logic_vector(2 downto 0); -- bit 2: dc (low) or ac (high), bit 1 and 0: table-nr.
ht_tables_address_o : out std_logic_vector(7 downto 0); -- address in bram: ht_select_o & ht_tables_address_o
ht_nr_of_symbols_address_o: out std_logic_vector(3 downto 0); -- address in distrib-ram: ht_select_o & ht_nr_of_symbols_address_o
ht_data_o : out std_logic_vector(7 downto 0);
-- initialize the quantization tables located in the dequantisation entity
qt_wea_o : out std_logic;
qt_select_o : out std_logic_vector(1 downto 0); -- bit 1 and 0: table-nr.
qt_data_o : out std_logic_vector(7 downto 0);
-- sos-field
comp1_huff_dc_o : out std_logic_vector(3 downto 0);
comp2_huff_dc_o : out std_logic_vector(3 downto 0);
comp3_huff_dc_o : out std_logic_vector(3 downto 0);
comp1_huff_ac_o : out std_logic_vector(3 downto 0);
comp2_huff_ac_o : out std_logic_vector(3 downto 0);
comp3_huff_ac_o : out std_logic_vector(3 downto 0);
--sof-field
height_o : out std_logic_vector(15 downto 0);
width_o : out std_logic_vector(15 downto 0);
sampling_o : out std_logic_vector(1 downto 0); -- "00"->gray, "01"->4:2:0, "10"->4:2:2, "11"->4:4:4
comp1_qt_number_o : out std_logic_vector(0 downto 0);
comp2_qt_number_o : out std_logic_vector(0 downto 0);
comp3_qt_number_o : out std_logic_vector(0 downto 0)
);
end entity jpeg_header;
 
 
 
architecture IMP of jpeg_header is
 
type states is ( st_start, st_search_ff, st_get_id,
st_sos_length1, st_sos_length2, st_sos_components, st_sos_id, st_sos_comp1_huff,
st_sos_comp2_huff, st_sos_comp3_huff, st_sos_wait1, st_sos_wait2, st_sos_wait3,
st_sof_length1, st_sof_length2, st_sof_precision, st_sof_height1, st_sof_height2, st_sof_width1,
st_sof_width2, st_sof_components, st_sof_id, st_sof_comp1_sampl_factor, st_sof_comp1_qt_number,
st_sof_comp2_sampl_factor, st_sof_comp2_qt_number, st_sof_comp3_sampl_factor, st_sof_comp3_qt_number,
st_dht_length1, st_dht_length2, st_dht_info,
st_dht_ht0_dc_table, st_dht_ht0_dc_symbols, st_dht_ht1_dc_table, st_dht_ht1_dc_symbols,
st_dht_ht2_dc_table, st_dht_ht2_dc_symbols, st_dht_ht3_dc_table, st_dht_ht3_dc_symbols,
st_dht_ht0_ac_table, st_dht_ht0_ac_symbols, st_dht_ht1_ac_table, st_dht_ht1_ac_symbols,
st_dht_ht2_ac_table, st_dht_ht2_ac_symbols, st_dht_ht3_ac_table, st_dht_ht3_ac_symbols,
st_dqt_length1, st_dqt_length2, st_dqt_info, st_dqt_qt0, st_dqt_qt1, st_dqt_qt2, st_dqt_qt3,
st_other_length1, st_other_length2, st_skipfield1,
st_idle);
signal state, next_state : states := st_start;
signal header_valid, next_header_valid : std_logic :='0';
signal header_select,next_header_select: std_logic :='0';
signal error, next_error : std_logic :='0';
signal counter1, next_counter1 : std_logic_vector(15 downto 0):=X"0000";
signal counter2, next_counter2 : std_logic_vector(15 downto 0):=X"0000";
-- header data
-- sos-field
signal next_components, components : std_logic_vector(7 downto 0):=X"00";
signal next_comp1_huff_dc, comp1_huff_dc : std_logic_vector(3 downto 0):=X"0";
signal next_comp2_huff_dc, comp2_huff_dc : std_logic_vector(3 downto 0):=X"0";
signal next_comp3_huff_dc, comp3_huff_dc : std_logic_vector(3 downto 0):=X"0";
signal next_comp1_huff_ac, comp1_huff_ac : std_logic_vector(3 downto 0):=X"0";
signal next_comp2_huff_ac, comp2_huff_ac : std_logic_vector(3 downto 0):=X"0";
signal next_comp3_huff_ac, comp3_huff_ac : std_logic_vector(3 downto 0):=X"0";
 
--sof-field
signal next_height, height : std_logic_vector(15 downto 0):=X"0000";
signal next_width, width : std_logic_vector(15 downto 0):=X"0000";
signal next_precision, precision : std_logic_vector(7 downto 0):=X"00";
-- for signal components use registe defined in sos-field
signal next_comp1_sampl_factor, comp1_sampl_factor : std_logic_vector(7 downto 0):=X"00";
signal next_comp1_qt_number, comp1_qt_number : std_logic_vector(7 downto 0):=X"00";
signal next_comp2_sampl_factor, comp2_sampl_factor : std_logic_vector(7 downto 0):=X"00";
signal next_comp2_qt_number, comp2_qt_number : std_logic_vector(7 downto 0):=X"00";
signal next_comp3_sampl_factor, comp3_sampl_factor : std_logic_vector(7 downto 0):=X"00";
signal next_comp3_qt_number, comp3_qt_number : std_logic_vector(7 downto 0):=X"00";
-- dht-field
signal next_nr_of_ht0_codes_ac, nr_of_ht0_codes_ac : std_logic_vector(7 downto 0):=X"00";
signal next_nr_of_ht0_codes_dc, nr_of_ht0_codes_dc : std_logic_vector(7 downto 0):=X"00";
signal next_nr_of_ht1_codes_ac, nr_of_ht1_codes_ac : std_logic_vector(7 downto 0):=X"00";
signal next_nr_of_ht1_codes_dc, nr_of_ht1_codes_dc : std_logic_vector(7 downto 0):=X"00";
signal next_nr_of_ht2_codes_ac, nr_of_ht2_codes_ac : std_logic_vector(7 downto 0):=X"00";
signal next_nr_of_ht2_codes_dc, nr_of_ht2_codes_dc : std_logic_vector(7 downto 0):=X"00";
signal next_nr_of_ht3_codes_ac, nr_of_ht3_codes_ac : std_logic_vector(7 downto 0):=X"00";
signal next_nr_of_ht3_codes_dc, nr_of_ht3_codes_dc : std_logic_vector(7 downto 0):=X"00";
-- initialize the huffmann tables located in the huffmann-decoder entity
signal next_ht_symbols_wea, ht_symbols_wea : std_logic :='0';
signal next_ht_tables_wea, ht_tables_wea : std_logic :='0';
signal next_ht_select, ht_select : std_logic_vector(2 downto 0):="000"; -- bit 2: dc (low) or ac (high), bit 1 and 0: table-nr.
-- dqt-field
-- initialize the quantisation tables located in the dequantisation entity
signal next_qt_wea, qt_wea : std_logic :='0';
signal next_qt_select, qt_select : std_logic_vector(1 downto 0) :="00";
-- other fields
signal next_otherlength, otherlength : std_logic_vector(15 downto 0) :=X"0000";
 
begin
 
--------------------------------------------------------------
-- Signale von/nach draussen
--------------------------------------------------------------
 
header_valid_o <= header_valid;
header_select_o<= header_select;
header_error_o <= error;
 
-- dht-field
ht_symbols_wea_o <= ht_symbols_wea;
ht_tables_wea_o <= ht_tables_wea;
ht_select_o <= ht_select;
ht_tables_address_o <= counter1(7 downto 0);
ht_nr_of_symbols_address_o <= counter1(3 downto 0);
ht_data_o <= data_i;
-- sos-field
comp1_huff_dc_o <= comp1_huff_dc;
comp2_huff_dc_o <= comp2_huff_dc;
comp3_huff_dc_o <= comp3_huff_dc;
comp1_huff_ac_o <= comp1_huff_ac;
comp2_huff_ac_o <= comp2_huff_ac;
comp3_huff_ac_o <= comp3_huff_ac;
 
--sof-field
height_o <= height;
width_o <= width;
comp1_qt_number_o <= comp1_qt_number(0 downto 0);
comp2_qt_number_o <= comp2_qt_number(0 downto 0);
comp3_qt_number_o <= comp3_qt_number(0 downto 0);
 
process(comp1_sampl_factor, comp2_sampl_factor, comp3_sampl_factor)
variable sampl_factor : std_logic_vector(23 downto 0):=(others=>'0');
begin
sampl_factor := comp1_sampl_factor & comp2_sampl_factor & comp3_sampl_factor;
case sampl_factor is
when X"111111" => sampling_o <= "11"; -- 4:4:4 MDU = 8x8
when X"211111" => sampling_o <= "10"; -- 4:2:2 MDU = 16x8
when X"221111" => sampling_o <= "01"; -- 4:2:0 MDU = 16x16
when others => sampling_o <= "00"; -- gray MDU = 8x8 (same as no upsampling)
end case;
end process;
 
-- dqt-field
-- initialize the quantization tables located in the dequantization entity
qt_wea_o <= qt_wea;
qt_select_o <= qt_select;
qt_data_o <= data_i;
--------------------------------------------------------------
 
 
 
process(eoi_i, header_select)
begin
next_header_select <= header_select;
if eoi_i='1' then
next_header_select <= not header_select;
end if;
end process;
 
 
 
 
process( data_i, datavalid_i, state, reset_i, eoi_i, counter1, counter2, error,
components, comp1_huff_dc, comp2_huff_dc, comp3_huff_dc, comp1_huff_ac, comp2_huff_ac, comp3_huff_ac,
height, width, precision,
comp1_sampl_factor, comp1_qt_number, comp2_sampl_factor, comp2_qt_number, comp3_sampl_factor, comp3_qt_number,
nr_of_ht0_codes_ac, nr_of_ht0_codes_dc, nr_of_ht1_codes_ac, nr_of_ht1_codes_dc,
nr_of_ht2_codes_ac, nr_of_ht2_codes_dc, nr_of_ht3_codes_ac, nr_of_ht3_codes_dc,
ht_select, qt_select, otherlength)
begin
next_state <= state;
next_header_valid <= '0';
next_error <= error;
next_counter1 <= counter1;
next_counter2 <= counter2;
-- sos field
next_components <= components;
next_comp1_huff_dc <= comp1_huff_dc;
next_comp2_huff_dc <= comp2_huff_dc;
next_comp3_huff_dc <= comp3_huff_dc;
next_comp1_huff_ac <= comp1_huff_ac;
next_comp2_huff_ac <= comp2_huff_ac;
next_comp3_huff_ac <= comp3_huff_ac;
 
-- sof-field
next_height <= height;
next_width <= width;
next_precision <= precision;
next_components <= components; -- use register from sos-field
next_comp1_sampl_factor <= comp1_sampl_factor;
next_comp1_qt_number <= comp1_qt_number;
next_comp2_sampl_factor <= comp2_sampl_factor;
next_comp2_qt_number <= comp2_qt_number;
next_comp3_sampl_factor <= comp3_sampl_factor;
next_comp3_qt_number <= comp3_qt_number;
 
-- dht-field
next_nr_of_ht0_codes_ac <= nr_of_ht0_codes_ac;
next_nr_of_ht0_codes_dc <= nr_of_ht0_codes_dc;
next_nr_of_ht1_codes_ac <= nr_of_ht1_codes_ac;
next_nr_of_ht1_codes_dc <= nr_of_ht1_codes_dc;
next_nr_of_ht2_codes_ac <= nr_of_ht2_codes_ac;
next_nr_of_ht2_codes_dc <= nr_of_ht2_codes_dc;
next_nr_of_ht3_codes_ac <= nr_of_ht3_codes_ac;
next_nr_of_ht3_codes_dc <= nr_of_ht3_codes_dc;
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '0';
next_ht_select <= ht_select;
-- dqt-field
next_qt_wea <= '0';
next_qt_select <= qt_select;
-- other field
next_otherlength <= otherlength;
 
 
 
case state is
 
-----------------------------------------------------
-- START
-----------------------------------------------------
when st_start =>
if (datavalid_i='1') and (data_i=X"FF") then
next_state <= st_start;
next_counter1 <= X"0001";
elsif (datavalid_i='1') and (data_i=X"D8") and counter1=X"0001" then
next_state <= st_search_ff;
next_counter1 <= X"0000";
else
next_state <= st_start;
next_counter1 <= X"0000";
end if;
 
-----------------------------------------------------
-- SEARCH_FF
-----------------------------------------------------
when st_search_ff =>
next_state <= st_search_ff;
if (datavalid_i='1') and (data_i=X"FF") then
next_state <= st_get_id;
end if;
 
 
-----------------------------------------------------
-- GET_ID
-----------------------------------------------------
when st_get_id =>
if (datavalid_i='1') then
case data_i is
when X"DA" =>
next_state <= st_sos_length1;
when X"DB" =>
next_state <= st_dqt_length1;
when X"C4" =>
next_state <= st_dht_length1;
when X"C0" =>
next_state <= st_sof_length1;
when X"FF" =>
next_state <= st_get_id;
when X"E0" | X"FE" | X"E1" | X"EE" => -- carefull: try only to skip that sort of fields which actually have length-bytes
next_state <= st_other_length1;
when others =>
next_state <= st_search_ff;
end case;
end if;
 
 
-----------------------------------------------------
-- SOS
-----------------------------------------------------
when st_sos_length1 =>
if (datavalid_i='1') then
next_state <= st_sos_length2;
end if;
when st_sos_length2 =>
if (datavalid_i='1') then
next_state <= st_sos_components;
end if;
when st_sos_components =>
if (datavalid_i='1') then
next_counter1 <= (others=>'0');
next_components <= data_i;
next_state <= st_sos_id;
if ((data_i /= 1) and (data_i /= 3)) then
next_error <= '1';
next_state <= st_idle;
end if;
end if;
when st_sos_id =>
if (datavalid_i='1') then
next_counter1 <= counter1+1;
if (data_i = 1) then
next_state <= st_sos_comp1_huff;
elsif(data_i = 2) then
next_state <= st_sos_comp2_huff;
elsif(data_i = 3) then
next_state <= st_sos_comp3_huff;
else
next_error <= '1';
next_state <= st_idle;
end if;
end if;
when st_sos_comp1_huff =>
if (datavalid_i='1') then
next_comp1_huff_dc <= data_i(7 downto 4);
next_comp1_huff_ac <= data_i(3 downto 0);
if (components = counter1(7 downto 0)) then
next_state <= st_sos_wait1;
else
next_state <= st_sos_id;
end if;
end if;
when st_sos_comp2_huff =>
if (datavalid_i='1') then
next_comp2_huff_dc <= data_i(7 downto 4);
next_comp2_huff_ac <= data_i(3 downto 0);
if (components = counter1(7 downto 0)) then
next_state <= st_sos_wait1;
else
next_state <= st_sos_id;
end if;
end if;
when st_sos_comp3_huff =>
if (datavalid_i='1') then
next_comp3_huff_dc <= data_i(7 downto 4);
next_comp3_huff_ac <= data_i(3 downto 0);
if (components = counter1(7 downto 0)) then
next_state <= st_sos_wait1;
else
next_state <= st_sos_id;
end if;
end if;
when st_sos_wait1 =>
if (datavalid_i='1') then
next_state <= st_sos_wait2;
end if;
when st_sos_wait2 =>
if (datavalid_i='1') then
next_state <= st_sos_wait3;
end if;
when st_sos_wait3 =>
if (datavalid_i='1') then
next_header_valid <= not error;
next_state <= st_idle;
end if;
 
-----------------------------------------------------
-- DQT
-- * counter1: address for bram (and control variable)
-- * counter2: used to check if the field is at the end or if
-- another table is appended
-----------------------------------------------------
when st_dqt_length1 =>
if (datavalid_i='1') then
next_counter2(15 downto 8) <= data_i;
next_state <= st_dqt_length2;
end if;
when st_dqt_length2 =>
if (datavalid_i='1') then
next_counter2 <= (counter2(15 downto 8) & data_i)-2;
next_state <= st_dqt_info;
end if;
when st_dqt_info =>
if (datavalid_i='1') then
next_counter1 <= (others => '0');
next_counter2 <= counter2 - 1;
next_state <= st_dqt_info;
case data_i(3 downto 0) is
when "0000" =>
next_qt_select <= "00";
next_state <= st_dqt_qt0;
next_qt_wea <= '1';
when "0001" =>
next_qt_select <= "01";
next_state <= st_dqt_qt1;
next_qt_wea <= '1';
when "0010" =>
next_qt_select <= "10";
next_state <= st_dqt_qt2;
next_qt_wea <= '1';
when "0011" =>
next_qt_select <= "11";
next_state <= st_dqt_qt3;
next_qt_wea <= '1';
when others =>
next_error <= '1';
next_state <= st_idle;
end case;
if data_i(7 downto 4) /= "00" then -- 16bit-precision not supported
next_error <= '1';
next_state <= st_idle;
end if;
end if;
when st_dqt_qt0 =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_qt_wea <= '1';
if (counter2=1) then
next_qt_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = 63) then
next_qt_wea <= '0';
next_state <= st_dqt_info;
else
next_qt_wea <= '1';
next_state <= st_dqt_qt0;
end if;
end if;
when st_dqt_qt1 =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_qt_wea <= '1';
if (counter2=1) then
next_qt_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = 63) then
next_qt_wea <= '0';
next_state <= st_dqt_info;
else
next_qt_wea <= '1';
next_state <= st_dqt_qt1;
end if;
end if;
when st_dqt_qt2 =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_qt_wea <= '1';
if (counter2=1) then
next_qt_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = 63) then
next_qt_wea <= '0';
next_state <= st_dqt_info;
else
next_qt_wea <= '1';
next_state <= st_dqt_qt2;
end if;
end if;
when st_dqt_qt3 =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_qt_wea <= '1';
if (counter2=1) then
next_qt_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = 63) then
next_qt_wea <= '0';
next_state <= st_dqt_info;
else
next_qt_wea <= '1';
next_state <= st_dqt_qt3;
end if;
end if;
 
-----------------------------------------------------
-- DHT
-- * counter1: address for bram (and control variable)
-- * counter2: used to check if the field is at the end or if
-- another table is appended
-----------------------------------------------------
when st_dht_length1 =>
if (datavalid_i='1') then
next_counter2(15 downto 8) <= data_i;
next_state <= st_dht_length2;
end if;
when st_dht_length2 =>
if (datavalid_i='1') then
next_counter2 <= (counter2(15 downto 8) & data_i)-2;
next_state <= st_dht_info;
end if;
when st_dht_info =>
if (datavalid_i='1') then
next_counter1 <= (others => '0');
next_counter2 <= counter2 - 1;
next_state <= st_dht_info;
case data_i(4 downto 0) is
when "00000" =>
next_ht_symbols_wea <= '1';
next_ht_select <= "000";
next_state <= st_dht_ht0_dc_symbols;
next_nr_of_ht0_codes_dc <= (others =>'0');
when "00001" =>
next_ht_symbols_wea <= '1';
next_ht_select <= "001";
next_state <= st_dht_ht1_dc_symbols;
next_nr_of_ht1_codes_dc <= (others =>'0');
when "00010" =>
next_ht_symbols_wea <= '1';
next_ht_select <= "010";
next_state <= st_dht_ht2_dc_symbols;
next_nr_of_ht2_codes_dc <= (others =>'0');
when "00011" =>
next_ht_symbols_wea <= '1';
next_ht_select <= "011";
next_state <= st_dht_ht3_dc_symbols;
next_nr_of_ht3_codes_dc <= (others =>'0');
when "10000" =>
next_ht_symbols_wea <= '1';
next_ht_select <= "100";
next_state <= st_dht_ht0_ac_symbols;
next_nr_of_ht0_codes_ac <= (others =>'0');
when "10001" =>
next_ht_symbols_wea <= '1';
next_ht_select <= "101";
next_state <= st_dht_ht1_ac_symbols;
next_nr_of_ht1_codes_ac <= (others =>'0');
when "10010" =>
next_ht_symbols_wea <= '1';
next_ht_select <= "110";
next_state <= st_dht_ht2_ac_symbols;
next_nr_of_ht2_codes_ac <= (others =>'0');
when "10011" =>
next_ht_symbols_wea <= '1';
next_ht_select <= "111";
next_state <= st_dht_ht3_ac_symbols;
next_nr_of_ht3_codes_ac <= (others =>'0');
when others =>
next_ht_symbols_wea <= '0';
next_error <= '1';
next_state <= st_idle;
end case;
end if;
when st_dht_ht0_dc_symbols =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_nr_of_ht0_codes_dc <= nr_of_ht0_codes_dc + data_i;
next_ht_symbols_wea <= '1';
next_state <= st_dht_ht0_dc_symbols;
if (counter1=15) then
next_counter1 <= (others=>'0');
next_ht_tables_wea <= '1';
next_ht_symbols_wea <= '0';
next_state <= st_dht_ht0_dc_table;
end if;
end if;
when st_dht_ht0_dc_table =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_ht_tables_wea <= '1';
if (counter2=1) then
next_ht_tables_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = nr_of_ht0_codes_dc-1) then
next_ht_tables_wea <= '0';
next_state <= st_dht_info;
else
next_ht_tables_wea <= '1';
next_state <= st_dht_ht0_dc_table;
end if;
end if;
when st_dht_ht1_dc_symbols =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_nr_of_ht1_codes_dc <= nr_of_ht1_codes_dc + data_i;
next_ht_symbols_wea <= '1';
next_state <= st_dht_ht1_dc_symbols;
if (counter1=15) then
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '1';
next_counter1 <= (others=>'0');
next_state <= st_dht_ht1_dc_table;
end if;
end if;
when st_dht_ht1_dc_table =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_ht_tables_wea <= '1';
if (counter2=1) then
next_ht_tables_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = nr_of_ht1_codes_dc-1) then
next_ht_tables_wea <= '0';
next_state <= st_dht_info;
else
next_ht_tables_wea <= '1';
next_state <= st_dht_ht1_dc_table;
end if;
end if;
when st_dht_ht2_dc_symbols =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_nr_of_ht2_codes_dc <= nr_of_ht2_codes_dc + data_i;
next_ht_symbols_wea <= '1';
next_state <= st_dht_ht2_dc_symbols;
if (counter1=15) then
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '1';
next_counter1 <= (others=>'0');
next_state <= st_dht_ht2_dc_table;
end if;
end if;
when st_dht_ht2_dc_table =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_ht_tables_wea <= '1';
if (counter2=1) then
next_ht_tables_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = nr_of_ht2_codes_dc-1) then
next_ht_tables_wea <= '0';
next_state <= st_dht_info;
else
next_ht_tables_wea <= '1';
next_state <= st_dht_ht2_dc_table;
end if;
end if;
when st_dht_ht3_dc_symbols =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_nr_of_ht3_codes_dc <= nr_of_ht3_codes_dc + data_i;
next_ht_symbols_wea <= '1';
next_state <= st_dht_ht3_dc_symbols;
if (counter1=15) then
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '1';
next_counter1 <= (others=>'0');
next_state <= st_dht_ht3_dc_table;
end if;
end if;
when st_dht_ht3_dc_table =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_ht_tables_wea <= '1';
if (counter2=1) then
next_ht_tables_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = nr_of_ht3_codes_dc-1) then
next_ht_tables_wea <= '0';
next_state <= st_dht_info;
else
next_ht_tables_wea <= '1';
next_state <= st_dht_ht3_dc_table;
end if;
end if;
when st_dht_ht0_ac_symbols =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_nr_of_ht0_codes_ac <= nr_of_ht0_codes_ac + data_i;
next_ht_symbols_wea <= '1';
next_state <= st_dht_ht0_ac_symbols;
if (counter1=15) then
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '1';
next_counter1 <= (others=>'0');
next_state <= st_dht_ht0_ac_table;
end if;
end if;
when st_dht_ht0_ac_table =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_ht_tables_wea <= '0';
if (counter2=1) then
next_ht_tables_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = nr_of_ht0_codes_ac-1) then
next_ht_tables_wea <= '0';
next_state <= st_dht_info;
else
next_ht_tables_wea <= '1';
next_state <= st_dht_ht0_ac_table;
end if;
end if;
when st_dht_ht1_ac_symbols =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_nr_of_ht1_codes_ac <= nr_of_ht1_codes_ac + data_i;
next_ht_symbols_wea <= '1';
next_state <= st_dht_ht1_ac_symbols;
if (counter1=15) then
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '1';
next_counter1 <= (others=>'0');
next_state <= st_dht_ht1_ac_table;
end if;
end if;
when st_dht_ht1_ac_table =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_ht_tables_wea <= '0';
if (counter2=1) then
next_ht_tables_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = nr_of_ht1_codes_ac-1) then
next_ht_tables_wea <= '0';
next_state <= st_dht_info;
else
next_ht_tables_wea <= '1';
next_state <= st_dht_ht1_ac_table;
end if;
end if;
when st_dht_ht2_ac_symbols =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_nr_of_ht2_codes_ac <= nr_of_ht2_codes_ac + data_i;
next_ht_symbols_wea <= '1';
next_state <= st_dht_ht2_ac_symbols;
if (counter1=15) then
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '1';
next_counter1 <= (others=>'0');
next_state <= st_dht_ht2_ac_table;
end if;
end if;
when st_dht_ht2_ac_table =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_ht_tables_wea <= '0';
if (counter2=1) then
next_ht_tables_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = nr_of_ht2_codes_ac-1) then
next_ht_tables_wea <= '0';
next_state <= st_dht_info;
else
next_ht_tables_wea <= '1';
next_state <= st_dht_ht2_ac_table;
end if;
end if;
when st_dht_ht3_ac_symbols =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_nr_of_ht3_codes_ac <= nr_of_ht3_codes_ac + data_i;
next_ht_symbols_wea <= '1';
next_state <= st_dht_ht3_ac_symbols;
if (counter1=15) then
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '1';
next_counter1 <= (others=>'0');
next_state <= st_dht_ht3_ac_table;
end if;
end if;
when st_dht_ht3_ac_table =>
if (datavalid_i='1') then
next_counter1 <= counter1 + 1;
next_counter2 <= counter2 - 1;
next_ht_tables_wea <= '0';
if (counter2=1) then
next_ht_tables_wea <= '0';
next_state <= st_search_ff;
elsif (counter1 = nr_of_ht3_codes_ac-1) then
next_ht_tables_wea <= '0';
next_state <= st_dht_info;
else
next_ht_tables_wea <= '1';
next_state <= st_dht_ht3_ac_table;
end if;
end if;
 
 
-------------------------------------------------------
---- SOF
-------------------------------------------------------
when st_sof_length1 =>
if (datavalid_i='1') then
next_state <= st_sof_length2;
end if;
when st_sof_length2 =>
if (datavalid_i='1') then
next_state <= st_sof_precision;
end if;
when st_sof_precision =>
if (datavalid_i='1') then
next_precision <= data_i;
next_state <= st_sof_height1;
if (data_i /= 8) then
next_error <= '1';
next_state <= st_idle;
end if;
end if;
when st_sof_height1 =>
if (datavalid_i='1') then
next_height(15 downto 8) <= data_i;
next_state <= st_sof_height2;
end if;
when st_sof_height2 =>
if (datavalid_i='1') then
next_height(7 downto 0) <= data_i;
next_state <= st_sof_width1;
end if;
when st_sof_width1 =>
if (datavalid_i='1') then
next_width(15 downto 8) <= data_i;
next_state <= st_sof_width2;
end if;
when st_sof_width2 =>
if (datavalid_i='1') then
next_width(7 downto 0) <= data_i;
next_state <= st_sof_components;
end if;
when st_sof_components =>
if (datavalid_i='1') then
next_components <= data_i;
next_counter1 <= (others => '0');
next_state <= st_sof_id;
if ((data_i /= 1) and (data_i /= 3)) then
next_error <= '1';
next_state <= st_idle;
end if;
end if;
when st_sof_id =>
if (datavalid_i='1') then
next_counter1 <= counter1+1;
if (data_i = 1) then
next_state <= st_sof_comp1_sampl_factor;
elsif(data_i = 2) then
next_state <= st_sof_comp2_sampl_factor;
elsif(data_i = 3) then
next_state <= st_sof_comp3_sampl_factor;
else
next_error <= '1';
next_state <= st_idle;
end if;
end if;
when st_sof_comp1_sampl_factor =>
if (datavalid_i='1') then
next_comp1_sampl_factor <= data_i;
next_state <= st_sof_comp1_qt_number;
end if;
when st_sof_comp1_qt_number =>
if (datavalid_i='1') then
next_comp1_qt_number <= data_i;
if (components = counter1(7 downto 0)) then
next_state <= st_search_ff;
else
next_state <= st_sof_id;
end if;
end if;
when st_sof_comp2_sampl_factor =>
if (datavalid_i='1') then
next_comp2_sampl_factor <= data_i;
next_state <= st_sof_comp2_qt_number;
end if;
when st_sof_comp2_qt_number =>
if (datavalid_i='1') then
next_comp2_qt_number <= data_i;
if (components = counter1(7 downto 0)) then
next_state <= st_search_ff;
else
next_state <= st_sof_id;
end if;
end if;
when st_sof_comp3_sampl_factor =>
if (datavalid_i='1') then
next_comp3_sampl_factor <= data_i;
next_state <= st_sof_comp3_qt_number;
end if;
when st_sof_comp3_qt_number =>
if (datavalid_i='1') then
next_comp3_qt_number <= data_i;
if (components = counter1(7 downto 0)) then
next_state <= st_search_ff;
else
next_state <= st_sof_id;
end if;
end if;
-------------------------------------------------------
-- Get length for app0- and com-field and skip it
-- (this is done because these fields may contain
-- "FFxx"-Bytes (e.g. in thumbnail pictures) that
-- are not to be interpreted)
-------------------------------------------------------
when st_other_length1 =>
if (datavalid_i='1') then
next_otherlength(15 downto 8) <= data_i;
next_state <= st_other_length2;
end if;
 
when st_other_length2 =>
if (datavalid_i='1') then
next_state <= st_skipfield1;
next_otherlength <= (otherlength(15 downto 8) & data_i);
if (otherlength(15 downto 8) & data_i) = 2 then -- handle empty fields
next_state <= st_search_ff;
end if;
end if;
when st_skipfield1 =>
if (datavalid_i='1') then
next_otherlength <= otherlength - 1;
next_state <= st_skipfield1;
if otherlength <= 5 then
next_state <= st_search_ff;
end if;
end if;
 
-----------------------------------------------------
-- IDLE
-----------------------------------------------------
when st_idle =>
next_header_valid <= not error;
if (eoi_i)='1' then
next_state <= st_start;
next_header_valid <= '0';
end if;
end case;
 
-----------------------------------------------------
 
 
 
 
 
-----------------------------------------------------
-- RESET
-----------------------------------------------------
if (reset_i='1') then
next_state <= st_start;
next_header_valid <= '0';
next_error <= '0';
next_counter1 <= (others=>'0');
next_counter2 <= (others=>'0');
 
 
-- sos field
next_components <= X"00";
next_comp1_huff_dc <= X"0";
next_comp2_huff_dc <= X"0";
next_comp3_huff_dc <= X"0";
next_comp1_huff_ac <= X"0";
next_comp2_huff_ac <= X"0";
next_comp3_huff_ac <= X"0";
-- sof-field
next_height <= X"0000";
next_width <= X"0000";
next_precision <= X"00";
next_comp1_sampl_factor <= X"00";
next_comp1_qt_number <= X"00";
next_comp2_sampl_factor <= X"00";
next_comp2_qt_number <= X"00";
next_comp3_sampl_factor <= X"00";
next_comp3_qt_number <= X"00";
-- dht-field
next_nr_of_ht0_codes_ac <= (others=>'0');
next_nr_of_ht0_codes_dc <= (others=>'0');
next_nr_of_ht1_codes_ac <= (others=>'0');
next_nr_of_ht1_codes_dc <= (others=>'0');
next_nr_of_ht2_codes_ac <= (others=>'0');
next_nr_of_ht2_codes_dc <= (others=>'0');
next_nr_of_ht3_codes_ac <= (others=>'0');
next_nr_of_ht3_codes_dc <= (others=>'0');
next_ht_symbols_wea <= '0';
next_ht_tables_wea <= '0';
next_ht_select <= (others=>'0');
 
-- dqt-field
next_qt_wea <= '0';
next_qt_select <= (others=>'0');
-- other field
next_otherlength <= (others =>'0');
end if;
-----------------------------------------------------
 
end process;
-------------------------------------------
 
-------------------------------------------
-- Update registers on rising edge
-------------------------------------------
process(Clk)
begin
if (rising_edge(Clk)) then
state <= next_state;
header_valid <= next_header_valid;
header_select <= next_header_select;
error <= next_error;
counter1 <= next_counter1;
counter2 <= next_counter2;
-- sos field
components <= next_components;
comp1_huff_dc <= next_comp1_huff_dc;
comp2_huff_dc <= next_comp2_huff_dc;
comp3_huff_dc <= next_comp3_huff_dc;
comp1_huff_ac <= next_comp1_huff_ac;
comp2_huff_ac <= next_comp2_huff_ac;
comp3_huff_ac <= next_comp3_huff_ac;
-- sof-field
height <= next_height;
width <= next_width;
precision <= next_precision;
comp1_sampl_factor <= next_comp1_sampl_factor;
comp1_qt_number <= next_comp1_qt_number;
comp2_sampl_factor <= next_comp2_sampl_factor;
comp2_qt_number <= next_comp2_qt_number;
comp3_sampl_factor <= next_comp3_sampl_factor;
comp3_qt_number <= next_comp3_qt_number;
-- dht-field
nr_of_ht0_codes_ac <= next_nr_of_ht0_codes_ac;
nr_of_ht0_codes_dc <= next_nr_of_ht0_codes_dc;
nr_of_ht1_codes_ac <= next_nr_of_ht1_codes_ac;
nr_of_ht1_codes_dc <= next_nr_of_ht1_codes_dc;
nr_of_ht2_codes_ac <= next_nr_of_ht2_codes_ac;
nr_of_ht2_codes_dc <= next_nr_of_ht2_codes_dc;
nr_of_ht3_codes_ac <= next_nr_of_ht3_codes_ac;
nr_of_ht3_codes_dc <= next_nr_of_ht3_codes_dc;
ht_symbols_wea <= next_ht_symbols_wea;
ht_tables_wea <= next_ht_tables_wea;
ht_select <= next_ht_select;
 
-- dqt-field
qt_wea <= next_qt_wea;
qt_select <= next_qt_select;
-- other field
otherlength <= next_otherlength;
 
end if;
end process;
--------------------------------------------
 
end IMP;
 
/myipif/hdl/vhdl/jpeg_check_FF.vhd
0,0 → 1,142
--------------------------------------------------------------------
-- This entity is not very well written. A redesign may not be the worst idea.
--------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg_check_FF is
port
( Clk : in std_logic;
reset_i : in std_logic;
header_valid_i : in std_logic;
header_select_i: in std_logic;
eoi_o : out std_logic :='0';
 
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
 
-- bit occupancy
-- 0: header_valid
-- 1: header_select
-- 2: end of block
-- 3: end of image
context_o : out std_logic_vector(3 downto 0);
-- flow control
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end entity jpeg_check_FF;
 
 
 
 
 
architecture IMP of jpeg_check_FF is
 
signal data : std_logic_vector(7 downto 0) :=(others => '0');
signal ff_received, ff_received_D : std_logic :='0';
signal eoi, eoi_D, eoi_for_context : std_logic :='0'; -- End of Image
signal header_valid : std_logic :='0';
 
signal context : std_logic_vector(3 downto 0) :=(others =>'0');
 
-- flowcontroll
signal datavalid : std_logic := '0';
signal ce : std_logic :='0';
signal reset : std_logic :='1';
 
 
begin
 
ce <= datavalid_i and ready_i;
datavalid <= (ce and not ff_received_D and header_valid and header_valid_i)
or (context(3) and ready_i); -- write random data with eoi-flag set in fifo
datavalid_o <= datavalid;
ready_o <= ce;
reset <= reset_i;
context_o <= context;
 
process(data_i, data, ff_received, ff_received_D)
begin
data <= data;
ff_received <= ff_received;
eoi <= '0';
if(data_i=X"FF") then
ff_received <= '1';
else
ff_received <= '0';
end if;
if(data_i=X"00" and ff_received_D='1') then
data <= X"FF";
elsif(data_i=X"D9" and ff_received_D='1') then
eoi <= '1';
data <= (others=>'0');
else
data <= data_i;
end if;
end process;
 
 
 
 
-- to write an "eoi"-word
process(Clk)
begin
if rising_edge(Clk) then
-- eoi_for_context <= eoi_for_context;
if(datavalid='1' or reset='1') then
eoi_for_context <= '0';
elsif eoi='1' then
eoi_for_context <= '1';
end if;
end if;
end process;
 
 
context(3) <= eoi_for_context;
process(Clk)
begin
if rising_edge(Clk) then
if (reset='1') then
eoi_o <= '0';
eoi_D <= '0';
context(2 downto 0) <= (others=>'0');
else
eoi_D <= eoi;
eoi_o <= header_valid_i and eoi and not eoi_D; -- use "rising_edge(eoi)" to prevent deadlock with input_fifo,
-- header_valid_i to prevent loop (under impropable circumstance)
context(2 downto 0) <= '0' & header_select_i & header_valid_i;
end if;
end if;
end process;
 
process(Clk)
begin
if rising_edge(Clk) then
 
if reset='1' then
data_o <= (others=>'0');
ff_received_D <= '0';
header_valid <= '0';
elsif ce ='1' then
data_o <= data;
ff_received_D <= ff_received;
header_valid <= header_valid_i;
end if;
end if;
end process;
end IMP;
/myipif/hdl/vhdl/jpeg_qt_sr.vhd
0,0 → 1,102
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file jpeg_qt_sr.vhd when simulating
-- the core, jpeg_qt_sr. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_qt_sr IS
port (
d: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
ce: IN std_logic;
q: OUT std_logic_VECTOR(7 downto 0));
END jpeg_qt_sr;
 
ARCHITECTURE jpeg_qt_sr_a OF jpeg_qt_sr IS
-- synopsys translate_off
component wrapped_jpeg_qt_sr
port (
d: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
ce: IN std_logic;
q: OUT std_logic_VECTOR(7 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_jpeg_qt_sr use entity XilinxCoreLib.c_shift_ram_v8_0(behavioral)
generic map(
c_has_aset => 0,
c_read_mif => 0,
c_has_a => 0,
c_sync_priority => 1,
c_opt_goal => 0,
c_has_sclr => 0,
c_width => 8,
c_enable_rlocs => 0,
c_default_data_radix => 1,
c_generate_mif => 0,
c_ainit_val => "0000000000000000",
c_has_ce => 1,
c_has_aclr => 0,
c_mem_init_radix => 1,
c_sync_enable => 0,
c_depth => 64,
c_has_ainit => 0,
c_sinit_val => "0000000000000000",
c_has_sset => 0,
c_has_sinit => 0,
c_mem_init_file => "no_coe_file_loaded",
c_shift_type => 0,
c_default_data => "00000000",
c_reg_last_bit => 0,
c_elaboration_dir => "./",
c_addr_width => 4);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_qt_sr
port map (
d => d,
clk => clk,
ce => ce,
q => q);
-- synopsys translate_on
 
END jpeg_qt_sr_a;
 
/myipif/hdl/vhdl/myipif.vhd
0,0 → 1,790
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity myipif is
generic
(
C_BASEADDR : std_logic_vector := X"50000000";
C_HIGHADDR : std_logic_vector := X"5000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p";
C_SDRAM_ADDR : std_logic_vector := X"00000000"
);
port
(
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
-- slave
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
-- master
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic;
LEDs : out std_logic_vector(3 downto 0);
BUTTONs : in std_logic_vector(4 downto 0); -- 0:left, 1:right, 2:up, 3:down, 4:center
SWITCHEs : in std_logic_vector(3 downto 0);
 
VGA_OUT_PIXEL_CLOCK: out STD_LOGIC;
VGA_COMP_SYNCH: out STD_LOGIC;
VGA_OUT_BLANK_Z: out STD_LOGIC;
VGA_HSYNCH: out STD_LOGIC;
VGA_VSYNCH: out STD_LOGIC;
VGA_OUT_RED: out STD_LOGIC_VECTOR (7 downto 0);
VGA_OUT_GREEN: out STD_LOGIC_VECTOR (7 downto 0);
VGA_OUT_BLUE: out STD_LOGIC_VECTOR (7 downto 0)
);
end entity myipif;
 
 
 
architecture IMP of myipif is
 
 
-- **********************************************************************************************
-- * Components
-- **********************************************************************************************
 
--------------------------------------------------------------
---- Chipscope Stuff
--------------------------------------------------------------
-- component icon
-- port (
-- control0 : out std_logic_vector(35 downto 0));
-- end component;
--
-- component ila
-- port(
-- control : in std_logic_vector(35 downto 0);
-- clk : in std_logic;
-- trig0 : in std_logic_vector(127 downto 0));
-- end component;
--
-- signal control0 : std_logic_vector(35 downto 0);
-- signal trig0 : std_logic_vector(127 downto 0);
------------------------------------------------------------
 
 
 
--------------------------------------------------------------
-- JPEG - Decoder
--------------------------------------------------------------
component jpeg is
port(
Clk : in std_logic;
data_i : in std_logic_vector(31 downto 0);
reset_i : in std_logic;
 
eoi_o : out std_logic;
error_o : out std_logic;
context_o : out std_logic_vector (3 downto 0);
red_o : out STD_LOGIC_VECTOR (7 downto 0);
green_o : out STD_LOGIC_VECTOR (7 downto 0);
blue_o : out STD_LOGIC_VECTOR (7 downto 0);
width_o : out std_logic_vector(15 downto 0);
height_o : out std_logic_vector(15 downto 0);
sampling_o : out std_logic_vector( 1 downto 0);
-- -- debug
-- LEDs : out std_logic_vector(3 downto 0);
-- BUTTONs : in std_logic_vector(4 downto 0); -- 0:left, 1:right, 2:up, 3:down, 4:center
-- SWITCHEs : in std_logic_vector(3 downto 0);
-- -- chipscope-debugging
-- chipscope_o : out std_logic_vector(127 downto 0);
--
-- flow controll
datavalid_i : in std_logic;
datavalid_o : out std_logic;
ready_i : in std_logic;
ready_o : out std_logic
);
end component jpeg;
------------------------------------------------------------
 
 
 
------------------------------------------------------------
-- VGA-handling
------------------------------------------------------------
component vga is
port(
Clk : in std_logic;
reset_i : in std_logic;
eoi_i : in std_logic;
red_i : in STD_LOGIC_VECTOR (7 downto 0);
green_i : in STD_LOGIC_VECTOR (7 downto 0);
blue_i : in STD_LOGIC_VECTOR (7 downto 0);
width_i : in std_logic_vector(15 downto 0);
height_i : in std_logic_vector(15 downto 0);
sampling_i : in std_logic_vector( 1 downto 0);
 
VGA_OUT_PIXEL_CLOCK: out STD_LOGIC;
VGA_COMP_SYNCH: out STD_LOGIC;
VGA_OUT_BLANK_Z: out STD_LOGIC;
VGA_HSYNCH: out STD_LOGIC;
VGA_VSYNCH: out STD_LOGIC;
VGA_OUT_RED: out STD_LOGIC_VECTOR (7 downto 0);
VGA_OUT_GREEN: out STD_LOGIC_VECTOR (7 downto 0);
VGA_OUT_BLUE: out STD_LOGIC_VECTOR (7 downto 0);
 
-- -- chipscope-debugging
-- chipscope_o : out std_logic_vector(127 downto 0);
 
-- flow controll
datavalid_i : in std_logic;
ready_o : out std_logic
);
end component vga;
------------------------------------------------------------
 
 
-- **********************************************************************************************
-- * Signals
-- **********************************************************************************************
type OPB_states is (idle, MasterRead1, MasterRead2);
signal OPB_state, OPB_next_state: OPB_states := idle;
 
signal Sl_DBus_D : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal Sl_toutSup_D : std_logic;
signal Sl_xferAck_D : std_logic;
signal Sl_retry_D : std_logic;
signal Sl_errAck_D : std_logic;
signal M_ABus_D : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal M_BE_D : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal M_busLock_D : std_logic;
signal M_request_D : std_logic;
signal M_RNW_D : std_logic;
signal M_select_D : std_logic;
signal M_seqAddr_D : std_logic;
signal SLAVE_MEM : std_logic_vector (0 to 31);
signal MASTER_MEM : std_logic_vector (0 to 31);
signal MASTER_MEM_SET : std_logic;
signal ddr_address: std_logic_vector(31 downto 0) :=X"00000000";
signal we: std_logic :='0';
signal go, go_D : std_logic :='0';
signal burst, burst_D : std_logic :='1';
signal reset, reset_D, last_reset : std_logic :='1';
-- jpeg
signal jpeg_OPB_datavalid : std_logic :='0';
signal jpeg_width, jpeg_height : std_logic_vector(15 downto 0) :=(others=>'0');
signal jpeg_sampling : std_logic_vector(1 downto 0) :=(others=>'0');
signal jpeg_red, jpeg_green, jpeg_blue : std_logic_vector(7 downto 0) :=(others=>'0');
signal jpeg_error, jpeg_eoi, jpeg_datavalid, jpeg_ready : std_logic :='0';
signal jpeg_context : std_logic_vector(3 downto 0) :=(others=>'0');
 
-- vga
signal vga_ready : std_logic :='0';
 
-- -- debug
-- signal jpeg_chipscope : std_logic_vector(127 downto 0) :=(others=>'0');
-- signal vga_chipscope : std_logic_vector(127 downto 0) :=(others=>'0');
-- signal BUTTONs_deb : std_logic_vector(4 downto 0) :=(others=>'1');
-- signal SWITCHEs_deb, SWITCHEs_deb_D : std_logic_vector(3 downto 0) :=(others=>'1');
-- signal LEDs_intern : std_logic_vector(3 downto 0) := "1111";
 
-- quick n dirty
type address_states is (repeat_frame, continue);
signal address_state, address_state_D : address_states := repeat_frame;
 
signal eoi_counter, eoi_counter_D : std_logic_vector(3 downto 0) :=(others=>'0');
signal eoi_counter_threshold, eoi_counter_threshold_D : std_logic_vector(3 downto 0) :="0001";
signal old_ddr_address, old_ddr_address_D : std_logic_vector(31 downto 0) :=X"00000000";
signal soi, soi_D, eoi, eoi_D, eoi_hold, eoi_hold_D : std_logic :='0';
signal received_ff, received_ff_D : std_logic :='0';
 
signal pause, pause_D : std_logic :='1';
signal slower, slower_D, last_slower : std_logic :='1';
signal faster, faster_D, last_faster : std_logic :='1';
signal next_frame, next_frame_D : std_logic :='0';
 
 
 
begin
 
-- **********************************************************************************************
-- * Debugging
-- **********************************************************************************************
 
--------------------------------------------------------------
---- Chipscope Stuff
--------------------------------------------------------------
--i_icon : icon
--port map(
-- control0 => control0
--);
--
--i_ila : ila
--port map(
-- control => control0,
-- clk => OPB_Clk,
-- trig0 => trig0
--);
 
--process(SWITCHES_deb)
--begin
-- case SWITCHES_deb is
-- when "1111" =>
-- trig0 <= ddr_address &
---- jpeg_width & jpeg_height &
-- old_ddr_address &
---- jpeg_red & jpeg_green & jpeg_blue & jpeg_error & jpeg_eoi & jpeg_datavalid & jpeg_ready & jpeg_context &
-- OPB_DBus &
-- vga_ready & go & burst & reset & "000" & address_state_cs_flag & we & jpeg_ready & jpeg_context & jpeg_error & received_ff & jpeg_eoi & pause & next_frame & slower & faster & eoi_hold & eoi & soi & eoi_counter_threshold & eoi_counter;
-- when "1110" =>
-- trig0 <= vga_chipscope;
-- when "1101" =>
-- trig0 <= jpeg_chipscope;
------ when "0011" =>
---- when "0100" =>
---- when "0101" =>
---- when "0110" =>
---- when "0111" =>
---- when "1000" =>
---- when "1001" =>
---- when "1010" =>
---- when "1011" =>
---- when "1100" =>
---- when "1101" =>
---- when "1110" =>
-- when others =>
-- end case;
--end process;
--------------------------------------------------------------
 
 
------------------------------------------------------------------
---- LEDs debugging
------------------------------------------------------------------
--process(LEDs_intern, SWITCHEs_deb)
--begin
-- case SWITCHEs_deb is
-- when "1111" =>
-- LEDs <= LEDs_intern;
-- when "1110" =>
-- LEDs <= not jpeg_sampling & not jpeg_error & not go;
-- when "1101" =>
-- LEDs <= eoi_counter_threshold;
-- when "1100" =>
-- LEDs <= not OPB_retry & not OPB_xferAck & not OPB_timeout & not jpeg_error;
-- when "1001" =>
-- LEDs <= not OPB_retry_hold & not OPB_xferAck_hold & not OPB_timeout_hold & not jpeg_error;
-- when others =>
-- LEDs <= go & burst & burst & go;
-- end case;
--end process;
------------------------------------------------------------------
 
-- **********************************************************************************************
-- * debounce buttons and switches
-- **********************************************************************************************
--process(OPB_Clk)
--begin
-- if rising_edge(OPB_Clk) then
-- counter <= counter + 1;
-- last_counter <= counter(8);
--
-- if counter(8)='1' and last_counter='0' then
-- BUTTONs_deb <= BUTTONs;
---- SWITCHEs_deb <= SWITCHEs;
-- end if;
--
-- end if;
--end process;
 
 
 
-- **********************************************************************************************
-- * Port Maps
-- **********************************************************************************************
 
--------------------------------------------------------------
-- JPEG - Decoder
--------------------------------------------------------------
jpeg_decoder:jpeg
port map(
Clk => OPB_Clk,
data_i => OPB_DBus,
reset_i => reset,
eoi_o => jpeg_eoi,
error_o => jpeg_error,
-- -- debug
-- LEDs => LEDs_intern,
-- BUTTONs => BUTTONs_deb,
-- SWITCHEs => SWITCHEs_deb,
-- chipscope_o => jpeg_chipscope,
--
context_o => jpeg_context,
red_o => jpeg_red,
green_o => jpeg_green,
blue_o => jpeg_blue,
width_o => jpeg_width,
height_o => jpeg_height,
sampling_o => jpeg_sampling,
 
datavalid_i => jpeg_OPB_datavalid,
datavalid_o => jpeg_datavalid,
ready_i => vga_ready,
ready_o => jpeg_ready
);
--------------------------------------------------------------
jpeg_OPB_datavalid <= we;
we <= MASTER_MEM_SET and OPB_xferAck;
 
 
 
vga_core:vga
port map(
Clk => OPB_Clk,
reset_i => reset,
eoi_i => jpeg_context(3),
red_i => jpeg_red,
green_i => jpeg_green,
blue_i => jpeg_blue,
width_i => jpeg_width,
height_i => jpeg_height,
sampling_i => jpeg_sampling,
 
VGA_OUT_PIXEL_CLOCK => VGA_OUT_PIXEL_CLOCK,
VGA_COMP_SYNCH => VGA_COMP_SYNCH,
VGA_OUT_BLANK_Z => VGA_OUT_BLANK_Z,
VGA_HSYNCH => VGA_HSYNCH,
VGA_VSYNCH => VGA_VSYNCH,
VGA_OUT_RED => VGA_OUT_RED,
VGA_OUT_GREEN => VGA_OUT_GREEN,
VGA_OUT_BLUE => VGA_OUT_BLUE,
 
-- -- chipscope-debugging
-- chipscope_o => vga_chipscope,
 
-- flow controll
datavalid_i => jpeg_datavalid,
ready_o => vga_ready
);
 
 
 
 
 
 
-- **********************************************************************************************
-- * Processes
-- **********************************************************************************************
 
 
------------------------------------------------------------
-- eoi and soi detection
------------------------------------------------------------
process(OPB_DBus, received_ff)
begin
 
soi_D <= '0';
eoi_D <= '0';
received_ff_D <= '0';
 
if(OPB_DBus(0 to 15)=X"FFD9" or
OPB_DBus(8 to 23)=X"FFD9" or
OPB_DBus(16 to 31)=X"FFD9" or
(OPB_Dbus(0 to 7) =X"D9" and received_ff='1') ) then
eoi_D <='1';
end if;
 
if(OPB_DBus(0 to 15)=X"FFD8" or
OPB_DBus(8 to 23)=X"FFD8" or
OPB_DBus(16 to 31)=X"FFD8" or
(OPB_Dbus(0 to 7) =X"D8" and received_ff='1') ) then
soi_D <='1';
end if;
 
if (OPB_DBus(24 to 31)=X"FF") then
received_ff_D <= '1';
end if;
end process;
 
process(OPB_Clk)
begin
if rising_edge(OPB_Clk) then
if reset='1' then
soi <= '0';
eoi <= '0';
received_ff <= '0';
elsif(we='1') then
soi <= soi_D;
eoi <= eoi_D;
received_ff <= received_ff_D;
end if;
end if;
end process;
------------------------------------------------------------
 
 
 
 
 
 
 
------------------------------------------------------------
-- keep address in sync with data
------------------------------------------------------------
process(OPB_Clk)
begin
if rising_edge(OPB_Clk) then
if reset='1' or OPB_DBus=X"454e4445" then -- OPB_DBus=X"454e4445" ("ENDE" in ASCII) is a very ugly proof of concept hack
ddr_address <= X"00000000";
elsif (jpeg_eoi='1' and eoi_hold='0') then
ddr_address <= old_ddr_address;
elsif we ='1' and jpeg_ready='1' then
ddr_address <= ddr_address+4;
end if;
end if;
end process;
------------------------------------------------------------
 
 
 
 
 
------------------------------------------------------------
-- decide whether this or following frame to be displayed
------------------------------------------------------------
process( eoi_hold, old_ddr_address, eoi_counter, address_state, soi, ddr_address, jpeg_eoi,
eoi_counter_threshold, pause, next_frame)
begin
eoi_hold_D <= eoi_hold;
old_ddr_address_D <= old_ddr_address;
eoi_counter_D <= eoi_counter;
address_state_D <= address_state;
 
 
if jpeg_eoi='1' then
eoi_counter_D <= eoi_counter+1;
end if;
 
 
case address_state is
when repeat_frame =>
if (jpeg_eoi='1' and ((eoi_counter=eoi_counter_threshold and pause='0') or next_frame='1')) then
eoi_counter_D <= (others=>'0');
address_state_D <= continue;
end if;
when continue =>
if eoi='1' then
eoi_hold_D<='1';
end if;
if jpeg_eoi='1' and eoi_counter_threshold/="0000" then
address_state_D <= repeat_frame;
end if;
end case;
 
 
-- independant from state because it is not certain whether jpeg_eoi or soi comes first
if eoi_hold='1' and soi='1' then
old_ddr_address_D <= ddr_address-4;
eoi_hold_D<='0';
end if;
 
end process;
 
 
 
process(OPB_Clk)
begin
if rising_edge(OPB_Clk) then
if reset='1' then
eoi_hold <= '0';
old_ddr_address<= X"00000000";
eoi_counter <= (others=>'0');
address_state <= repeat_frame;
else
eoi_hold <= eoi_hold_D;
old_ddr_address<= old_ddr_address_D;
eoi_counter <= eoi_counter_D;
address_state <= address_state_D;
end if;
end if;
end process;
 
------------------------------------------------------------
 
 
--------------------------------------------------------------
-- adjust the framerate
--------------------------------------------------------------
process(faster, slower, eoi_counter_threshold)
begin
eoi_counter_threshold_D <= eoi_counter_threshold;
if faster='1' and last_faster='0' and eoi_counter_threshold/="0000" then
eoi_counter_threshold_D <= eoi_counter_threshold-1;
end if;
if slower='1' and last_slower='0' and eoi_counter_threshold/="1111" then
eoi_counter_threshold_D <= eoi_counter_threshold+1;
end if;
end process;
 
process(OPB_Clk)
begin
if rising_edge(OPB_Clk) then
if reset='1' then
eoi_counter_threshold<="0001";
else
eoi_counter_threshold<=eoi_counter_threshold_D;
end if;
end if;
end process;
--------------------------------------------------------------
 
 
 
 
 
 
 
 
 
--------------------------------------------------------------
---- configure bus transfer
--------------------------------------------------------------
process(OPB_CLK)
begin
if rising_edge(OPB_CLK) then
 
faster <= faster_D;
slower <= slower_D;
last_faster <= faster;
last_slower <= slower;
 
if reset='1' then
go <= '0';
burst <= '1';
reset <= '0';
-- SWITCHEs_deb <= (others=>'1');
pause <= '1';
next_frame <= '0';
else
go <= go_D;
burst <= burst_D;
reset <= reset_D;
-- SWITCHEs_deb <= SWITCHEs_deb_D;
pause <= pause_D;
next_frame <= next_frame_D;
end if;
 
end if;
end process;
------------------------------------------------------------
 
 
 
 
------------------------------------------------------------
-- Myipif: communicate over the OPB-Bus
------------------------------------------------------------
process (OPB_state, OPB_ABus, OPB_DBus, OPB_RNW, OPB_select, OPB_Rst, OPB_xferAck, OPB_MGrant,
ddr_address, go, burst, pause, next_frame, jpeg_eoi, --SWITCHEs_deb,
jpeg_ready, jpeg_error, reset)
begin
Sl_toutSup_D <= '0';
Sl_xferAck_D <= '0';
Sl_errAck_D <= '0';
Sl_retry_D <= '0';
Sl_DBus_D <= X"00000000";
M_ABus_D <= X"00000000";
M_BE_D <= (others => '1');
M_busLock_D <= '0';
M_request_D <= '0';
M_RNW_D <= '0';
M_select_D <= '0';
M_seqAddr_D <= '0';
 
go_D <= go;
burst_D <= burst;
reset_D <= '0';
-- SWITCHEs_deb_D <= SWITCHEs_deb;
pause_D <= pause;
 
next_frame_D <= next_frame;
if jpeg_eoi='1' then
next_frame_D <= '0';
end if;
faster_D <= '0';
slower_D <= '0';
 
 
MASTER_MEM_SET <= '0';
case OPB_state is
when idle =>
OPB_next_state <= idle;
 
----
-- OPB-Bus configuration (via ppc and UART)
if (OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000001") then
go_D <= '1';
 
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000002") then
go_D <= '0';
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000003") then
burst_D <= '1';
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000004") then
burst_D <= '0';
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000005") then
reset_D <= '1';
-- elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000006") then
-- SWITCHEs_deb_D(0) <= '0';
--
-- elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000007") then
-- SWITCHEs_deb_D(0) <= '1';
--
-- elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000008") then
-- SWITCHEs_deb_D(1) <= '0';
--
-- elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000009") then
-- SWITCHEs_deb_D(1) <= '1';
--
-- elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"0000000A") then
-- SWITCHEs_deb_D(2) <= '0';
--
-- elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"0000000B") then
-- SWITCHEs_deb_D(2) <= '1';
--
-- elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"0000000C") then
-- SWITCHEs_deb_D(3) <= '0';
--
-- elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"0000000D") then
-- SWITCHEs_deb_D(3) <= '1';
--
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"0000000E") then
pause_D <= '1';
 
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"0000000F") then
pause_D <= '0';
 
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000010") then
next_frame_D <= '1';
 
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000011") then
faster_D <= '1';
 
elsif(OPB_ABus(0 to 31)=X"50000004" and OPB_RNW='0' and OPB_DBus=X"00000012") then
slower_D <= '1';
 
----------
-- get jpeg data from ram
elsif (jpeg_ready='1' and jpeg_error='0' and go='1' and OPB_DBus/=X"454e4445") then
OPB_next_state <= MasterRead1;
end if;
----------
 
 
 
when MasterRead1 =>
M_request_D <= '1';
if (OPB_MGrant = '1') then
M_seqAddr_D <= burst;
M_busLock_D <= '1';
OPB_next_state <= MasterRead2;
else
OPB_next_state <= MasterRead1;
end if;
when MasterRead2 =>
M_seqAddr_D <= burst;
M_busLock_D <= '1';
M_select_D <= '1';
M_RNW_D <= '1';
M_ABus_D <= "000" & ddr_address(28 downto 0); -- begin with 3 zeroes to prevent writing to sonething different than DDR-RAM
MASTER_MEM_SET <= '1';
if(jpeg_ready='1' and jpeg_error='0' and burst='1' and OPB_DBus/=X"454e4445") then
OPB_next_state <= MasterRead2;
else
OPB_next_state <= idle;
end if;
 
end case;
-- Reset
if (OPB_Rst = '1' or reset='1' or jpeg_eoi='1') then
OPB_next_state <= idle;
Sl_DBus_D <= X"00000000";
Sl_xferAck_D <= '0';
M_ABus_D <= X"00000000";
end if;
end process;
------------------------------------------------------------
 
 
------------------------------------------------------------
-- OPB_state: Reset and Synchronization
------------------------------------------------------------
process (OPB_Clk, OPB_Rst)
begin
if (OPB_Rst='1') then
OPB_state <= idle;
elsif (OPB_Clk'event and OPB_Clk='1') then
OPB_state <= OPB_next_state;
end if;
end process;
------------------------------------------------------------
 
------------------------------------------------------------
-- Synchronize other signals
------------------------------------------------------------
process(OPB_CLK)
begin
if rising_edge(OPB_CLK) then
Sl_toutSup <= Sl_toutSup_D;
Sl_xferAck <= Sl_xferAck_D;
Sl_errAck <= Sl_errAck_D;
Sl_DBus <= Sl_DBus_D;
Sl_retry <= Sl_retry_D;
 
M_ABus <= M_ABus_D;
M_BE <= M_BE_D;
M_busLock <= M_busLock_D;
M_request <= M_request_D;
M_RNW <= M_RNW_D;
M_select <= M_select_D;
M_seqAddr <= M_seqAddr_D;
end if;
end process;
------------------------------------------------------------
 
end IMP;
/myipif/hdl/vhdl/vga_signals.vhd
0,0 → 1,374
---------------------------------------------------------------
-- This code is a simplified port from the Verilog sources that can be found here:
-- http://embedded.olin.edu/xilinx_docs/projects/bitvga-v2p.php
--
-- The Verilog sources are based on code from Xilinx and released under
-- "Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License"
--
-- with the note, that Xilinx claims the following copyright for their
-- initial code:
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
---------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Needed for 'OFDDRTRSE'
library UNISIM;
use UNISIM.VCOMPONENTS.all;
 
 
entity vga_signals is
Generic(
CHARACTER_DECODE_DELAY : integer := 4;
 
-- 640 X 480 @ 60Hz with a 25.175MHz pixel clock
H_ACTIVE : integer := 640; -- pixels
H_FRONT_PORCH : integer := 16; -- pixels
H_SYNCH : integer := 96; -- pixels
H_BACK_PORCH : integer := 48; -- pixels
H_TOTAL : integer := 800; -- pixels
V_ACTIVE : integer := 480; -- lines
V_FRONT_PORCH : integer := 11; -- lines
V_SYNCH : integer := 2; -- lines
V_BACK_PORCH : integer := 31; -- lines
V_TOTAL : integer := 524; -- lines
CLK_MULTIPLY : integer := 2; -- 100 * 2/8 = 25.000 MHz
CLK_DIVIDE : integer := 8
);
Port (
system_clock : in std_logic;
VGA_OUT_PIXEL_CLOCK : out std_logic;
VGA_COMP_SYNCH : out std_logic;
VGA_OUT_BLANK_Z : out std_logic;
VGA_HSYNCH : out std_logic;
VGA_VSYNCH : out std_logic;
 
o_pixel_clock : out std_logic;
o_pixel_count : out std_logic_vector(10 downto 0);
o_line_count : out std_logic_vector( 9 downto 0)
);
end vga_signals;
 
 
architecture Behavioral of vga_signals is
 
--******************************************************
--** Components
--******************************************************
 
-- Clock Buffer
component BUFG
port (
I: in STD_LOGIC;
O: out STD_LOGIC
);
end component;
 
-- DCM to generate pixel_clock
component DCM
generic (
DLL_FREQUENCY_MODE : string := "LOW";
DFS_FREQUENCY_MODE : string := "LOW";
CLK_FEEDBACK : string := "1X";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
CLKFX_MULTIPLY : integer := CLK_MULTIPLY;
CLKFX_DIVIDE : integer := CLK_DIVIDE;
CLKIN_DIVIDE_BY_2 : boolean := FALSE;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
STARTUP_WAIT : boolean := false;
PHASE_SHIFT : integer := 0 ;
CLKDV_DIVIDE : real := 4.0
);
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector(7 downto 0)
);
end component;
 
-- 16 Bit Shift Register for Clockgen
component SRL16
-- synthesis translate_off
generic (
INIT : std_logic_vector := X"000F"
);
-- synthesis translate_on
port (
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
 
-- ** End Components *************************************
 
signal pixel_count : std_logic_vector(10 downto 0);
signal line_count : std_logic_vector(9 downto 0);
signal reset, hsynch, vsynch, comp_synch, blank : std_logic;
signal dcm_reset, dcm_locked: std_logic;
signal pixel_clock, pixel_clock_buffered, n_pixel_clock_buffered, system_clock_dcm_in, system_clock_dcm_out : std_logic;
signal v_c_synch, h_c_synch, h_blank, v_blank : std_logic;
signal hsynch_delay, hsynch_delay0, vsynch_delay, vsynch_delay0 : std_logic;
 
begin
 
--******************************************************
--** Clockgen: generate and buffer clocks
--******************************************************
 
-- buffering clocks
buffg_for_system_clock: BUFG
port map (
I => system_clock_dcm_out,
O => system_clock_dcm_in
);
buffg_for_pixel_clock: BUFG
port map (
I => pixel_clock,
O => pixel_clock_buffered
);
 
-- DCM for generating pixel_clock
dcm_for_pixel_clock: DCM
port map (
CLKIN => system_clock,
CLKFB => system_clock_dcm_in,
DSSEN => '0',
PSINCDEC => '0',
PSEN => '0',
PSCLK => '0',
RST => dcm_reset,
CLK0 => system_clock_dcm_out,
CLKFX => pixel_clock,
LOCKED => dcm_locked
);
 
-- 16 Bit Shift Register
SRL16_INSTANCE_NAME : SRL16
-- synthesis translate_off
generic map(
INIT => X"000F"
)
-- synthesis translate_on
port map (
Q => dcm_reset,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CLK => system_clock,
D => '0'
);
 
reset <= not dcm_locked;
-- ** End Clockgen *************************************
 
 
 
--******************************************************
--** Timings: generate timing signals
--******************************************************
 
--CREATE THE HORIZONTAL LINE PIXEL COUNTER
process (pixel_clock_buffered, reset)
begin
pixel_count <= pixel_count;
if (reset='1') then
pixel_count <= (others => '0');
elsif (pixel_clock_buffered'event and pixel_clock_buffered='1') then
pixel_count <= pixel_count + 1; --"00000000001";
if (pixel_count=H_TOTAL-1) then
pixel_count <= (others => '0'); --"00000000000";
end if;
end if;
end process;
 
 
-- CREATE THE HORIZONTAL SYNCH PULSE
process (pixel_clock_buffered, reset)
begin
hsynch <= hsynch;
if (reset='1') then
hsynch <= '0';
elsif (pixel_clock_buffered'event and pixel_clock_buffered='1') then --or (reset'event and reset='1') then
if (pixel_count = (H_ACTIVE + H_FRONT_PORCH -1)) then
hsynch <= '1';
elsif (pixel_count = (H_TOTAL - H_BACK_PORCH -1)) then
hsynch <= '0';
end if;
end if;
end process;
 
 
-- CREATE THE VERTICAL FRAME LINE COUNTER
process (pixel_clock_buffered, reset)
begin
line_count <= line_count;
if (reset='1') then
line_count <= (others => '0');
elsif (pixel_clock_buffered'event and pixel_clock_buffered='1') then --or (reset'event and reset='1') then
if ((line_count = (V_TOTAL - 1)) and (pixel_count = (H_TOTAL - 1))) then
line_count <= (others => '0');
elsif ((pixel_count = (H_TOTAL - 1))) then
line_count <= line_count + 1;
end if;
end if;
end process;
 
 
-- CREATE THE VERTICAL SYNCH PULSE
process (pixel_clock_buffered, reset)
begin
vsynch <= vsynch;
if (reset='1') then
vsynch <= '0';
elsif (pixel_clock_buffered'event and pixel_clock_buffered='1') then --or (reset'event and reset='1') then
if ((line_count = V_ACTIVE + V_FRONT_PORCH -1) and (pixel_count = H_TOTAL - 1)) then
vsynch <= '1';
elsif ((line_count = (V_TOTAL - V_BACK_PORCH - 1)) and (pixel_count = (H_TOTAL - 1))) then
vsynch <= '0';
end if;
end if;
end process;
 
 
-- ADD TWO PIPELINE DELAYS TO THE SYNCHs COMPENSATE FOR THE DAC PIPELINE DELAY
process (pixel_clock_buffered, reset)
begin
if (reset='1') then
hsynch_delay0 <= '0';
vsynch_delay0 <= '0';
hsynch_delay <= '0';
vsynch_delay <= '0';
elsif (pixel_clock_buffered'event and pixel_clock_buffered='1') then --or (reset'event and reset='1') then
hsynch_delay0 <= hsynch;
vsynch_delay0 <= vsynch;
hsynch_delay <= hsynch_delay0;
vsynch_delay <= vsynch_delay0;
end if;
end process;
 
 
-- CREATE THE HORIZONTAL BLANKING SIGNAL
-- the "-2" is used instead of "-1" because of the extra register delay
-- for the composite blanking signal
process (pixel_clock_buffered, reset)
begin
h_blank <= h_blank;
if (reset='1') then
h_blank <= '0';
elsif (pixel_clock_buffered'event and pixel_clock_buffered='1') then --or (reset'event and reset='1') then
if (pixel_count = (H_ACTIVE -2)) then
h_blank <= '1';
elsif (pixel_count = (H_TOTAL -2)) then
h_blank <= '0';
end if;
end if;
end process;
 
 
-- CREATE THE VERTICAL BLANKING SIGNAL
-- the "-2" is used instead of "-1" in the horizontal factor because of the extra
-- register delay for the composite blanking signal
process (pixel_clock_buffered, reset)
begin
if (reset='1') then
v_blank <= '0';
elsif (pixel_clock_buffered'event and pixel_clock_buffered='1') then --or (reset'event and reset='1') then
if ((line_count = (V_ACTIVE - 1) and (pixel_count = H_TOTAL - 2))) then
v_blank <= '1';
elsif ((line_count = (V_TOTAL - 1)) and (pixel_count = (H_TOTAL - 2))) then
v_blank <= '0';
end if;
end if;
end process;
 
 
-- CREATE THE COMPOSITE BLANKING SIGNAL
process (pixel_clock_buffered, reset)
begin
if (pixel_clock_buffered'event and pixel_clock_buffered='1') then --or (reset'event and reset='1') then
blank <= (not reset) and (h_blank or v_blank);
end if;
end process;
 
 
--******************************************************
--** Output: connect output signals
--******************************************************
 
-- don't ask me why I do this,
-- generate VGA_OUT_PIXEL_CLOCK:
OFDDRTRSE_inst : OFDDRTRSE
port map (
O => VGA_OUT_PIXEL_CLOCK,
C0 => pixel_clock_buffered,
C1 => n_pixel_clock_buffered,
CE => '1',
D0 => '0',
D1 => '1',
R => reset,
S => '0',
T => '0'
);
n_pixel_clock_buffered <= not pixel_clock_buffered;
 
o_pixel_clock <= pixel_clock_buffered;
 
process (pixel_clock_buffered, reset)
begin
-- if rising_edge(pixel_clock_buffered) then
if (pixel_clock_buffered'event and pixel_clock_buffered='1') then --or (reset'event and reset='1') then
VGA_COMP_SYNCH <= not reset;
VGA_OUT_BLANK_Z <= not blank and not reset;
VGA_HSYNCH <= hsynch or reset;
VGA_VSYNCH <= vsynch or reset;
o_pixel_count <= pixel_count;
o_line_count <= line_count;
end if;
end process;
-- ** End Output *************************************
 
end Behavioral;
 
/myipif/data/myipif_v2_1_0.pao
0,0 → 1,26
##############################################################################
## Filename: /home/smanz/Diplomarbeit/learn_vhdl/trunk/EDK-pong-uart/pcores/myipif/data/myipif_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Jul 3 11:09:07 2007 (by Create and Import Peripheral Wizard)
##############################################################################
 
lib myipif jpeg_checkff_fifo vhdl
lib myipif jpeg_check_FF vhdl
lib myipif jpeg_dequant_multiplier vhdl
lib myipif jpeg_dequantize vhdl
lib myipif jpeg_dezigzag vhdl
lib myipif jpeg_header vhdl
lib myipif jpeg_ht_nr_of_symbols vhdl
lib myipif jpeg_ht_tables vhdl
lib myipif jpeg_huffman vhdl
lib myipif jpeg_idct_core_12 vhdl
lib myipif jpeg_idct vhdl
lib myipif jpeg_input_fifo vhdl
lib myipif jpeg_qt_sr vhdl
lib myipif jpeg_upsampling vhdl
lib myipif jpeg vhdl
lib myipif jpeg_YCbCr2RGB vhdl
lib myipif vga_memory vhdl
lib myipif vga_signals vhdl
lib myipif vga vhdl
lib myipif myipif vhdl
/myipif/data/myipif_v2_1_0.mpd
0,0 → 1,70
###################################################################
##
## Name : myipif
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
 
BEGIN myipif
 
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION CORE_STATE = DEVELOPMENT
OPTION IP_GROUP = MICROBLAZE:PPC:USER
 
 
## Bus Interfaces
BUS_INTERFACE BUS = MSOPB, BUS_TYPE = MASTER_SLAVE, BUS_STD = OPB
 
## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0x50000000, DT = std_logic_vector, BUS = MSOPB, ADDRESS = BASE, PAIR = C_HIGHADDR
PARAMETER C_HIGHADDR = 0x5000ffff, DT = std_logic_vector, BUS = MSOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = MSOPB
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = MSOPB
PARAMETER C_FAMILY = virtex2p, DT = STRING
PARAMETER C_SDRAM_ADDR = 0x00000000, DT = std_logic_vector
 
## Ports
PORT OPB_Clk = "", DIR = I, BUS = MSOPB, SIGIS = CLK
PORT OPB_Rst = OPB_Rst, DIR = I, BUS = MSOPB, SIGIS = RST
PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
PORT Sl_errAck = Sl_errAck, DIR = O, BUS = MSOPB
PORT Sl_retry = Sl_retry, DIR = O, BUS = MSOPB
PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = MSOPB
PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = MSOPB
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB
PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = MSOPB
PORT OPB_select = OPB_select, DIR = I, BUS = MSOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = MSOPB
PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB
PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB
PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB
PORT M_request = M_request, DIR = O, BUS = MSOPB
PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB
PORT M_select = M_select, DIR = O, BUS = MSOPB
PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB
PORT OPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB
PORT OPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB
PORT OPB_retry = OPB_retry, DIR = I, BUS = MSOPB
PORT OPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB
PORT OPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB
 
PORT LEDs = "", DIR = O, VEC = [3:0]
PORT BUTTONs = "", DIR = I, VEC = [4:0]
PORT SWITCHEs = "", DIR = I, VEC = [3:0]
PORT VGA_OUT_PIXEL_CLOCK = "", DIR = O
PORT VGA_COMP_SYNCH = "", DIR = O
PORT VGA_OUT_BLANK_Z = "", DIR = O
PORT VGA_HSYNCH = "", DIR = O
PORT VGA_VSYNCH = "", DIR = O
PORT VGA_OUT_RED = "", DIR = O, VEC = [7:0]
PORT VGA_OUT_GREEN = "", DIR = O, VEC = [7:0]
PORT VGA_OUT_BLUE = "", DIR = O, VEC = [7:0]
 
END

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