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URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mkjpeg/trunk/design
    from Rev 31 to Rev 32
    ↔ Reverse comparison
  •

Rev 31 → Rev 32

/quantizer/QUANTIZER.vhd
1,7 → 1,7
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
-- --
16,8 → 16,6
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Pipelined DCT Quantizer --
-- Pipeline delay: 2*SIZE_C+INTERN_PIPE_C --
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
30,7 → 28,7
generic
(
SIZE_C : INTEGER := 12;
RAMQADDR_W : INTEGER := 6;
RAMQADDR_W : INTEGER := 7;
RAMQDATA_W : INTEGER := 8
);
port
40,8 → 38,9
di : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
divalid : in STD_LOGIC;
qdata : in std_logic_vector(7 downto 0);
qwaddr : in std_logic_vector(5 downto 0);
qwaddr : in std_logic_vector(6 downto 0);
qwren : in std_logic;
cmp_idx : in unsigned(1 downto 0);
do : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
dovalid : out STD_LOGIC
52,7 → 51,7
constant INTERN_PIPE_C : INTEGER := 3;
signal romaddr_s : UNSIGNED(RAMQADDR_W-1 downto 0);
signal romaddr_s : UNSIGNED(RAMQADDR_W-2 downto 0);
signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0);
signal romdatao_s : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0);
signal divisor_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
64,6 → 63,8
signal pipeline_reg : STD_LOGIC_VECTOR(4 downto 0);
signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0);
signal do_rdiv : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal table_select : std_logic;
begin
----------------------------
86,25 → 87,7
q => romdatao_s
);
----------------------------
-- S_DIVIDER
----------------------------
--U_S_DIVIDER : entity work.s_divider
-- generic map
-- (
-- SIZE_C => SIZE_C
-- )
-- port map
-- (
-- rst => rst,
-- clk => clk,
-- a => di_d1,
-- d => divisor_s,
--
-- q => do_s,
-- r => remainder_s, -- if ever used, needs to be 1T delayed
-- round => round_s
-- );
 
divisor_s(RAMQDATA_W-1 downto 0) <= romdatao_s;
divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
120,32 → 103,27
q => do_s
) ;
do <= do_s;
slv_romaddr_s <= STD_LOGIC_VECTOR(romaddr_s);
slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);
------------------------------
---- round to nearest integer
-- Quantization sub table select
------------------------------
--process(clk)
--begin
-- if clk = '1' and clk'event then
-- if rst = '1' then
-- do <= (others => '0');
-- else
-- -- round to nearest integer?
-- if round_s = '1' then
-- -- negative number, subtract 1
-- if sign_bit_pipe(sign_bit_pipe'length-1) = '1' then
-- do <= STD_LOGIC_VECTOR(SIGNED(do_s)-TO_SIGNED(1,SIZE_C));
-- -- positive number, add 1
-- else
-- do <= STD_LOGIC_VECTOR(SIGNED(do_s)+TO_SIGNED(1,SIZE_C));
-- end if;
-- else
-- do <= do_s;
-- end if;
-- end if;
-- end if;
--end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
table_select <= '0';
else
-- luminance table select
if cmp_idx = 0 then
table_select <= '0';
-- chrominance table select
else
table_select <= '1';
end if;
end if;
end if;
end process;
----------------------------
-- address incrementer
160,7 → 138,7
sign_bit_pipe <= (others => '0');
else
if divalid = '1' then
romaddr_s <= romaddr_s + TO_UNSIGNED(1,RAMQADDR_W);
romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);
end if;
pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
/top/JpegEnc.vhd
79,7 → 79,7
architecture RTL of JpegEnc is
 
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(5 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
310,6 → 310,7
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
 
-- RLE
rle_buf_sel => rle_buf_sel,
/JFIFGen/JFIFGen.vhd
58,7 → 58,7
-- HOST IF
qwren : in std_logic;
qwaddr : in std_logic_vector(5 downto 0);
qwaddr : in std_logic_vector(6 downto 0);
qwdata : in std_logic_vector(7 downto 0);
image_size_reg : in std_logic_vector(31 downto 0);
image_size_reg_wr : in std_logic;
83,6 → 83,8
constant C_SIZE_X_L : integer := 28;
constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9";
constant C_QLUM_BASE : integer := 44;
constant C_QCHR_BASE : integer := 44+69;
 
signal hr_data : std_logic_vector(7 downto 0);
178,8 → 180,17
end if;
-- write Quantization table
elsif qwren = '1' then
hr_waddr <= std_logic_vector( resize(unsigned(qwaddr),hr_waddr'length) +
to_unsigned(44,hr_waddr'length));
-- luminance table select
if qwaddr(6) = '0' then
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QLUM_BASE,hr_waddr'length));
else
-- chrominance table select
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QCHR_BASE,hr_waddr'length));
end if;
hr_we <= '1';
hr_data <= qwdata;
end if;
/common/JPEG_PKG.vhd
27,12 → 27,12
package JPEG_PKG is
 
-- do not change, constant
constant C_HDR_SIZE : integer := 338;
constant C_HDR_SIZE : integer := 407;
-- warning! this parameter heavily affects memory size required
-- if expected image width is known change this parameter to match this
-- otherwise some onchip RAM will be wasted and never used
constant C_MAX_LINE_WIDTH : integer := 1024;
constant C_MAX_LINE_WIDTH : integer := 640;
 
-- 0=highest clock per pixel performance
-- 1=memory used by BUF_FIFO halved, speed performance reduced by circa 18%
/zigzag/ZZ_TOP.VHD
34,7 → 34,8
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
 
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
48,6 → 49,7
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- RLE
rle_buf_sel : in std_logic;
62,7 → 64,7
-- HOST
qdata : in std_logic_vector(7 downto 0);
qaddr : in std_logic_vector(5 downto 0);
qaddr : in std_logic_vector(6 downto 0);
qwren : in std_logic
);
end entity ZZ_TOP;
138,7 → 140,7
generic map
(
SIZE_C => 12,
RAMQADDR_W => 6,
RAMQADDR_W => 7,
RAMQDATA_W => 8
)
port map
150,6 → 152,7
qdata => qdata,
qwaddr => qaddr,
qwren => qwren,
cmp_idx => zig_sm_settings.cmp_idx,
do => quant_dout,
dovalid => quant_dovalid
/hostif/HostIF.vhd
41,7 → 41,7
-- Quantizer RAM
qdata : out std_logic_vector(7 downto 0);
qaddr : out std_logic_vector(5 downto 0);
qaddr : out std_logic_vector(6 downto 0);
qwren : out std_logic;
-- CTRL
75,8 → 75,10
constant C_ENC_STS_REG : std_logic_vector(31 downto 0) := X"0000_000C";
constant C_COD_DATA_ADDR_REG : std_logic_vector(31 downto 0) := X"0000_0010";
constant C_ENC_LENGTH_REG : std_logic_vector(31 downto 0) := X"0000_0014";
constant C_QUANTIZER_RAM : std_logic_vector(31 downto 0) :=
constant C_QUANTIZER_RAM_LUM : std_logic_vector(31 downto 0) :=
X"0000_01" & "------00";
constant C_QUANTIZER_RAM_CHR : std_logic_vector(31 downto 0) :=
X"0000_02" & "------00";
constant C_IMAGE_RAM : std_logic_vector(31 downto 0) :=
X"001" & "------------------00";
91,8 → 93,6
signal rd_dval : std_logic;
signal data_read : std_logic_vector(31 downto 0);
signal quantizer_ram_q : std_logic_vector(31 downto 0);
signal image_ram_q : std_logic_vector(31 downto 0);
signal write_done : std_logic;
signal OPB_select_d : std_logic;
105,10 → 105,6
OPB_toutSup <= '0';
OPB_errAck <= '0';
-- temporary!!
quantizer_ram_q <= (others => '0');
image_ram_q <= (others => '0');
img_size_x <= image_size_reg(31 downto 16);
img_size_y <= image_size_reg(15 downto 0);
229,12 → 225,20
null;
end case;
if std_match(OPB_ABus, C_QUANTIZER_RAM) then
if std_match(OPB_ABus, C_QUANTIZER_RAM_LUM) then
qdata <= OPB_DBus_in(qdata'range);
qaddr <= OPB_ABus(qaddr'high+2 downto 2);
qaddr <= '0' & OPB_ABus(qaddr'high+2-1 downto 2);
qwren <= '1';
write_done <= '1';
end if;
if std_match(OPB_ABus, C_QUANTIZER_RAM_CHR) then
qdata <= OPB_DBus_in(qdata'range);
qaddr <= '1' & OPB_ABus(qaddr'high+2-1 downto 2);
qwren <= '1';
write_done <= '1';
end if;
end if;
end if;

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