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URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

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  • This comparison shows the changes necessary to convert path 
    /mkjpeg
    from Rev 18 to Rev 19
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  •

Rev 18 → Rev 19

/branches/main/design/huffman/Huffman.vhd
86,7 → 86,7
 
signal state : T_STATE;
signal rle_buf_sel_s : std_logic;
signal read_cnt : unsigned(5 downto 0);
signal first_rle_word : std_logic;
signal VLC_VLI_sel : std_logic;
signal word_reg : unsigned(C_M-1 downto 0);
signal bit_ptr : unsigned(4 downto 0);
215,7 → 215,7
VLC_size <= (others => '0');
VLC <= (others => '0');
elsif CLK'event and CLK = '1' then
if read_cnt = 0 then
if first_rle_word = '1' then
VLC_size <= unsigned('0' & VLC_DC_size);
VLC <= resize(VLC_DC, VLC'length);
else
336,7 → 336,7
if RST = '1' then
rd_en <= '0';
ready_pb <= '0';
read_cnt <= (others => '0');
first_rle_word <= '0';
VLC_VLI_sel <= '0';
state <= IDLE;
word_reg <= (others => '0');
352,7 → 352,7
when IDLE =>
if start_pb = '1' then
read_cnt <= (others => '0');
first_rle_word <= '1';
VLC_VLI_sel <= '0';
state <= RUN_VLC;
rd_en <= '1';
360,8 → 360,8
when RUN_VLC =>
-- data valid DC or data valid AC
if (d_val_d2 = '1' and read_cnt = 0) or
(d_val = '1' and read_cnt /= 0) then
if (d_val_d2 = '1' and first_rle_word = '1') or
(d_val = '1' and first_rle_word = '0') then
for i in 0 to C_M-1 loop
if i < to_integer(VLC_size) then
word_reg(C_M-1-to_integer(bit_ptr)-i) <= VLC(to_integer(VLC_size)-1-i);
422,10 → 422,10
state <= IDLE;
end if;
else
rd_en <= '1';
read_cnt <= read_cnt + 1;
VLC_VLI_sel <= '0';
state <= RUN_VLC;
rd_en <= '1';
first_rle_word <= '0';
VLC_VLI_sel <= '0';
state <= RUN_VLC;
end if;
end if;
/branches/main/design/mdct/DCT1D.vhd
64,31 → 64,46
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
begin
 
ramwaddro <= ramwaddro_d2;
ramwe <= ramwe_d2;
ramdatai <= dcto_2(DA_W-1 downto 12);
wmemsel <= wmemsel_d2;
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk,rst)
begin
98,23 → 113,12
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
ramwe_s <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwaddro_s <= (others => '0');
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
col_2_reg <= (others => '0');
ramwaddro_d1 <= (others => '0');
even_not_odd <= '0';
even_not_odd_d1 <= '0';
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
179,30 → 183,63
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00") +
(RESIZE(SIGNED(romedatao(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao(4)),DA_W-4) & "0000"),
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00") +
(RESIZE(SIGNED(romodatao(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao(4)),DA_W-4) & "0000"),
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
209,20 → 246,44
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d1(6)),DA_W-6) & "000000") +
(RESIZE(SIGNED(romedatao_d1(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d1(8)),DA_W-8) & "00000000"),
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d1(6)),DA_W-6) & "000000") +
(RESIZE(SIGNED(romodatao_d1(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d1(8)),DA_W-8) & "00000000"),
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
255,9 → 316,17
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
/branches/main/design/mdct/DCT2D.VHD
67,14 → 67,28
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
 
ramraddro_sg:
96,21 → 110,14
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
odv_d0 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
even_not_odd <= '0';
even_not_odd_d1 <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
 
dataready_2_reg <= dataready;
----------------------------------
190,55 → 197,114
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00") +
(RESIZE(SIGNED(romedatao(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao(4)),DA2_W-4) & "0000") +
(RESIZE(SIGNED(romedatao(5)),DA2_W-5) & "00000"),
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00") +
(RESIZE(SIGNED(romodatao(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao(4)),DA2_W-4) & "0000") +
(RESIZE(SIGNED(romodatao(5)),DA2_W-5) & "00000"),
DA2_W));
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(6)),DA2_W-6) & "000000") +
(RESIZE(SIGNED(romedatao_d1(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d1(8)),DA2_W-8) & "00000000") +
(RESIZE(SIGNED(romedatao_d1(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d1(10)),DA2_W-10) & "0000000000"),
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(6)),DA2_W-6) & "000000") +
(RESIZE(SIGNED(romodatao_d1(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d1(8)),DA2_W-8) & "00000000") +
(RESIZE(SIGNED(romodatao_d1(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d1(10)),DA2_W-10) & "0000000000"),
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_2(DA2_W-1 downto 12);
odv <= odv_d2;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
263,14 → 329,26
end if;
end process;
 
p_romdatao_d1 : process(CLK, RST)
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;

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