OpenCores
URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

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  • This comparison shows the changes necessary to convert path 
    /mkjpeg
    from Rev 51 to Rev 52
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  •

Rev 51 → Rev 52

/trunk/tb/wave.do
129,72 → 129,38
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/sof
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/iram_wren
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/iram_wdata
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(10)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(9)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(8)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(7)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(6)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(5)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(4)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(3)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(2)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(1)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/block_lock(0)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_almost_full
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fdct_fifo_hf_full
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fdct_block_cnt
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fdct_fifo_rd
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fdct_fifo_empty
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fdct_fifo_q
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fdct_fifo_hf_full
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_rd
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_data
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_data_d1
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr(7)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr(6)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr(5)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr(4)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr(3)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr(2)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr(1)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_wr(0)
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/wblock_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_empty
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full(7)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full(6)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full(5)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full(4)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full(3)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full(2)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full(1)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_full(0)
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count(0)
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count(1)
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count(2)
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count(3)
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count(4)
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count(5)
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count(6)
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count(7)
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full(7)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full(6)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full(5)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full(4)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full(3)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full(2)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full(1)
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_half_full(0)
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_count
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/pixel_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/last_idx
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/idx_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/wr_idx_reg
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/pixel_cnt
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/line_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramq
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramd
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/ramwaddr_d1
add wave -noupdate -format Literal -height 74 -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/ramwaddr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/ramenw
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramd
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/ramwaddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramwaddr_offset
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramwaddr_base
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramraddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramraddr_base
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramraddr_offset
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/ramenr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_ramwaddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_ramenw
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_ramraddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/fifo_ramenr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/offset_ramwaddr
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/ramraddr
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/write_ptr
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/read_ptr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/pix_inblk_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/line_inblk_cnt
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/write_block_cnt
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_buf_fifo/read_block_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_buf_fifo/ramraddr_int
add wave -noupdate -divider FDCT
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/rst
204,7 → 170,7
add wave -noupdate -format Literal -radix unsigned -expand /jpeg_tb/u_jpegenc/u_fdct/fdct_sm_settings
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/bf_block_cnt
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/bf_fifo_rd
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/bf_fifo_empty
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/bf_dval
add wave -noupdate -format Literal -radix hexadecimal /jpeg_tb/u_jpegenc/u_fdct/bf_fifo_q
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/bf_fifo_hf_full
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/start_int
215,7 → 181,6
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_fdct/fram1_raddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/fram1_rd_d
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/fram1_rd
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/bf_fifo_empty_d1
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/rd_started
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/zz_buf_sel
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/zz_rd_addr
230,10 → 195,6
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/mdct_data_out
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/odv1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/dcto1
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_fdct/x_block_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/y_block_cnt
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_fdct/x_block_cnt_cur
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/y_block_cnt_cur
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/cmp_idx
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/cur_cmp_idx
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/rd_addr
241,7 → 202,6
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/rd_en
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/rd_en_d1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/rdaddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/bf_dval
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/wr_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/dbuf_data
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/dbuf_q
607,9 → 567,9
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_outmux/ram_wren
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_outmux/ram_wraddr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {39105000 ps} 0}
WaveRestoreCursors {{Cursor 4} {15100525000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 55
configure wave -valuecolwidth 83
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
622,4 → 582,4
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {511965 ps} {1652957 ps}
WaveRestoreZoom {3854654563 ps} {22956070813 ps}
/trunk/tb/vhdl/HostBFM.vhd
271,7 → 271,7
wait until rising_edge(clk);
end loop;
--for i in 0 to 10 loop
--for i in 0 to 9 loop
-- wait until rising_edge(clk);
--end loop;
/trunk/design/BufFifo/BUF_FIFO.vhd
57,9 → 57,7
fifo_almost_full : out std_logic;
-- FDCT
fdct_block_cnt : in std_logic_vector(12 downto 0);
fdct_fifo_rd : in std_logic;
fdct_fifo_empty : out std_logic;
fdct_fifo_q : out std_logic_vector(23 downto 0);
fdct_fifo_hf_full : out std_logic
);
72,102 → 70,46
-------------------------------------------------------------------------------
architecture RTL of BUF_FIFO is
 
constant C_NUM_SUBF : integer := C_MAX_LINE_WIDTH/8;
signal pixel_cnt : unsigned(15 downto 0);
signal line_cnt : unsigned(15 downto 0);
 
signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramwaddr : unsigned(log2(C_MAX_LINE_WIDTH*8)-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : unsigned(log2(C_MAX_LINE_WIDTH*8)-1 downto 0);
constant C_SUBF_ADDRW : integer := 7-C_MEMORY_OPTIMIZED;
--constant C_LOG2_NUM_SUBF : integer := integer(log2(real(C_NUM_SUBF)));
signal pix_inblk_cnt : unsigned(7 downto 0);
signal line_inblk_cnt : unsigned(7 downto 0);
type T_DATA_ARR is array (0 to C_NUM_SUBF-1) of std_logic_vector(23 downto 0);
type T_CNT_ARR is array (0 to C_NUM_SUBF-1) of
std_logic_vector(C_SUBF_ADDRW downto 0);
type T_FIFO_RAMADDR is array (0 to C_NUM_SUBF-1) of
STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0);
 
signal fifo_rd : std_logic_vector(C_NUM_SUBF-1 downto 0);
signal fifo_wr : std_logic_vector(C_NUM_SUBF-1 downto 0);
signal fifo_data : std_logic_vector(C_PIXEL_BITS-1 downto 0);
signal fifo_data_d1 : std_logic_vector(C_PIXEL_BITS-1 downto 0);
signal fifo_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
signal fifo_empty : std_logic_vector(C_NUM_SUBF-1 downto 0);
signal fifo_half_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
signal fifo_count : T_CNT_ARR;
signal read_block_cnt : unsigned(12 downto 0);
signal write_block_cnt : unsigned(12 downto 0);
signal pixel_cnt : unsigned(15 downto 0);
signal wblock_cnt : unsigned(12 downto 0);
signal last_idx : unsigned(12 downto 0);
signal idx_reg : unsigned(log2(C_NUM_SUBF)-1 downto 0);
signal wr_idx_reg : unsigned(log2(C_NUM_SUBF)-1 downto 0);
signal ramraddr_int : unsigned(23 downto 0);
signal raddr_base_line : unsigned(23 downto 0);
signal raddr_tmp : unsigned(15 downto 0);
signal ramwaddr_d1 : unsigned(log2(C_MAX_LINE_WIDTH*8)-1 downto 0);
signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramd : STD_LOGIC_VECTOR (C_PIXEL_BITS-1 downto 0);
signal ramwaddr : STD_LOGIC_VECTOR
(log2(C_NUM_SUBF)+C_SUBF_ADDRW-1 downto 0);
signal ramwaddr_offset : unsigned(C_SUBF_ADDRW-1 downto 0);
signal ramwaddr_base : unsigned(log2(C_NUM_SUBF)+C_SUBF_ADDRW downto 0);
signal ramenw : STD_LOGIC;
signal ramenw_m1 : STD_LOGIC;
signal ramenw_m2 : STD_LOGIC;
signal ramraddr : STD_LOGIC_VECTOR
(log2(C_NUM_SUBF)+C_SUBF_ADDRW-1 downto 0);
signal ramraddr_base : unsigned(log2(C_NUM_SUBF)+C_SUBF_ADDRW downto 0);
signal ramraddr_offset : unsigned(C_SUBF_ADDRW-1 downto 0);
signal ramenr : STD_LOGIC;
signal block_lock : unsigned(C_MAX_LINE_WIDTH/8-1 downto 0);
signal fifo_ramwaddr : T_FIFO_RAMADDR;
signal fifo_ramenw : STD_LOGIC_VECTOR(C_NUM_SUBF-1 downto 0);
signal fifo_ramraddr : T_FIFO_RAMADDR;
signal fifo_ramenr : STD_LOGIC_VECTOR(C_NUM_SUBF-1 downto 0);
signal offset_ramwaddr : STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
 
begin
-------------------------------------------------------------------
-- SUB_FIFOs
-------------------------------------------------------------------
G_SUB_FIFO : for i in 0 to C_NUM_SUBF-1 generate
U_SUB_FIFO : entity work.SUB_FIFO
generic map
(
DATA_WIDTH => C_PIXEL_BITS,
ADDR_WIDTH => C_SUBF_ADDRW
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo_rd(i),
winc => fifo_wr(i),
fullo => fifo_full(i),
emptyo => fifo_empty(i),
count => fifo_count(i),
ramwaddr => fifo_ramwaddr(i),
ramenw => fifo_ramenw(i),
ramraddr => fifo_ramraddr(i),
ramenr => fifo_ramenr(i)
);
end generate G_SUB_FIFO;
-------------------------------------------------------------------
-- RAM for SUB_FIFOs
-------------------------------------------------------------------
U_SUB_RAMZ : entity work.SUB_RAMZ
generic map
(
RAMADDR_W => log2(C_NUM_SUBF)+C_SUBF_ADDRW,
RAMADDR_W => log2(C_MAX_LINE_WIDTH*8),
RAMDATA_W => C_PIXEL_BITS
)
port map
(
d => ramd,
waddr => ramwaddr,
raddr => ramraddr,
waddr => std_logic_vector(ramwaddr_d1),
raddr => std_logic_vector(ramraddr),
we => ramenw,
clk => clk,
175,205 → 117,170
);
-------------------------------------------------------------------
-- FIFO almost full
-- register RAM data input
-------------------------------------------------------------------
p_fifo_almost_full : process(CLK, RST)
p_mux1 : process(CLK, RST)
begin
if RST = '1' then
fifo_almost_full <= '1';
last_idx <= (others => '0');
ramenw <= '0';
ramd <= (others => '0');
elsif CLK'event and CLK = '1' then
if img_size_x = (img_size_x'range => '0') then
last_idx <= (others => '0');
else
last_idx <= unsigned(img_size_x(15 downto 3))-1;
end if;
if C_MEMORY_OPTIMIZED = 0 then
if unsigned(fifo_count(to_integer(wblock_cnt))) > to_unsigned(128-2*8,8) then
fifo_almost_full <= '1';
else
fifo_almost_full <= '0';
end if;
else
if unsigned(fifo_count(to_integer(wblock_cnt))) >= to_unsigned(62,8) then
fifo_almost_full <= '1';
-- due to FIFO full latency next subFIFO is in danger of being
-- overwritten thus its fifo full must be checked ahead
else
-- next=0 when current is last
if wblock_cnt = last_idx then
-- latency from FIFO full till it is recognized by Host is 2T (64-2)=62
if unsigned(fifo_count(0)) >= to_unsigned(62,8) then
fifo_almost_full <= '1';
else
fifo_almost_full <= '0';
end if;
-- next is just current+1
else
-- latency from FIFO full till it is recognized by Host is 2T (64-2)=62
if unsigned(fifo_count(to_integer(wblock_cnt)+1)) >= to_unsigned(62,8) then
fifo_almost_full <= '1';
else
fifo_almost_full <= '0';
end if;
end if;
end if;
end if;
ramd <= iram_wdata;
ramenw <= iram_wren;
end if;
end process;
-------------------------------------------------------------------
-- pixel_cnt
-- resolve RAM write address
-------------------------------------------------------------------
p_pixel_cnt : process(CLK, RST)
begin
if RST = '1' then
pixel_cnt <= (others => '0');
line_cnt <= (others => '0');
ramwaddr <= (others => '0');
ramwaddr_d1 <= (others => '0');
elsif CLK'event and CLK = '1' then
ramwaddr_d1 <= ramwaddr;
if iram_wren = '1' then
-- pixel index in line
if pixel_cnt = unsigned(img_size_x)-1 then
pixel_cnt <= (others => '0');
-- line counter
line_cnt <= line_cnt + 1;
-- RAM is only 8 lines buffer
if line_cnt(2 downto 0) = 8-1 then
ramwaddr <= (others => '0');
else
ramwaddr <= ramwaddr + 1;
end if;
else
pixel_cnt <= pixel_cnt + 1;
ramwaddr <= ramwaddr + 1;
end if;
end if;
if sof = '1' then
pixel_cnt <= (others => '0');
ramwaddr <= (others => '0');
end if;
end if;
end process;
wblock_cnt <= pixel_cnt(pixel_cnt'high downto 3);
 
write_block_cnt <= pixel_cnt(15 downto 3);
 
-------------------------------------------------------------------
-- FIFO half full
-- lock written blocks, unlock after read
-------------------------------------------------------------------
p_half_full : process(CLK, RST)
p_mux6 : process(CLK, RST)
begin
if RST = '1' then
for i in 0 to C_NUM_SUBF-1 loop
fifo_half_full(i) <= '0';
end loop;
block_lock <= (others => '0');
elsif CLK'event and CLK = '1' then
for i in 0 to C_NUM_SUBF-1 loop
if C_MEMORY_OPTIMIZED = 0 then
if unsigned(fifo_count(i)) >= 64 then
fifo_half_full(i) <= '1';
else
fifo_half_full(i) <= '0';
end if;
else
fifo_half_full(i) <= fifo_full(i);
if pixel_cnt(2 downto 0) = 8-1 then
if line_cnt(2 downto 0) = 8-1 then
block_lock(to_integer(write_block_cnt)) <= '1';
end if;
end loop;
end if;
if pix_inblk_cnt = 8-1 then
if line_inblk_cnt = 8-1 then
block_lock(to_integer(read_block_cnt)) <= '0';
end if;
end if;
end if;
end process;
 
-------------------------------------------------------------------
-- Mux1
-- FIFO half full / almost full flag generation
-------------------------------------------------------------------
p_mux1 : process(CLK, RST)
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
for i in 0 to C_NUM_SUBF-1 loop
fifo_wr(i) <= '0';
end loop;
fdct_fifo_hf_full <= '0';
fifo_almost_full <= '0';
elsif CLK'event and CLK = '1' then
for i in 0 to C_NUM_SUBF-1 loop
if wblock_cnt(log2(C_NUM_SUBF)-1 downto 0) = i then
fifo_wr(i) <= iram_wren;
if block_lock(to_integer(read_block_cnt)) = '1' then
fdct_fifo_hf_full <= '1';
else
fdct_fifo_hf_full <= '0';
end if;
if write_block_cnt = unsigned(img_size_x(15 downto 3))-1 then
if block_lock(0) = '1' then
fifo_almost_full <= '1';
else
fifo_wr(i) <= '0';
fifo_almost_full <= '0';
end if;
end loop;
elsif block_lock(to_integer(write_block_cnt+1)) = '1' then
fifo_almost_full <= '1';
else
fifo_almost_full <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Mux2
-- read side
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
p_mux5 : process(CLK, RST)
begin
if RST = '1' then
for i in 0 to C_NUM_SUBF-1 loop
fifo_rd(i) <= '0';
end loop;
fdct_fifo_empty <= '0';
fdct_fifo_hf_full <= '0';
idx_reg <= (others => '0');
read_block_cnt <= (others => '0');
pix_inblk_cnt <= (others => '0');
line_inblk_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
idx_reg <= unsigned(fdct_block_cnt(log2(C_NUM_SUBF)-1 downto 0));
for i in 0 to C_NUM_SUBF-1 loop
if idx_reg = i then
fifo_rd(i) <= fdct_fifo_rd;
if fdct_fifo_rd = '1' then
if pix_inblk_cnt = 8-1 then
pix_inblk_cnt <= (others => '0');
if line_inblk_cnt = 8-1 then
line_inblk_cnt <= (others => '0');
if read_block_cnt = unsigned(img_size_x(15 downto 3))-1 then
read_block_cnt <= (others => '0');
else
read_block_cnt <= read_block_cnt + 1;
end if;
else
line_inblk_cnt <= line_inblk_cnt + 1;
end if;
else
fifo_rd(i) <= '0';
pix_inblk_cnt <= pix_inblk_cnt + 1;
end if;
end loop;
 
fdct_fifo_empty <= fifo_empty(to_integer(idx_reg));
fdct_fifo_hf_full <= fifo_half_full(to_integer(idx_reg));
end if;
if sof = '1' then
read_block_cnt <= (others => '0');
pix_inblk_cnt <= (others => '0');
line_inblk_cnt <= (others => '0');
end if;
end if;
end process;
 
-- generate RAM data output based on 16 or 24 bit mode selection
fdct_fifo_q <= (ramq(15 downto 11) & "000" &
ramq(10 downto 5) & "00" &
ramq(4 downto 0) & "000") when C_PIXEL_BITS = 16 else
std_logic_vector(resize(unsigned(ramq), 24));
-------------------------------------------------------------------
-- Mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
ramwaddr <= (others => '0');
ramwaddr_offset <= (others => '0');
ramwaddr_base <= (others => '0');
ramenw <= '0';
ramenw_m1 <= '0';
wr_idx_reg <= (others => '0');
ramd <= (others => '0');
fifo_data <= (others => '0');
fifo_data_d1 <= (others => '0');
elsif CLK'event and CLK = '1' then
wr_idx_reg <= unsigned(wblock_cnt(log2(C_NUM_SUBF)-1 downto 0));
fifo_data <= iram_wdata;
fifo_data_d1 <= fifo_data;
ramd <= fifo_data_d1;
ramenw_m1 <= fifo_ramenw(to_integer(wr_idx_reg));
ramenw <= ramenw_m1;
ramwaddr_offset <= unsigned(fifo_ramwaddr(to_integer(wr_idx_reg)));
ramwaddr_base <= to_unsigned(2**C_SUBF_ADDRW, C_SUBF_ADDRW+1) *
wr_idx_reg;
ramwaddr <= std_logic_vector(ramwaddr_base(ramwaddr'range) +
resize(ramwaddr_offset, ramwaddr'length));
end if;
end process;
ramraddr <= ramraddr_int(ramraddr'range);
-------------------------------------------------------------------
-- Mux4
-- resolve RAM read address
-------------------------------------------------------------------
p_mux4 : process(CLK, RST)
begin
if RST = '1' then
ramraddr <= (others => '0');
ramraddr_base <= (others => '0');
ramraddr_offset <= (others => '0');
ramraddr_int <= (others => '0');
elsif CLK'event and CLK = '1' then
ramraddr_offset <= unsigned(fifo_ramraddr(to_integer(idx_reg)));
ramraddr_base <= to_unsigned(2**C_SUBF_ADDRW, C_SUBF_ADDRW+1) *
idx_reg;
ramraddr <= std_logic_vector(ramraddr_base(ramraddr'range) +
resize(unsigned(ramraddr_offset), ramraddr'length));
raddr_base_line <= line_inblk_cnt * unsigned(img_size_x);
raddr_tmp <= (read_block_cnt & "000") + pix_inblk_cnt;
ramraddr_int <= raddr_tmp + raddr_base_line;
end if;
end process;
 
/trunk/design/top/JpegEnc.vhd
146,9 → 146,7
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_block_cnt : std_logic_vector(12 downto 0);
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_empty : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
217,9 → 215,7
fifo_almost_full => iram_fifo_afull,
 
-- FDCT
fdct_block_cnt => fdct_block_cnt,
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_empty => fdct_fifo_empty,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
297,9 → 293,7
fdct_sm_settings => fdct_sm_settings,
 
-- BUF_FIFO
bf_block_cnt => fdct_block_cnt,
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_empty => fdct_fifo_empty,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
 
/trunk/design/mdct/FDCT.vhd
52,9 → 52,7
fdct_sm_settings : in T_SM_SETTINGS;
-- BUF_FIFO
bf_block_cnt : out std_logic_vector(12 downto 0);
bf_fifo_rd : out std_logic;
bf_fifo_empty : in std_logic;
bf_fifo_q : in std_logic_vector(23 downto 0);
bf_fifo_hf_full : in std_logic;
95,16 → 93,16
signal mdct_data_out : std_logic_vector(11 downto 0);
signal odv1 : std_logic;
signal dcto1 : std_logic_vector(11 downto 0);
signal x_block_cnt : unsigned(15 downto 0);
signal y_block_cnt : unsigned(15 downto 0);
signal x_block_cnt_cur : unsigned(15 downto 0);
signal y_block_cnt_cur : unsigned(15 downto 0);
signal x_pixel_cnt : unsigned(15 downto 0);
signal y_line_cnt : unsigned(15 downto 0);
signal rd_addr : std_logic_vector(31 downto 0);
signal input_rd_cnt : unsigned(5 downto 0);
signal rd_en : std_logic;
signal rd_en_d1 : std_logic;
signal rdaddr : unsigned(31 downto 0);
signal bf_dval : std_logic_vector(3 downto 0);
signal bf_dval : std_logic;
signal bf_dval_m1 : std_logic;
signal bf_dval_m2 : std_logic;
signal wr_cnt : unsigned(5 downto 0);
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
168,7 → 166,6
signal fram1_raddr : std_logic_vector(5 downto 0);
signal fram1_rd_d : std_logic_vector(8 downto 0);
signal fram1_rd : std_logic;
signal bf_fifo_empty_d1 : std_logic;
signal rd_started : std_logic;
signal writing_en : std_logic;
180,7 → 177,6
zz_data <= dbuf_q;
bf_fifo_rd <= bf_fifo_rd_s;
bf_block_cnt <= std_logic_vector(x_block_cnt_cur(15 downto 3));
-------------------------------------------------------------------
-- FRAM1
202,7 → 198,7
q => fram1_q
);
fram1_we <= bf_dval(bf_dval'high);
fram1_we <= bf_dval;
fram1_data <= bf_fifo_q;
-------------------------------------------------------------------
227,8 → 223,8
if RST = '1' then
rd_en <= '0';
rd_en_d1 <= '0';
x_block_cnt <= (others => '0');
y_block_cnt <= (others => '0');
x_pixel_cnt <= (others => '0');
y_line_cnt <= (others => '0');
input_rd_cnt <= (others => '0');
cmp_idx <= (others => '0');
cur_cmp_idx <= (others => '0');
242,11 → 238,11
cur_cmp_idx_d8 <= (others => '0');
cur_cmp_idx_d9 <= (others => '0');
eoi_fdct <= '0';
x_block_cnt_cur <= (others => '0');
y_block_cnt_cur <= (others => '0');
start_int <= '0';
bf_fifo_rd_s <= '0';
bf_dval <= (others => '0');
bf_dval <= '0';
bf_dval_m1 <= '0';
bf_dval_m2 <= '0';
fram1_rd <= '0';
fram1_rd_d <= (others => '0');
fram1_raddr <= (others => '0');
263,7 → 259,9
cur_cmp_idx_d9 <= cur_cmp_idx_d8;
start_int <= '0';
bf_dval <= bf_dval(bf_dval'length-2 downto 0) & bf_fifo_rd_s;
bf_dval_m2 <= bf_fifo_rd_s;
bf_dval_m1 <= bf_dval_m2;
bf_dval <= bf_dval_m1;
fram1_rd_d <= fram1_rd_d(fram1_rd_d'length-2 downto 0) & fram1_rd;
-- SOF or internal self-start
276,28 → 274,28
if cmp_idx = 3-1 then
cmp_idx <= (others => '0');
-- horizontal block counter
if x_block_cnt = unsigned(img_size_x)-8 then
x_block_cnt <= (others => '0');
if x_pixel_cnt = unsigned(img_size_x)-8 then
x_pixel_cnt <= (others => '0');
-- vertical block counter
if y_block_cnt = unsigned(img_size_y)-8 then
y_block_cnt <= (others => '0');
if y_line_cnt = unsigned(img_size_y)-8 then
y_line_cnt <= (others => '0');
-- set end of image flag
eoi_fdct <= '1';
else
y_block_cnt <= y_block_cnt + 8;
y_line_cnt <= y_line_cnt + 8;
end if;
else
x_block_cnt <= x_block_cnt + 8;
x_pixel_cnt <= x_pixel_cnt + 8;
end if;
else
cmp_idx <=cmp_idx + 1;
end if;
x_block_cnt_cur <= x_block_cnt;
y_block_cnt_cur <= y_block_cnt;
cur_cmp_idx <= cmp_idx;
end if;
-- wait until FIFO becomes half full
-- wait until FIFO becomes half full but only for component 0
-- as we read buf FIFO only during component 0
if rd_started = '1' and (bf_fifo_hf_full = '1' or cur_cmp_idx /= 0) then
rd_en <= '1';
rd_started <= '0';
316,6 → 314,7
-- count number of samples read from input in one run
if input_rd_cnt = 64-1 then
rd_en <= '0';
-- internal restart
start_int <= '1' and not eoi_fdct;
eoi_fdct <= '0';
else
406,7 → 405,7
-------------------------------------------------------------------
-- FIFO rd controller
-- FIFO1 rd controller
-------------------------------------------------------------------
p_fifo_rd_ctrl : process(CLK, RST)
begin
/trunk/design/common/JPEG_PKG.vhd
33,14 → 33,10
-- if expected image width is known change this parameter to match this
-- otherwise some onchip RAM will be wasted and never used
constant C_MAX_LINE_WIDTH : integer := 1280;
 
-- 0=highest clock per pixel performance
-- 1=memory used by BUF_FIFO halved, speed performance reduced by circa 18%
constant C_MEMORY_OPTIMIZED : integer := 0;
-- 24 bit format RGB 888 bits
-- 16 bit format RGB 565 bits
constant C_PIXEL_BITS : integer := 16;
constant C_PIXEL_BITS : integer := 24;
type T_SM_SETTINGS is record
x_cnt : unsigned(15 downto 0);
/branches/16rgb/trunk/tb/vhdl/JPEG_TB.VHD
204,21 → 204,22
wait;
end process;
 
outif_almost_full <= '0';
backpressure : process(CLK, RST)
begin
if RST = '1' then
outif_almost_full <= '0';
count1 <= (others => '0');
elsif CLK'event and CLK = '1' then
if count1 = 10000 then
count1 <= (others => '0');
outif_almost_full <= not outif_almost_full;
else
count1 <= count1 + 1;
end if;
end if;
end process;
--backpressure : process(CLK, RST)
--begin
-- if RST = '1' then
-- outif_almost_full <= '0';
-- count1 <= (others => '0');
-- elsif CLK'event and CLK = '1' then
-- if count1 = 10000 then
-- count1 <= (others => '0');
-- outif_almost_full <= not outif_almost_full;
-- else
-- count1 <= count1 + 1;
-- end if;
-- end if;
--end process;
 
end TB;
-----------------------------------
/branches/16rgb/trunk/design/common/JPEG_PKG.vhd
36,7 → 36,7
 
-- 0=highest clock per pixel performance
-- 1=memory used by BUF_FIFO halved, speed performance reduced by circa 18%
constant C_MEMORY_OPTIMIZED : integer := 0;
constant C_MEMORY_OPTIMIZED : integer := 1;
type T_SM_SETTINGS is record
x_cnt : unsigned(15 downto 0);

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