OpenCores
URL https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk

Subversion Repositories mod_mult_exp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mod_mult_exp/trunk/bench/vhdl
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/mod_mult/ModularMultiplierIterative32bitTB.vhd
0,0 → 1,182
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- This is TestBench for the Montgomery modular multiplier ----
---- with the 64 bit width. ----
---- it takes two nubers and modulus as the input and results ----
---- the Montgomery product A*B*(R^{-1}) mod M ----
---- where R^{-1} is the modular multiplicative inverse. ----
---- R*R^{-1} == 1 mod M ----
---- R = 2^word_length mod M ----
---- and word_length is the binary width of the ----
---- operated word (in this case 64 bit) ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ModularMultiplierIterative32bitTB IS
END ModularMultiplierIterative32bitTB;
ARCHITECTURE behavior OF ModularMultiplierIterative32bitTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ModularMultiplierIterative
PORT(
A : IN STD_LOGIC_VECTOR(31 downto 0);
B : IN STD_LOGIC_VECTOR(31 downto 0);
M : IN STD_LOGIC_VECTOR(31 downto 0);
start : IN STD_LOGIC;
product : OUT STD_LOGIC_VECTOR(31 downto 0);
ready : OUT STD_LOGIC;
clk : IN STD_LOGIC
);
END COMPONENT;
 
--Inputs
signal A : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal B : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal M : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal start : STD_LOGIC := '0';
signal clk : STD_LOGIC := '0';
 
--Outputs
signal product : std_logic_vector(31 downto 0);
signal ready : STD_LOGIC;
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ModularMultiplierIterative PORT MAP (
A => A,
B => B,
M => M,
start => start,
product => product,
ready => ready,
clk => clk
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
start <= '0';
wait for 100 ns;
 
---- Preparation for test case 1 -----------------
-- A = 1073741827 in decimal
-- B = 1876543287 in decimal
-- M = 2147483659 in decimal
-- expected_result = 1075674849379283795 in decimal, in hex 66e4624e
-- mod(1073741827*1876543287*1659419191, 2147483659) = 1726243406
-- where 2703402148733296366 is the inverse modulus
--------------------------------------------------
start <= '1';
-- A = 1073741827 in decimal
A <= "01000000000000000000000000000011";
-- B = 1876543210987 in decimal
B <= "01101111110110011100011100110111";
-- M = 2147483659 in decimal
M <= "10000000000000000000000000001011";
--wait for 80*clk_period;
wait until ready = '1' and clk = '0';
if product /= x"66e4624e" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
 
start <= '0';
---- Preparation for test case 2 -----------------
-- A = 1073741826 in decimal
-- B = 1876543286 in decimal
-- M = 2147483659 in decimal
-- expected_result = 1075674849379283795 in decimal, in hex 66e4624e
-- mod(1073741826*1876543286*1659419191, 2147483659) = 1567508594
-- where 1659419191 is the inverse modulus
--------------------------------------------------
 
-- A = 1073741826 in decimal
A <= "01000000000000000000000000000010";
-- B = 1876543210986 in decimal
B <= "01101111110110011100011100110110";
-- M = 2147483659 in decimal
M <= "10000000000000000000000000001011";
wait for clk_period;
start <= '1';
--wait for 80*clk_period;
wait until ready = '1' and clk = '0';
if product /= x"5d6e4872" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
assert false severity failure;
end process;
 
END;
/mod_mult/ModularMultiplierIterative512bitTB.vhd
0,0 → 1,197
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- This is TestBench for the Montgomery modular multiplier ----
---- with the 512 bit width. ----
---- it takes two nubers and modulus as the input and results ----
---- the Montgomery product A*B*(R^{-1}) mod M ----
---- where R^{-1} is the modular multiplicative inverse. ----
---- R*R^{-1} == 1 mod M ----
---- R = 2^word_length mod M ----
---- and word_length is the binary width of the ----
---- operated word (in this case 512 bit) ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ModularMultiplierIterative512bitTB IS
END ModularMultiplierIterative512bitTB;
ARCHITECTURE behavior OF ModularMultiplierIterative512bitTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ModularMultiplierIterative
PORT(
A : in STD_LOGIC_VECTOR(511 downto 0);
B : in STD_LOGIC_VECTOR(511 downto 0);
M : in STD_LOGIC_VECTOR(511 downto 0);
start : in STD_LOGIC;
product : out STD_LOGIC_VECTOR(511 downto 0);
ready : out STD_LOGIC;
clk : in STD_LOGIC
);
END COMPONENT;
 
--Inputs
signal A : STD_LOGIC_VECTOR(511 downto 0) := (others => '0');
signal B : STD_LOGIC_VECTOR(511 downto 0) := (others => '0');
signal M : STD_LOGIC_VECTOR(511 downto 0) := (others => '0');
signal start : STD_LOGIC := '0';
signal clk : STD_LOGIC := '0';
 
--Outputs
signal product : STD_LOGIC_VECTOR(511 downto 0);
signal ready : STD_LOGIC;
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ModularMultiplierIterative PORT MAP (
A => A,
B => B,
M => M,
start => start,
product => product,
ready => ready,
clk => clk
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
start <= '0';
wait for 100 ns;
 
---- Preparation for test case 1 -----------------
-- A = 1135574785903187283000914738069914842639275616893687122668359807022003618585980215260939798952644749528921700342000274265548842002316414917974647561961683 in decimal
-- B = 97927786390663519429528993360368267006249228136794892056090651513080073109454331808866772457049032741774590681339704155886317906072752116837364369820881 in decimal
-- M = 3351951982485649274893506249551461531869841455148098344430890360930446855046914914263767984168972974033957028381338463851007479808527777429670210341401251 in decimal
-- expected_result = 2228133496571818711622350692880669459929128102839647013792122413518929533298354919965858625663488002993791315812426542313874032336596139553001249634708855 in decimal,
-- in hex 2a8ae3c12ae96d6babce2e342ec7beeff5754a14e7c8e6057eeebf6dc1cb12145e26e97c874f8e05cfa6fcaf83240f90d2fd21b3f41016b74607c143e49eed77
-- mod(
-- 1135574785903187283000914738069914842639275616893687122668359807022003618585980215260939798952644749528921700342000274265548842002316414917974647561961683 *
-- 97927786390663519429528993360368267006249228136794892056090651513080073109454331808866772457049032741774590681339704155886317906072752116837364369820881 *
-- 2591367877621154684380773880291249237701602230100736077754314629198930824379666744084279080961590867282481555124997788427853751639203524473059719065731751 ,
-- 3351951982485649274893506249551461531869841455148098344430890360930446855046914914263767984168972974033957028381338463851007479808527777429670210341401251 ) =
-- = 2228133496571818711622350692880669459929128102839647013792122413518929533298354919965858625663488002993791315812426542313874032336596139553001249634708855
-- where 2591367877621154684380773880291249237701602230100736077754314629198930824379666744084279080961590867282481555124997788427853751639203524473059719065731751 is the inverse modulus
--------------------------------------------------
start <= '1';
-- A = 1135574785903187283000914738069914842639275616893687122668359807022003618585980215260939798952644749528921700342000274265548842002316414917974647561961683 in decimal
A <= "00010101101011101001001011101101001001011100110110111011001010010100010110000100000101001010110100011010001010001111101000110101111101011011111111000011000100011101011111100001111011111110110110111010011101010011111001001000110011001110111000011110100111111111000111010001011000000111000101000100010010011011111101101111100001011010000011100011111111100000011110000100010101001000101100111100010001100001101011000101111110111111001010001011011110100001110000111100100000111111010011011111111101101100000011010011";
-- B = 97927786390663519429528993360368267006249228136794892056090651513080073109454331808866772457049032741774590681339704155886317906072752116837364369820881 in decimal
B <= "00000001110111101010100100111010100000100100111111101001100100111011001111000010101011111001001001110011011010010100101000100010110011011101111000010011100100101000011010000110110010101101101100000111101000001111010101000110100001100011101110100011100111101100000001000110010110111001110111111110101000001110001000011001000001000000111100000001100110000100011100010011101110010100111110010111110001000110111010010010101101001111110000111001110000100111111111100011011101100000011110100100100000011000110011010001";
-- M = 3351951982485649274893506249551461531869841455148098344430890360930446855046914914263767984168972974033957028381338463851007479808527777429670210341401251 in decimal
M <= "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000001010010010100100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110101111001111111011110110110111001010100011";
--wait for 600*clk_period;
-- Result = 2228133496571818711622350692880669459929128102839647013792122413518929533298354919965858625663488002993791315812426542313874032336596139553001249634708855 in decimal
wait until ready = '1' and clk = '0';
if product /= x"2a8ae3c12ae96d6babce2e342ec7beeff5754a14e7c8e6057eeebf6dc1cb12145e26e97c874f8e05cfa6fcaf83240f90d2fd21b3f41016b74607c143e49eed77" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
start <= '0';
 
---- Preparation for test case 2 -----------------
-- A = 3351951982485649274893506249551461531869841455148098344430890360930441007518386744200468574541725856922507964546621512713438470702986642486608412251521039 in decimal
-- B = 97927786390663519429528993360368267006249228136794892056090651513080073109454331808866772457049032741774590681339704155886317906072752116837364369820881 in decimal
-- M = 6703903964971298549787012499102923063739682910296196688861780721860882015036773488400937149083451713845015929093243025426876941405973284973216824503042159 in decimal
-- expected_result = 5770539552593938046267215339235143056108840937616962443047031076129629580294766891795665005337423591502330655021878623252853392851503861478061794255888635 in decimal,
-- in hex 6e2dcf4e2226cb7a14afa007b0bafdf50d573776681c0cca8d7ff56515076baffd05eaa8ee73d63874a1df6d13e2bbc0aeb6dcd21d8ee10613df1e2e5e02e0fb
-- mod(
-- 3351951982485649274893506249551461531869841455148098344430890360930441007518386744200468574541725856922507964546621512713438470702986642486608412251521039 *
-- 97927786390663519429528993360368267006249228136794892056090651513080073109454331808866772457049032741774590681339704155886317906072752116837364369820881 *
-- 6311333012067573859934619875281580722169341118251824810685189958869028563705791257098179568281267604475713194506701767181158922314632507024334758203314465 ,
-- 6703903964971298549787012499102923063739682910296196688861780721860882015036773488400937149083451713845015929093243025426876941405973284973216824503042159 ) =
-- = 5770539552593938046267215339235143056108840937616962443047031076129629580294766891795665005337423591502330655021878623252853392851503861478061794255888635
-- where 6311333012067573859934619875281580722169341118251824810685189958869028563705791257098179568281267604475713194506701767181158922314632507024334758203314465 is the inverse modulus
--------------------------------------------------
 
-- A = 3351951982485649274893506249551461531869841455148098344430890360930441007518386744200468574541725856922507964546621512713438470702986642486608412251521039 in decimal
A <= "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111";
-- B = 97927786390663519429528993360368267006249228136794892056090651513080073109454331808866772457049032741774590681339704155886317906072752116837364369820881 in decimal
B <= "00000001110111101010100100111010100000100100111111101001100100111011001111000010101011111001001001110011011010010100101000100010110011011101111000010011100100101000011010000110110010101101101100000111101000001111010101000110100001100011101110100011100111101100000001000110010110111001110111111110101000001110001000011001000001000000111100000001100110000100011100010011101110010100111110010111110001000110111010010010101101001111110000111001110000100111111111100011011101100000011110100100100000011000110011010001";
-- M = 6703903964971298549787012499102923063739682910296196688861780721860882015036773488400937149083451713845015929093243025426876941405973284973216824503042159 in decimal
M <= "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101111";
wait for clk_period;
-- Result = 1075674849379283795 in decimal
start <= '1';
--wait for 600*clk_period;
wait until ready = '1' and clk = '0';
if product /= x"6e2dcf4e2226cb7a14afa007b0bafdf50d573776681c0cca8d7ff56515076baffd05eaa8ee73d63874a1df6d13e2bbc0aeb6dcd21d8ee10613df1e2e5e02e0fb" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
assert false severity failure;
end process;
 
END;
/mod_mult/ModularMultiplierIterative64bitTB.vhd
0,0 → 1,183
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- This is TestBench for the Montgomery modular multiplier ----
---- with the 64 bit width. ----
---- it takes two nubers and modulus as the input and results ----
---- the Montgomery product A*B*(R^{-1}) mod M ----
---- where R^{-1} is the modular multiplicative inverse. ----
---- R*R^{-1} == 1 mod M ----
---- R = 2^word_length mod M ----
---- and word_length is the binary width of the ----
---- operated word (in this case 64 bit) ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ModularMultiplierIterative64bitTB IS
END ModularMultiplierIterative64bitTB;
ARCHITECTURE behavior OF ModularMultiplierIterative64bitTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ModularMultiplierIterative
PORT(
A : IN STD_LOGIC_VECTOR(63 downto 0);
B : IN STD_LOGIC_VECTOR(63 downto 0);
M : IN STD_LOGIC_VECTOR(63 downto 0);
start : IN STD_LOGIC;
product : OUT STD_LOGIC_VECTOR(63 downto 0);
ready : OUT STD_LOGIC;
clk : IN STD_LOGIC
);
END COMPONENT;
 
--Inputs
signal A : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
signal B : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
signal M : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
signal start : STD_LOGIC := '0';
signal clk : STD_LOGIC := '0';
 
--Outputs
signal product : std_logic_vector(63 downto 0);
signal ready : STD_LOGIC;
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ModularMultiplierIterative PORT MAP (
A => A,
B => B,
M => M,
start => start,
product => product,
ready => ready,
clk => clk
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
start <= '0';
wait for 100 ns;
 
---- Preparation for test case 1 -----------------
-- A = 1234567890123 in decimal
-- B = 9876543210987 in decimal
-- M = 9223372036854775837 in decimal
-- expected_result = 1075674849379283795 in decimal, in hex
-- mod(1234567890123*9876543210987*2703402148733296366, 9223372036854775837) = 1075674849379283795
-- where 2703402148733296366 is the inverse modulus
--------------------------------------------------
start <= '1';
-- A = 1234567890123 in decimal
A <= "0000000000000000000000010001111101110001111110110000010011001011";
-- B = 9876543210987 in decimal
B <= "0000000000000000000010001111101110001111110110011000010111101011";
-- M = 9223372036854775837 in decimal
M <= "1000000000000000000000000000000000000000000000000000000000011101";
--wait for 80*clk_period;
wait until ready = '1' and clk = '0';
if product /= x"0eed90938b12f353" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
 
---- Preparation for test case 2 -----------------
-- A = 2405361651273580285 in decimal
-- B = 1851187696912577658 in decimal
-- M = 4612794175830006917 in decimal
-- expected_result = 1075674849379283795 in decimal
-- mod(2405361651273580285*1851187696912577658*377014635792245467, 4612794175830006917) = 1424433616378222832
-- where 377014635792245467 is the inverse modulus
--------------------------------------------------
 
 
start <= '0';
-- A = 2405361651273580285
A <= "0010000101100001100011111010110101111100100000100011111011111101";
-- B = 1851187696912577658
B <= "0001100110110000101111010110011011111111000011000011010001111010";
-- M = 4612794175830006917
M <= "0100000000000011111011111101110100000000010101101001110010000101";
wait for clk_period;
start <= '1';
--wait for 80*clk_period;
wait until ready = '1' and clk = '0';
if product /= x"13c49ad3be5958f0" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
assert false severity failure;
end process;
 
END;
/txt_util.vhd
0,0 → 1,586
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
 
 
package txt_util is
 
-- prints a message to the screen
procedure print(text: string);
 
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
 
-- converts std_logic into a character
function chr(sl: std_logic) return character;
 
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
 
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
 
-- converts boolean into a string
function str(b: boolean) return string;
 
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
 
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
 
-- converts integer to string, using base 10
function str(int: integer) return string;
 
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
 
 
-- functions to manipulate strings
-----------------------------------
 
-- convert a character to upper case
function to_upper(c: character) return character;
 
-- convert a character to lower case
function to_lower(c: character) return character;
 
-- convert a string to upper case
function to_upper(s: string) return string;
 
-- convert a string to lower case
function to_lower(s: string) return string;
 
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
 
 
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
 
 
 
 
package body txt_util is
 
 
 
 
-- prints text to the screen
 
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
 
 
 
 
-- prints text to the screen when active
 
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
 
 
-- converts std_logic into a character
 
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
 
 
 
-- converts std_logic into a string (1 to 1)
 
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
 
 
 
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
 
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
 
 
function str(b: boolean) return string is
 
begin
if b then
return "true";
else
return "false";
end if;
end str;
 
 
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
 
 
 
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function str(int: integer; base: integer) return string is
 
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
 
begin
 
-- bug fix for negative numbers
abs_int := abs(int);
 
num := abs_int;
 
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
 
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
 
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
 
end str;
 
 
-- convert integer to string, using base 10
function str(int: integer) return string is
 
begin
 
return str(int, 10) ;
 
end str;
 
 
 
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
 
 
 
-- functions to manipulate strings
-----------------------------------
 
 
-- convert a character to upper case
 
function to_upper(c: character) return character is
 
variable u: character;
 
begin
 
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
 
return u;
 
end to_upper;
 
 
-- convert a character to lower case
 
function to_lower(c: character) return character is
 
variable l: character;
 
begin
 
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
 
return l;
 
end to_lower;
 
 
 
-- convert a string to upper case
 
function to_upper(s: string) return string is
 
variable uppercase: string (s'range);
 
begin
 
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
 
end to_upper;
 
 
 
-- convert a string to lower case
 
function to_lower(s: string) return string is
 
variable lowercase: string (s'range);
 
begin
 
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
 
end to_lower;
 
 
 
-- functions to convert strings into other types
 
 
-- converts a character into a std_logic
 
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
 
 
-- converts a string into std_logic_vector
 
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
 
 
 
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
 
 
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
 
 
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
 
 
 
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
 
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
 
 
 
 
end txt_util;
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.