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/vhdl/mod_mult/ModMultIter_SM.vhd
0,0 → 1,166
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- This is state machine for the modular multiplier it consists----
---- of three states, NOP the preparation stage, CALCULATE_START ----
---- for the modular multiply and STOP for the presentation ----
---- result. ----
---- ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ModMultIter_SM is
generic (
word_size : integer := WORD_LENGTH;
word_binary : integer := WORD_INTEGER
);
port(
x : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
start : in STD_LOGIC;
clk : in STD_LOGIC;
s_0 : in STD_LOGIC;
y_0 : in STD_LOGIC;
ready : out STD_LOGIC;
out_reg_en : out STD_LOGIC;
mux_mult_ctrl : out STD_LOGIC;
mux_4in_ctrl : out STD_LOGIC_VECTOR(1 downto 0)
);
end ModMultIter_SM;
 
architecture Behavioral of ModMultIter_SM is
 
signal state : multiplier_states := NOP;
signal next_state : multiplier_states := NOP;
signal position_counter : STD_LOGIC_VECTOR(word_binary downto 0) := (others => '0');
signal shift_reg : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (others => '0');
 
signal q : STD_LOGIC;
 
begin
q <= (shift_reg(0) and y_0) xor s_0;
mux_4in_ctrl <= shift_reg(0) & q;
SM : process(state, start, position_counter)
begin
case state is
-- Prepare for the Montgomery iterations
when NOP =>
ready <= '0';
if (start = '1') then
next_state <= CALCULATE_START;
out_reg_en <= '1';
mux_mult_ctrl <= '1';
else
out_reg_en <= '0';
mux_mult_ctrl <= '0';
next_state <= NOP;
end if;
-- State for the calculations of the Montgomery iterations
when CALCULATE_START =>
mux_mult_ctrl <= '1';
ready <= '0';
-- End of iterations (counter contains the 'word_size' number)
if (position_counter = (word_size - 1)) then
out_reg_en <= '0';
next_state <= STOP;
-- Calculation process
else
out_reg_en <= '1';
next_state <= CALCULATE_START;
end if;
-- End of the calculations
when STOP =>
ready <= '1';
mux_mult_ctrl <= '1';
out_reg_en <= '0';
if (start = '1') then
next_state <= STOP;
else
next_state <= NOP;
end if;
end case;
end process SM;
 
-- Shift register enabling proper calculations of the all Montgomery iterations
shift : process (clk, state)
begin
if (clk = '0' and clk'Event) then
if (state = CALCULATE_START) then
shift_reg <= shift_reg(0) & shift_reg(word_size - 1 downto 1);
else
shift_reg <= x;
end if;
end if;
end process shift;
 
-- Process for the state change between each clock tick
state_control : process (clk, start)
begin
if (start = '0') then
state <= NOP;
elsif (clk = '1' and clk'Event) then
state <= next_state;
end if;
end process state_control;
 
-- Counter for controlling the number of the montgomery iterations during counting
couner_modifier : process (clk)
begin
if (clk = '1' and clk'Event) then
if (state = CALCULATE_START) then
position_counter <= position_counter + 1;
else
position_counter <= (others => '0');
end if;
end if;
end process couner_modifier;
end Behavioral;
/vhdl/mod_mult/ModularMultiplierIterative.vhd
0,0 → 1,195
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- Montgomery modular multiplier main module. It combines all ----
---- subomponents. It takes two numbers and modulus as the input ----
---- and returns the Montgomery product A*B*(R^{-1}) mod M ----
---- where R^{-1} is the modular multiplicative inverse. ----
---- R*R^{-1} == 1 mod M ----
---- R = 2^word_length mod M ----
---- and word_length is the binary width of the ----
---- operated word (in this case 64 bit) ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ModularMultiplierIterative is
generic (
word_size : integer := WORD_LENGTH
);
port (
A : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- multiplicand
B : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- multiplier
M : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- modulus
start : in STD_LOGIC;
product : out STD_LOGIC_VECTOR(word_size - 1 downto 0); -- product
ready : out STD_LOGIC;
clk : in STD_LOGIC
);
end ModularMultiplierIterative;
 
architecture Behavioral of ModularMultiplierIterative is
 
-- Multiplexer
component MontMult4inMux is
generic (
word_size : integer := WORD_LENGTH
);
port (
ctrl : in STD_LOGIC_VECTOR(1 downto 0);
zero : in STD_LOGIC_VECTOR(word_size downto 0);
M : in STD_LOGIC_VECTOR(word_size downto 0);
Y : in STD_LOGIC_VECTOR(word_size downto 0);
YplusM : in STD_LOGIC_VECTOR(word_size downto 0);
output : out STD_LOGIC_VECTOR(word_size downto 0)
);
end component MontMult4inMux;
 
-- State machine
component ModMultIter_SM is
generic (
word_size : integer := WORD_LENGTH
);
port(
x : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
start : in STD_LOGIC;
clk : in STD_LOGIC;
s_0 : in STD_LOGIC;
y_0 : in STD_LOGIC;
ready : out STD_LOGIC;
out_reg_en : out STD_LOGIC;
mux_mult_ctrl : out STD_LOGIC;
mux_4in_ctrl : out STD_LOGIC_VECTOR(1 downto 0)
);
end component ModMultIter_SM;
 
-- Signals
signal Mi : STD_LOGIC_VECTOR(word_size downto 0);
signal Yi : STD_LOGIC_VECTOR(word_size downto 0);
signal sumYM : STD_LOGIC_VECTOR(word_size downto 0);
signal zero_sig : STD_LOGIC_VECTOR(word_size downto 0) := (others => '0');
signal four_in_mux_out : STD_LOGIC_VECTOR(word_size downto 0);
 
signal mux_4in_ctrl_sig : STD_LOGIC_VECTOR(1 downto 0);
signal mult_mux_ctrl_sig : STD_LOGIC;
 
signal mult_mux_out : STD_LOGIC_VECTOR(word_size downto 0);
signal out_reg_sig : STD_LOGIC_VECTOR(word_size downto 0);
signal product_sig : STD_LOGIC_VECTOR(word_size downto 0);
signal out_en : STD_LOGIC;
 
signal sum_mult_out : STD_LOGIC_VECTOR(word_size + 1 downto 0);
signal sum_div_2 : STD_LOGIC_VECTOR(word_size downto 0);
 
begin
zero_sig <= (others => '0'); -- '0'
-- 'widening' to store the intermediate steps
Mi <= '0' & M;
Yi <= '0' & B;
-- Operations needed to compute the Montgomery multiplications
sum_div_2 <= sum_mult_out(word_size + 1 downto 1);
sum_mult_out <= ('0' & four_in_mux_out) + ('0' & mult_mux_out);
sumYM <= ('0' & B) + ('0' & M);
 
-- Multiplexer component
four_in_mux : MontMult4inMux port map(
ctrl => mux_4in_ctrl_sig, zero => zero_sig, M => Mi, Y => Yi,
YplusM => sumYM, output => four_in_mux_out
);
 
-- Two input asynchronuos multiplexer for output 'not clear' code due to
-- 'historical works'
mult_mux_out <= (others => '0') when (mult_mux_ctrl_sig = '0') else
out_reg_sig;
 
-- State machine
state_machine : ModMultIter_SM port map(
x => A,
start => start,
clk => clk,
s_0 => out_reg_sig(0),
y_0 => B(0),
ready => ready,
out_reg_en => out_en,
mux_mult_ctrl => mult_mux_ctrl_sig,
mux_4in_ctrl => mux_4in_ctrl_sig
);
-- Register like structure for signal synchronous work
clock : process(clk, start)
begin
if (clk = '1' and clk'Event) then
if (start = '0') then
out_reg_sig <= (others => '0');
elsif out_en = '1' then
out_reg_sig <= sum_div_2;
end if;
end if;
end process clock;
-- One additional 'subtract' component which was added after
-- first experiments with Montgomery multiplication. It was
-- observed that sometimes intermediate step can be higher
-- than modulus. In this situation 'M' substraction is
-- compulsory
product_proc : process(clk, Mi, out_reg_sig)
begin
if(out_reg_sig < ("0" & Mi)) then
product_sig <= out_reg_sig;
else
product_sig <= out_reg_sig - Mi;
end if;
end process product_proc;
product <= product_sig(word_size - 1 downto 0);
 
end Behavioral;
/vhdl/commons/properties_32bit.vhd
0,0 → 1,113
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- Properties file for multiplier and exponentiator ----
---- (32 bit). ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package properties is
 
-- Declare constants
constant BYTE : INTEGER := 8;
constant WORD_LENGTH : INTEGER := 32;
constant WORD_INTEGER : INTEGER := 6;
constant WORD_INT_LOG : INTEGER := 3;
constant WORD_INT_LOG_STR : STD_LOGIC_VECTOR(WORD_INT_LOG - 1 downto 0) := "110";
 
constant count_up : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant count_down : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant do_nothing : STD_LOGIC_VECTOR(1 downto 0) := "11";
 
type multiplier_states is (NOP, CALCULATE_START, STOP);
 
type finalizer_states is (FIRST_RUN, NOP,
READ_DATA_HASH_M, READ_DATA_C1, READ_DATA_N, READ_DATA_E, READ_DATA_D2, READ_DATA_CINV,
COUNT_C2, EXP_Z_C2, SAVE_EXP_Z_C2, EXP_P_C2, SAVE_EXP_P_C2, EXP_CONTROL_C2, EXP_END_C2, SAVE_EXP_MULT_C2,
COUNT_Cinv, MULT_CINV, SAVE_MULT_CINV,
COUNT_C, MULT_C, SAVE_MULT_C,
COUNT_M, EXP_Z_M, SAVE_EXP_Z_M, EXP_P_M, SAVE_EXP_P_M, EXP_CONTROL_M, EXP_END_M, SAVE_EXP_M,
MAKE_COMPARE, COMP, COMPARE_RESULT,
INFO_RESULT, SHOW_RESULT, FAIL_STATE);
 
type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE,
DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE,
TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA);
 
---- mnemonics for finalizer
constant mn_read_hash_m : STD_LOGIC_VECTOR(7 downto 0) := "00000001";
constant mn_read_c1 : STD_LOGIC_VECTOR(7 downto 0) := "00000010";
constant mn_read_n : STD_LOGIC_VECTOR(7 downto 0) := "00000011";
constant mn_read_e : STD_LOGIC_VECTOR(7 downto 0) := "00000100";
constant mn_read_d2 : STD_LOGIC_VECTOR(7 downto 0) := "00000110";
constant mn_read_cinv : STD_LOGIC_VECTOR(7 downto 0) := "00000111";
constant mn_finalize : STD_LOGIC_VECTOR(7 downto 0) := "00001000";
constant mn_show_result : STD_LOGIC_VECTOR(7 downto 0) := "00001001";
constant mn_show_status : STD_LOGIC_VECTOR(7 downto 0) := "00001010";
constant mn_prepare_for_data : STD_LOGIC_VECTOR(7 downto 0) := "00001011";
 
---- addresses for memory data
constant addr_hashM : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant addr_c1 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant addr_N : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant addr_E : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant addr_d2 : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant addr_c2 : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant addr_c : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant addr_hashMc : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant addr_cinv : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101";
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110";
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111";
 
---- help_statuses_for_clarity
constant stat_all_data_readed : STD_LOGIC_VECTOR(5 downto 0) := "111111";
constant stat_clear_status : STD_LOGIC_VECTOR(5 downto 0) := "000000";
 
end properties;
 
package body properties is
end properties;
/vhdl/commons/properties_64bit.vhd
0,0 → 1,113
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- Properties file for multiplier and exponentiator ----
---- (64 bit). ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package properties is
 
-- Declare constants
constant BYTE : INTEGER := 8;
constant WORD_LENGTH : INTEGER := 64;
constant WORD_INTEGER : INTEGER := 7;
constant WORD_INT_LOG : INTEGER := 3;
constant WORD_INT_LOG_STR : STD_LOGIC_VECTOR(WORD_INT_LOG - 1 downto 0) := "111";
 
constant count_up : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant count_down : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant do_nothing : STD_LOGIC_VECTOR(1 downto 0) := "11";
 
type multiplier_states is (NOP, CALCULATE_START, STOP);
 
type finalizer_states is (FIRST_RUN, NOP,
READ_DATA_HASH_M, READ_DATA_C1, READ_DATA_N, READ_DATA_E, READ_DATA_D2, READ_DATA_CINV,
COUNT_C2, EXP_Z_C2, SAVE_EXP_Z_C2, EXP_P_C2, SAVE_EXP_P_C2, EXP_CONTROL_C2, EXP_END_C2, SAVE_EXP_MULT_C2,
COUNT_Cinv, MULT_CINV, SAVE_MULT_CINV,
COUNT_C, MULT_C, SAVE_MULT_C,
COUNT_M, EXP_Z_M, SAVE_EXP_Z_M, EXP_P_M, SAVE_EXP_P_M, EXP_CONTROL_M, EXP_END_M, SAVE_EXP_M,
MAKE_COMPARE, COMP, COMPARE_RESULT,
INFO_RESULT, SHOW_RESULT, FAIL_STATE);
 
type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE,
DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE,
TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA);
 
---- mnemonics for finalizer
constant mn_read_hash_m : STD_LOGIC_VECTOR(7 downto 0) := "00000001";
constant mn_read_c1 : STD_LOGIC_VECTOR(7 downto 0) := "00000010";
constant mn_read_n : STD_LOGIC_VECTOR(7 downto 0) := "00000011";
constant mn_read_e : STD_LOGIC_VECTOR(7 downto 0) := "00000100";
constant mn_read_d2 : STD_LOGIC_VECTOR(7 downto 0) := "00000110";
constant mn_read_cinv : STD_LOGIC_VECTOR(7 downto 0) := "00000111";
constant mn_finalize : STD_LOGIC_VECTOR(7 downto 0) := "00001000";
constant mn_show_result : STD_LOGIC_VECTOR(7 downto 0) := "00001001";
constant mn_show_status : STD_LOGIC_VECTOR(7 downto 0) := "00001010";
constant mn_prepare_for_data : STD_LOGIC_VECTOR(7 downto 0) := "00001011";
 
---- addresses for memory data
constant addr_hashM : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant addr_c1 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant addr_N : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant addr_E : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant addr_d2 : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant addr_c2 : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant addr_c : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant addr_hashMc : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant addr_cinv : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101";
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110";
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111";
 
---- help_statuses_for_clarity
constant stat_all_data_readed : STD_LOGIC_VECTOR(5 downto 0) := "111111";
constant stat_clear_status : STD_LOGIC_VECTOR(5 downto 0) := "000000";
 
end properties;
 
package body properties is
end properties;
/vhdl/commons/MontMult4inMux.vhd
0,0 → 1,77
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- Simple construction of 4 input asynchronous multiplexer. ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity MontMult4inMux is
generic (
word_size : integer := WORD_LENGTH
);
port (
ctrl : in STD_LOGIC_VECTOR(1 downto 0);
zero : in STD_LOGIC_VECTOR(word_size downto 0);
M : in STD_LOGIC_VECTOR(word_size downto 0);
Y : in STD_LOGIC_VECTOR(word_size downto 0);
YplusM : in STD_LOGIC_VECTOR(word_size downto 0);
output : out STD_LOGIC_VECTOR(word_size downto 0)
);
end MontMult4inMux;
 
architecture Behavioral of MontMult4inMux is
 
begin
output <= zero when ctrl = "00" else
M when ctrl = "01" else
Y when ctrl = "10" else
YplusM;
end Behavioral;
/vhdl/commons/properties.vhd
0,0 → 1,112
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- Properties file for multiplier and exponentiator ----
---- (512 bit). ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package properties is
 
-- Declare constants
constant BYTE : INTEGER := 8;
 
constant WORD_LENGTH : INTEGER := 512;
constant WORD_INTEGER : INTEGER := 10;
constant WORD_INT_LOG : INTEGER := 6;
constant WORD_INT_LOG_STR : STD_LOGIC_VECTOR(WORD_INT_LOG - 1 downto 0) := "111111";
 
constant count_up : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant count_down : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant do_nothing : STD_LOGIC_VECTOR(1 downto 0) := "11";
 
type multiplier_states is (NOP, CALCULATE_START, STOP);
 
type finalizer_states is (FIRST_RUN, NOP,
READ_DATA_HASH_M, READ_DATA_C1, READ_DATA_N, READ_DATA_E, READ_DATA_D2, READ_DATA_CINV,
COUNT_C2, EXP_Z_C2, SAVE_EXP_Z_C2, EXP_P_C2, SAVE_EXP_P_C2, EXP_CONTROL_C2, EXP_END_C2, SAVE_EXP_MULT_C2,
COUNT_Cinv, MULT_CINV, SAVE_MULT_CINV,
COUNT_C, MULT_C, SAVE_MULT_C,
COUNT_M, EXP_Z_M, SAVE_EXP_Z_M, EXP_P_M, SAVE_EXP_P_M, EXP_CONTROL_M, EXP_END_M, SAVE_EXP_M,
MAKE_COMPARE, COMP, COMPARE_RESULT,
INFO_RESULT, SHOW_RESULT, FAIL_STATE);
 
type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE,
DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE,
TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA);
 
---- mnemonics for finalizer
constant mn_read_hash_m : STD_LOGIC_VECTOR(7 downto 0) := "00000001";
constant mn_read_c1 : STD_LOGIC_VECTOR(7 downto 0) := "00000010";
constant mn_read_n : STD_LOGIC_VECTOR(7 downto 0) := "00000011";
constant mn_read_e : STD_LOGIC_VECTOR(7 downto 0) := "00000100";
constant mn_read_d2 : STD_LOGIC_VECTOR(7 downto 0) := "00000110";
constant mn_read_cinv : STD_LOGIC_VECTOR(7 downto 0) := "00000111";
constant mn_finalize : STD_LOGIC_VECTOR(7 downto 0) := "00001000";
constant mn_show_result : STD_LOGIC_VECTOR(7 downto 0) := "00001001";
constant mn_show_status : STD_LOGIC_VECTOR(7 downto 0) := "00001010";
constant mn_prepare_for_data : STD_LOGIC_VECTOR(7 downto 0) := "00001011";
 
---- addresses for memory data
constant addr_hashM : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant addr_c1 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant addr_N : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant addr_E : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant addr_d2 : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant addr_c2 : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant addr_c : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant addr_hashMc : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant addr_cinv : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101";
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110";
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111";
 
---- help_statuses_for_clarity
constant stat_all_data_readed : STD_LOGIC_VECTOR(5 downto 0) := "111111";
constant stat_clear_status : STD_LOGIC_VECTOR(5 downto 0) := "000000";
 
end properties;
 
package body properties is
end properties;
/vhdl/commons
vhdl/commons Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property

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