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URL https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk

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Rev 5 → Rev 6

/vhdl/commons/AsyncMux.vhd
0,0 → 1,75
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- Asynchronous multiplexer - nothing special. ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity AsyncMux is
generic (
word_size : integer := WORD_LENGTH
);
port (
input0 : in STD_LOGIC_VECTOR(word_size downto 0);
input1 : in STD_LOGIC_VECTOR(word_size downto 0);
ctrl : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(word_size downto 0)
);
end AsyncMux;
 
architecture Behavioral of AsyncMux is
 
begin
output <= input0 when (ctrl = '0') else
input1;
 
end Behavioral;
 
/vhdl/commons/RS232RefComp.vhd
0,0 → 1,406
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
 
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
 
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
 
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
 
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
 
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
 
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
 
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
 
--Clock Dividing Functions--
 
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
 
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
 
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
 
tClk <= rClkDiv(3); --define tClk
 
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
 
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
 
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
 
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
 
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
 
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
 
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
 
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
 
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
 
CE <= '1';
strNext <= strIdle;
end case;
end process;
 
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
 
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
 
case stbeCur is
 
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
 
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
 
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
 
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
 
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
 
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
 
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral;
/vhdl/commons/ShiftReg.vhd
0,0 → 1,94
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- Shift register - nothing special. ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ShiftReg is
generic (
length_1 : integer := BYTE;
length_2 : integer := WORD_LENGTH;
internal_data : integer := WORD_LENGTH
);
port (
input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
en : in STD_LOGIC;
shift : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end ShiftReg;
 
architecture Behavioral of ShiftReg is
 
signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0);
 
begin
reg : process (clk, reset, data)
begin
if (reset = '1') then
data <= (others => '0');
elsif (clk'event and clk = '1') then
if (en = '1') then
data(internal_data - 1 downto internal_data - length_1) <= input;
else
if (shift = '1') then
data <= '0' & data(internal_data - 1 downto 1);
end if;
end if;
end if;
output <= data(length_2 - 1 downto 0);
end process reg;
 
end Behavioral;
 
/vhdl/commons/counter.vhd
0,0 → 1,89
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- Counter - nothing special. ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity counter is
generic(
size : integer := 4
);
port (
count : in STD_LOGIC;
zero : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(size - 1 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end counter;
 
architecture Behavioral of Counter is
signal c : STD_LOGIC_VECTOR(size - 1 downto 0);
begin
licznik: process (reset,clk)
begin
if (clk = '1' and clk'Event) then
if (reset = '1') then
c <= (others => '0');
elsif count = '1' then
c <= c + 1;
elsif zero = '1' then
c <= (others => '0');
else
c <= c;
end if;
end if;
end process licznik;
OUTPUT <= c;
end Behavioral;
/vhdl/commons/dcms/dcms.v
0,0 → 1,67
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.1
// \ \ Application : xaw2verilog
// / / Filename : dcms.v
// /___/ /\ Timestamp : 03/24/2013 14:44:49
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle E:/spent i praca/OpenCores/fin_134above/dcms.xaw -st dcms.v
//Design Name: dcms
//Device: xc3s500e-5fg320
//
// Module dcms
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
 
module dcms(CLKIN_IN,
CLKDV_OUT,
CLK0_OUT);
 
input CLKIN_IN;
output CLKDV_OUT;
output CLK0_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IN),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
endmodule
/vhdl/commons/dcms/dcms.xaw
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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/vhdl/commons/dcms/dcms_arwz.ucf
0,0 → 1,17
# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_SP_INST CLK_FEEDBACK = 1X;
INST DCM_SP_INST CLKDV_DIVIDE = 4.0;
INST DCM_SP_INST CLKFX_DIVIDE = 1;
INST DCM_SP_INST CLKFX_MULTIPLY = 4;
INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_SP_INST CLKIN_PERIOD = 20.000;
INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_SP_INST FACTORY_JF = C080;
INST DCM_SP_INST PHASE_SHIFT = 0;
INST DCM_SP_INST STARTUP_WAIT = FALSE;
/vhdl/commons/dcms
vhdl/commons/dcms Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: vhdl/commons/dcms.vhd =================================================================== --- vhdl/commons/dcms.vhd (nonexistent) +++ vhdl/commons/dcms.vhd (revision 6) @@ -0,0 +1,102 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 14.2 +-- \ \ Application : xaw2vhdl +-- / / Filename : dcms.vhd +-- /___/ /\ Timestamp : 08/13/2019 22:16:29 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-intstyle E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/commons/dcms/dcms.xaw -st dcms.vhd +--Design Name: dcms +--Device: xc3s500e-5fg320 +-- +-- Module dcms +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity dcms is + port ( CLKIN_IN : in std_logic; + CLKDV_OUT : out std_logic; + CLKDV_OUT1 : out std_logic; + CLKDV_OUT2 : out std_logic; + CLKDV_OUT3 : out std_logic; + CLK0_OUT : out std_logic); +end dcms; + +architecture BEHAVIORAL of dcms is + signal CLKDV_BUF : std_logic; + signal CLKFB_IN : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLK0_OUT <= CLKFB_IN; + CLKDV_BUFG_INST : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT); + + CLKDV_BUFG_INST1 : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT1); + + CLKDV_BUFG_INST2 : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT2); + + CLKDV_BUFG_INST3 : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT3); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 5.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>CLKDV_BUF, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: vhdl/commons/properties.vhd =================================================================== --- vhdl/commons/properties.vhd (revision 5) +++ vhdl/commons/properties.vhd (revision 6) @@ -17,7 +17,7 @@ ---- ---- ----------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- Copyright (C) 2019 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- @@ -66,9 +66,9 @@ COUNT_POWER, EXP_Z, SAVE_EXP_Z, EXP_P, SAVE_EXP_P, EXP_CONTROL, EXP_END, SAVE_EXP_MULT, INFO_RESULT, SHOW_RESULT); -type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE, - DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE, - TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA); +type comm_ctrl_states is (NOP, DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_MOD_EXP, + OUTPUT_DATA, INFO_STATE, TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, + MOVE_DATA, MOVE_OUTPUT_DATA); ---- mnemonics for exponentiator constant mn_read_base : STD_LOGIC_VECTOR(2 downto 0) := "000"; @@ -77,7 +77,6 @@ constant mn_read_residuum : STD_LOGIC_VECTOR(2 downto 0) := "011"; constant mn_count_power : STD_LOGIC_VECTOR(2 downto 0) := "100"; constant mn_show_result : STD_LOGIC_VECTOR(2 downto 0) := "101"; -constant mn_show_status : STD_LOGIC_VECTOR(2 downto 0) := "110"; constant mn_prepare_for_data : STD_LOGIC_VECTOR(2 downto 0) := "111"; ---- addresses for memory data
/vhdl/communication/ModExpComm.vhd
0,0 → 1,351
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- This module is example implementation of the Montgomery ----
---- modular exponentiator combined with the RS-232 communication----
---- with PC. All related to the communication logic was ----
---- inclueded here. Input data are retrieved by serial input ----
---- and converted into parallel data by the shift registers ----
---- After exponentiation in similar way parallel data are ----
---- converted into serial data. For the communication, the ----
---- RS232RefComp module made by Digilent was used and slightly ----
---- modified (increased data transfer speed to 115 200 bps). ----
---- ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
-- Definition of the component
entity ModExpComm is
generic (word_size : integer := WORD_LENGTH);
port (
DATA_RXD : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
DATA_TXD : out STD_LOGIC
);
end ModExpComm;
 
architecture Behavioral of ModExpComm is
 
-- This is DCM component generated by the ISE. It was used due
-- to maximum clock speed available in the S3EBOARD served by
-- the Digilent (50 MHz) it is used in order to decrease speed
-- of exponentiator core. RS232 is working with 50 MHz and the
-- rest part of the core is working with 10 MHz. This is due
-- to timing estimation of ISE.
component dcms is
port (
CLKIN_IN : in STD_LOGIC;
CLKDV_OUT : out STD_LOGIC;
CLK0_OUT : out STD_LOGIC
);
end component dcms;
 
-- Montgomery modular exponentiator
component ModExp is
generic (
word_size : integer := WORD_LENGTH;
word_binary : integer := WORD_INTEGER
);
Port (
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
ctrl : in STD_LOGIC_VECTOR(2 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in_ready : in STD_LOGIC;
ready : out STD_LOGIC;
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0)
);
end component ModExp;
 
-- RS232 component made by the Digilent
-- all checking was ignored but for communication
-- odd parity is used
component Rs232RefComp is
port (
TXD : out STD_LOGIC := '1';
RXD : in STD_LOGIC;
CLK : in STD_LOGIC; --Master Clock
DBIN : in STD_LOGIC_VECTOR(7 downto 0); --Data Bus in
DBOUT : out STD_LOGIC_VECTOR(7 downto 0); --Data Bus out
RDA : inout STD_LOGIC; --Read Data Available
TBE : inout STD_LOGIC := '1'; --Transfer Bus Empty
RD : in STD_LOGIC; --Read Strobe
WR : in STD_LOGIC; --Write Strobe
PE : out STD_LOGIC; --Parity Error Flag
FE : out STD_LOGIC; --Frame Error Flag
OE : out STD_LOGIC; --Overwrite Error Flag
RST : in STD_LOGIC := '0' --Master Reset
);
end component Rs232RefComp;
 
-- Register for storing control word for ModExpComm component
component Reg is
generic(word_size : integer := 8);
port(
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component Reg;
 
---- Shift registers for input and output data for the modular exponentiator
component ShiftReg is
generic (
length_1 : integer := BYTE;
length_2 : integer := WORD_LENGTH;
internal_data : integer := WORD_LENGTH
);
port (
input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
en : in STD_LOGIC;
shift : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component ShiftReg;
 
---- some 'help' mux at the output of the component
component AsyncMux is
generic(
word_size : integer := WORD_LENGTH
);
port(
input0 : in STD_LOGIC_VECTOR(word_size downto 0);
input1 : in STD_LOGIC_VECTOR(word_size downto 0);
ctrl : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(word_size downto 0)
);
end component AsyncMux;
 
---- State machine
component ModExpDataCtrlSM is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
RDAsig : in STD_LOGIC;
TBEsig : in STD_LOGIC;
RDsig : out STD_LOGIC;
WRsig : out STD_LOGIC;
data_in_ready : out STD_LOGIC;
readySig : in STD_LOGIC;
modExpCtrlRegEn : out STD_LOGIC;
dataToModExpEn : out STD_LOGIC;
dataToModExpShift : out STD_LOGIC;
dataFromModExpEn : out STD_LOGIC;
dataFromModExpShift : out STD_LOGIC;
muxCtrl : out STD_LOGIC;
opcodes : in STD_LOGIC_VECTOR(2 downto 0);
controlStateOut : out STD_LOGIC_VECTOR(2 downto 0)
);
end component ModExpDataCtrlSM;
 
-- All signals needed in the implementation
signal clk_div : STD_LOGIC;
signal clk_0 : STD_LOGIC;
 
signal dataTXD : STD_LOGIC_VECTOR(7 downto 0);
signal dataRXD : STD_LOGIC_VECTOR(7 downto 0);
signal RDAsig : STD_LOGIC;
signal TBEsig : STD_LOGIC;
signal RDsig : STD_LOGIC;
signal WRsig : STD_LOGIC;
signal PEsig : STD_LOGIC;
signal FEsig : STD_LOGIC;
signal OEsig : STD_LOGIC;
 
signal modExpInput : STD_LOGIC_VECTOR(word_size - 1 downto 0);
signal modExpCtrl : STD_LOGIC_VECTOR(2 downto 0);
signal modExpCtrlRegEn : STD_LOGIC;
signal data_in_ready : STD_LOGIC;
signal readySig : STD_LOGIC;
signal modExpOutput : STD_LOGIC_VECTOR(word_size - 1 downto 0);
 
signal dataToModExpEn : STD_LOGIC;
signal dataToModExpShift : STD_LOGIC;
 
signal dataFromModExpEn : STD_LOGIC;
signal dataFromModExpShift : STD_LOGIC;
 
signal inputToMux : STD_LOGIC_VECTOR(BYTE - 1 downto 0);
signal controlStateOut : STD_LOGIC_VECTOR(2 downto 0);
signal muxCtrl : STD_LOGIC;
 
signal ctrl_zero : STD_LOGIC_VECTOR(4 downto 0) := "00000";
signal control_state_to_out : STD_LOGIC_VECTOR(7 downto 0);
begin
-- Architecture definition
ctrl_zero <= (others => '0');
control_state_to_out <= controlStateOut & ctrl_zero;
-- DCM
dcm_module : dcms
port map(
CLKIN_IN => CLK,
CLKDV_OUT => clk_div, --clk_null,
CLK0_OUT => clk_0
);
-- RS232 component
serialPort : Rs232RefComp
port map (
TXD => DATA_TXD,
RXD => DATA_RXD,
CLK => clk_0,
DBIN => dataTXD,
DBOUT => dataRXD,
RDA => RDAsig, --Read Data Available
TBE => TBEsig, --Transfer Bus Empty
RD => RDsig, --Read Strobe
WR => WRsig, --Write Strobe
PE => PEsig, --Parity Error Flag
FE => FEsig, --Frame Error Flag
OE => OEsig, --Overwrite Error Flag
RST => RESET --Master Reset
);
-- Shift register at input of the modular exponentiator
-- (convert data from 8 bit to 32 bit, 64 bit, 512 bit, etc.)
modExpCompIn : ShiftReg
generic map(
length_1 => BYTE,
length_2 => WORD_LENGTH,
internal_data => WORD_LENGTH
)
port map (
input => dataRXD,
output => modExpInput,
en => dataToModExpEn,
shift => dataToModExpShift,
clk => CLK_div,
reset => RESET
);
-- Control register
modCtrl : Reg
generic map(
word_size => 3
)
port map (
input => dataRXD(2 downto 0),
output => modExpCtrl,
enable => modExpCtrlRegEn,
clk => CLK_div,
reset => RESET
);
 
-- Modular exponentiator component
ModExpComp : ModExp
port map (
input => modExpInput,
ctrl => modExpCtrl,
clk => CLK_div,
reset => RESET,
data_in_ready => data_in_ready,
ready => readySig,
output => modExpOutput
);
-- Shift register at output of the modular exponentiator
-- (convert data from 32 bit, 64 bit, 512 bit, etc. to 8 bit)
dataFromModExpComponent : ShiftReg
generic map(
length_1 => WORD_LENGTH,
length_2 => BYTE,
internal_data => WORD_LENGTH
)
port map (
input => modExpOutput,
output => inputToMux,
en => dataFromModExpEn,
shift => dataFromModExpShift,
clk => CLK_div,
reset => RESET
);
-- Multiplexer at the output of the component
outMux : AsyncMux
generic map(
word_size => BYTE - 1
)
port map(
input0 => inputToMux,
input1 => control_state_to_out,
ctrl => muxCtrl,
output => dataTXD
);
 
-- State machine
stateMachine : ModExpDataCtrlSM
port map(
clk => CLK_div,
reset => RESET,
RDAsig => RDAsig,
TBEsig => TBEsig,
RDsig => RDsig,
WRsig => WRsig,
data_in_ready => data_in_ready,
readySig => readySig,
modExpCtrlRegEn => modExpCtrlRegEn,
dataToModExpEn => dataToModExpEn,
dataToModExpShift => dataToModExpShift,
dataFromModExpEn => dataFromModExpEn,
dataFromModExpShift => dataFromModExpShift,
muxCtrl => muxCtrl,
opcodes => dataRXD(2 downto 0),
controlStateOut => controlStateOut
);
 
end Behavioral;
/vhdl/communication/ModExpDataCtrlSM.vhd
0,0 → 1,563
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- This module is state machine for the example implementation ----
---- of the Montgomery modular exponentiatorcombined with the ----
---- RS-232 communication with PC. ----
---- ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ModExpDataCtrlSM is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
RDAsig : in STD_LOGIC;
TBEsig : in STD_LOGIC;
RDsig : out STD_LOGIC;
WRsig : out STD_LOGIC;
data_in_ready : out STD_LOGIC;
readySig : in STD_LOGIC;
modExpCtrlRegEn : out STD_LOGIC;
dataToModExpEn : out STD_LOGIC;
dataToModExpShift : out STD_LOGIC;
dataFromModExpEn : out STD_LOGIC;
dataFromModExpShift : out STD_LOGIC;
muxCtrl : out STD_LOGIC;
opcodes : in STD_LOGIC_VECTOR(2 downto 0);
controlStateOut : out STD_LOGIC_VECTOR(2 downto 0)
);
end ModExpDataCtrlSM;
 
architecture Behavioral of ModExpDataCtrlSM is
 
-- Counters are used for both bit counting in byte
-- and composing full length word in exponentiator
component counter is
generic(
size : integer := 4
);
port (
count : in STD_LOGIC;
zero : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (size - 1 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component counter;
 
-- some constants for temp_state signal which is used in TEMPORARY_STATE.
-- This state is used as something like "wait" command due to data
-- propagation in the core
constant rd_data : STD_LOGIC_VECTOR(2 downto 0) := "000";
constant mk_fin : STD_LOGIC_VECTOR(2 downto 0) := "001";
constant dat_out_prop : STD_LOGIC_VECTOR(2 downto 0) := "010";
constant info_st : STD_LOGIC_VECTOR(2 downto 0) := "011";
constant mv_dat : STD_LOGIC_VECTOR(2 downto 0) := "100";
constant nothing : STD_LOGIC_VECTOR(2 downto 0) := "101";
 
signal state : comm_ctrl_states := NOP;
signal next_state : comm_ctrl_states := NOP;
 
signal temp_state : STD_LOGIC_VECTOR (2 downto 0) := nothing;
 
-- This signals are used for control the counters for data shifting
-- in shift registers (by bytes). This length have to be modified
-- with changing the used word size.
-- Modify for variable key size
-- In fact it is modified from the properties file
signal serialDataCtrCt : STD_LOGIC;
signal serialDataCtrZero : STD_LOGIC;
signal serialDataCtrOut : STD_LOGIC_VECTOR(WORD_INT_LOG downto 0);
 
-- This signals are used for control the counters for data shifting - bits in
-- bytes.
-- DO NOT MODIFY!!!
signal shiftDataCtrCt : STD_LOGIC;
signal shiftDataCtrZero : STD_LOGIC;
signal shiftDataCtrOut : STD_LOGIC_VECTOR(3 downto 0);
 
begin
-- State machine process
SM : process(state, RDAsig, TBEsig, shiftDataCtrOut,
serialDataCtrOut, opcodes, readySig)
begin
case state is
-- This state prepares whoole core before calculations
-- 'No operation' state
when NOP =>
WRsig <= '0';
modExpCtrlRegEn <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrZero <= '1';
serialDataCtrCt <= '0';
shiftDataCtrZero <= '1';
shiftDataCtrCt <= '0';
RDsig <= '0';
-- This is something like 'info' word
if (readySig = '1') then
controlStateOut <= "100";
else
controlStateOut <= "000";
end if;
muxCtrl <= '1';
data_in_ready <= '0';
temp_state <= nothing; -- not important
-- RDAsig = '1' means that some data
-- appeard in the RS-232 input
if (RDAsig = '1') then
next_state <= DECODE_IN;
else
next_state <= NOP;
end if;
when DECODE_IN =>
WRsig <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrZero <= '1';
serialDataCtrCt <= '0';
shiftDataCtrZero <= '1';
shiftDataCtrCt <= '0';
RDsig <= '1';
controlStateOut <= "000";
muxCtrl <= '1';
data_in_ready <= '0';
modExpCtrlRegEn <= '1';
 
-- firstly from the RS-232 input comes OPCODE informing the core
-- what to do. Data can appeard in any order. This opcode are saved
-- in the suitable register at the input of the modular exponentiator
if (opcodes = mn_read_base) or (opcodes = mn_read_modulus) or
(opcodes = mn_read_exponent) or (opcodes = mn_read_residuum) then
next_state <= TEMPORARY_STATE;
temp_state <= rd_data;
elsif (opcodes = mn_count_power) then
next_state <= TEMPORARY_STATE;
temp_state <= mk_fin;
elsif (opcodes = mn_show_result) then
if (readySig = '1') then
next_state <= TEMPORARY_STATE;
temp_state <= dat_out_prop;
else
next_state <= TEMPORARY_STATE;
temp_state <= info_st;
end if;
elsif (opcodes = mn_prepare_for_data) then
next_state <= TEMPORARY_STATE;
temp_state <= nothing;
else
next_state <= NOP;
temp_state <= nothing; -- not important
end if;
when READ_DATA =>
-- For now need to 'restart' all the flow of reading data
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
dataToModExpEn <= '1';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
controlStateOut <= "000";
muxCtrl <= '1';
data_in_ready <= '0';
temp_state <= nothing; -- not important
if (RDAsig = '0') then
next_state <= READ_DATA;
else
next_state <= DECODE_READ;
end if;
-- This state is for the control of number of the 8-bit 'packets'
-- of the input data for the modular exponentiator
when DECODE_READ =>
modExpCtrlRegEn <= '0';
WRsig <= '0';
serialDataCtrCt <= '1';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
RDsig <= '1';
dataToModExpEn <= '1';
controlStateOut <= "000";
muxCtrl <= '1';
data_in_ready <= '0';
-- Data reading X times 8 bit -> modify for variable key length
-- In fact it is modified from the properties file
if (serialDataCtrOut(WORD_INT_LOG - 1 downto 0) = WORD_INT_LOG_STR) then
next_state <= DECODE_READ_PROP;
temp_state <= nothing; -- not important
else
next_state <= TEMPORARY_STATE;
temp_state <= mv_dat;
end if;
-- Some info state for the modular exponentiator core,
-- that some data are at the input - after the end of the
-- reading data
when DECODE_READ_PROP =>
modExpCtrlRegEn <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
RDsig <= '0';
dataToModExpEn <= '0';
serialDataCtrCt <= '0';
muxCtrl <= '1';
data_in_ready <= '1';
temp_state <= nothing; -- not important
controlStateOut <= "000";
next_state <= INFO_STATE;
-- This state is for moving bits in data word for the
-- modular exponentiator counter counts to 8 while data
-- are shifted
when MOVE_DATA =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '1';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrZero <= '0';
temp_state <= nothing;
controlStateOut <= "000";
muxCtrl <= '1';
data_in_ready <= '0';
--- shifting data in register -> DO NOT MODIFY!!!
if (shiftDataCtrOut(2 downto 0) = "111") then
shiftDataCtrZero <= '1';
shiftDataCtrCt <= '0';
next_state <= READ_DATA;
else
shiftDataCtrZero <= '0';
shiftDataCtrCt <= '1';
next_state <= MOVE_DATA;
end if;
-- If all the needed data appeared at the input
-- and 'mn_count_power' command appeared modular exponentiation
-- is performed. This state is present until modular exponentiation
-- is calculated
when MAKE_MOD_EXP =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
muxCtrl <= '1';
data_in_ready <= '1';
-- Here
if (readySig = '1') then
controlStateOut <= "100";
next_state <= TEMPORARY_STATE;
temp_state <= info_st;
else
controlStateOut <= "001";
next_state <= MAKE_MOD_EXP;
temp_state <= nothing;
end if;
-- When 'mn_show_result' command appears in the core input,
-- the result from the modular exponentiation feeds the output
-- Here and below state are also for 'data propagation'
when DATA_TO_OUT_PROPAGATE =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
dataFromModExpEn <= '1';
dataFromModExpShift <= '0';
next_state <= DATA_TO_OUT_PROPAGATE2;
temp_state <= nothing;
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
temp_state <= nothing; -- not important
when DATA_TO_OUT_PROPAGATE2 =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '1';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
next_state <= OUTPUT_DATA;
temp_state <= nothing;
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
temp_state <= nothing; -- not important
-- Here data from parallel form are transformed to serial form.
-- This state is for the control of number of the 8-bit 'packets'
-- of the input data for the modular exponentiator
when OUTPUT_DATA =>
modExpCtrlRegEn <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
serialDataCtrZero <= '0';
RDsig <= '0';
WRsig <= '1';
serialDataCtrCt <= '1';
temp_state <= nothing;
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
if (serialDataCtrOut(WORD_INT_LOG) = '1') then
next_state <= NOP;
else
next_state <= MOVE_OUTPUT_DATA;
end if;
-- This state is for moving bits in data word for the
-- modular exponentiator counter counts to 8 while data
-- are shifted
when MOVE_OUTPUT_DATA =>
if (TBEsig = '0') then
-- Here we have to wait for the sending the previous serial data
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
next_state <= MOVE_OUTPUT_DATA;
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
temp_state <= nothing; -- not important
else
-- Here data are shifted in the output data word
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '1';
shiftDataCtrCt <= '1';
serialDataCtrZero <= '0';
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
temp_state <= nothing; -- not important
-- Output register shifting DO NOT MODIFY!!!
if (shiftDataCtrOut(3) = '1') then
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '1';
dataFromModExpShift <= '0';
next_state <= DATA_TO_OUT_PROPAGATE2;
else
shiftDataCtrZero <= '0';
next_state <= MOVE_OUTPUT_DATA;
end if;
end if;
-- State for informing 'the world' about the end of
-- the modular exponentiation
when INFO_STATE =>
modExpCtrlRegEn <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
if (readySig = '1') then
controlStateOut <= "100";
else
controlStateOut <= "000";
end if;
muxCtrl <= '1';
data_in_ready <= '0';
temp_state <= nothing; -- not important
RDsig <= '0';
WRsig <= '1';
next_state <= NOP;
-- This state is mostly used for 'data propagation'
-- and control of work of the modular exponentiator
-- its work/state depends on the 'temp_state' signal.
-- temp_state = nothing means that this state is not used
when TEMPORARY_STATE =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
if (readySig = '1') then
controlStateOut <= "100";
next_state <= TEMPORARY_STATE;
temp_state <= info_st;
else
controlStateOut <= "001";
next_state <= MAKE_MOD_EXP;
temp_state <= nothing;
end if;
if (temp_state = rd_data) then
muxCtrl <= '0';
data_in_ready <= '0';
next_state <= READ_DATA;
temp_state <= rd_data;
elsif (temp_state = mk_fin) then
muxCtrl <= '0';
data_in_ready <= '1';
next_state <= MAKE_MOD_EXP;
temp_state <= mk_fin;
elsif (temp_state = dat_out_prop) then
muxCtrl <= '1';
data_in_ready <= '0';
next_state <= DATA_TO_OUT_PROPAGATE;
temp_state <= dat_out_prop;
elsif (temp_state = info_st) then
muxCtrl <= '0';
data_in_ready <= '0';
next_state <= INFO_STATE;
temp_state <= info_st;
elsif (temp_state = mv_dat) then
muxCtrl <= '0';
data_in_ready <= '0';
next_state <= MOVE_DATA;
temp_state <= mv_dat;
else
muxCtrl <= '0';
data_in_ready <= '0';
next_state <= NOP;
temp_state <= nothing;
end if;
end case;
end process SM;
 
state_modifier : process (clk, reset)
begin
if (clk = '1' and clk'Event) then
if (reset = '1') then
state <= NOP;
else
state <= next_state;
end if;
end if;
end process state_modifier;
 
-- modify for changing width of the hey
-- in fact it is modified from the properties file
dataCounter : counter
generic map(
size => WORD_INT_LOG + 1
)
port map (
count => serialDataCtrCt,
zero => serialDataCtrZero,
output => serialDataCtrOut,
clk => clk,
reset => reset
);
shiftCounter : counter
generic map(
size => 4
)
port map (
count => shiftDataCtrCt,
zero => shiftDataCtrZero,
output => shiftDataCtrOut,
clk => clk,
reset => reset
);
 
end Behavioral;
/vhdl/communication/ModExpDataCtrlUCF.ucf
0,0 → 1,8
NET "DATA_RXD" LOC= "R7" | IOSTANDARD= LVTTL | SLEW= FAST ;
NET "DATA_TXD" LOC= "M14" | IOSTANDARD= LVTTL | DRIVE= 8 | SLEW= FAST ;
NET "CLK" LOC= "C9" | IOSTANDARD= LVCMOS33 | SLEW= FAST ;
NET "CLK" TNM_NET = "clk_group";
TIMESPEC "TS_CLK" = PERIOD "clk_group" 20 ns HIGH 40%;
 
NET "RESET" LOC= "K17" | IOSTANDARD= LVTTL | PULLDOWN;
SYSTEM_JITTER = 1 ns;
/vhdl/communication
vhdl/communication Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: vhdl/mod_exp/ModExp.vhd =================================================================== --- vhdl/mod_exp/ModExp.vhd (revision 5) +++ vhdl/mod_exp/ModExp.vhd (revision 6) @@ -8,7 +8,7 @@ ---- ---- ---- Description: ---- ---- Montgomery modular exponentiator main module. It combines ---- ----- all subomponents. It takes four numbers as the input: ---- +---- all subcomponents. It takes four numbers as the input: ---- ---- base, power, modulus and Montgomery residuum ---- ---- (2^(2*word_length) mod N) and results the modular ---- ---- exponentiation A^B mod M. ---- @@ -22,7 +22,7 @@ ---- ---- ----------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- Copyright (C) 2019 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- Index: vhdl/mod_mult/ModularMultiplierIterative.vhd =================================================================== --- vhdl/mod_mult/ModularMultiplierIterative.vhd (revision 5) +++ vhdl/mod_mult/ModularMultiplierIterative.vhd (revision 6) @@ -14,7 +14,7 @@ ---- R*R^{-1} == 1 mod M ---- ---- R = 2^word_length mod M ---- ---- and word_length is the binary width of the ---- ----- operated word (in this case 64 bit) ---- +---- operated word (in this case 32, 64 or 512 bit) ---- ---- To Do: ---- ---- ---- ---- Author(s): ---- @@ -23,7 +23,7 @@ ---- ---- ----------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- Copyright (C) 2019 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ----

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