URL
https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk
Subversion Repositories mod_mult_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_mult_exp/trunk/syn
- from Rev 3 to Rev 5
- ↔ Reverse comparison
Rev 3 → Rev 5
/XC3ES500/mod_exp/ModExp64.prj
0,0 → 1,8
vhdl work "../../../rtl/vhdl/mod_exp/blockMemory64/blockMemory.vhd" |
vhdl work "../../../rtl/vhdl/commons/properties_64bit.vhd" |
vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd" |
vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd" |
vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd" |
vhdl work "../../../rtl/vhdl/commons/Reg.vhd" |
vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd" |
vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd" |
/XC3ES500/mod_exp/ModExp512.xst
0,0 → 1,57
set -tmpdir "xst/projnav.tmp" |
set -xsthdpdir "xst" |
run |
-ifn ModExp512.prj |
-ifmt mixed |
-ofn ModExp |
-ofmt NGC |
-p xc3s500e-5-fg320 |
-top ModExp |
-opt_mode Speed |
-opt_level 1 |
-iuc NO |
-keep_hierarchy Soft |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-sd {"../../../rtl/vhdl/mod_exp/blockMemory512" } |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-verilog2001 YES |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style LUT |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-mux_style Auto |
-decoder_extract YES |
-priority_extract Yes |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-rom_style Auto |
-auto_bram_packing NO |
-mux_extract Yes |
-resource_sharing YES |
-async_to_sync NO |
-mult_style Auto |
-iobuf YES |
-max_fanout 100000 |
-bufg 24 |
-register_duplication YES |
-register_balancing No |
-slice_packing YES |
-optimize_primitives NO |
-use_clock_enable Yes |
-use_sync_set Yes |
-use_sync_reset Yes |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
/XC3ES500/mod_exp/ModExp.ut
0,0 → 1,22
-w |
-g DebugBitstream:No |
-g Binary:no |
-g CRC:Enable |
-g ConfigRate:1 |
-g ProgPin:PullUp |
-g DonePin:PullUp |
-g TckPin:PullUp |
-g TdiPin:PullUp |
-g TdoPin:PullUp |
-g TmsPin:PullUp |
-g UnusedPin:PullDown |
-g UserID:0xFFFFFFFF |
-g DCMShutdown:Disable |
-g StartUpClk:CClk |
-g DONE_cycle:4 |
-g GTS_cycle:5 |
-g GWE_cycle:6 |
-g LCK_cycle:NoWait |
-g Security:None |
-g DonePipe:Yes |
-g DriveDone:No |
/XC3ES500/mod_exp/ModExp64.xst
0,0 → 1,57
set -tmpdir "xst/projnav.tmp" |
set -xsthdpdir "xst" |
run |
-ifn ModExp64.prj |
-ifmt mixed |
-ofn ModExp |
-ofmt NGC |
-p xc3s500e-5-fg320 |
-top ModExp |
-opt_mode Speed |
-opt_level 1 |
-iuc NO |
-keep_hierarchy Soft |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-sd {"../../../rtl/vhdl/mod_exp/blockMemory64" } |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-verilog2001 YES |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style LUT |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-mux_style Auto |
-decoder_extract YES |
-priority_extract Yes |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-rom_style Auto |
-auto_bram_packing NO |
-mux_extract Yes |
-resource_sharing YES |
-async_to_sync NO |
-mult_style Auto |
-iobuf YES |
-max_fanout 100000 |
-bufg 24 |
-register_duplication YES |
-register_balancing No |
-slice_packing YES |
-optimize_primitives NO |
-use_clock_enable Yes |
-use_sync_set Yes |
-use_sync_reset Yes |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
/XC3ES500/mod_exp/ModExp32.prj
0,0 → 1,8
vhdl work "../../../rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd" |
vhdl work "../../../rtl/vhdl/commons/properties_32bit.vhd" |
vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd" |
vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd" |
vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd" |
vhdl work "../../../rtl/vhdl/commons/Reg.vhd" |
vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd" |
vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd" |
/XC3ES500/mod_exp/Makefile
0,0 → 1,58
PROJECT=mont-exp |
|
RM=/bin/rm -rf |
CP=/bin/cp |
|
PLATFORM=xc3s500e-fg320-5 |
|
XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/" |
XST_DIR=$(XILINX_DIR)"xst.exe" |
NGDBUILD_DIR=$(XILINX_DIR)"ngdbuild.exe" |
MAP=$(XILINX_DIR)"map.exe" |
PAR=$(XILINX_DIR)"par.exe" |
TRCE=$(XILINX_DIR)"trce.exe" |
BITGEN=$(XILINX_DIR)"bitgen.exe" |
|
clean: clean_postgen |
$(RM) "./out/"*.* |
$(RM) "./log/"*.* |
$(RM) "./out/" |
$(RM) "./log/" |
|
clean_postgen: |
$(RM) "./_xmsgs" |
$(RM) "./_ngo" |
$(RM) "./xlnx_auto_0_xdb" |
$(RM) "./xst" |
$(RM) *_vhdl.prj *.bgn *.bld *.csv *.drc *.lso *.map *.mrp *.ncd *.ngc *.ngd *.ngm *.ngr *.pad *.par *.pcf *.ptwx *.syr *.twr *.twx *.unroutes *.xpi *.xwbt |
|
synthesize: clean |
mkdir "./xst" |
mkdir "./xst/projnav.tmp" |
mkdir "./out/" |
mkdir "./log/" |
|
$(XST_DIR) -intstyle ise -ifn "./ModExp$(word).xst" -ofn "./ModExp.syr" |
|
translate: synthesize |
$(NGDBUILD_DIR) -intstyle ise -dd _ngo -sd "../../../rtl/vhdl/mod_exp/blockMemory$(word)" -nt timestamp -i -p $(PLATFORM) "ModExp.ngc" ModExp.ngd |
|
map: translate |
$(MAP) -intstyle ise -p $(PLATFORM) -cm area -ir off -pr off -c 100 -o ModExp_map.ncd ModExp.ngd ModExp.pcf |
|
par: map |
$(PAR) -w -intstyle ise -ol high -t 1 ModExp_map.ncd ModExp.ncd ModExp.pcf |
|
trce: par |
$(TRCE) -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml ModExp.twx ModExp.ncd -o ModExp.twr ModExp.pcf |
|
bitgen: trce |
$(BITGEN) -intstyle ise -f ModExp.ut ModExp.ncd |
|
postgen: |
mv *.log ./log |
mv *.xrpt ./log |
mv *.txt ./log |
mv *.xml ./log |
mv *.html ./log |
mv *.bit ./out |
/XC3ES500/mod_exp/ModExp512.prj
0,0 → 1,8
vhdl work "../../../rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd" |
vhdl work "../../../rtl/vhdl/commons/properties.vhd" |
vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd" |
vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd" |
vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd" |
vhdl work "../../../rtl/vhdl/commons/Reg.vhd" |
vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd" |
vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd" |
/XC3ES500/mod_exp/ModExp32.xst
0,0 → 1,57
set -tmpdir "xst/projnav.tmp" |
set -xsthdpdir "xst" |
run |
-ifn ModExp32.prj |
-ifmt mixed |
-ofn ModExp |
-ofmt NGC |
-p xc3s500e-5-fg320 |
-top ModExp |
-opt_mode Speed |
-opt_level 1 |
-iuc NO |
-keep_hierarchy Soft |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-sd {"../../../rtl/vhdl/mod_exp/blockMemory32" } |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-verilog2001 YES |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style LUT |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-mux_style Auto |
-decoder_extract YES |
-priority_extract Yes |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-rom_style Auto |
-auto_bram_packing NO |
-mux_extract Yes |
-resource_sharing YES |
-async_to_sync NO |
-mult_style Auto |
-iobuf YES |
-max_fanout 100000 |
-bufg 24 |
-register_duplication YES |
-register_balancing No |
-slice_packing YES |
-optimize_primitives NO |
-use_clock_enable Yes |
-use_sync_set Yes |
-use_sync_reset Yes |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
XC3ES500/mod_exp
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property