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/mod_sim_exp_pkg.vhd
0,0 → 1,605
----------------------------------------------------------------------
---- mod_sim_exp_pkg ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- Package for the Modular Simultaneous Exponentiation Core ----
---- Project. Contains the component declarations and used ----
---- constants. ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
package mod_sim_exp_pkg is
--------------------------------------------------------------------
---------------------- COMPONENT DECLARATIONS ----------------------
--------------------------------------------------------------------
--------------------------------------------------------------------
-- d_flip_flop
--------------------------------------------------------------------
-- 1-bit D flip-flop with asynchronous active high reset
--
component d_flip_flop is
port(
core_clk : in std_logic; -- clock signal
reset : in std_logic; -- active high reset
din : in std_logic; -- data in
dout : out std_logic -- data out
);
end component d_flip_flop;
--------------------------------------------------------------------
-- register_1b
--------------------------------------------------------------------
-- 1-bit register with asynchronous reset and clock enable
--
component register_1b is
port(
core_clk : in std_logic; -- clock input
ce : in std_logic; -- clock enable (active high)
reset : in std_logic; -- reset (active high)
din : in std_logic; -- data in
dout : out std_logic -- data out
);
end component register_1b;
--------------------------------------------------------------------
-- register_n
--------------------------------------------------------------------
-- n-bit register with asynchronous reset and clock enable
--
component register_n is
generic(
width : integer := 4
);
port(
core_clk : in std_logic; -- clock input
ce : in std_logic; -- clock enable (active high)
reset : in std_logic; -- reset (active high)
din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit
dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit
);
end component register_n;
--------------------------------------------------------------------
-- cell_1b_adder
--------------------------------------------------------------------
-- 1-bit full adder cell using combinatorial logic
--
component cell_1b_adder is
port (
-- input operands a, b
a : in std_logic;
b : in std_logic;
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- result out
r : out std_logic
);
end component cell_1b_adder;
--------------------------------------------------------------------
-- cell_1b_mux
--------------------------------------------------------------------
-- 1-bit mux for a standard cell in the montgommery multiplier
-- systolic array
--
component cell_1b_mux is
port (
-- input bits
my : in std_logic;
y : in std_logic;
m : in std_logic;
-- selection bits
x : in std_logic;
q : in std_logic;
-- mux out
result : out std_logic
);
end component cell_1b_mux;
--------------------------------------------------------------------
-- cell_1b
--------------------------------------------------------------------
-- 1-bit cell for the systolic array
--
component cell_1b is
port (
-- operand input bits (m+y, y and m)
my : in std_logic;
y : in std_logic;
m : in std_logic;
-- operand x input bit and q
x : in std_logic;
q : in std_logic;
-- previous result input bit
a : in std_logic;
-- carry's
cin : in std_logic;
cout : out std_logic;
-- cell result out
r : out std_logic
);
end component cell_1b;
--------------------------------------------------------------------
-- adder_block
--------------------------------------------------------------------
-- (width)-bit full adder block using cell_1b_adders with buffered
-- carry out
--
component adder_block is
generic (
width : integer := 32 --adder operand widths
);
port (
-- clock input
core_clk : in std_logic;
-- adder input operands a, b (width)-bit
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- adder result out (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end component adder_block;
--------------------------------------------------------------------
-- standard_cell_block
--------------------------------------------------------------------
-- a standard cell block of (width)-bit for the montgommery multiplier
-- systolic array
--
component standard_cell_block is
generic (
width : integer := 16
);
port (
-- modulus and y operand input (width)-bit
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
-- q and x operand input (serial input)
x : in std_logic;
q : in std_logic;
-- previous result in (width)-bit
a : in std_logic_vector((width-1) downto 0);
-- carry in and out
cin : in std_logic;
cout : out std_logic;
-- result out (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end component standard_cell_block;
--------------------------------------------------------------------
-- counter_sync
--------------------------------------------------------------------
-- counter with synchronous count enable. It generates an
-- overflow when max_value is reached
--
component counter_sync is
generic(
max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
);
port(
reset_value : in integer; -- value the counter counts to
core_clk : in std_logic; -- clock input
ce : in std_logic; -- count enable
reset : in std_logic; -- reset input
overflow : out std_logic -- gets high when counter reaches reset_value
);
end component counter_sync;
--------------------------------------------------------------------
-- stepping_logic
--------------------------------------------------------------------
-- stepping logic for the pipeline, generates the start pulses for the
-- first stage and keeps track of when the last stages are done
--
component stepping_logic is
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic; -- clock input
start : in std_logic; -- start signal for pipeline (one multiplication)
reset : in std_logic; -- reset signal
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
start_first_stage : out std_logic; -- start pulse output for first stage
stepping_done : out std_logic -- done signal
);
end component stepping_logic;
 
--------------------------------------------------------------------
-- x_shift_reg
--------------------------------------------------------------------
-- shift register for the x operand of the multiplier
-- outputs the lsb of the register or bit at offset according to the
-- selected pipeline part
--
component x_shift_reg is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 48; -- total number of stages
tl : integer := 16 -- lower number of stages
);
port(
-- clock input
clk : in std_logic;
-- x operand in (n-bit)
x_in : in std_logic_vector((n-1) downto 0);
-- control signals
reset : in std_logic; -- reset, clears register
load_x : in std_logic; -- load operand into shift register
next_x : in std_logic; -- next bit of x
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
-- x operand bit out (serial)
xi : out std_logic
);
end component x_shift_reg;
 
--------------------------------------------------------------------
-- mod_sim_exp_core
--------------------------------------------------------------------
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
--
component mod_sim_exp_core is
generic(
C_NR_BITS_TOTAL : integer := 1536;
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true
);
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
fifo_push : in std_logic; -- push data in exponent fifo
fifo_full : out std_logic; -- high if fifo is full
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
);
end component mod_sim_exp_core;
 
component autorun_cntrl is
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
op_sel : out std_logic_vector (1 downto 0);
start_multiplier : out std_logic;
multiplier_done : in std_logic;
read_buffer : out std_logic;
buffer_din : in std_logic_vector (31 downto 0);
buffer_empty : in std_logic
);
end component autorun_cntrl;
component fifo_primitive is
port (
clk : in std_logic;
din : in std_logic_vector (31 downto 0);
dout : out std_logic_vector (31 downto 0);
empty : out std_logic;
full : out std_logic;
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end component fifo_primitive;
component modulus_ram is
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end component modulus_ram;
--------------------------------------------------------------------
-- mont_ctrl
--------------------------------------------------------------------
-- This module controls the montgommery mutliplier and controls traffic between
-- RAM and multiplier. Also contains the autorun logic for exponentiations.
--
component mont_ctrl is
port (
clk : in std_logic;
reset : in std_logic;
-- bus side
start : in std_logic;
x_sel_single : in std_logic_vector(1 downto 0);
y_sel_single : in std_logic_vector(1 downto 0);
run_auto : in std_logic;
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
done : out std_logic;
calc_time : out std_logic;
-- multiplier side
op_sel : out std_logic_vector(1 downto 0);
load_x : out std_logic;
load_result : out std_logic;
start_multiplier : out std_logic;
multiplier_ready : in std_logic
);
end component mont_ctrl;
component operand_dp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component operand_dp;
component operand_mem is
generic(
n : integer := 1536
);
port(
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
write_enable : in std_logic;
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector((n-1) downto 0);
m : out std_logic_vector((n-1) downto 0);
result_in : in std_logic_vector((n-1) downto 0);
-- control signals
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
end component operand_mem;
component operand_ram is
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (1536 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
end component operand_ram;
component operands_sp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end component operands_sp;
component sys_stage is
generic(
width : integer := 32 -- width of the stage
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y operand input (width)-bit
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width) downto 0);
my_cin : in std_logic;
my_cout : out std_logic;
-- q and x operand input (serial input)
xin : in std_logic;
qin : in std_logic;
-- q and x operand output (serial output)
xout : out std_logic;
qout : out std_logic;
-- msb input (lsb from next stage, for shift right operation)
a_msb : in std_logic;
a_0 : out std_logic;
-- carry out(clocked) and in
cin : in std_logic;
cout : out std_logic;
-- reduction adder carry's
red_cin : in std_logic;
red_cout : out std_logic;
-- control singals
start : in std_logic;
reset : in std_logic;
done : out std_logic;
-- result out
r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
r : out std_logic_vector((width-1) downto 0)
);
end component sys_stage;
 
--------------------------------------------------------------------
-- sys_last_cell_logic
--------------------------------------------------------------------
-- logic needed as the last piece in the systolic array pipeline
-- calculates the last 2 bits of the cell_result and finishes the reduction
-- also generates the result selection signal
--
component sys_last_cell_logic is
port (
core_clk : in std_logic; -- clock input
reset : in std_logic;
a_0 : out std_logic; -- a_msb for last stage
cin : in std_logic; -- cout from last stage
red_cin : in std_logic; -- red_cout from last stage
r_sel : out std_logic; -- result selection bit
start : in std_logic -- done signal from last stage
);
end component sys_last_cell_logic;
--------------------------------------------------------------------
-- sys_first_cell_logic
--------------------------------------------------------------------
-- logic needed as the first piece in the systolic array pipeline
-- calculates the first my_cout and generates q signal
--
component sys_first_cell_logic is
port (
m0 : in std_logic; -- lsb from m operand
y0 : in std_logic; -- lsb from y operand
my_cout : out std_logic; -- my_cin for first stage
xi : in std_logic; -- xi operand input
xout : out std_logic; -- xin for first stage
qout : out std_logic; -- qin for first stage
cout : out std_logic; -- cin for first stage
a_0 : in std_logic; -- a_0 from first stage
red_cout : out std_logic -- red_cin for first stage
);
end component sys_first_cell_logic;
 
--------------------------------------------------------------------
-- sys_pipeline
--------------------------------------------------------------------
-- the pipelined systolic array for a montgommery multiplier
-- contains a structural description of the pipeline using the systolic stages
--
component sys_pipeline is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- total number of stages (minimum 2)
tl : integer := 64; -- lower number of stages (minimum 1)
split : boolean := true -- if true the pipeline wil be split in 2 parts,
-- if false there are no lower stages, only t counts
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y opperand input (n)-bit
y : in std_logic_vector((n-1) downto 0);
m : in std_logic_vector((n-1) downto 0);
-- x operand input (serial)
xi : in std_logic;
next_x : out std_logic; -- next x operand bit
-- control signals
start : in std_logic; -- start multiplier
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
-- result out
r : out std_logic_vector((n-1) downto 0)
);
end component sys_pipeline;
component mont_multiplier is
generic (
n : integer := 1536; -- width of the operands
t : integer := 96; -- total number of stages (minimum 2)
tl : integer := 32; -- lower number of stages (minimum 1)
split : boolean := true -- if true the pipeline wil be split in 2 parts,
-- if false there are no lower stages, only t counts
);
port (
-- clock input
core_clk : in std_logic;
-- operand inputs
xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
m : in std_logic_vector((n-1) downto 0); -- modulus
-- result output
r : out std_logic_vector((n-1) downto 0); -- result
-- control signals
start : in std_logic;
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
load_x : in std_logic;
ready : out std_logic
);
end component mont_multiplier;
end package mod_sim_exp_pkg;
/mod_sim_exp_core.vhd
0,0 → 1,194
----------------------------------------------------------------------
---- mod_sim_exp_core ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- toplevel of a modular simultaneous exponentiation core ----
---- using a pipelined montgommery multiplier with split ----
---- pipeline and auto-run support ----
---- ----
---- Dependencies: ----
---- - mont_mult_sys_pipeline ----
---- - operand_mem ----
---- - fifo_primitive ----
---- - mont_ctrl ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
entity mod_sim_exp_core is
generic(
C_NR_BITS_TOTAL : integer := 1536;
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true
);
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
fifo_push : in std_logic; -- push data in exponent fifo
fifo_full : out std_logic; -- high if fifo is full
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
);
end mod_sim_exp_core;
 
 
architecture Structural of mod_sim_exp_core is
-- data busses
signal xy : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- x and y operand data bus RAM -> multiplier
signal m : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- modulus data bus RAM -> multiplier
signal r : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- result data bus RAM <- multiplier
-- control signals
signal op_sel : std_logic_vector(1 downto 0); -- operand selection
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
signal mult_ready : std_logic;
signal start_mult : std_logic;
signal load_x : std_logic;
signal load_result : std_logic;
-- fifo signals
signal fifo_empty : std_logic;
signal fifo_pop : std_logic;
signal fifo_nopop : std_logic;
signal fifo_dout : std_logic_vector(31 downto 0);
begin
 
-- The actual multiplier
the_multiplier : mont_multiplier
generic map(
n => C_NR_BITS_TOTAL,
t => C_NR_STAGES_TOTAL,
tl => C_NR_STAGES_LOW,
split => C_SPLIT_PIPELINE
)
port map(
core_clk => clk,
xy => xy,
m => m,
r => r,
start => start_mult,
reset => reset,
p_sel => p_sel,
load_x => load_x,
ready => mult_ready
);
 
-- Block ram memory for storing the operands and the modulus
the_memory : operand_mem
generic map(
n => C_NR_BITS_TOTAL
)
port map(
data_in => data_in,
data_out => data_out,
rw_address => rw_address,
write_enable => write_enable,
op_sel => op_sel,
xy_out => xy,
m => m,
result_in => r,
load_result => load_result,
result_dest_op => result_dest_op,
collision => collision,
clk => clk
);
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
-- A fifo for auto-run operand selection
the_exponent_fifo : fifo_primitive
port map(
clk => clk,
din => fifo_din,
dout => fifo_dout,
empty => fifo_empty,
full => fifo_full,
push => fifo_push,
pop => fifo_pop,
reset => reset,
nopop => fifo_nopop,
nopush => fifo_nopush
);
-- The control logic for the core
the_control_unit : mont_ctrl
port map(
clk => clk,
reset => reset,
start => start,
x_sel_single => x_sel_single,
y_sel_single => y_sel_single,
run_auto => exp_m,
op_buffer_empty => fifo_empty,
op_sel_buffer => fifo_dout,
read_buffer => fifo_pop,
done => ready,
calc_time => calc_time,
op_sel => op_sel,
load_x => load_x,
load_result => load_result,
start_multiplier => start_mult,
multiplier_ready => mult_ready
);
 
end Structural;
/autorun_cntrl.vhd
0,0 → 1,185
----------------------------------------------------------------------
---- autorun_ctrl ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- autorun control unit for a pipelined montgomery ----
---- multiplier ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity autorun_cntrl is
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
op_sel : out std_logic_vector (1 downto 0);
start_multiplier : out std_logic;
multiplier_done : in std_logic;
read_buffer : out std_logic;
buffer_din : in std_logic_vector (31 downto 0);
buffer_empty : in std_logic
);
end autorun_cntrl;
 
 
architecture Behavioral of autorun_cntrl is
 
signal bit_counter_i : integer range 0 to 15 := 0;
signal bit_counter_0_i : std_logic;
signal bit_counter_15_i : std_logic;
signal next_bit_i : std_logic := '0';
signal start_cycle_i : std_logic := '0';
signal start_cycle_del_i : std_logic;
signal done_i : std_logic;
signal running_i : std_logic;
signal start_multiplier_i : std_logic;
signal start_multiplier_del_i : std_logic;
signal mult_done_del_i : std_logic;
signal e0_i : std_logic_vector(15 downto 0);
signal e1_i : std_logic_vector(15 downto 0);
signal e0_bit_i : std_logic;
signal e1_bit_i : std_logic;
signal e_bits_i : std_logic_vector(1 downto 0);
signal e_bits_0_i : std_logic;
signal cycle_counter_i : std_logic;
signal op_sel_sel_i : std_logic;
signal op_sel_i : std_logic_vector(1 downto 0);
begin
 
done <= done_i;
-- the two exponents
e0_i <= buffer_din(15 downto 0);
e1_i <= buffer_din(31 downto 16);
 
-- generate the index to select a single bit from the two exponents
SYNC_BIT_COUNTER: process (clk, reset)
begin
if reset = '1' then
bit_counter_i <= 15;
elsif rising_edge(clk) then
if start = '1' then -- make sure we start @ bit 0
bit_counter_i <= 15;
elsif next_bit_i = '1' then -- count
if bit_counter_i = 0 then
bit_counter_i <= 15;
else
bit_counter_i <= bit_counter_i - 1;
end if;
end if;
end if;
end process SYNC_BIT_COUNTER;
-- signal when bit_counter_i = 0
bit_counter_0_i <= '1' when bit_counter_i=0 else '0';
bit_counter_15_i <= '1' when bit_counter_i=15 else '0';
-- the bits...
e0_bit_i <= e0_i(bit_counter_i);
e1_bit_i <= e1_i(bit_counter_i);
e_bits_i <= e0_bit_i & e1_bit_i;
e_bits_0_i <= '1' when (e_bits_i = "00") else '0';
-- operand pre-select
with e_bits_i select
op_sel_i <= "00" when "10", -- gt0
"01" when "01", -- gt1
"10" when "11", -- gt01
"11" when others;
-- select operands
op_sel_sel_i <= '0' when e_bits_0_i = '1' else (cycle_counter_i);
op_sel <= op_sel_i when op_sel_sel_i = '1' else "11";
-- process that drives running_i signal ('1' when in autorun, '0' when not)
RUNNING_PROC: process(clk, reset)
begin
if reset = '1' then
running_i <= '0';
elsif rising_edge(clk) then
running_i <= start or (running_i and (not done_i));
end if;
end process RUNNING_PROC;
-- ctrl logic
start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i));
read_buffer <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15'
start_multiplier <= start_multiplier_del_i and running_i;
-- start/stop logic
start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal)
done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty
next_bit_i <= (mult_done_del_i and e_bits_0_i) or (mult_done_del_i and (not e_bits_0_i) and (not cycle_counter_i));
 
-- process for delaying signals with 1 clock cycle
DEL_PROC: process(clk)
begin
if rising_edge(clk) then
start_multiplier_del_i <= start_multiplier_i;
start_cycle_del_i <= start_cycle_i;
mult_done_del_i <= multiplier_done;
end if;
end process DEL_PROC;
-- process for delaying signals with 1 clock cycle
CYCLE_CNTR_PROC: process(clk, start, reset)
begin
if start = '1' or reset = '1' then
cycle_counter_i <= '0';
elsif rising_edge(clk) then
if (e_bits_0_i = '0') and (multiplier_done = '1') then
cycle_counter_i <= not cycle_counter_i;
elsif (e_bits_0_i = '1') and (multiplier_done = '1') then
cycle_counter_i <= '0';
else
cycle_counter_i <= cycle_counter_i;
end if;
end if;
end process CYCLE_CNTR_PROC;
end Behavioral;
 
/mont_ctrl.vhd
0,0 → 1,197
----------------------------------------------------------------------
---- mont_ctrl ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- control unit for a pipelined montgomery multiplier, with ----
---- split pipeline operation and "auto-run" support ----
---- ----
---- Dependencies: ----
---- - autorun_cntrl ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- This module controls the montgommery mutliplier and controls traffic between
-- RAM and multiplier. Also contains the autorun logic for exponentiations.
entity mont_ctrl is
port (
clk : in std_logic;
reset : in std_logic;
-- bus side
start : in std_logic;
x_sel_single : in std_logic_vector(1 downto 0);
y_sel_single : in std_logic_vector(1 downto 0);
run_auto : in std_logic;
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
done : out std_logic;
calc_time : out std_logic;
-- multiplier side
op_sel : out std_logic_vector(1 downto 0);
load_x : out std_logic;
load_result : out std_logic;
start_multiplier : out std_logic;
multiplier_ready : in std_logic
);
end mont_ctrl;
 
 
architecture Behavioral of mont_ctrl is
signal start_d : std_logic; -- delayed version of start input
signal start_pulse : std_logic;
signal auto_start_pulse : std_logic;
signal start_multiplier_i : std_logic;
signal start_up_counter : std_logic_vector(2 downto 0) := "100"; -- used in op_sel at multiplier start
 
signal calc_time_i : std_logic; -- high ('1') during multiplication
 
signal x_sel : std_logic_vector(1 downto 0); -- the operand used as x input
signal y_sel : std_logic_vector(1 downto 0); -- the operand used as y input
signal x_sel_buffer : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
 
signal auto_done : std_logic;
signal start_auto : std_logic;
signal auto_multiplier_done_i : std_logic;
begin
 
-----------------------------------------------------------------------------------
-- Processes related to starting and stopping the multiplier
-----------------------------------------------------------------------------------
-- generate a start pulse (duration 1 clock cycle) based on ext. start sig
START_PULSE_PROC: process(clk)
begin
if rising_edge(clk) then
start_d <= start;
end if;
end process START_PULSE_PROC;
start_pulse <= start and (not start_d);
start_auto <= start_pulse and run_auto;
 
-- to start the multiplier we first need to select the x_operand and
-- clock it in the x shift register
-- the we select the y_operand and start the multiplier
-- start_up_counter
-- default state : "100"
-- at start pulse counter resets to 0 and counts up to "100"
START_MULT_PROC: process(clk, reset)
begin
if reset = '1' then
start_up_counter <= "100";
elsif rising_edge(clk) then
if start_pulse = '1' or auto_start_pulse = '1' then
start_up_counter <= "000";
elsif start_up_counter(2) /= '1' then
start_up_counter <= start_up_counter + '1';
else
start_up_counter <= "100";
end if;
end if;
end process;
-- select operands (autorun/single run)
x_sel <= x_sel_buffer when (run_auto = '1') else x_sel_single;
y_sel <= "11" when (run_auto = '1') else y_sel_single; -- y is operand3 in auto mode
-- clock operands to operand_mem output (first x, then y)
with start_up_counter(2 downto 1) select
op_sel <= x_sel when "00", -- start_up_counter="00x" (first 2 cycles)
y_sel when others; --
load_x <= start_up_counter(0) and (not start_up_counter(1)); -- latch x operand if start_up_counter="x01"
-- start multiplier when start_up_counter="x11"
start_multiplier_i <= start_up_counter(1) and start_up_counter(0);
start_multiplier <= start_multiplier_i;
 
-- signal calc time is high during multiplication
CALC_TIME_PROC: process(clk, reset)
begin
if reset = '1' then
calc_time_i <= '0';
elsif rising_edge(clk) then
if start_multiplier_i = '1' then
calc_time_i <= '1';
elsif multiplier_ready = '1' then
calc_time_i <= '0';
else
calc_time_i <= calc_time_i;
end if;
end if;
end process CALC_TIME_PROC;
calc_time <= calc_time_i;
-- what happens when a multiplication has finished
load_result <= multiplier_ready;
-- ignore multiplier_ready when in automode, the logic will assert auto_done when finished
done <= ((not run_auto) and multiplier_ready) or auto_done;
-----------------------------------------------------------------------------------
-- Processes related to op_buffer cntrl and auto_run mode
-- start_auto -> start autorun mode operation
-- auto_start_pulse <- autorun logic starts the multiplier
-- auto_done <- autorun logic signals when autorun operation has finished
-- x_sel_buffer <- autorun logic determines which operand is used as x
-- check buffer empty signal
-----------------------------------------------------------------------------------
 
-- multiplier_ready is only passed to autorun control when in autorun mode
auto_multiplier_done_i <= (multiplier_ready and run_auto);
autorun_control_logic : autorun_cntrl port map(
clk => clk,
reset => reset,
start => start_auto,
done => auto_done,
op_sel => x_sel_buffer,
start_multiplier => auto_start_pulse,
multiplier_done => auto_multiplier_done_i,
read_buffer => read_buffer,
buffer_din => op_sel_buffer,
buffer_empty => op_buffer_empty
);
 
end Behavioral;
/counter_sync.vhd
0,0 → 1,94
----------------------------------------------------------------------
---- counter_sync ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- counter with synchronous count enable. It generates an ----
---- overflow when max_value is reached ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- counter with synchronous count enable. It generates an
-- overflow when max_value is reached
entity counter_sync is
generic(
max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
);
port(
reset_value : in integer; -- value the counter counts to
core_clk : in std_logic; -- clock input
ce : in std_logic; -- count enable
reset : in std_logic; -- reset input
overflow : out std_logic -- gets high when counter reaches reset_value
);
end counter_sync;
 
 
architecture Behavioral of counter_sync is
begin
-- counter process with asynchronous active high reset
count_proc: process(core_clk, reset)
variable steps_counter : integer range 0 to max_value-1;
begin
if reset = '1' then -- reset counter
steps_counter := 0;
overflow <= '0';
elsif rising_edge(core_clk) then
-- counter is enabled, count till reset_value
if ce = '1' then
if steps_counter = (reset_value-1) then -- generate overflow and reset counter
steps_counter := 0;
overflow <= '1';
else -- just count
steps_counter := steps_counter + 1;
overflow <= '0';
end if;
else
--counter disabled, halt counter
overflow <= '0';
steps_counter := steps_counter;
end if;
end if;
end process;
end Behavioral;
/sys_last_cell_logic.vhd
0,0 → 1,94
----------------------------------------------------------------------
---- sys_last_cell_logic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- last cell logic for use int the montogommery mulitplier ----
---- pipelined systolic array ----
---- ----
---- Dependencies: ----
---- - register_n ----
---- - cell_1b_adder ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- logic needed as the last piece in the systolic array pipeline
-- calculates the last 2 bits of the cell_result and finishes the reduction
-- also generates the result selection signal
entity sys_last_cell_logic is
port (
core_clk : in std_logic; -- clock input
reset : in std_logic;
a_0 : out std_logic; -- a_msb for last stage
cin : in std_logic; -- cout from last stage
red_cin : in std_logic; -- red_cout from last stage
r_sel : out std_logic; -- result selection bit
start : in std_logic -- done signal from last stage
);
end sys_last_cell_logic;
 
 
architecture Behavorial of sys_last_cell_logic is
signal cin_reg : std_logic;
begin
a_0 <= cin_reg;
last_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => cin,
dout => cin_reg
);
-- reduction, finishing last bit
reduction_adder : cell_1b_adder
port map(
a => '1', -- for 2s complement of m
b => cin_reg,
cin => red_cin,
cout => r_sel
);
 
end Behavorial;
/operand_mem.vhd
0,0 → 1,148
----------------------------------------------------------------------
---- operand_mem ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to the store 4 (1536-bit) operands ----
---- and the modulus for the montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - operand_ram ----
---- - modulus_ram ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity operand_mem is
generic(
n : integer := 1536
);
port(
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
write_enable : in std_logic;
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
 
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector((n-1) downto 0);
m : out std_logic_vector((n-1) downto 0);
result_in : in std_logic_vector((n-1) downto 0);
-- control signals
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
end operand_mem;
 
 
architecture Behavioral of operand_mem is
signal xy_data_i : std_logic_vector(31 downto 0);
signal xy_addr_i : std_logic_vector(5 downto 0);
signal operand_in_sel_i : std_logic_vector(1 downto 0);
signal collision_i : std_logic;
 
signal xy_out_i : std_logic_vector(1535 downto 0);
signal m_i : std_logic_vector(1535 downto 0);
signal result_in_i : std_logic_vector(1535 downto 0);
signal load_op : std_logic;
 
signal m_addr_i : std_logic_vector(5 downto 0);
signal load_m : std_logic;
signal m_data_i : std_logic_vector(31 downto 0);
 
begin
 
-- map outputs
xy_out <= xy_out_i((n-1) downto 0);
m <= m_i((n-1) downto 0);
result_in_i((n-1) downto 0) <= result_in;
collision <= collision_i;
 
-- map inputs
xy_addr_i <= rw_address(5 downto 0);
m_addr_i <= rw_address(5 downto 0);
operand_in_sel_i <= rw_address(7 downto 6);
xy_data_i <= data_in;
m_data_i <= data_in;
load_op <= write_enable when (rw_address(8) = '0') else '0';
load_m <= write_enable when (rw_address(8) = '1') else '0';
 
-- xy operand storage
xy_ram : operand_ram
port map(
clk => clk,
collision => collision_i,
operand_addr => xy_addr_i,
operand_in => xy_data_i,
operand_in_sel => operand_in_sel_i,
result_out => data_out,
write_operand => load_op,
operand_out => xy_out_i,
operand_out_sel => op_sel,
result_dest_op => result_dest_op,
write_result => load_result,
result_in => result_in_i
);
 
-- modulus storage
m_ram : modulus_ram
port map(
clk => clk,
modulus_addr => m_addr_i,
write_modulus => load_m,
modulus_in => m_data_i,
modulus_out => m_i
);
end Behavioral;
/operand_ram.vhd
0,0 → 1,168
----------------------------------------------------------------------
---- operand_ram ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to the store 4 (1536-bit) operands ----
---- for the montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - operand_dp (coregen) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity operand_ram is
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (1536 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
end operand_ram;
 
 
architecture Behavioral of operand_ram is
-- port a signals
signal addra : std_logic_vector(5 downto 0);
signal part_enable : std_logic_vector(3 downto 0);
signal wea : std_logic_vector(3 downto 0);
signal write_operand_i : std_logic;
 
-- port b signals
signal addrb : std_logic_vector(5 downto 0);
signal web : std_logic_vector(0 downto 0);
signal doutb0 : std_logic_vector(31 downto 0);
signal doutb1 : std_logic_vector(31 downto 0);
signal doutb2 : std_logic_vector(31 downto 0);
 
begin
 
-- WARNING: Very Important!
-- wea & web signals must never be high at the same time !!
-- web has priority
write_operand_i <= write_operand and not write_result;
web(0) <= write_result;
collision <= write_operand and write_result;
-- the dual port ram has a depth of 4 (each layer contains an operand)
-- result is always stored in position 3
-- doutb is always result
with write_operand_i select
addra <= operand_in_sel & operand_addr(3 downto 0) when '1',
operand_out_sel & "0000" when others;
with operand_addr(5 downto 4) select
part_enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
 
with write_operand_i select
wea <= part_enable when '1',
"0000" when others;
-- we can only read back from the result (stored in result_dest_op)
addrb <= result_dest_op & operand_addr(3 downto 0);
with operand_addr(5 downto 4) select
result_out <= doutb0 when "00",
doutb1 when "01",
doutb2 when others;
-- 3 instances of a dual port ram to store the parts of the operand
op_0 : operand_dp
port map (
clka => clk,
wea => wea(0 downto 0),
addra => addra,
dina => operand_in,
douta => operand_out(511 downto 0),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(511 downto 0),
doutb => doutb0
);
 
op_1 : operand_dp
port map (
clka => clk,
wea => wea(1 downto 1),
addra => addra,
dina => operand_in,
douta => operand_out(1023 downto 512),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(1023 downto 512),
doutb => doutb1
);
 
op_2 : operand_dp
port map (
clka => clk,
wea => wea(2 downto 2),
addra => addra,
dina => operand_in,
douta => operand_out(1535 downto 1024),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(1535 downto 1024),
doutb => doutb2
);
 
end Behavioral;
/sys_pipeline.vhd
0,0 → 1,314
----------------------------------------------------------------------
---- sys_pipeline ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- the pipelined systolic array for a montgommery multiplier ----
---- ----
---- Dependencies: ----
---- - sys_stage ----
---- - register_n ----
---- - d_flip_flop ----
---- - cell_1b_adder ----
---- - cell_1b_mux ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- the pipelined systolic array for a montgommery multiplier
-- contains a structural description of the pipeline using the systolic stages
entity sys_pipeline is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- total number of stages (minimum 2)
tl : integer := 64; -- lower number of stages (minimum 1)
split : boolean := true -- if true the pipeline wil be split in 2 parts,
-- if false there are no lower stages, only t counts
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y opperand input (n)-bit
y : in std_logic_vector((n-1) downto 0);
m : in std_logic_vector((n-1) downto 0);
-- x operand input (serial)
xi : in std_logic;
next_x : out std_logic; -- next x operand bit
-- control signals
start : in std_logic; -- start multiplier
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
-- result out
r : out std_logic_vector((n-1) downto 0)
);
end sys_pipeline;
 
architecture Structural of sys_pipeline is
constant s : integer := n/t;
signal m_i : std_logic_vector(n downto 0);
signal y_i : std_logic_vector(n downto 0);
-- systolic stages signals
signal my_cin_stage : std_logic_vector((t-1) downto 0);
signal my_cout_stage : std_logic_vector((t-1) downto 0);
signal xin_stage : std_logic_vector((t-1) downto 0);
signal qin_stage : std_logic_vector((t-1) downto 0);
signal xout_stage : std_logic_vector((t-1) downto 0);
signal qout_stage : std_logic_vector((t-1) downto 0);
signal a_msb_stage : std_logic_vector((t-1) downto 0);
signal a_0_stage : std_logic_vector((t-1) downto 0);
signal cin_stage : std_logic_vector((t-1) downto 0);
signal cout_stage : std_logic_vector((t-1) downto 0);
signal red_cin_stage : std_logic_vector((t-1) downto 0);
signal red_cout_stage : std_logic_vector((t-1) downto 0);
signal start_stage : std_logic_vector((t-1) downto 0);
signal done_stage : std_logic_vector((t-1) downto 0);
signal r_sel_stage : std_logic_vector((t-1) downto 0);
-- end logic signals
signal r_sel_end : std_logic;
-- signals needed if pipeline is split
---------------------------------------
signal r_sel_l : std_logic;
signal r_sel_h : std_logic;
-- mid end logic signals
signal a_0_midend : std_logic;
signal r_sel_midend : std_logic;
-- mid start logic signals
signal my_cout_midstart : std_logic;
signal xout_midstart : std_logic;
signal qout_midstart : std_logic;
signal cout_midstart : std_logic;
signal red_cout_midstart : std_logic;
 
begin
 
m_i <= '0' & m;
y_i <= '0' & y;
 
-- generate the stages for the full pipeline
pipeline_stages : for i in 0 to (t-1) generate
stage : sys_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
y => y_i((i+1)*s downto (i*s)+1),
m => m_i((i+1)*s downto (i*s)),
my_cin => my_cin_stage(i),
my_cout => my_cout_stage(i),
xin => xin_stage(i),
qin => qin_stage(i),
xout => xout_stage(i),
qout => qout_stage(i),
a_0 => a_0_stage(i),
a_msb => a_msb_stage(i),
cin => cin_stage(i),
cout => cout_stage(i),
red_cin => red_cin_stage(i),
red_cout => red_cout_stage(i),
start => start_stage(i),
reset => reset,
done => done_stage(i),
r_sel => r_sel_stage(i),
r => r(((i+1)*s)-1 downto (i*s))
);
end generate;
-- first cell logic
--------------------
first_cell : sys_first_cell_logic
port map (
m0 => m_i(0),
y0 => y_i(0),
my_cout => my_cin_stage(0),
xi => xi,
xout => xin_stage(0),
qout => qin_stage(0),
cout => cin_stage(0),
a_0 => a_0_stage(0),
red_cout => red_cin_stage(0)
);
-- last cell logic
-------------------
last_cell : sys_last_cell_logic
port map (
core_clk => core_clk,
reset => reset,
a_0 => a_msb_stage(t-1),
cin => cout_stage(t-1),
red_cin => red_cout_stage(t-1),
r_sel => r_sel_end,
start => done_stage(t-1)
);
------------------------------------
-- SINGLE PART PIPELINE CONNECTIONS
------------------------------------
single_pipeline : if split=false generate
-- link stages to eachother
stage_connect : for i in 1 to (t-1) generate
my_cin_stage(i) <= my_cout_stage(i-1);
cin_stage(i) <= cout_stage(i-1);
xin_stage(i) <= xout_stage(i-1);
qin_stage(i) <= qout_stage(i-1);
red_cin_stage(i) <= red_cout_stage(i-1);
start_stage(i) <= done_stage(i-1);
a_msb_stage(i-1) <= a_0_stage(i);
r_sel_stage(i) <= r_sel_end;
end generate;
r_sel_stage(0) <= r_sel_end;
start_stage(0) <= start;
next_x <= done_stage(0);
end generate;
 
----------------------------------------
-- SPLIT PIPELINE CONNECTIONS AND LOGIC
----------------------------------------
split_pipeline : if split=true generate
-- only start first stage if lower part is used
with p_sel select
start_stage(0) <= '0' when "10",
start when others;
-- select start or midstart stage for requesting new xi bit
with p_sel select
next_x <= done_stage(tl) when "10",
done_stage(0) when others;
-- link lower stages to eachother
stage_connect_l : for i in 1 to (tl-1) generate
my_cin_stage(i) <= my_cout_stage(i-1);
cin_stage(i) <= cout_stage(i-1);
xin_stage(i) <= xout_stage(i-1);
qin_stage(i) <= qout_stage(i-1);
red_cin_stage(i) <= red_cout_stage(i-1);
start_stage(i) <= done_stage(i-1);
a_msb_stage(i-1) <= a_0_stage(i);
r_sel_stage(i) <= r_sel_l;
end generate;
r_sel_stage(0) <= r_sel_l;
-- mid end logic
-----------------
mid_end_cell : sys_last_cell_logic
port map (
core_clk => core_clk,
reset => reset,
a_0 => a_0_midend,
cin => cout_stage(tl-1),
red_cin => red_cout_stage(tl-1),
r_sel => r_sel_midend,
start => done_stage(tl-1)
);
--muxes for midend signals
with p_sel select
a_msb_stage(tl-1) <= a_0_midend when "01",
a_0_stage(tl) when others;
-- mid start logic
-------------------
mid_start_logic : sys_first_cell_logic
port map (
m0 => m_i(tl*s),
y0 => y_i(tl*s),
my_cout => my_cout_midstart,
xi => xi,
xout => xout_midstart,
qout => qout_midstart,
cout => cout_midstart,
a_0 => a_0_stage(tl),
red_cout => red_cout_midstart
);
-- only start stage tl if only higher part is used
with p_sel select
start_stage(tl) <= start when "10",
done_stage(tl-1) when "11",
'0' when others;
with p_sel select
my_cin_stage(tl) <= my_cout_midstart when "10",
my_cout_stage(tl-1) when others;
with p_sel select
xin_stage(tl) <= xout_midstart when "10",
xout_stage(tl-1) when others;
with p_sel select
qin_stage(tl) <= qout_midstart when "10",
qout_stage(tl-1) when others;
with p_sel select
cin_stage(tl) <= cout_midstart when "10",
cout_stage(tl-1) when others;
with p_sel select
red_cin_stage(tl) <= red_cout_midstart when "10",
red_cout_stage(tl-1) when others;
-- link higher stages to eachother
stage_connect_h : for i in (tl+1) to (t-1) generate
my_cin_stage(i) <= my_cout_stage(i-1);
cin_stage(i) <= cout_stage(i-1);
xin_stage(i) <= xout_stage(i-1);
qin_stage(i) <= qout_stage(i-1);
red_cin_stage(i) <= red_cout_stage(i-1);
start_stage(i) <= done_stage(i-1);
a_msb_stage(i-1) <= a_0_stage(i);
r_sel_stage(i) <= r_sel_h;
end generate;
r_sel_stage(tl) <= r_sel_h;
with p_sel select
r_sel_l <= r_sel_midend when "01",
r_sel_end when "11",
'0' when others;
with p_sel select
r_sel_h <= '0' when "01",
r_sel_end when others;
end generate;
 
end Structural;
/mont_multiplier.vhd
0,0 → 1,204
----------------------------------------------------------------------
---- mont_multiplier ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- n-bit montgomery multiplier with a pipelined systolic ----
---- array ----
---- ----
---- Dependencies: ----
---- - x_shift_reg ----
---- - adder_n ----
---- - d_flip_flop ----
---- - sys_pipeline ----
---- - cell_1b_adder ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- Structural description of the montgommery multiply pipeline
-- contains the x operand shift register, my adder, the pipeline and
-- reduction adder. To do a multiplication, the following actions must take place:
--
-- * load in the x operand in the shift register using the xy bus and load_x
-- * place the y operand on the xy bus for the rest of the operation
-- * generate a start pulse of 1 clk cycle long on start
-- * wait for ready signal
-- * result is avaiable on the r bus
--
entity mont_multiplier is
generic (
n : integer := 1536; -- width of the operands
t : integer := 96; -- total number of stages (minimum 2)
tl : integer := 32; -- lower number of stages (minimum 1)
split : boolean := true -- if true the pipeline wil be split in 2 parts,
-- if false there are no lower stages, only t counts
);
port (
-- clock input
core_clk : in std_logic;
-- operand inputs
xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
m : in std_logic_vector((n-1) downto 0); -- modulus
-- result output
r : out std_logic_vector((n-1) downto 0); -- result
-- control signals
start : in std_logic;
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
load_x : in std_logic;
ready : out std_logic
);
end mont_multiplier;
 
architecture Structural of mont_multiplier is
constant s : integer := n/t; -- stage width (# bits)
constant nl : integer := s*tl; -- lower pipeline width (# bits)
constant nh : integer := n - nl; -- higher pipeline width (# bits)
signal reset_multiplier : std_logic;
signal start_multiplier : std_logic;
signal p_sel_i : std_logic_vector(1 downto 0);
signal t_sel : integer range 0 to t; -- width in stages of selected pipeline part
signal n_sel : integer range 0 to n; -- width in bits of selected pipeline part
signal next_xi : std_logic;
signal xi : std_logic;
signal start_first_stage : std_logic;
begin
-- multiplier is reset every calculation or reset
reset_multiplier <= reset or start;
 
-- start is delayed 1 cycle
delay_1_cycle : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start,
dout => start_multiplier
);
-- register to store the x value in
-- outputs the operand in serial using a shift register
x_selection : x_shift_reg
generic map(
n => n,
t => t,
tl => tl
)
port map(
clk => core_clk,
reset => reset,
x_in => xy,
load_x => load_x,
next_x => next_xi,
p_sel => p_sel_i,
xi => xi
);
----------------------------------------
-- SINGLE PIPELINE ASSIGNMENTS
----------------------------------------
single_pipeline : if split=false generate
p_sel_i <= "11";
t_sel <= t;
n_sel <= n-1;
end generate;
 
----------------------------------------
-- SPLIT PIPELINE ASSIGNMENTS
----------------------------------------
split_pipeline : if split=true generate
-- this module controls the pipeline operation
-- width in stages for selected pipeline
with p_sel select
t_sel <= tl when "01", -- lower pipeline part
t-tl when "10", -- higher pipeline part
t when others; -- full pipeline
 
-- width in bits for selected pipeline
with p_sel select
n_sel <= nl-1 when "01", -- lower pipeline part
nh-1 when "10", -- higher pipeline part
n-1 when others; -- full pipeline
p_sel_i <= p_sel;
end generate;
 
-- stepping control logic to keep track off the multiplication and when it is done
stepping_control : stepping_logic
generic map(
n => n, -- max nr of steps required to complete a multiplication
t => t -- total nr of steps in the pipeline
)
port map(
core_clk => core_clk,
start => start_multiplier,
reset => reset_multiplier,
t_sel => t_sel,
n_sel => n_sel,
start_first_stage => start_first_stage,
stepping_done => ready
);
systolic_array : sys_pipeline
generic map(
n => n,
t => t,
tl => tl,
split => split
)
port map(
core_clk => core_clk,
y => xy,
m => m,
xi => xi,
next_x => next_xi,
start => start_first_stage,
reset => reset_multiplier,
p_sel => p_sel_i,
r => r
);
end Structural;
/sys_first_cell_logic.vhd
0,0 → 1,97
----------------------------------------------------------------------
---- sys_first_cell_logic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- first cell logic for use int the montogommery mulitplier ----
---- pipelined systolic array ----
---- ----
---- Dependencies: ----
---- - register_n ----
---- - cell_1b_adder ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- logic needed as the first piece in the systolic array pipeline
-- calculates the first my_cout and generates q signal
entity sys_first_cell_logic is
port (
m0 : in std_logic; -- lsb from m operand
y0 : in std_logic; -- lsb from y operand
my_cout : out std_logic; -- my_cin for first stage
xi : in std_logic; -- xi operand input
xout : out std_logic; -- xin for first stage
qout : out std_logic; -- qin for first stage
cout : out std_logic; -- cin for first stage
a_0 : in std_logic; -- a_0 from first stage
red_cout : out std_logic -- red_cin for first stage
);
end sys_first_cell_logic;
 
architecture Behavorial of sys_first_cell_logic is
-- first cell signals
signal my0_mux_result : std_logic;
signal my0 : std_logic;
signal qout_i : std_logic;
begin
-- half adder for m0 +y0
my0 <= m0 xor y0;
my_cout <= m0 and y0; -- carry
xout <= xi;
qout_i <= (xi and y0) xor a_0;
cout <= my0_mux_result and a_0;
red_cout <= '1'; -- add 1 for 2s complement
my0_mux : cell_1b_mux
port map(
my => my0,
m => m0,
y => y0,
x => xi,
q => qout_i,
result => my0_mux_result
);
qout <= qout_i;
end Behavorial;
/sys_stage.vhd
0,0 → 1,226
----------------------------------------------------------------------
---- sys_stage ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- stage for use in the montgommery multiplier pipelined ----
---- systolic array ----
---- ----
---- Dependencies: ----
---- - adder_block ----
---- - standard_cell_block ----
---- - d_flip_flop ----
---- - register_n ----
---- - register_1b ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
entity sys_stage is
generic(
width : integer := 32 -- width of the stage
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y operand input (width)-bit
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width) downto 0);
my_cin : in std_logic;
my_cout : out std_logic;
-- q and x operand input (serial input)
xin : in std_logic;
qin : in std_logic;
-- q and x operand output (serial output)
xout : out std_logic;
qout : out std_logic;
-- msb input (lsb from next stage, for shift right operation)
a_msb : in std_logic;
a_0 : out std_logic;
-- carry out(clocked) and in
cin : in std_logic;
cout : out std_logic;
-- reduction adder carry's
red_cin : in std_logic;
red_cout : out std_logic;
-- control singals
start : in std_logic;
reset : in std_logic;
done : out std_logic;
-- result out
r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
r : out std_logic_vector((width-1) downto 0)
);
end sys_stage;
 
architecture Structural of sys_stage is
signal my : std_logic_vector((width-1) downto 0);
signal m_inv : std_logic_vector((width-1) downto 0);
signal a : std_logic_vector((width-1) downto 0);
signal cell_result : std_logic_vector((width-1) downto 0);
signal cell_result_reg : std_logic_vector((width-1) downto 0);
signal red_r : std_logic_vector((width-1) downto 0);
signal cout_i : std_logic;
begin
-- my adder
------------
my_adder : adder_block
generic map (
width => width
)
port map(
core_clk => core_clk,
a => m(width downto 1),
b => y,
cin => my_cin,
cout => my_cout,
r => my
);
-- systolic pipeline cells
---------------------------
a <= a_msb & cell_result_reg((width-1) downto 1);
a_0 <= cell_result_reg(0);
sys_cells : standard_cell_block
generic map (
width => width
)
port map (
-- modulus and y operand input (width)-bit
my => my,
y => y,
m => m(width downto 1),
-- q and x operand input (serial input)
x => xin,
q => qin,
-- previous result in (width)-bit
a => a,
-- carry in and out
cin => cin,
cout => cout_i,
-- result out (width)-bit
r => cell_result
);
-- cell result register (width)-bit
result_reg : register_n
generic map(
width => width
)
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => cell_result,
dout => cell_result_reg
);
-- result reduction
--------------------
m_inv <= not(m(width-1 downto 0));
reduction_adder : adder_block
generic map (
width => width
)
port map(
core_clk => core_clk,
a => m_inv,
b => cell_result_reg,
cin => red_cin,
cout => red_cout,
r => red_r
);
with r_sel select
r <= cell_result_reg when '0',
red_r when others;
-- stage clocked outputs
-------------------------
-- stage done signal
-- 1 cycle after start of stage
done_signal : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start,
dout => done
);
-- xout register
xout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => xin,
dout => xout
);
-- qout register
qout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => qin,
dout => qout
);
 
-- carry out register
cout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => cout_i,
dout => cout
);
end Structural;
 
/x_shift_reg.vhd
0,0 → 1,100
----------------------------------------------------------------------
---- x_shift_reg ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- n bit shift register for the x operand of the multiplier ----
---- with bit output ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- shift register for the x operand of the multiplier
-- outputs the lsb of the register or bit at offset according to the
-- selected pipeline part
entity x_shift_reg is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 48; -- total number of stages
tl : integer := 16 -- lower number of stages
);
port(
-- clock input
clk : in std_logic;
-- x operand in (n-bit)
x_in : in std_logic_vector((n-1) downto 0);
-- control signals
reset : in std_logic; -- reset, clears register
load_x : in std_logic; -- load operand into shift register
next_x : in std_logic; -- next bit of x
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
-- x operand bit out (serial)
xi : out std_logic
);
end x_shift_reg;
 
 
architecture Behavioral of x_shift_reg is
signal x_reg : std_logic_vector((n-1) downto 0); -- register
constant s : integer := n/t; -- stage width
constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
begin
 
REG_PROC: process(reset, clk)
begin
if reset = '1' then -- Reset, clear the register
x_reg <= (others => '0');
elsif rising_edge(clk) then
if load_x = '1' then -- Load_x, load the register with x_in
x_reg <= x_in;
elsif next_x = '1' then -- next_x, shift to right. LSbit gets lost and zero's are shifted in
x_reg((n-2) downto 0) <= x_reg((n-1) downto 1);
else -- else remember state
x_reg <= x_reg;
end if;
end if;
end process;
 
with p_sel select -- pipeline select
xi <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline
x_reg(0) when others; -- use LS bit for lower part of pipeline
 
end Behavioral;
/stepping_logic.vhd
0,0 → 1,166
----------------------------------------------------------------------
---- stepping_logic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- stepping logic to control the pipeline for one ----
---- montgommery multiplication ----
---- ----
---- Dependencies: ----
---- - d_flip_flop ----
---- - counter_sync ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- stepping logic for the pipeline, generates the start pulses for the
-- first stage and keeps track of when the last stages are done
entity stepping_logic is
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic; -- clock input
start : in std_logic; -- start signal for pipeline (one multiplication)
reset : in std_logic; -- reset signal
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
start_first_stage : out std_logic; -- start pulse output for first stage
stepping_done : out std_logic -- done signal
);
end stepping_logic;
 
 
architecture Behavioral of stepping_logic is
 
-- signals for the first stage control, pulses and counters
signal first_stage_done : std_logic; -- indicates the first stage is done running for this multiplication
signal first_stage_active : std_logic; -- indicates the first stage is active
signal first_stage_active_d : std_logic; -- delayed version of first_stage_active
signal start_first_stage_i : std_logic; -- internal version of start_first_stage output
 
-- signals for the last stages control and counter
signal last_stages_done : std_logic; -- indicates the last stages are done running for this multiplication
signal last_stages_active : std_logic; -- indicates the last stages are active
signal last_stages_active_d : std_logic; -- delayed version of last_stages_active
 
begin
 
-- map outputs
stepping_done <= last_stages_done;
-- internal signals
--------------------
-- first_stage_active signal gets active from a start pulse
-- inactive from first_stage_done pulse
first_stage_active <= start or (first_stage_active_d and not first_stage_done);
-- done signal gets active from a first_stage_done pulse
-- inactive from last_stages_done pulse
last_stages_active <= first_stage_done or (last_stages_active_d and not last_stages_done);
-- map start_first_stage_i to output, but also use the initial start pulse
start_first_stage <= start or start_first_stage_i;
last_stages_active_delay : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => last_stages_active,
dout => last_stages_active_d
);
 
first_stage_active_delay : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => first_stage_active,
dout => first_stage_active_d
);
-- the counters
----------------
-- for counting the last steps (waiting for the other stages to stop)
-- counter for keeping track of how many stages are done
laststeps_counter : counter_sync
generic map(
max_value => t
)
port map(
reset_value => t_sel,
core_clk => core_clk,
ce => last_stages_active,
reset => reset,
overflow => last_stages_done
);
 
-- counter for keeping track of how many times the first stage is started
-- counts bits in operand x till operand width then generates pulse on first_stage_done
steps_counter : counter_sync
generic map(
max_value => n
)
port map(
reset_value => (n_sel),
core_clk => core_clk,
ce => start_first_stage_i,
reset => reset,
overflow => first_stage_done
);
 
-- the output (overflow) of this counter starts the first stage every 2 clock cycles
substeps_counter : counter_sync
generic map(
max_value => 2
)
port map(
reset_value => 2,
core_clk => core_clk,
ce => first_stage_active,
reset => reset,
overflow => start_first_stage_i
);
 
end Behavioral;
/standard_cell_block.vhd
0,0 → 1,105
----------------------------------------------------------------------
---- standard_cell_block ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- a block of (width) cell_1b cells for use in the ----
---- montgommery multiplier systolic array ----
---- ----
---- Dependencies: ----
---- - cell_1b ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- a standard cell block of (width)-bit for the montgommery multiplier
-- systolic array
entity standard_cell_block is
generic (
width : integer := 16
);
port (
-- modulus and y operand input (width)-bit
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
-- q and x operand input (serial input)
x : in std_logic;
q : in std_logic;
-- previous result in (width)-bit
a : in std_logic_vector((width-1) downto 0);
-- carry in and out
cin : in std_logic;
cout : out std_logic;
-- result out (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end standard_cell_block;
 
 
architecture Structural of standard_cell_block is
-- vector for the carry bits
signal carry : std_logic_vector(width downto 0);
begin
-- carry in
carry(0) <= cin;
-- structure of (width) 1-bit cells
cell_block : for i in 0 to (width-1) generate
cells : cell_1b
port map(
my => my(i),
y => y(i),
m => m(i),
x => x,
q => q,
a => a(i),
cin => carry(i),
cout => carry(i+1),
r => r(i)
);
end generate;
-- carry out
cout <= carry(width);
end Structural;
/register_n.vhd
0,0 → 1,81
----------------------------------------------------------------------
---- register_n ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- n bit register with active high asynchronious reset and ce----
---- used in montgommery multiplier systolic array stages ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- n-bit register with asynchronous reset and clock enable
entity register_n is
generic(
width : integer := 4
);
port(
core_clk : in std_logic; -- clock input
ce : in std_logic; -- clock enable (active high)
reset : in std_logic; -- reset (active high)
din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit
dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit
);
end register_n;
 
 
architecture Behavorial of register_n is
begin
-- process for (width)-bit register
reg_nb : process (reset, ce, core_clk, din)
begin
if reset='1' then -- asynchronous active high reset
dout <= (others=>'0');
else
if rising_edge(core_clk) then -- clock in data on rising edge
if ce='1' then -- active high clock enable to clock in data
dout <= din;
end if;
end if;
end if;
end process;
 
end Behavorial;
/cell_1b.vhd
0,0 → 1,102
----------------------------------------------------------------------
---- cell_1b ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1-bit cell for use in the montgommery multiplier systolic ----
---- array ----
---- ----
---- Dependencies: ----
---- - cell_1bit_adder ----
---- - cell_1bit_mux ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- 1-bit cell for the systolic array
entity cell_1b is
port (
-- operand input bits (m+y, y and m)
my : in std_logic;
y : in std_logic;
m : in std_logic;
-- operand x input bit and q
x : in std_logic;
q : in std_logic;
-- previous result input bit
a : in std_logic;
-- carry's
cin : in std_logic;
cout : out std_logic;
-- cell result out
r : out std_logic
);
end cell_1b;
 
 
architecture Structural of cell_1b is
-- mux to adder connection
signal mux2adder : std_logic;
begin
-- mux for my, y and m input bits
cell_mux : cell_1b_mux
port map(
my => my,
y => y,
m => m,
x => x,
q => q,
result => mux2adder
);
-- full adder for a+mux2adder
cell_adder : cell_1b_adder
port map(
a => a,
b => mux2adder,
cin => cin,
cout => cout,
r => r
);
 
end Structural;
/adder_block.vhd
0,0 → 1,106
----------------------------------------------------------------------
---- adder_block ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- Adder block with a flipflop for the carry out so result ----
---- is available after 1 clock cycle ----
---- for use in the montgommery multiplier pre and post ----
---- computation adders ----
---- ----
---- Dependencies: ----
---- - cell_1b_adder ----
---- - d_flip_flop ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- (width)-bit full adder block using cell_1b_adders
-- with buffered carry out -> result after 1 clock cycle
entity adder_block is
generic (
width : integer := 32 --adder operand widths
);
port (
-- clock input
core_clk : in std_logic;
-- adder input operands a, b (width)-bit
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- adder result out (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end adder_block;
 
 
architecture Structural of adder_block is
-- vector for the carry bits
signal carry : std_logic_vector(width downto 0);
begin
-- carry in
carry(0) <= cin;
 
-- structure of (width) cell_1b_adders
adder_chain : for i in 0 to (width-1) generate
adders : cell_1b_adder
port map(
a => a(i),
b => b(i),
cin => carry(i),
cout => carry(i+1),
r => r(i)
);
end generate;
-- buffer the carry every clock cycle
carry_reg : d_flip_flop
port map(
core_clk => core_clk,
reset => '0',
din => carry(width),
dout => cout
);
 
end Structural;
/cell_1b_adder.vhd
0,0 → 1,74
----------------------------------------------------------------------
---- cell_1b_adder ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- This file contains the implementation of a 1-bit full ----
---- adder cell using combinatorial logic ----
---- used in adder_block ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- 1-bit full adder cell
entity cell_1b_adder is
port (
-- input operands a, b
a : in std_logic;
b : in std_logic;
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- result out
r : out std_logic
);
end cell_1b_adder;
 
 
architecture Behavioral of cell_1b_adder is
signal a_xor_b : std_logic;
begin
-- 1-bit full adder with combinatorial logic
-- uses 2 XOR's, 2 AND's and 1 OR port
a_xor_b <= a xor b;
r <= a_xor_b xor cin;
cout <= (a and b) or (cin and a_xor_b);
end Behavioral;
/cell_1b_mux.vhd
0,0 → 1,78
----------------------------------------------------------------------
---- cel_1b_mux ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1-bit mux for a standard cell in the montgommery ----
---- multiplier systolic array ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- 1-bit mux for a standard cell in the montgommery multiplier systolic array
entity cell_1b_mux is
port (
-- input bits
my : in std_logic;
y : in std_logic;
m : in std_logic;
-- selection bits
x : in std_logic;
q : in std_logic;
-- mux out
result : out std_logic
);
end cell_1b_mux;
 
 
architecture Behavioral of cell_1b_mux is
signal sel : std_logic_vector(1 downto 0);
begin
-- selection bits
sel <= x & q;
-- multipexer
with sel select
result <= my when "11",
y when "10",
m when "01",
'0' when others;
 
end Behavioral;
/register_1b.vhd
0,0 → 1,79
----------------------------------------------------------------------
---- register_1b ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1 bit register with active high asynchronious reset and ce----
---- used in montgommery multiplier systolic array stages ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- 1-bit register with asynchronous reset and clock enable
entity register_1b is
port(
core_clk : in std_logic; -- clock input
ce : in std_logic; -- clock enable (active high)
reset : in std_logic; -- reset (active high)
din : in std_logic; -- data in
dout : out std_logic -- data out
);
end register_1b;
 
 
architecture Behavorial of register_1b is
begin
-- process for 1-bit register
reg_1b : process (reset, ce, core_clk, din)
begin
if reset='1' then -- asynchronous active high reset
dout <= '0';
else
if rising_edge(core_clk) then -- clock in data on rising edge
if ce='1' then -- active high clock enable to clock in data
dout <= din;
end if;
end if;
end if;
end process;
end Behavorial;
/d_flip_flop.vhd
0,0 → 1,76
----------------------------------------------------------------------
---- d_flip_flop ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1-bit D flip-flop implemented with behavorial (generic) ----
---- description. With asynchronous active high reset. ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- 1-bit D flip-flop with asynchronous active high reset
entity d_flip_flop is
port(
core_clk : in std_logic; -- clock signal
reset : in std_logic; -- active high reset
din : in std_logic; -- data in
dout : out std_logic -- data out
);
end d_flip_flop;
 
 
architecture Behavorial of d_flip_flop is
begin
-- process for 1-bit D flip-flop
d_FF : process (reset, core_clk, din)
begin
if reset='1' then -- asynchronous active high reset
dout <= '0';
else
if rising_edge(core_clk) then -- clock in data on rising edge
dout <= din;
end if;
end if;
end process;
end Behavorial;
/fifo_primitive.vhd
0,0 → 1,143
----------------------------------------------------------------------
---- fifo_primitive ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 512 x 32 bit fifo ----
---- ----
---- Dependencies: ----
---- - FIFO18E1 (xilinx primitive) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- Xilinx primitives used in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity fifo_primitive is
port (
clk : in std_logic;
din : in std_logic_vector (31 downto 0);
dout : out std_logic_vector (31 downto 0);
empty : out std_logic;
full : out std_logic;
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end fifo_primitive;
 
 
architecture Behavioral of fifo_primitive is
signal rdcount : std_logic_vector(11 downto 0); -- debugging
signal wrcount : std_logic_vector(11 downto 0); -- debugging
signal reset_i, pop_i, push_i, empty_i, full_i, wrerr_i, rderr_i : std_logic;
begin
empty <= empty_i;
full <= full_i;
-- these logical equations need to be extended where necessary
nopop <= rderr_i or (pop and reset_i);
nopush <= wrerr_i or (push and reset_i);
pop_i <= pop and (not reset_i);
push_i <= push and (not reset_i);
-- makes the reset at least three clk_cycles long
RESET_PROC: process (reset, clk)
variable clk_counter : integer range 0 to 3 := 3;
begin
if reset = '1' then
reset_i <= '1';
clk_counter := 3;
elsif rising_edge(clk) then
if clk_counter = 0 then
clk_counter := 0;
reset_i <= '0';
else
clk_counter := clk_counter - 1;
reset_i <= '1';
end if;
end if;
end process;
 
FIFO18E1_inst : FIFO18E1
generic map (
ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty threshold
ALMOST_FULL_OFFSET => X"00080", -- Sets almost full threshold
DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36
DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"
EN_SYN => TRUE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36
FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"
INIT => X"000000000", -- Initial values on output port
SRVAL => X"000000000" -- Set/Reset value for output port
)
port map (
-- ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flag
-- ALMOSTFULL => ALMOSTFULL, -- 1-bit almost full output flag
DO => dout, -- 32-bit data output
-- DOP => DOP, -- 4-bit parity data output
EMPTY => empty_i, -- 1-bit empty output flag
FULL => full_i, -- 1-bit full output flag
-- WRCOUNT, RDCOUNT: 12-bit (each) FIFO pointers
RDCOUNT => RDCOUNT, -- 12-bit read count output
WRCOUNT => WRCOUNT, -- 12-bit write count output
-- WRERR, RDERR: 1-bit (each) FIFO full or empty error
RDERR => rderr_i, -- 1-bit read error output
WRERR => wrerr_i, -- 1-bit write error
DI => din, -- 32-bit data input
DIP => "0000", -- 4-bit parity input
RDEN => pop_i, -- 1-bit read enable input
REGCE => '1', -- 1-bit clock enable input
RST => reset_i, -- 1-bit reset input
RSTREG => reset_i, -- 1-bit output register set/reset
-- WRCLK, RDCLK: 1-bit (each) Clocks
RDCLK => clk, -- 1-bit read clock input
WRCLK => clk, -- 1-bit write clock input
WREN => push_i -- 1-bit write enable input
);
 
end Behavioral;
/operand_dp.vhd
0,0 → 1,195
----------------------------------------------------------------------
---- operand_dp ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 4 x 512 bit dual port ram for the operands ----
---- 32 bit read and write for bus side and 512 bit read and ----
---- write for multiplier side ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file operand_dp.vhd when simulating
-- the core, operand_dp. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
 
library ieee;
use ieee.std_logic_1164.ALL;
-- synthesis translate_off
library XilinxCoreLib;
-- synthesis translate_on
 
 
entity operand_dp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end operand_dp;
 
 
architecture operand_dp_a of operand_dp is
-- synthesis translate_off
component wrapped_operand_dp
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component;
 
-- Configuration specification
for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 2,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 32,
c_initb_val => "0",
c_family => "virtex6",
c_read_width_a => 512,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "virtex6",
c_write_depth_b => 4,
c_write_depth_a => 64,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 6,
c_addrb_width => 6,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 512,
c_write_width_a => 32,
c_read_depth_b => 64,
c_read_depth_a => 4,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0
);
-- synthesis translate_on
begin
-- synthesis translate_off
U0 : wrapped_operand_dp
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
 
end operand_dp_a;
/operands_sp.vhd
0,0 → 1,180
----------------------------------------------------------------------
---- operands_sp ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 512 bit single port ram for the modulus ----
---- 32 write for bus side and 512 bit read for multplier side ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file operand_dp.vhd when simulating
-- the core, operand_dp. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
 
library ieee;
use ieee.std_logic_1164.all;
-- synthesis translate_off
library XilinxCoreLib;
-- synthesis translate_on
 
 
entity operands_sp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end operands_sp;
 
 
architecture operands_sp_a of operands_sp is
-- synthesis translate_off
component wrapped_operands_sp
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end component;
 
-- Configuration specification
for all : wrapped_operands_sp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 32,
c_initb_val => "0",
c_family => "virtex6",
c_read_width_a => 512,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "virtex6",
c_write_depth_b => 32,
c_write_depth_a => 32,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 5,
c_addrb_width => 5,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 32,
c_write_width_a => 32,
c_read_depth_b => 32,
c_read_depth_a => 2,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0
);
-- synthesis translate_on
 
begin
-- synthesis translate_off
u0 : wrapped_operands_sp
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
 
end operands_sp_a;
/modulus_ram.vhd
0,0 → 1,113
----------------------------------------------------------------------
---- modulus_ram ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to store the 1536-bit modulus ----
---- ----
---- Dependencies: ----
---- - operands_sp (coregen) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity modulus_ram is
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end modulus_ram;
 
 
architecture Behavioral of modulus_ram is
signal part_enable : std_logic_vector(3 downto 0);
signal wea : std_logic_vector(3 downto 0);
signal addra : std_logic_vector(4 downto 0);
begin
 
-- the blockram has a write depth of 2 but we only use the lower half
addra <= '0' & modulus_addr(3 downto 0);
-- the two highest bits of the address are used to select the bloc
with modulus_addr(5 downto 4) select
part_enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
 
with write_modulus select
wea <= part_enable when '1',
"0000" when others;
-- 4 instances of 512 bits blockram
modulus_0 : operands_sp
port map (
clka => clk,
wea => wea(0 downto 0),
addra => addra,
dina => modulus_in,
douta => modulus_out(511 downto 0)
);
 
modulus_1 : operands_sp
port map (
clka => clk,
wea => wea(1 downto 1),
addra => addra,
dina => modulus_in,
douta => modulus_out(1023 downto 512)
);
 
modulus_2 : operands_sp
port map (
clka => clk,
wea => wea(2 downto 2),
addra => addra,
dina => modulus_in,
douta => modulus_out(1535 downto 1024)
);
 
end Behavioral;

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