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/fifo/xil_prim_fifo_syn.html
0,0 → 1,5
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<BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>wo 6. mrt 15:12:33 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.12 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.13 secs<BR> <BR>--> Reading design: fifo_primitive.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "fifo_primitive.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "fifo_primitive"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : fifo_primitive<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Auto<BR>Use Synchronous Set : Auto<BR>Use Synchronous Reset : Auto<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"../../SVN/mod_sim_exp/rtl/vhdl/core" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd" into library mod_sim_exp<BR>Parsing entity <FIFO_PRIMITIVE>.<BR>Parsing architecture <BEHAVIORAL> of entity <FIFO_PRIMITIVE>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <FIFO_PRIMITIVE> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <FIFO_PRIMITIVE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd".<BR> Found 1-bit register for signal <RESET_I>.<BR> Found 2-bit register for signal <RESET_PROC.CLK_COUNTER>.<BR> Found 2-bit subtractor for signal <GND_6_O_GND_6_O_SUB_2_OUT<1:0>> created at line 100.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 3 D-type flip-flop(s).<BR> inferred 1 Multiplexer(s).<BR>Unit <FIFO_PRIMITIVE> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># Adders/Subtractors : 1<BR> 2-bit subtractor : 1<BR># Registers : 2<BR> 1-bit register : 1<BR> 2-bit register : 1<BR># Multiplexers : 1<BR> 2-bit 2-to-1 multiplexer : 1<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># Adders/Subtractors : 1<BR> 2-bit subtractor : 1<BR># Registers : 3<BR> Flip-Flops : 3<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <FIFO_PRIMITIVE> ...<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block fifo_primitive, actual ratio is 0.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Macro Statistics<BR># Registers : 3<BR> Flip-Flops : 3<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : fifo_primitive.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 9<BR># GND : 1<BR># LUT2 : 5<BR># LUT3 : 2<BR># VCC : 1<BR># FlipFlops/Latches : 3<BR># FDP : 3<BR># RAMS : 1<BR># FIFO18E1 : 1<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice Registers: 3 out of 301440 0% <BR> Number of Slice LUTs: 7 out of 150720 0% <BR> Number used as Logic: 7 out of 150720 0% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 10<BR> Number with an unused Flip Flop: 7 out of 10 70% <BR> Number with an unused LUT: 3 out of 10 30% <BR> Number of fully used LUT-FF pairs: 0 out of 10 0% <BR> Number of unique control sets: 1<BR><BR>IO Utilization: <BR> Number of IOs: 72<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 1 out of 416 0% <BR> Number using FIFO only: 1<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+------------------------+-------+<BR>clk | NONE(reset_i) | 4 |<BR>-----------------------------------+------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>No asynchronous control signals found in this design<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: 1.842ns (Maximum Frequency: 542.888MHz)<BR> Minimum input arrival time before clock: 1.109ns<BR> Maximum output required time after clock: 2.145ns<BR> Maximum combinational path delay: 0.250ns<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default period analysis for Clock 'clk'<BR> Clock period: 1.842ns (frequency: 542.888MHz)<BR> Total number of paths / destination ports: 9 / 6<BR>-------------------------------------------------------------------------<BR>Delay: 1.842ns (Levels of Logic = 1)<BR> Source: reset_i (FF)<BR> Destination: FIFO18E1_inst (UNKNOWN)<BR> Source Clock: clk rising<BR> Destination Clock: clk rising<BR><BR> Data Path: reset_i to FIFO18E1_inst<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FDP:C->Q 6 0.375 0.450 reset_i (reset_i)<BR> LUT2:I1->O 1 0.068 0.399 push_i1 (push_i)<BR> FIFO18E1:WREN 0.550 FIFO18E1_inst<BR> ----------------------------------------<BR> Total 1.842ns (0.993ns logic, 0.849ns route)<BR> (53.9% logic, 46.1% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 5 / 5<BR>-------------------------------------------------------------------------<BR>Offset: 1.109ns (Levels of Logic = 1)<BR> Source: push (PAD)<BR> Destination: FIFO18E1_inst (UNKNOWN)<BR> Destination Clock: clk rising<BR><BR> Data Path: push to FIFO18E1_inst<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT2:I0->O 1 0.068 0.399 push_i1 (push_i)<BR> FIFO18E1:WREN 0.550 FIFO18E1_inst<BR> ----------------------------------------<BR> Total 1.109ns (0.710ns logic, 0.399ns route)<BR> (64.0% logic, 36.0% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 42 / 36<BR>-------------------------------------------------------------------------<BR>Offset: 2.145ns (Levels of Logic = 2)<BR> Source: reset_i (FF)<BR> Destination: nopush (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: reset_i to nopush<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FDP:C->Q 6 0.375 0.432 reset_i (reset_i)<BR> FIFO18E1:RST->WRERR 1 0.853 0.417 FIFO18E1_inst (wrerr_i)<BR> LUT3:I2->O 0 0.068 0.000 nopush1 (nopush)<BR> ----------------------------------------<BR> Total 2.145ns (1.296ns logic, 0.849ns route)<BR> (60.4% logic, 39.6% route)<BR><BR>=========================================================================<BR>Timing constraint: Default path analysis<BR> Total number of paths / destination ports: 2 / 2<BR>-------------------------------------------------------------------------<BR>Delay: 0.250ns (Levels of Logic = 1)<BR> Source: pop (PAD)<BR> Destination: nopop (PAD)<BR><BR> Data Path: pop to nopop<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT3:I0->O 0 0.068 0.000 nopop1 (nopop)<BR> ----------------------------------------<BR> Total 0.250ns (0.250ns logic, 0.000ns route)<BR> (100.0% logic, 0.0% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>Clock to Setup on destination clock clk<BR>---------------+---------+---------+---------+---------+<BR> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<BR>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<BR>---------------+---------+---------+---------+---------+<BR>clk | 1.842| | | |<BR>---------------+---------+---------+---------+---------+<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 4.00 secs<BR>Total CPU time to Xst completion: 3.94 secs<BR> <BR>--> <BR><BR>Total memory usage is 239608 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 0 ( 0 filtered)<BR>Number of infos : 1 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML> |
/fifo/generic_fifo_sum.html
0,0 → 1,176
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE> |
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<BODY aLink=#ff0000 bgColor=#ffffff text=#000000 vLink=#551a8b link=#0000ee> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>modulus_ram_asym Project Status (03/06/2013 |
- 15:20:55)</B></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Project File:</B></TD> |
<TD>RAMtest.xise</TD> |
<TD bgColor=#ffff99><B>Parser Errors:</B></TD> |
<TD>No Errors </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Module Name:</B></TD> |
<TD>fifo_generic</TD> |
<TD bgColor=#ffff99><B>Implementation State:</B></TD> |
<TD>Synthesized</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Errors:</B></LI></UL></TD> |
<TD>No Errors</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Product Version:</B></TD> |
<TD>ISE 12.4</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Warnings:</B></LI></UL></TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/RAMtest\_xmsgs/*.xmsgs?&DataKey=Warning">1 |
Warning (0 new)</A></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Goal:</B></DIF></TD> |
<TD>Balanced</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Routing Results:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Strategy:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="Xilinx Default (unlocked)?&DataKey=Strategy">Xilinx |
Default (unlocked)</A></TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Environment:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/RAMtest\fifo_generic_envsettings.html">System |
Settings</A> </TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>Device Utilization Summary (estimated |
values)</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></A></TD></TR> |
<TR align=center bgColor=#ffff99> |
<TD align=left><B>Logic Utilization</B></TD> |
<TD><B>Used</B></TD> |
<TD><B>Available</B></TD> |
<TD colSpan=2><B>Utilization</B></TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice Registers</TD> |
<TD align=right>15</TD> |
<TD align=right>301440</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice LUTs</TD> |
<TD align=right>32</TD> |
<TD align=right>150720</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of fully used LUT-FF pairs</TD> |
<TD align=right>15</TD> |
<TD align=right>32</TD> |
<TD colSpan=2 align=right>46%</TD></TR> |
<TR align=right> |
<TD align=left>Number of bonded IOBs</TD> |
<TD align=right>0</TD> |
<TD align=right>600</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Block RAM/FIFO</TD> |
<TD align=right>1</TD> |
<TD align=right>416</TD> |
<TD colSpan=2 align=right>0%</TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=6 align=center><B>Detailed Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD><A HREF_DISABLED="D:/Dropbox/ISE/RAMtest\fifo_generic.syr">Synthesis |
Report</A></TD> |
<TD>Current</TD> |
<TD>wo 6. mrt 15:20:55 2013</TD> |
<TD align=left>0</TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/RAMtest\_xmsgs/xst.xmsgs?&DataKey=Warning">1 |
Warning (0 new)</A></TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/RAMtest\_xmsgs/xst.xmsgs?&DataKey=Info">2 |
Infos (1 new)</A></TD></TR> |
<TR align=left> |
<TD>Translation Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Map Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Place and Route Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Power Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Post-PAR Static Timing Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Bitgen Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=3 align=center><B>Secondary Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD colSpan=2><B>Generated</B></TD></TR></TBODY></TABLE><BR> |
<CENTER><B>Date Generated:</B> 03/06/2013 - 15:20:55</CENTER></BODY></HTML> |
/fifo/generic_fifo_syn.html
0,0 → 1,5
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<HTML><HEAD><TITLE>Synthesis Report</TITLE> |
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<BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>wo 6. mrt 15:22:27 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.10 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.10 secs<BR> <BR>--> Reading design: fifo_generic.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "fifo_generic.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "fifo_generic"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : fifo_generic<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Yes<BR>Use Synchronous Set : Yes<BR>Use Synchronous Reset : Yes<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"ipcore_dir" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Parsing VHDL file "\Dropbox\ISE\RAMtest\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<BR>Parsing package <STD_FUNCTIONS>.<BR>Parsing package body <STD_FUNCTIONS>.<BR>Parsing VHDL file "\Dropbox\ISE\RAMtest\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <DPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\RAMtest\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp<BR>Parsing package <MOD_SIM_EXP_PKG>.<BR>Parsing VHDL file "\Dropbox\ISE\RAMtest\../../SVN/mod_sim_exp/rtl/vhdl/core/fifo_generic.vhd" into library work<BR>Parsing entity <FIFO_GENERIC>.<BR>Parsing architecture <ARCH> of entity <FIFO_GENERIC>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <FIFO_GENERIC> (architecture <ARCH>) with generics from library <WORK>.<BR><BR>Elaborating entity <DPRAM_GENERIC> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <FIFO_GENERIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_generic.vhd".<BR> depth = 32<BR> Found 6-bit register for signal <RD_ADDR>.<BR> Found 1-bit register for signal <PUSH_I_D>.<BR> Found 1-bit register for signal <NOPOP>.<BR> Found 1-bit register for signal <NOPUSH>.<BR> Found 6-bit register for signal <WR_ADDR>.<BR> Found 6-bit adder for signal <WR_ADDR[5]_GND_7_O_ADD_0_OUT> created at line 96.<BR> Found 6-bit adder for signal <RD_ADDR[5]_GND_7_O_ADD_10_OUT> created at line 121.<BR> Found 6-bit comparator equal for signal <WR_ADDR[5]_RD_ADDR[5]_EQUAL_2_O> created at line 96<BR> Found 6-bit comparator equal for signal <EMPTY> created at line 100<BR> Summary:<BR> inferred 2 Adder/Subtractor(s).<BR> inferred 15 D-type flip-flop(s).<BR> inferred 2 Comparator(s).<BR>Unit <FIFO_GENERIC> synthesized.<BR><BR>Synthesizing Unit <DPRAM_GENERIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd".<BR> depth = 33<BR> Set property "ram_style = block" for signal <RAM>.<BR>WARNING:Xst:3035 - Index value(s) does not match array range for signal <RAM>, simulation mismatch.<BR> Found 33x32-bit dual-port RAM <MRAM_RAM> for signal <RAM>.<BR> Found 32-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 RAM(s).<BR> inferred 32 D-type flip-flop(s).<BR>Unit <DPRAM_GENERIC> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 1<BR> 33x32-bit dual-port RAM : 1<BR># Adders/Subtractors : 2<BR> 6-bit adder : 2<BR># Registers : 6<BR> 1-bit register : 3<BR> 32-bit register : 1<BR> 6-bit register : 2<BR># Comparators : 2<BR> 6-bit comparator equal : 2<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR><BR>Synthesizing (advanced) Unit <DPRAM_GENERIC>.<BR>INFO:Xst:3040 - The RAM <MRAM_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOUT><BR> -----------------------------------------------------------------------<BR> | ram_type | Block | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 33-word x 32-bit | |<BR> | mode | read-first | |<BR> | clkA | connected to signal <CLK> | rise |<BR> | weA | connected to signal <WE> | high |<BR> | addrA | connected to signal <WADDR> | |<BR> | diA | connected to signal <DIN> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR> | Port B |<BR> | aspect ratio | 33-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkB | connected to signal <CLK> | rise |<BR> | addrB | connected to signal <RADDR> | |<BR> | doB | connected to signal <DOUT> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR>Unit <DPRAM_GENERIC> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <FIFO_GENERIC>.<BR>The following registers are absorbed into counter <RD_ADDR>: 1 register on signal <RD_ADDR>.<BR>The following registers are absorbed into counter <WR_ADDR>: 1 register on signal <WR_ADDR>.<BR>Unit <FIFO_GENERIC> synthesized (advanced).<BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 1<BR> 33x32-bit dual-port block RAM : 1<BR># Adders/Subtractors : 1<BR> 6-bit adder : 1<BR># Counters : 2<BR> 6-bit up counter : 2<BR># Registers : 3<BR> Flip-Flops : 3<BR># Comparators : 2<BR> 6-bit comparator equal : 2<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <FIFO_GENERIC> ...<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block fifo_generic, actual ratio is 0.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Macro Statistics<BR># Registers : 15<BR> Flip-Flops : 15<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : fifo_generic.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 34<BR># GND : 1<BR># INV : 3<BR># LUT2 : 5<BR># LUT3 : 4<BR># LUT4 : 5<BR># LUT5 : 7<BR># LUT6 : 8<BR># VCC : 1<BR># FlipFlops/Latches : 15<BR># FD : 2<BR># FDR : 3<BR># FDRE : 10<BR># RAMS : 1<BR># RAMB18E1 : 1<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice Registers: 15 out of 301440 0% <BR> Number of Slice LUTs: 32 out of 150720 0% <BR> Number used as Logic: 32 out of 150720 0% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 32<BR> Number with an unused Flip Flop: 17 out of 32 53% <BR> Number with an unused LUT: 0 out of 32 0% <BR> Number of fully used LUT-FF pairs: 15 out of 32 46% <BR> Number of unique control sets: 6<BR><BR>IO Utilization: <BR> Number of IOs: 72<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 1 out of 416 0% <BR> Number using Block RAM only: 1<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+------------------------+-------+<BR>clk | NONE(nopush) | 16 |<BR>-----------------------------------+------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>No asynchronous control signals found in this design<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: 3.673ns (Maximum Frequency: 272.257MHz)<BR> Minimum input arrival time before clock: 1.304ns<BR> Maximum output required time after clock: 2.301ns<BR> Maximum combinational path delay: No path found<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default period analysis for Clock 'clk'<BR> Clock period: 3.673ns (frequency: 272.257MHz)<BR> Total number of paths / destination ports: 834 / 53<BR>-------------------------------------------------------------------------<BR>Delay: 3.673ns (Levels of Logic = 4)<BR> Source: wr_addr_4 (FF)<BR> Destination: wr_addr_1 (FF)<BR> Source Clock: clk rising<BR> Destination Clock: clk rising<BR><BR> Data Path: wr_addr_4 to wr_addr_1<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FDRE:C->Q 5 0.375 0.802 wr_addr_4 (wr_addr_4)<BR> LUT5:I0->O 2 0.068 0.497 Result<4>11 (Result<4>1)<BR> LUT4:I2->O 2 0.068 0.423 full1 (full1)<BR> LUT6:I5->O 5 0.068 0.444 full4 (full)<BR> LUT4:I3->O 5 0.068 0.426 Mcount_wr_addr_val1 (Mcount_wr_addr_val)<BR> FDRE:R 0.434 wr_addr_0<BR> ----------------------------------------<BR> Total 3.673ns (1.081ns logic, 2.592ns route)<BR> (29.4% logic, 70.6% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 75 / 59<BR>-------------------------------------------------------------------------<BR>Offset: 1.304ns (Levels of Logic = 1)<BR> Source: reset (PAD)<BR> Destination: rd_addr_1 (FF)<BR> Destination Clock: clk rising<BR><BR> Data Path: reset to rd_addr_1<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT5:I0->O 5 0.068 0.426 Mcount_rd_addr_val1 (Mcount_rd_addr_val)<BR> FDRE:R 0.434 rd_addr_0<BR> ----------------------------------------<BR> Total 1.304ns (0.878ns logic, 0.426ns route)<BR> (67.3% logic, 32.7% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 85 / 36<BR>-------------------------------------------------------------------------<BR>Offset: 2.301ns (Levels of Logic = 3)<BR> Source: wr_addr_4 (FF)<BR> Destination: full (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: wr_addr_4 to full<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FDRE:C->Q 5 0.375 0.802 wr_addr_4 (wr_addr_4)<BR> LUT5:I0->O 2 0.068 0.497 Result<4>11 (Result<4>1)<BR> LUT4:I2->O 2 0.068 0.423 full1 (full1)<BR> LUT6:I5->O 5 0.068 0.000 full4 (full)<BR> ----------------------------------------<BR> Total 2.301ns (0.579ns logic, 1.722ns route)<BR> (25.2% logic, 74.8% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>Clock to Setup on destination clock clk<BR>---------------+---------+---------+---------+---------+<BR> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<BR>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<BR>---------------+---------+---------+---------+---------+<BR>clk | 3.673| | | |<BR>---------------+---------+---------+---------+---------+<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 7.00 secs<BR>Total CPU time to Xst completion: 6.56 secs<BR> <BR>--> <BR><BR>Total memory usage is 234232 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 1 ( 0 filtered)<BR>Number of infos : 2 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML> |
/fifo/xil_prim_fifo_sum.html
0,0 → 1,173
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE> |
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<BODY aLink=#ff0000 bgColor=#ffffff text=#000000 vLink=#551a8b link=#0000ee> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>operand_ram Project Status (03/06/2013 - |
15:11:48)</B></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Project File:</B></TD> |
<TD>mod_exp_core.xise</TD> |
<TD bgColor=#ffff99><B>Parser Errors:</B></TD> |
<TD>No Errors </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Module Name:</B></TD> |
<TD>fifo_primitive</TD> |
<TD bgColor=#ffff99><B>Implementation State:</B></TD> |
<TD>Synthesized</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Errors:</B></LI></UL></TD> |
<TD>No Errors</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Product Version:</B></TD> |
<TD>ISE 12.4</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Warnings:</B></LI></UL></TD> |
<TD align=left>No Warnings</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Goal:</B></DIF></TD> |
<TD>Balanced</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Routing Results:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Strategy:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="Xilinx Default (unlocked)?&DataKey=Strategy">Xilinx |
Default (unlocked)</A></TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Environment:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\fifo_primitive_envsettings.html">System |
Settings</A> </TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>Device Utilization Summary (estimated |
values)</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></A></TD></TR> |
<TR align=center bgColor=#ffff99> |
<TD align=left><B>Logic Utilization</B></TD> |
<TD><B>Used</B></TD> |
<TD><B>Available</B></TD> |
<TD colSpan=2><B>Utilization</B></TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice Registers</TD> |
<TD align=right>3</TD> |
<TD align=right>301440</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice LUTs</TD> |
<TD align=right>7</TD> |
<TD align=right>150720</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of fully used LUT-FF pairs</TD> |
<TD align=right>0</TD> |
<TD align=right>10</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of bonded IOBs</TD> |
<TD align=right>0</TD> |
<TD align=right>600</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Block RAM/FIFO</TD> |
<TD align=right>1</TD> |
<TD align=right>416</TD> |
<TD colSpan=2 align=right>0%</TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=6 align=center><B>Detailed Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\fifo_primitive.syr">Synthesis |
Report</A></TD> |
<TD>Current</TD> |
<TD>wo 6. mrt 15:11:46 2013</TD> |
<TD align=left>0</TD> |
<TD align=left>0</TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Info">1 |
Info (0 new)</A></TD></TR> |
<TR align=left> |
<TD>Translation Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Map Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Place and Route Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Power Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Post-PAR Static Timing Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Bitgen Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=3 align=center><B>Secondary Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD colSpan=2><B>Generated</B></TD></TR></TBODY></TABLE><BR> |
<CENTER><B>Date Generated:</B> 03/06/2013 - 15:11:48</CENTER></BODY></HTML> |
/operand_mem/xil_prim_syn.html
0,0 → 1,5
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<BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>wo 6. mrt 15:03:01 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.11 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.11 secs<BR> <BR>--> Reading design: operand_mem.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "operand_mem.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "operand_mem"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : operand_mem<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Auto<BR>Use Synchronous Set : Auto<BR>Use Synchronous Reset : Auto<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"../../SVN/mod_sim_exp/rtl/vhdl/core" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.v\" into library work<BR>Parsing module <OPERAND_DP>.<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.v\" into library work<BR>Parsing module <OPERANDS_SP>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<BR>Parsing package <STD_FUNCTIONS>.<BR>Parsing package body <STD_FUNCTIONS>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAM_ASYM>.<BR>Parsing architecture <BEHAVORIAL> of entity <TDPRAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAM_ASYM>.<BR>Parsing architecture <BEHAVORIAL> of entity <DPRAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <TDPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpramblock_asym.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAMBLOCK_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <TDPRAMBLOCK_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <DPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpramblock_asym.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAMBLOCK_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <DPRAMBLOCK_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp<BR>Parsing package <MOD_SIM_EXP_PKG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM_ASYM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <MODULUS_RAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_MEM>.<BR>Parsing architecture <STRUCTURAL> of entity <OPERAND_MEM>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <OPERAND_MEM> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <OPERAND_RAM> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:89 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" Line 476: <OPERAND_DP> remains a black-box since it has no binding entity.<BR><BR>Elaborating entity <MODULUS_RAM> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:89 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" Line 496: <OPERANDS_SP> remains a black-box since it has no binding entity.<BR>WARNING:HDLCompiler:321 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" Line 160: Comparison between arrays of unequal length always returns FALSE.<BR>WARNING:HDLCompiler:321 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" Line 199: Comparison between arrays of unequal length always returns FALSE.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <OPERAND_MEM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd".<BR> width = 1536<BR> nr_op = 4<BR> nr_m = 2<BR> mem_style = "xil_prim"<BR> device = "xilinx"<BR>WARNING:Xst:647 - Input <MODULUS_SEL<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.<BR> Summary:<BR> inferred 2 Multiplexer(s).<BR>Unit <OPERAND_MEM> synthesized.<BR><BR>Synthesizing Unit <OPERAND_RAM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd".<BR> Found 32-bit 3-to-1 multiplexer for signal <RESULT_OUT> created at line 120.<BR> Summary:<BR> inferred 3 Multiplexer(s).<BR>Unit <OPERAND_RAM> synthesized.<BR><BR>Synthesizing Unit <MODULUS_RAM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd".<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <MODULUS_RAM> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># Multiplexers : 6<BR> 1-bit 2-to-1 multiplexer : 2<BR> 32-bit 3-to-1 multiplexer : 1<BR> 4-bit 2-to-1 multiplexer : 2<BR> 6-bit 2-to-1 multiplexer : 1<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR>Reading core <../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.ngc>.<BR>Reading core <../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.ngc>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_0>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_1>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_2>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_0>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_1>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_2>.<BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># Multiplexers : 6<BR> 1-bit 2-to-1 multiplexer : 2<BR> 32-bit 3-to-1 multiplexer : 1<BR> 4-bit 2-to-1 multiplexer : 2<BR> 6-bit 2-to-1 multiplexer : 1<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <OPERAND_MEM> ...<BR><BR>Optimizing unit <OPERAND_RAM> ...<BR><BR>Optimizing unit <MODULUS_RAM> ...<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block operand_mem, actual ratio is 0.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Found no macro<BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : operand_mem.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 58<BR># GND : 7<BR># LUT3 : 1<BR># LUT4 : 7<BR># LUT5 : 37<BR># VCC : 6<BR># RAMS : 96<BR># RAMB36E1 : 96<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice LUTs: 45 out of 150720 0% <BR> Number used as Logic: 45 out of 150720 0% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 45<BR> Number with an unused Flip Flop: 45 out of 45 100% <BR> Number with an unused LUT: 0 out of 45 0% <BR> Number of fully used LUT-FF pairs: 0 out of 45 0% <BR> Number of unique control sets: 0<BR><BR>IO Utilization: <BR> Number of IOs: 4690<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 96 out of 416 23% <BR> Number using Block RAM only: 96<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------+<BR>clk | NONE(xil_prim_RAM.xy_ram_xil/op_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 96 |<BR>-----------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>---------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-------+<BR>Control Signal | Buffer(FF name) | Load |<BR>---------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-------+<BR>xil_prim_RAM.m_ram_xil/modulus_0/BU2/doutb(0)(xil_prim_RAM.m_ram_xil/modulus_0/BU2/XST_GND:G)| NONE(xil_prim_RAM.m_ram_xil/modulus_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>xil_prim_RAM.m_ram_xil/modulus_1/BU2/doutb(0)(xil_prim_RAM.m_ram_xil/modulus_1/BU2/XST_GND:G)| NONE(xil_prim_RAM.m_ram_xil/modulus_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>xil_prim_RAM.m_ram_xil/modulus_2/BU2/doutb(0)(xil_prim_RAM.m_ram_xil/modulus_2/BU2/XST_GND:G)| NONE(xil_prim_RAM.m_ram_xil/modulus_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>xil_prim_RAM.xy_ram_xil/op_0/BU2/rdaddrecc(0)(xil_prim_RAM.xy_ram_xil/op_0/BU2/XST_GND:G) | NONE(xil_prim_RAM.xy_ram_xil/op_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>xil_prim_RAM.xy_ram_xil/op_1/BU2/rdaddrecc(0)(xil_prim_RAM.xy_ram_xil/op_1/BU2/XST_GND:G) | NONE(xil_prim_RAM.xy_ram_xil/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>xil_prim_RAM.xy_ram_xil/op_2/BU2/rdaddrecc(0)(xil_prim_RAM.xy_ram_xil/op_2/BU2/XST_GND:G) | NONE(xil_prim_RAM.xy_ram_xil/op_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>---------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-------+<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: No path found<BR> Minimum input arrival time before clock: 1.518ns<BR> Maximum output required time after clock: 2.779ns<BR> Maximum combinational path delay: 0.444ns<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 5376 / 3072<BR>-------------------------------------------------------------------------<BR>Offset: 1.518ns (Levels of Logic = 2)<BR> Source: rw_address<5> (PAD)<BR> Destination: xil_prim_RAM.xy_ram_xil/op_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (RAM)<BR> Destination Clock: clk rising<BR><BR> Data Path: rw_address<5> to xil_prim_RAM.xy_ram_xil/op_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT5:I0->O 64 0.068 0.559 xil_prim_RAM.xy_ram_xil/wea<2>1 (xil_prim_RAM.xy_ram_xil/wea<2>)<BR> begin scope: 'xil_prim_RAM.xy_ram_xil/op_2'<BR> begin scope: 'BU2'<BR> RAMB36E1:WEA3 0.515 U0/blk_mem_generator/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> ----------------------------------------<BR> Total 1.518ns (0.959ns logic, 0.559ns route)<BR> (63.2% logic, 36.8% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 96 / 32<BR>-------------------------------------------------------------------------<BR>Offset: 2.779ns (Levels of Logic = 2)<BR> Source: xil_prim_RAM.xy_ram_xil/op_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (RAM)<BR> Destination: data_out<31> (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: xil_prim_RAM.xy_ram_xil/op_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram to data_out<31><BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> RAMB36E1:CLKARDCLK->DOBDO1 1 2.073 0.638 U0/blk_mem_generator/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (doutb(31))<BR> end scope: 'BU2'<BR> end scope: 'xil_prim_RAM.xy_ram_xil/op_0'<BR> LUT5:I1->O 0 0.068 0.000 xil_prim_RAM.xy_ram_xil/Mmux_result_out251 (data_out<31>)<BR> ----------------------------------------<BR> Total 2.779ns (2.141ns logic, 0.638ns route)<BR> (77.0% logic, 23.0% route)<BR><BR>=========================================================================<BR>Timing constraint: Default path analysis<BR> Total number of paths / destination ports: 67 / 33<BR>-------------------------------------------------------------------------<BR>Delay: 0.444ns (Levels of Logic = 1)<BR> Source: rw_address<5> (PAD)<BR> Destination: data_out<31> (PAD)<BR><BR> Data Path: rw_address<5> to data_out<31><BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT5:I0->O 0 0.068 0.000 xil_prim_RAM.xy_ram_xil/Mmux_result_out110 (data_out<0>)<BR> ----------------------------------------<BR> Total 0.444ns (0.444ns logic, 0.000ns route)<BR> (100.0% logic, 0.0% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 22.00 secs<BR>Total CPU time to Xst completion: 21.76 secs<BR> <BR>--> <BR><BR>Total memory usage is 238904 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 5 ( 0 filtered)<BR>Number of infos : 1 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML> |
/operand_mem/asym_sum.html
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<TD colSpan=4 align=center><B>operand_ram Project Status (03/06/2013 - |
15:05:52)</B></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Project File:</B></TD> |
<TD>mod_exp_core.xise</TD> |
<TD bgColor=#ffff99><B>Parser Errors:</B></TD> |
<TD>No Errors </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Module Name:</B></TD> |
<TD>operand_mem</TD> |
<TD bgColor=#ffff99><B>Implementation State:</B></TD> |
<TD>Synthesized</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Errors:</B></LI></UL></TD> |
<TD>No Errors</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Product Version:</B></TD> |
<TD>ISE 12.4</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Warnings:</B></LI></UL></TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/*.xmsgs?&DataKey=Warning">4 |
Warnings (2 new)</A></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Goal:</B></DIF></TD> |
<TD>Balanced</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Routing Results:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Strategy:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="Xilinx Default (unlocked)?&DataKey=Strategy">Xilinx |
Default (unlocked)</A></TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Environment:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\operand_mem_envsettings.html">System |
Settings</A> </TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>Device Utilization Summary (estimated |
values)</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></A></TD></TR> |
<TR align=center bgColor=#ffff99> |
<TD align=left><B>Logic Utilization</B></TD> |
<TD><B>Used</B></TD> |
<TD><B>Available</B></TD> |
<TD colSpan=2><B>Utilization</B></TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice LUTs</TD> |
<TD align=right>41</TD> |
<TD align=right>150720</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of fully used LUT-FF pairs</TD> |
<TD align=right>0</TD> |
<TD align=right>41</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of bonded IOBs</TD> |
<TD align=right>0</TD> |
<TD align=right>600</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Block RAM/FIFO</TD> |
<TD align=right>96</TD> |
<TD align=right>416</TD> |
<TD colSpan=2 align=right>23%</TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=6 align=center><B>Detailed Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\operand_mem.syr">Synthesis |
Report</A></TD> |
<TD>Current</TD> |
<TD>wo 6. mrt 15:05:51 2013</TD> |
<TD align=left>0</TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Warning">4 |
Warnings (2 new)</A></TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Info">3 |
Infos (1 new)</A></TD></TR> |
<TR align=left> |
<TD>Translation Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Map Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Place and Route Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Power Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Post-PAR Static Timing Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Bitgen Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=3 align=center><B>Secondary Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD colSpan=2><B>Generated</B></TD></TR></TBODY></TABLE><BR> |
<CENTER><B>Date Generated:</B> 03/06/2013 - 15:05:52</CENTER></BODY></HTML> |
/operand_mem/generic_sum.html
0,0 → 1,172
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE> |
<META content="text/html; charset=windows-1252" http-equiv=Content-Type> |
<META name=GENERATOR content="MSHTML 9.00.8112.16457"></HEAD> |
<BODY aLink=#ff0000 bgColor=#ffffff text=#000000 vLink=#551a8b link=#0000ee> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>operand_ram Project Status (03/06/2013 - |
15:04:08)</B></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Project File:</B></TD> |
<TD>mod_exp_core.xise</TD> |
<TD bgColor=#ffff99><B>Parser Errors:</B></TD> |
<TD>No Errors </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Module Name:</B></TD> |
<TD>operand_mem</TD> |
<TD bgColor=#ffff99><B>Implementation State:</B></TD> |
<TD>Synthesized</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Errors:</B></LI></UL></TD> |
<TD>No Errors</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Product Version:</B></TD> |
<TD>ISE 12.4</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Warnings:</B></LI></UL></TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/*.xmsgs?&DataKey=Warning">2 |
Warnings (0 new)</A></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Goal:</B></DIF></TD> |
<TD>Balanced</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Routing Results:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Strategy:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="Xilinx Default (unlocked)?&DataKey=Strategy">Xilinx |
Default (unlocked)</A></TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Environment:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\operand_mem_envsettings.html">System |
Settings</A> </TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>Device Utilization Summary (estimated |
values)</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></A></TD></TR> |
<TR align=center bgColor=#ffff99> |
<TD align=left><B>Logic Utilization</B></TD> |
<TD><B>Used</B></TD> |
<TD><B>Available</B></TD> |
<TD colSpan=2><B>Utilization</B></TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice LUTs</TD> |
<TD align=right>623</TD> |
<TD align=right>150720</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of fully used LUT-FF pairs</TD> |
<TD align=right>0</TD> |
<TD align=right>623</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of bonded IOBs</TD> |
<TD align=right>0</TD> |
<TD align=right>600</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Block RAM/FIFO</TD> |
<TD align=right>72</TD> |
<TD align=right>416</TD> |
<TD colSpan=2 align=right>17%</TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=6 align=center><B>Detailed Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\operand_mem.syr">Synthesis |
Report</A></TD> |
<TD>Current</TD> |
<TD>wo 6. mrt 15:04:07 2013</TD> |
<TD align=left>0</TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Warning">2 |
Warnings (0 new)</A></TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Info">3 |
Infos (2 new)</A></TD></TR> |
<TR align=left> |
<TD>Translation Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Map Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Place and Route Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Power Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Post-PAR Static Timing Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Bitgen Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=3 align=center><B>Secondary Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD colSpan=2><B>Generated</B></TD></TR></TBODY></TABLE><BR> |
<CENTER><B>Date Generated:</B> 03/06/2013 - 15:04:08</CENTER></BODY></HTML> |
/operand_mem/asym_syn.html
0,0 → 1,5
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<HTML><HEAD><TITLE>Synthesis Report</TITLE> |
<META content="text/html; charset=windows-1252" http-equiv=Content-Type> |
<META name=GENERATOR content="MSHTML 9.00.8112.16457"></HEAD> |
<BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>wo 6. mrt 15:06:12 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.12 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.12 secs<BR> <BR>--> Reading design: operand_mem.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "operand_mem.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "operand_mem"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : operand_mem<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Auto<BR>Use Synchronous Set : Auto<BR>Use Synchronous Reset : Auto<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"../../SVN/mod_sim_exp/rtl/vhdl/core" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.v\" into library work<BR>Parsing module <OPERAND_DP>.<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.v\" into library work<BR>Parsing module <OPERANDS_SP>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<BR>Parsing package <STD_FUNCTIONS>.<BR>Parsing package body <STD_FUNCTIONS>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAM_ASYM>.<BR>Parsing architecture <BEHAVORIAL> of entity <TDPRAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAM_ASYM>.<BR>Parsing architecture <BEHAVORIAL> of entity <DPRAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <TDPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpramblock_asym.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAMBLOCK_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <TDPRAMBLOCK_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <DPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpramblock_asym.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAMBLOCK_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <DPRAMBLOCK_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp<BR>Parsing package <MOD_SIM_EXP_PKG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM_ASYM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <MODULUS_RAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_MEM>.<BR>Parsing architecture <STRUCTURAL> of entity <OPERAND_MEM>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <OPERAND_MEM> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:321 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" Line 131: Comparison between arrays of unequal length always returns FALSE.<BR>WARNING:HDLCompiler:321 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" Line 160: Comparison between arrays of unequal length always returns FALSE.<BR><BR>Elaborating entity <OPERAND_RAM_ASYM> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <TDPRAMBLOCK_ASYM> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <TDPRAM_ASYM> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:634 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_asym.vhd" Line 145: Net <MULTIPLE_FULL_BLOCKS.DOUTA_RAM[3][31]> does not have a driver.<BR><BR>Elaborating entity <MODULUS_RAM_ASYM> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <DPRAMBLOCK_ASYM> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <DPRAM_ASYM> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <OPERAND_MEM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd".<BR> width = 1536<BR> nr_op = 4<BR> nr_m = 2<BR> mem_style = "asym"<BR> device = "xilinx"<BR> Summary:<BR> inferred 2 Multiplexer(s).<BR>Unit <OPERAND_MEM> synthesized.<BR><BR>Synthesizing Unit <OPERAND_RAM_ASYM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram_asym.vhd".<BR> width = 1536<BR> depth = 4<BR> device = "xilinx"<BR>WARNING:Xst:653 - Signal <MULTIPLE_FULL_BLOCKS.DOUTA_RAM<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.<BR> Found 32-bit 4-to-1 multiplexer for signal <OPERAND_ADDR[5]_MULTIPLE_FULL_BLOCKS.DOUTA_RAM[3][31]_WIDE_MUX_5_OUT> created at line 185.<BR> Found 2-bit comparator greater for signal <OPERAND_ADDR[5]_PWR_8_O_LESSTHAN_5_O> created at line 186<BR> Summary:<BR> inferred 1 Comparator(s).<BR> inferred 6 Multiplexer(s).<BR>Unit <OPERAND_RAM_ASYM> synthesized.<BR><BR>Synthesizing Unit <TDPRAMBLOCK_ASYM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/tdpramblock_asym.vhd".<BR> depth = 4<BR> width = 512<BR> device = "xilinx"<BR> Summary:<BR> no macro.<BR>Unit <TDPRAMBLOCK_ASYM> synthesized.<BR><BR>Synthesizing Unit <TDPRAM_ASYM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/tdpram_asym.vhd".<BR> depthB = 4<BR> widthA = 2<BR> device = "xilinx"<BR> Found 64x2:4x32-bit dual-port RAM <MRAM_RAM> for signal <RAM>.<BR> Found 32-bit register for signal <DOUTB>.<BR> Found 2-bit register for signal <DOUTA>.<BR> Summary:<BR> inferred 1 RAM(s).<BR> inferred 34 D-type flip-flop(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <TDPRAM_ASYM> synthesized.<BR><BR>Synthesizing Unit <MODULUS_RAM_ASYM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram_asym.vhd".<BR> width = 1536<BR> depth = 2<BR> device = "xilinx"<BR> Summary:<BR> inferred 3 Multiplexer(s).<BR>Unit <MODULUS_RAM_ASYM> synthesized.<BR><BR>Synthesizing Unit <DPRAMBLOCK_ASYM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpramblock_asym.vhd".<BR> width = 512<BR> depth = 2<BR> device = "xilinx"<BR> Summary:<BR> no macro.<BR>Unit <DPRAMBLOCK_ASYM> synthesized.<BR><BR>Synthesizing Unit <DPRAM_ASYM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_asym.vhd".<BR> rddepth = 2<BR> wrwidth = 2<BR> device = "xilinx"<BR> Set property "ram_style = block" for signal <RAM>.<BR> Found 32x2:2x32-bit dual-port RAM <MRAM_RAM> for signal <RAM>.<BR> Found 32-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 RAM(s).<BR> inferred 32 D-type flip-flop(s).<BR>Unit <DPRAM_ASYM> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 96<BR> 32x2:2x32-bit dual-port RAM : 48<BR> 64x2:4x32-bit dual-port RAM : 48<BR># Registers : 144<BR> 2-bit register : 48<BR> 32-bit register : 96<BR># Comparators : 1<BR> 2-bit comparator greater : 1<BR># Multiplexers : 107<BR> 1-bit 2-to-1 multiplexer : 8<BR> 2-bit 2-to-1 multiplexer : 49<BR> 32-bit 2-to-1 multiplexer : 49<BR> 32-bit 4-to-1 multiplexer : 1<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR><BR>Synthesizing (advanced) Unit <DPRAM_ASYM>.<BR>INFO:Xst:3040 - The RAM <MRAM_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOUT><BR> -----------------------------------------------------------------------<BR> | ram_type | Block | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 32-word x 2-bit | |<BR> | mode | read-first | |<BR> | clkA | connected to signal <CLK> | rise |<BR> | weA | connected to signal <WE> | high |<BR> | addrA | connected to signal <WADDR> | |<BR> | diA | connected to signal <DIN> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR> | Port B |<BR> | aspect ratio | 2-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkB | connected to signal <CLK> | rise |<BR> | addrB | connected to signal <RADDR> | |<BR> | doB | connected to signal <DOUT> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR>Unit <DPRAM_ASYM> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <TDPRAM_ASYM>.<BR>INFO:Xst:3040 - The RAM <MRAM_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOUTA> <DOUTB><BR> -----------------------------------------------------------------------<BR> | ram_type | Block | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 64-word x 2-bit | |<BR> | mode | write-first | |<BR> | clkA | connected to signal <CLK> | rise |<BR> | weA | connected to signal <WEA> | high |<BR> | addrA | connected to signal <ADDRA> | |<BR> | diA | connected to signal <DINA> | |<BR> | doA | connected to signal <DOUTA> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR> | Port B |<BR> | aspect ratio | 4-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkB | connected to signal <CLK> | rise |<BR> | weB | connected to signal <WEB> | high |<BR> | addrB | connected to signal <ADDRB> | |<BR> | diB | connected to signal <DINB> | |<BR> | doB | connected to signal <DOUTB> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR>Unit <TDPRAM_ASYM> synthesized (advanced).<BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 96<BR> 32x2:2x32-bit dual-port block RAM : 48<BR> 64x2:4x32-bit dual-port block RAM : 48<BR># Comparators : 1<BR> 2-bit comparator greater : 1<BR># Multiplexers : 11<BR> 1-bit 2-to-1 multiplexer : 8<BR> 2-bit 2-to-1 multiplexer : 1<BR> 32-bit 2-to-1 multiplexer : 1<BR> 32-bit 4-to-1 multiplexer : 1<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <OPERAND_MEM> ...<BR><BR>Optimizing unit <OPERAND_RAM_ASYM> ...<BR><BR>Optimizing unit <TDPRAMBLOCK_ASYM> ...<BR><BR>Optimizing unit <MODULUS_RAM_ASYM> ...<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block operand_mem, actual ratio is 0.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Found no macro<BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : operand_mem.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 43<BR># GND : 1<BR># LUT3 : 3<BR># LUT4 : 3<BR># LUT5 : 35<BR># VCC : 1<BR># RAMS : 96<BR># RAMB36E1 : 96<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice LUTs: 41 out of 150720 0% <BR> Number used as Logic: 41 out of 150720 0% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 41<BR> Number with an unused Flip Flop: 41 out of 41 100% <BR> Number with an unused LUT: 0 out of 41 0% <BR> Number of fully used LUT-FF pairs: 0 out of 41 0% <BR> Number of unique control sets: 0<BR><BR>IO Utilization: <BR> Number of IOs: 4690<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 96 out of 416 23% <BR> Number using Block RAM only: 96<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+-------------------------------------------------------------------------------------------------------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+-------------------------------------------------------------------------------------------------------------------------+-------+<BR>clk | NONE(asym_RAM.xy_ram_asym/multiple_full_blocks.ramblocks_full[2].full_ones.ramblock_full/ramblocks[0].ramblock/Mram_ram)| 96 |<BR>-----------------------------------+-------------------------------------------------------------------------------------------------------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>No asynchronous control signals found in this design<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: No path found<BR> Minimum input arrival time before clock: 1.518ns<BR> Maximum output required time after clock: 2.722ns<BR> Maximum combinational path delay: 0.444ns<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 4704 / 3168<BR>-------------------------------------------------------------------------<BR>Offset: 1.518ns (Levels of Logic = 1)<BR> Source: rw_address<5> (PAD)<BR> Destination: asym_RAM.xy_ram_asym/multiple_full_blocks.ramblocks_full[2].full_ones.ramblock_full/ramblocks[0].ramblock/Mram_ram (RAM)<BR> Destination Clock: clk rising<BR><BR> Data Path: rw_address<5> to asym_RAM.xy_ram_asym/multiple_full_blocks.ramblocks_full[2].full_ones.ramblock_full/ramblocks[0].ramblock/Mram_ram<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT5:I0->O 64 0.068 0.559 asym_RAM.xy_ram_asym/Mmux_multiple_full_blocks.weA_RAM<2>11 (asym_RAM.xy_ram_asym/multiple_full_blocks.weA_RAM<2>)<BR> RAMB36E1:WEA0 0.515 asym_RAM.xy_ram_asym/multiple_full_blocks.ramblocks_full[2].full_ones.ramblock_full/ramblocks[0].ramblock/Mram_ram<BR> ----------------------------------------<BR> Total 1.518ns (0.959ns logic, 0.559ns route)<BR> (63.2% logic, 36.8% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 3168 / 3104<BR>-------------------------------------------------------------------------<BR>Offset: 2.722ns (Levels of Logic = 1)<BR> Source: asym_RAM.xy_ram_asym/multiple_full_blocks.ramblocks_full[0].full_ones.ramblock_full/ramblocks[15].ramblock/Mram_ram (RAM)<BR> Destination: data_out<31> (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: asym_RAM.xy_ram_asym/multiple_full_blocks.ramblocks_full[0].full_ones.ramblock_full/ramblocks[15].ramblock/Mram_ram to data_out<31><BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> RAMB36E1:CLKARDCLK->DOADO1 1 2.073 0.581 asym_RAM.xy_ram_asym/multiple_full_blocks.ramblocks_full[0].full_ones.ramblock_full/ramblocks[15].ramblock/Mram_ram (asym_RAM.xy_ram_asym/multiple_full_blocks.doutA_RAM<0><31>)<BR> LUT5:I2->O 0 0.068 0.000 asym_RAM.xy_ram_asym/Mmux_result_out251 (data_out<31>)<BR> ----------------------------------------<BR> Total 2.722ns (2.141ns logic, 0.581ns route)<BR> (78.7% logic, 21.3% route)<BR><BR>=========================================================================<BR>Timing constraint: Default path analysis<BR> Total number of paths / destination ports: 67 / 33<BR>-------------------------------------------------------------------------<BR>Delay: 0.444ns (Levels of Logic = 1)<BR> Source: rw_address<5> (PAD)<BR> Destination: data_out<31> (PAD)<BR><BR> Data Path: rw_address<5> to data_out<31><BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT5:I0->O 0 0.068 0.000 asym_RAM.xy_ram_asym/Mmux_result_out110 (data_out<0>)<BR> ----------------------------------------<BR> Total 0.444ns (0.444ns logic, 0.000ns route)<BR> (100.0% logic, 0.0% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 40.00 secs<BR>Total CPU time to Xst completion: 40.28 secs<BR> <BR>--> <BR><BR>Total memory usage is 270976 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 4 ( 0 filtered)<BR>Number of infos : 3 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML> |
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<BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>wo 6. mrt 15:04:45 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.10 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.10 secs<BR> <BR>--> Reading design: operand_mem.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "operand_mem.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "operand_mem"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : operand_mem<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Auto<BR>Use Synchronous Set : Auto<BR>Use Synchronous Reset : Auto<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"../../SVN/mod_sim_exp/rtl/vhdl/core" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.v\" into library work<BR>Parsing module <OPERAND_DP>.<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.v\" into library work<BR>Parsing module <OPERANDS_SP>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<BR>Parsing package <STD_FUNCTIONS>.<BR>Parsing package body <STD_FUNCTIONS>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAM_ASYM>.<BR>Parsing architecture <BEHAVORIAL> of entity <TDPRAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAM_ASYM>.<BR>Parsing architecture <BEHAVORIAL> of entity <DPRAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <TDPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpramblock_asym.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAMBLOCK_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <TDPRAMBLOCK_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <DPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpramblock_asym.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAMBLOCK_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <DPRAMBLOCK_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp<BR>Parsing package <MOD_SIM_EXP_PKG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM_ASYM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram_asym.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM_ASYM>.<BR>Parsing architecture <STRUCTURAL> of entity <MODULUS_RAM_ASYM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_MEM>.<BR>Parsing architecture <STRUCTURAL> of entity <OPERAND_MEM>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <OPERAND_MEM> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:321 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" Line 131: Comparison between arrays of unequal length always returns FALSE.<BR><BR>Elaborating entity <OPERAND_RAM_GEN> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <TDPRAM_GENERIC> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <MODULUS_RAM_GEN> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <DPRAM_GENERIC> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:321 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" Line 199: Comparison between arrays of unequal length always returns FALSE.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <OPERAND_MEM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd".<BR> width = 1536<BR> nr_op = 4<BR> nr_m = 2<BR> mem_style = "generic"<BR> device = "xilinx"<BR> Summary:<BR> inferred 2 Multiplexer(s).<BR>Unit <OPERAND_MEM> synthesized.<BR><BR>Synthesizing Unit <OPERAND_RAM_GEN>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd".<BR> width = 1536<BR> depth = 4<BR> Found 32-bit 48-to-1 multiplexer for signal <ADDRB[5]_X_8_O_WIDE_MUX_59_OUT> created at line 174.<BR> Found 6-bit comparator greater for signal <ADDRB[5]_PWR_8_O_LESSTHAN_59_O> created at line 174<BR> Summary:<BR> inferred 1 Comparator(s).<BR> inferred 51 Multiplexer(s).<BR>Unit <OPERAND_RAM_GEN> synthesized.<BR><BR>Synthesizing Unit <TDPRAM_GENERIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd".<BR> depth = 4<BR> Set property "ram_style = block" for signal <RAM>.<BR> Found 4x32-bit dual-port RAM <MRAM_RAM> for signal <RAM>.<BR> Found 32-bit register for signal <DOUTB>.<BR> Found 32-bit register for signal <DOUTA>.<BR> Summary:<BR> inferred 1 RAM(s).<BR> inferred 64 D-type flip-flop(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <TDPRAM_GENERIC> synthesized.<BR><BR>Synthesizing Unit <MODULUS_RAM_GEN>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd".<BR> width = 1536<BR> depth = 2<BR> Summary:<BR> inferred 48 Multiplexer(s).<BR>Unit <MODULUS_RAM_GEN> synthesized.<BR><BR>Synthesizing Unit <DPRAM_GENERIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd".<BR> depth = 2<BR> Set property "ram_style = block" for signal <RAM>.<BR> Found 2x32-bit dual-port RAM <MRAM_RAM> for signal <RAM>.<BR> Found 32-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 RAM(s).<BR> inferred 32 D-type flip-flop(s).<BR>Unit <DPRAM_GENERIC> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 96<BR> 2x32-bit dual-port RAM : 48<BR> 4x32-bit dual-port RAM : 48<BR># Registers : 144<BR> 32-bit register : 144<BR># Comparators : 1<BR> 6-bit comparator greater : 1<BR># Multiplexers : 197<BR> 1-bit 2-to-1 multiplexer : 98<BR> 2-bit 2-to-1 multiplexer : 1<BR> 32-bit 2-to-1 multiplexer : 97<BR> 32-bit 48-to-1 multiplexer : 1<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR><BR>Synthesizing (advanced) Unit <DPRAM_GENERIC>.<BR>INFO:Xst:3040 - The RAM <MRAM_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOUT><BR> -----------------------------------------------------------------------<BR> | ram_type | Block | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 2-word x 32-bit | |<BR> | mode | read-first | |<BR> | clkA | connected to signal <CLK> | rise |<BR> | weA | connected to signal <WE> | high |<BR> | addrA | connected to signal <WADDR> | |<BR> | diA | connected to signal <DIN> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR> | Port B |<BR> | aspect ratio | 2-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkB | connected to signal <CLK> | rise |<BR> | addrB | connected to signal <RADDR> | |<BR> | doB | connected to signal <DOUT> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR>Unit <DPRAM_GENERIC> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <TDPRAM_GENERIC>.<BR>INFO:Xst:3040 - The RAM <MRAM_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOUTA> <DOUTB><BR> -----------------------------------------------------------------------<BR> | ram_type | Block | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 4-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkA | connected to signal <CLKA> | rise |<BR> | weA | connected to signal <WEA> | high |<BR> | addrA | connected to signal <ADDRA> | |<BR> | diA | connected to signal <DINA> | |<BR> | doA | connected to signal <DOUTA> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR> | Port B |<BR> | aspect ratio | 4-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkB | connected to signal <CLKB> | rise |<BR> | weB | connected to signal <WEB> | high |<BR> | addrB | connected to signal <ADDRB> | |<BR> | diB | connected to signal <DINB> | |<BR> | doB | connected to signal <DOUTB> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR>Unit <TDPRAM_GENERIC> synthesized (advanced).<BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 96<BR> 2x32-bit dual-port block RAM : 48<BR> 4x32-bit dual-port block RAM : 48<BR># Comparators : 1<BR> 6-bit comparator greater : 1<BR># Multiplexers : 101<BR> 1-bit 2-to-1 multiplexer : 98<BR> 2-bit 2-to-1 multiplexer : 1<BR> 32-bit 2-to-1 multiplexer : 1<BR> 32-bit 48-to-1 multiplexer : 1<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <OPERAND_MEM> ...<BR><BR>Optimizing unit <OPERAND_RAM_GEN> ...<BR><BR>Optimizing unit <MODULUS_RAM_GEN> ...<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block operand_mem, actual ratio is 0.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Found no macro<BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : operand_mem.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 689<BR># GND : 1<BR># LUT2 : 1<BR># LUT3 : 17<BR># LUT4 : 35<BR># LUT5 : 50<BR># LUT6 : 520<BR># MUXF7 : 64<BR># VCC : 1<BR># RAMS : 96<BR># RAMB18E1 : 48<BR># RAMB36E1 : 48<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice LUTs: 623 out of 150720 0% <BR> Number used as Logic: 623 out of 150720 0% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 623<BR> Number with an unused Flip Flop: 623 out of 623 100% <BR> Number with an unused LUT: 0 out of 623 0% <BR> Number of fully used LUT-FF pairs: 0 out of 623 0% <BR> Number of unique control sets: 0<BR><BR>IO Utilization: <BR> Number of IOs: 4690<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 72 out of 416 17% <BR> Number using Block RAM only: 72<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+--------------------------------------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+--------------------------------------------------------+-------+<BR>clk | NONE(gen_RAM.xy_ram_gen/ramblocks[1].ramblock/Mram_RAM)| 96 |<BR>-----------------------------------+--------------------------------------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>No asynchronous control signals found in this design<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: No path found<BR> Minimum input arrival time before clock: 2.133ns<BR> Maximum output required time after clock: 4.472ns<BR> Maximum combinational path delay: 2.140ns<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 8928 / 5664<BR>-------------------------------------------------------------------------<BR>Offset: 2.133ns (Levels of Logic = 2)<BR> Source: rw_address<1> (PAD)<BR> Destination: gen_RAM.xy_ram_gen/ramblocks[1].ramblock/Mram_RAM (RAM)<BR> Destination Clock: clk rising<BR><BR> Data Path: rw_address<1> to gen_RAM.xy_ram_gen/ramblocks[1].ramblock/Mram_RAM<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT6:I0->O 8 0.068 0.684 gen_RAM.xy_ram_gen/Mmux_weA_RAM<13>111 (gen_RAM.xy_ram_gen/N35)<BR> LUT4:I0->O 4 0.068 0.419 gen_RAM.xy_ram_gen/Mmux_weA_RAM<1>11 (gen_RAM.xy_ram_gen/weA_RAM<1>)<BR> RAMB36E1:WEA0 0.515 gen_RAM.xy_ram_gen/ramblocks[1].ramblock/Mram_RAM<BR> ----------------------------------------<BR> Total 2.133ns (1.030ns logic, 1.103ns route)<BR> (48.3% logic, 51.7% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 5632 / 3104<BR>-------------------------------------------------------------------------<BR>Offset: 4.472ns (Levels of Logic = 5)<BR> Source: gen_RAM.xy_ram_gen/ramblocks[26].ramblock/Mram_RAM (RAM)<BR> Destination: data_out<31> (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: gen_RAM.xy_ram_gen/ramblocks[26].ramblock/Mram_RAM to data_out<31><BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> RAMB36E1:CLKARDCLK->DOBDO31 1 2.073 0.638 gen_RAM.xy_ram_gen/ramblocks[26].ramblock/Mram_RAM (gen_RAM.xy_ram_gen/doutB_RAM<26><31>)<BR> LUT6:I2->O 1 0.068 0.638 gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_11121 (gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_11121)<BR> LUT6:I2->O 1 0.068 0.000 gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_624 (gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_624)<BR> MUXF7:I1->O 2 0.248 0.423 gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_5_f7_23 (gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_5_f724)<BR> LUT6:I5->O 1 0.068 0.000 gen_RAM.xy_ram_gen/Mmux_doutB251 (gen_RAM.xy_ram_gen/Mmux_doutB25)<BR> MUXF7:I1->O 0 0.248 0.000 gen_RAM.xy_ram_gen/Mmux_doutB25_f7 (data_out<31>)<BR> ----------------------------------------<BR> Total 4.472ns (2.773ns logic, 1.699ns route)<BR> (62.0% logic, 38.0% route)<BR><BR>=========================================================================<BR>Timing constraint: Default path analysis<BR> Total number of paths / destination ports: 1827 / 33<BR>-------------------------------------------------------------------------<BR>Delay: 2.140ns (Levels of Logic = 5)<BR> Source: rw_address<1> (PAD)<BR> Destination: data_out<31> (PAD)<BR><BR> Data Path: rw_address<1> to data_out<31><BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT6:I0->O 1 0.068 0.638 gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_111 (gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_111)<BR> LUT6:I2->O 1 0.068 0.000 gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_6 (gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_6)<BR> MUXF7:I1->O 2 0.248 0.423 gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_5_f7 (gen_RAM.xy_ram_gen/Mmux_addrB[5]_X_8_o_wide_mux_59_OUT_5_f7)<BR> LUT6:I5->O 1 0.068 0.000 gen_RAM.xy_ram_gen/Mmux_doutB110 (gen_RAM.xy_ram_gen/Mmux_doutB1)<BR> MUXF7:I1->O 0 0.248 0.000 gen_RAM.xy_ram_gen/Mmux_doutB1_f7 (data_out<0>)<BR> ----------------------------------------<BR> Total 2.140ns (1.079ns logic, 1.061ns route)<BR> (50.4% logic, 49.6% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 41.00 secs<BR>Total CPU time to Xst completion: 41.06 secs<BR> <BR>--> <BR><BR>Total memory usage is 277112 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 2 ( 0 filtered)<BR>Number of infos : 3 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML> |
/operand_mem/xil_prim_sum.html
0,0 → 1,172
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE> |
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<BODY aLink=#ff0000 bgColor=#ffffff text=#000000 vLink=#551a8b link=#0000ee> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>operand_ram Project Status (03/06/2013 - |
15:02:24)</B></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Project File:</B></TD> |
<TD>mod_exp_core.xise</TD> |
<TD bgColor=#ffff99><B>Parser Errors:</B></TD> |
<TD>No Errors </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Module Name:</B></TD> |
<TD>operand_mem</TD> |
<TD bgColor=#ffff99><B>Implementation State:</B></TD> |
<TD>Synthesized</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Errors:</B></LI></UL></TD> |
<TD>No Errors</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Product Version:</B></TD> |
<TD>ISE 12.4</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Warnings:</B></LI></UL></TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/*.xmsgs?&DataKey=Warning">5 |
Warnings (0 new)</A></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Goal:</B></DIF></TD> |
<TD>Balanced</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Routing Results:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Strategy:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="Xilinx Default (unlocked)?&DataKey=Strategy">Xilinx |
Default (unlocked)</A></TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Environment:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\operand_mem_envsettings.html">System |
Settings</A> </TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>Device Utilization Summary (estimated |
values)</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></A></TD></TR> |
<TR align=center bgColor=#ffff99> |
<TD align=left><B>Logic Utilization</B></TD> |
<TD><B>Used</B></TD> |
<TD><B>Available</B></TD> |
<TD colSpan=2><B>Utilization</B></TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice LUTs</TD> |
<TD align=right>45</TD> |
<TD align=right>150720</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of fully used LUT-FF pairs</TD> |
<TD align=right>0</TD> |
<TD align=right>45</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of bonded IOBs</TD> |
<TD align=right>0</TD> |
<TD align=right>600</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Block RAM/FIFO</TD> |
<TD align=right>96</TD> |
<TD align=right>416</TD> |
<TD colSpan=2 align=right>23%</TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=6 align=center><B>Detailed Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\operand_mem.syr">Synthesis |
Report</A></TD> |
<TD>Current</TD> |
<TD>wo 6. mrt 15:02:23 2013</TD> |
<TD align=left>0</TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Warning">5 |
Warnings (0 new)</A></TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Info">1 |
Info (0 new)</A></TD></TR> |
<TR align=left> |
<TD>Translation Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Map Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Place and Route Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Power Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Post-PAR Static Timing Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Bitgen Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=3 align=center><B>Secondary Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD colSpan=2><B>Generated</B></TD></TR></TBODY></TABLE><BR> |
<CENTER><B>Date Generated:</B> 03/06/2013 - 15:02:24</CENTER></BODY></HTML> |
/mod_sim_exp_core/ver010_msec_syn.html
0,0 → 1,5
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<BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>di 26. feb 15:21:57 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.11 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.11 secs<BR> <BR>--> Reading design: mod_sim_exp_core.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "mod_sim_exp_core.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "mod_sim_exp_core"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : mod_sim_exp_core<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Auto<BR>Use Synchronous Set : Auto<BR>Use Synchronous Reset : Auto<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"../../SVN/mod_sim_exp/rtl/vhdl/core" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.v\" into library work<BR>Parsing module <OPERAND_DP>.<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.v\" into library work<BR>Parsing module <OPERANDS_SP>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<BR>Parsing package <STD_FUNCTIONS>.<BR>Parsing package body <STD_FUNCTIONS>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp<BR>Parsing package <MOD_SIM_EXP_PKG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B_MUX>.<BR>Parsing architecture <BEHAVIORAL> of entity <CELL_1B_MUX>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B_ADDER>.<BR>Parsing architecture <BEHAVIORAL> of entity <CELL_1B_ADDER>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd" into library mod_sim_exp<BR>Parsing entity <D_FLIP_FLOP>.<BR>Parsing architecture <BEHAVORIAL> of entity <D_FLIP_FLOP>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B>.<BR>Parsing architecture <STRUCTURAL> of entity <CELL_1B>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd" into library mod_sim_exp<BR>Parsing entity <STANDARD_CELL_BLOCK>.<BR>Parsing architecture <STRUCTURAL> of entity <STANDARD_CELL_BLOCK>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_n.vhd" into library mod_sim_exp<BR>Parsing entity <REGISTER_N>.<BR>Parsing architecture <BEHAVORIAL> of entity <REGISTER_N>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_1b.vhd" into library mod_sim_exp<BR>Parsing entity <REGISTER_1B>.<BR>Parsing architecture <BEHAVORIAL> of entity <REGISTER_1B>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/adder_block.vhd" into library mod_sim_exp<BR>Parsing entity <ADDER_BLOCK>.<BR>Parsing architecture <STRUCTURAL> of entity <ADDER_BLOCK>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_STAGE>.<BR>Parsing architecture <STRUCTURAL> of entity <SYS_STAGE>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_LAST_CELL_LOGIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <SYS_LAST_CELL_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_FIRST_CELL_LOGIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <SYS_FIRST_CELL_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd" into library mod_sim_exp<BR>Parsing entity <COUNTER_SYNC>.<BR>Parsing architecture <BEHAVIORAL> of entity <COUNTER_SYNC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd" into library mod_sim_exp<BR>Parsing entity <X_SHIFT_REG>.<BR>Parsing architecture <BEHAVIORAL> of entity <X_SHIFT_REG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_PIPELINE>.<BR>Parsing architecture <STRUCTURAL> of entity <SYS_PIPELINE>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd" into library mod_sim_exp<BR>Parsing entity <STEPPING_LOGIC>.<BR>Parsing architecture <BEHAVIORAL> of entity <STEPPING_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd" into library mod_sim_exp<BR>Parsing entity <AUTORUN_CNTRL>.<BR>Parsing architecture <BEHAVIORAL> of entity <AUTORUN_CNTRL>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_MEM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_MEM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd" into library mod_sim_exp<BR>Parsing entity <MONT_MULTIPLIER>.<BR>Parsing architecture <STRUCTURAL> of entity <MONT_MULTIPLIER>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd" into library mod_sim_exp<BR>Parsing entity <MONT_CTRL>.<BR>Parsing architecture <BEHAVIORAL> of entity <MONT_CTRL>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd" into library mod_sim_exp<BR>Parsing entity <FIFO_PRIMITIVE>.<BR>Parsing architecture <BEHAVIORAL> of entity <FIFO_PRIMITIVE>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" into library mod_sim_exp<BR>Parsing entity <MOD_SIM_EXP_CORE>.<BR>Parsing architecture <STRUCTURAL> of entity <MOD_SIM_EXP_CORE>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <MOD_SIM_EXP_CORE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <MONT_MULTIPLIER> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <D_FLIP_FLOP> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <X_SHIFT_REG> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <STEPPING_LOGIC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_PIPELINE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_STAGE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <ADDER_BLOCK> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B_ADDER> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <STANDARD_CELL_BLOCK> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B> (architecture <STRUCTURAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B_MUX> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <REGISTER_N> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <REGISTER_1B> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_FIRST_CELL_LOGIC> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_LAST_CELL_LOGIC> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <OPERAND_MEM> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <OPERAND_RAM> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:89 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" Line 475: <OPERAND_DP> remains a black-box since it has no binding entity.<BR><BR>Elaborating entity <MODULUS_RAM> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:89 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" Line 495: <OPERANDS_SP> remains a black-box since it has no binding entity.<BR><BR>Elaborating entity <FIFO_PRIMITIVE> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <MONT_CTRL> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <AUTORUN_CNTRL> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <MOD_SIM_EXP_CORE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd".<BR> C_NR_BITS_TOTAL = 1536<BR> C_NR_STAGES_TOTAL = 96<BR> C_NR_STAGES_LOW = 32<BR> C_SPLIT_PIPELINE = true<BR> C_NR_OP = 4<BR> C_NR_M = 2<BR> C_FIFO_DEPTH = 32<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" line 167: Output port <NOPOP> of the instance <THE_EXPONENT_FIFO> is unconnected or connected to loadless signal.<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <MOD_SIM_EXP_CORE> synthesized.<BR><BR>Synthesizing Unit <MONT_MULTIPLIER>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> split = true<BR> Found 4x18-bit Read Only RAM for signal <_n0015><BR> Summary:<BR> inferred 1 RAM(s).<BR>Unit <MONT_MULTIPLIER> synthesized.<BR><BR>Synthesizing Unit <D_FLIP_FLOP>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd".<BR> Found 1-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 D-type flip-flop(s).<BR>Unit <D_FLIP_FLOP> synthesized.<BR><BR>Synthesizing Unit <X_SHIFT_REG>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> Found 1536-bit register for signal <X_REG>.<BR> Summary:<BR> inferred 1536 D-type flip-flop(s).<BR> inferred 1536 Multiplexer(s).<BR>Unit <X_SHIFT_REG> synthesized.<BR><BR>Synthesizing Unit <STEPPING_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd".<BR> n = 1536<BR> t = 96<BR> Summary:<BR> no macro.<BR>Unit <STEPPING_LOGIC> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_1>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 96<BR> Found 7-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 7-bit adder for signal <COUNT_PROC.STEPS_COUNTER[6]_GND_12_O_ADD_2_OUT> created at line 83.<BR> Found 32-bit subtractor for signal <RESET_VALUE[31]_GND_12_O_SUB_1_OUT<31:0>> created at line 79.<BR> Found 32-bit comparator equal for signal <RESET_VALUE[31]_GND_12_O_EQUAL_2_O> created at line 79<BR> Summary:<BR> inferred 2 Adder/Subtractor(s).<BR> inferred 8 D-type flip-flop(s).<BR> inferred 1 Comparator(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_1> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_2>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 1536<BR> Found 11-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 11-bit adder for signal <COUNT_PROC.STEPS_COUNTER[10]_GND_38_O_ADD_2_OUT> created at line 83.<BR> Found 32-bit subtractor for signal <RESET_VALUE[31]_GND_38_O_SUB_1_OUT<31:0>> created at line 79.<BR> Found 32-bit comparator equal for signal <RESET_VALUE[31]_GND_38_O_EQUAL_2_O> created at line 79<BR> Summary:<BR> inferred 2 Adder/Subtractor(s).<BR> inferred 12 D-type flip-flop(s).<BR> inferred 1 Comparator(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_2> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_3>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 2<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 1-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit adder for signal <COUNT_PROC.STEPS_COUNTER[0]_PWR_15_O_ADD_2_OUT<0>> created at line 83.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 2 D-type flip-flop(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_3> synthesized.<BR><BR>Synthesizing Unit <SYS_PIPELINE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> split = true<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <MY_COUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <XOUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <QOUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR> Found 1-bit 3-to-1 multiplexer for signal <START_STAGE<32>> created at line 270.<BR> Found 1-bit 4-to-1 multiplexer for signal <R_SEL_L> created at line 304.<BR> Summary:<BR> inferred 11 Multiplexer(s).<BR>Unit <SYS_PIPELINE> synthesized.<BR><BR>Synthesizing Unit <SYS_STAGE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd".<BR> width = 16<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <SYS_STAGE> synthesized.<BR><BR>Synthesizing Unit <ADDER_BLOCK>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/adder_block.vhd".<BR> width = 16<BR> Summary:<BR> no macro.<BR>Unit <ADDER_BLOCK> synthesized.<BR><BR>Synthesizing Unit <CELL_1B_ADDER>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd".<BR> Summary:<BR>Unit <CELL_1B_ADDER> synthesized.<BR><BR>Synthesizing Unit <STANDARD_CELL_BLOCK>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd".<BR> width = 16<BR> Summary:<BR> no macro.<BR>Unit <STANDARD_CELL_BLOCK> synthesized.<BR><BR>Synthesizing Unit <CELL_1B>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd".<BR> Summary:<BR> no macro.<BR>Unit <CELL_1B> synthesized.<BR><BR>Synthesizing Unit <CELL_1B_MUX>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd".<BR> Found 1-bit 4-to-1 multiplexer for signal <RESULT> created at line 72.<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <CELL_1B_MUX> synthesized.<BR><BR>Synthesizing Unit <REGISTER_N>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_n.vhd".<BR> width = 16<BR> Found 16-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 16 D-type flip-flop(s).<BR>Unit <REGISTER_N> synthesized.<BR><BR>Synthesizing Unit <REGISTER_1B>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_1b.vhd".<BR> Found 1-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 D-type flip-flop(s).<BR>Unit <REGISTER_1B> synthesized.<BR><BR>Synthesizing Unit <SYS_FIRST_CELL_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd".<BR> Summary:<BR>Unit <SYS_FIRST_CELL_LOGIC> synthesized.<BR><BR>Synthesizing Unit <SYS_LAST_CELL_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd".<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" line 86: Output port <R> of the instance <REDUCTION_ADDER> is unconnected or connected to loadless signal.<BR> Summary:<BR> no macro.<BR>Unit <SYS_LAST_CELL_LOGIC> synthesized.<BR><BR>Synthesizing Unit <OPERAND_MEM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd".<BR> n = 1536<BR> Summary:<BR> inferred 2 Multiplexer(s).<BR>Unit <OPERAND_MEM> synthesized.<BR><BR>Synthesizing Unit <OPERAND_RAM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd".<BR> Found 32-bit 3-to-1 multiplexer for signal <RESULT_OUT> created at line 120.<BR> Summary:<BR> inferred 3 Multiplexer(s).<BR>Unit <OPERAND_RAM> synthesized.<BR><BR>Synthesizing Unit <MODULUS_RAM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd".<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <MODULUS_RAM> synthesized.<BR><BR>Synthesizing Unit <FIFO_PRIMITIVE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd".<BR> Found 1-bit register for signal <RESET_I>.<BR> Found 2-bit register for signal <RESET_PROC.CLK_COUNTER>.<BR> Found 2-bit subtractor for signal <GND_108_O_GND_108_O_SUB_2_OUT<1:0>> created at line 100.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 3 D-type flip-flop(s).<BR> inferred 1 Multiplexer(s).<BR>Unit <FIFO_PRIMITIVE> synthesized.<BR><BR>Synthesizing Unit <MONT_CTRL>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd".<BR> Found 3-bit register for signal <START_UP_COUNTER>.<BR> Found 1-bit register for signal <CALC_TIME_I>.<BR> Found 1-bit register for signal <START_D>.<BR> Found 3-bit adder for signal <START_UP_COUNTER[2]_GND_114_O_ADD_0_OUT> created at line 128.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 5 D-type flip-flop(s).<BR> inferred 5 Multiplexer(s).<BR>Unit <MONT_CTRL> synthesized.<BR><BR>Synthesizing Unit <AUTORUN_CNTRL>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd".<BR> Found 4-bit register for signal <BIT_COUNTER_I>.<BR> Found 1-bit register for signal <RUNNING_I>.<BR> Found 1-bit register for signal <START_MULTIPLIER_DEL_I>.<BR> Found 1-bit register for signal <START_CYCLE_DEL_I>.<BR> Found 1-bit register for signal <MULT_DONE_DEL_I>.<BR> Found 1-bit register for signal <CYCLE_COUNTER_I>.<BR> Found 4-bit subtractor for signal <GND_115_O_GND_115_O_SUB_4_OUT<3:0>> created at line 113.<BR> Found 1-bit 16-to-1 multiplexer for signal <E0_BIT_I> created at line 122.<BR> Found 1-bit 16-to-1 multiplexer for signal <E1_BIT_I> created at line 123.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 9 D-type flip-flop(s).<BR> inferred 7 Multiplexer(s).<BR>Unit <AUTORUN_CNTRL> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 1<BR> 4x18-bit single-port Read Only RAM : 1<BR># Adders/Subtractors : 8<BR> 1-bit adder : 1<BR> 11-bit adder : 1<BR> 2-bit subtractor : 1<BR> 3-bit adder : 1<BR> 32-bit subtractor : 2<BR> 4-bit subtractor : 1<BR> 7-bit adder : 1<BR># Registers : 695<BR> 1-bit register : 593<BR> 11-bit register : 1<BR> 1536-bit register : 1<BR> 16-bit register : 96<BR> 2-bit register : 1<BR> 3-bit register : 1<BR> 4-bit register : 1<BR> 7-bit register : 1<BR># Comparators : 2<BR> 32-bit comparator equal : 2<BR># Multiplexers : 3207<BR> 1-bit 16-to-1 multiplexer : 2<BR> 1-bit 2-to-1 multiplexer : 1553<BR> 1-bit 3-to-1 multiplexer : 1<BR> 1-bit 4-to-1 multiplexer : 1539<BR> 11-bit 2-to-1 multiplexer : 1<BR> 16-bit 2-to-1 multiplexer : 96<BR> 2-bit 2-to-1 multiplexer : 6<BR> 3-bit 2-to-1 multiplexer : 2<BR> 32-bit 3-to-1 multiplexer : 1<BR> 4-bit 2-to-1 multiplexer : 4<BR> 6-bit 2-to-1 multiplexer : 1<BR> 7-bit 2-to-1 multiplexer : 1<BR># Xors : 9224<BR> 1-bit xor2 : 9224<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR>Reading core <../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.ngc>.<BR>Reading core <../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.ngc>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_0>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_1>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_2>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_0>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_1>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_2>.<BR>WARNING:Xst:1290 - Hierarchical block <CARRY_REG> is unconnected in block <MY_ADDER>.<BR> It will be removed from the design.<BR>WARNING:Xst:1290 - Hierarchical block <XOUT_REG> is unconnected in block <PIPELINE_STAGES[95].STAGE>.<BR> It will be removed from the design.<BR>WARNING:Xst:1290 - Hierarchical block <QOUT_REG> is unconnected in block <PIPELINE_STAGES[95].STAGE>.<BR> It will be removed from the design.<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_1>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER>: 1 register on signal <COUNT_PROC.STEPS_COUNTER>.<BR>Unit <COUNTER_SYNC_1> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_2>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER>: 1 register on signal <COUNT_PROC.STEPS_COUNTER>.<BR>Unit <COUNTER_SYNC_2> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_3>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER_0>: 1 register on signal <COUNT_PROC.STEPS_COUNTER_0>.<BR>Unit <COUNTER_SYNC_3> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <MONT_MULTIPLIER>.<BR>INFO:Xst:3031 - HDL ADVISOR - The RAM <MRAM__N0015> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.<BR> -----------------------------------------------------------------------<BR> | ram_type | Distributed | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 4-word x 18-bit | |<BR> | weA | connected to signal <GND> | high |<BR> | addrA | connected to signal <P_SEL> | |<BR> | diA | connected to signal <GND> | |<BR> | doA | connected to signal <T_SEL> | |<BR> -----------------------------------------------------------------------<BR>Unit <MONT_MULTIPLIER> synthesized (advanced).<BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 1<BR> 4x18-bit single-port distributed Read Only RAM : 1<BR># Adders/Subtractors : 5<BR> 2-bit subtractor : 1<BR> 3-bit adder : 1<BR> 32-bit subtractor : 2<BR> 4-bit subtractor : 1<BR># Counters : 3<BR> 1-bit up counter : 1<BR> 11-bit up counter : 1<BR> 7-bit up counter : 1<BR># Registers : 3673<BR> Flip-Flops : 3673<BR># Comparators : 2<BR> 32-bit comparator equal : 2<BR># Multiplexers : 3202<BR> 1-bit 16-to-1 multiplexer : 2<BR> 1-bit 2-to-1 multiplexer : 1552<BR> 1-bit 3-to-1 multiplexer : 1<BR> 1-bit 4-to-1 multiplexer : 1539<BR> 16-bit 2-to-1 multiplexer : 96<BR> 2-bit 2-to-1 multiplexer : 4<BR> 3-bit 2-to-1 multiplexer : 2<BR> 32-bit 3-to-1 multiplexer : 1<BR> 4-bit 2-to-1 multiplexer : 4<BR> 6-bit 2-to-1 multiplexer : 1<BR># Xors : 9224<BR> 1-bit xor2 : 9224<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <MOD_SIM_EXP_CORE> ...<BR><BR>Optimizing unit <OPERAND_RAM> ...<BR><BR>Optimizing unit <MODULUS_RAM> ...<BR><BR>Optimizing unit <FIFO_PRIMITIVE> ...<BR><BR>Optimizing unit <MONT_CTRL> ...<BR><BR>Optimizing unit <AUTORUN_CNTRL> ...<BR><BR>Optimizing unit <X_SHIFT_REG> ...<BR><BR>Optimizing unit <SYS_PIPELINE> ...<BR><BR>Optimizing unit <SYS_STAGE> ...<BR><BR>Optimizing unit <ADDER_BLOCK> ...<BR><BR>Optimizing unit <STANDARD_CELL_BLOCK> ...<BR><BR>Optimizing unit <REGISTER_N> ...<BR><BR>Optimizing unit <STEPPING_LOGIC> ...<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout xout_reg pipeline_stages[95].stage systolic_array> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout pipeline_stages[95].stage systolic_array qout_reg> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout pipeline_stages[95].stage systolic_array carry_reg my_adder> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block mod_sim_exp_core, actual ratio is 7.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Macro Statistics<BR># Registers : 3689<BR> Flip-Flops : 3689<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : mod_sim_exp_core.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 10150<BR># GND : 7<BR># INV : 1<BR># LUT2 : 14<BR># LUT3 : 788<BR># LUT4 : 799<BR># LUT5 : 3883<BR># LUT6 : 3864<BR># MUXCY : 10<BR># MUXF7 : 762<BR># MUXF8 : 2<BR># VCC : 7<BR># XORCY : 13<BR># FlipFlops/Latches : 3689<BR># FD : 4<BR># FDC : 1832<BR># FDCE : 1845<BR># FDP : 4<BR># FDPE : 4<BR># RAMS : 97<BR># FIFO18E1 : 1<BR># RAMB36E1 : 96<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice Registers: 3689 out of 301440 1% <BR> Number of Slice LUTs: 9349 out of 150720 6% <BR> Number used as Logic: 9349 out of 150720 6% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 9490<BR> Number with an unused Flip Flop: 5801 out of 9490 61% <BR> Number with an unused LUT: 141 out of 9490 1% <BR> Number of fully used LUT-FF pairs: 3548 out of 9490 37% <BR> Number of unique control sets: 108<BR><BR>IO Utilization: <BR> Number of IOs: 124<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 97 out of 416 23% <BR> Number using Block RAM only: 96<BR> Number using FIFO only: 1<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+----------------------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+----------------------------------------+-------+<BR>clk | NONE(the_multiplier/delay_1_cycle/dout)| 3786 |<BR>-----------------------------------+----------------------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+<BR>Control Signal | Buffer(FF name) | Load |<BR>---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+<BR>the_memory/m_ram/modulus_0/BU2/doutb(0)(the_memory/m_ram/modulus_0/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>the_memory/m_ram/modulus_1/BU2/doutb(0)(the_memory/m_ram/modulus_1/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>the_memory/m_ram/modulus_2/BU2/doutb(0)(the_memory/m_ram/modulus_2/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>the_memory/xy_ram/op_0/BU2/rdaddrecc(0)(the_memory/xy_ram/op_0/BU2/XST_GND:G) | NONE(the_memory/xy_ram/op_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>the_memory/xy_ram/op_1/BU2/rdaddrecc(0)(the_memory/xy_ram/op_1/BU2/XST_GND:G) | NONE(the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>the_memory/xy_ram/op_2/BU2/rdaddrecc(0)(the_memory/xy_ram/op_2/BU2/XST_GND:G) | NONE(the_memory/xy_ram/op_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: 5.964ns (Maximum Frequency: 167.673MHz)<BR> Minimum input arrival time before clock: 5.340ns<BR> Maximum output required time after clock: 3.208ns<BR> Maximum combinational path delay: 1.410ns<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default period analysis for Clock 'clk'<BR> Clock period: 5.964ns (frequency: 167.673MHz)<BR> Total number of paths / destination ports: 123290 / 9692<BR>-------------------------------------------------------------------------<BR>Delay: 5.964ns (Levels of Logic = 10)<BR> Source: the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout (FF)<BR> Destination: the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (RAM)<BR> Source Clock: clk rising<BR> Destination Clock: clk rising<BR><BR> Data Path: the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout to the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FDC:C->Q 3 0.375 0.431 the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout (the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout)<BR> LUT3:I2->O 2 0.068 0.423 the_multiplier/systolic_array/Mmux_red_cin_stage<32>11 (the_multiplier/systolic_array/red_cin_stage<32>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[1].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<2>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[3].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<4>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[5].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<6>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[7].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<8>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[9].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<10>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[11].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<12>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[13].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<14>)<BR> LUT4:I3->O 1 0.068 0.399 the_multiplier/systolic_array/pipeline_stages[32].stage/Mmux_r61 (r<526>)<BR> begin scope: 'the_memory/xy_ram/op_1'<BR> begin scope: 'BU2'<BR> RAMB36E1:DIBDI0 0.707 U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> ----------------------------------------<BR> Total 5.964ns (1.694ns logic, 4.270ns route)<BR> (28.4% logic, 71.6% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 15286 / 8029<BR>-------------------------------------------------------------------------<BR>Offset: 5.340ns (Levels of Logic = 10)<BR> Source: p_sel<1> (PAD)<BR> Destination: the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (RAM)<BR> Destination Clock: clk rising<BR><BR> Data Path: p_sel<1> to the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT3:I0->O 2 0.068 0.423 the_multiplier/systolic_array/Mmux_red_cin_stage<32>11 (the_multiplier/systolic_array/red_cin_stage<32>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[1].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<2>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[3].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<4>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[5].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<6>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[7].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<8>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[9].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<10>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[11].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<12>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[13].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<14>)<BR> LUT4:I3->O 1 0.068 0.399 the_multiplier/systolic_array/pipeline_stages[32].stage/Mmux_r61 (r<526>)<BR> begin scope: 'the_memory/xy_ram/op_1'<BR> begin scope: 'BU2'<BR> RAMB36E1:DIBDI0 0.707 U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> ----------------------------------------<BR> Total 5.340ns (1.501ns logic, 3.839ns route)<BR> (28.1% logic, 71.9% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 167 / 37<BR>-------------------------------------------------------------------------<BR>Offset: 3.208ns (Levels of Logic = 5)<BR> Source: the_exponent_fifo/FIFO18E1_inst (UNKNOWN)<BR> Destination: ready (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: the_exponent_fifo/FIFO18E1_inst to ready<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FIFO18E1:RDCLK->DO22 1 0.742 0.638 the_exponent_fifo/FIFO18E1_inst (fifo_dout<22>)<BR> LUT6:I2->O 1 0.068 0.000 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51)<BR> MUXF7:I1->O 1 0.248 0.000 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7)<BR> MUXF8:I0->O 6 0.175 0.614 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_2_f8 (the_control_unit/autorun_control_logic/e1_bit_i)<BR> LUT6:I3->O 2 0.068 0.587 the_control_unit/autorun_control_logic/done_i (the_control_unit/auto_done)<BR> LUT3:I0->O 0 0.068 0.000 the_control_unit/done1 (ready)<BR> ----------------------------------------<BR> Total 3.208ns (1.369ns logic, 1.839ns route)<BR> (42.7% logic, 57.3% route)<BR><BR>=========================================================================<BR>Timing constraint: Default path analysis<BR> Total number of paths / destination ports: 70 / 35<BR>-------------------------------------------------------------------------<BR>Delay: 1.410ns (Levels of Logic = 3)<BR> Source: exp_m (PAD)<BR> Destination: ready (PAD)<BR><BR> Data Path: exp_m to ready<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT3:I0->O 4 0.068 0.437 the_control_unit/start_auto1 (the_control_unit/start_auto)<BR> LUT6:I5->O 2 0.068 0.587 the_control_unit/autorun_control_logic/done_i (the_control_unit/auto_done)<BR> LUT3:I0->O 0 0.068 0.000 the_control_unit/done1 (ready)<BR> ----------------------------------------<BR> Total 1.410ns (0.386ns logic, 1.024ns route)<BR> (27.4% logic, 72.6% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>Clock to Setup on destination clock clk<BR>---------------+---------+---------+---------+---------+<BR> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<BR>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<BR>---------------+---------+---------+---------+---------+<BR>clk | 5.964| | | |<BR>---------------+---------+---------+---------+---------+<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 169.00 secs<BR>Total CPU time to Xst completion: 169.37 secs<BR> <BR>--> <BR><BR>Total memory usage is 382080 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 8 ( 0 filtered)<BR>Number of infos : 7 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML> |
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<TD colSpan=4 align=center><B>mod_sim_exp_core Project Status (02/26/2013 |
- 14:55:40)</B></TD></TR> |
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<TD bgColor=#ffff99><B>Project File:</B></TD> |
<TD>mod_exp_core.xise</TD> |
<TD bgColor=#ffff99><B>Parser Errors:</B></TD> |
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<TD bgColor=#ffff99><B>Module Name:</B></TD> |
<TD>mod_sim_exp_core</TD> |
<TD bgColor=#ffff99><B>Implementation State:</B></TD> |
<TD>Synthesized</TD></TR> |
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<TD bgColor=#ffff99><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
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<UL> |
<LI><B>Errors:</B></LI></UL></TD> |
<TD>No Errors</TD></TR> |
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<TD bgColor=#ffff99><B>Product Version:</B></TD> |
<TD>ISE 12.4</TD> |
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<UL> |
<LI><B>Warnings:</B></LI></UL></TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/*.xmsgs?&DataKey=Warning">8 |
Warnings (0 new)</A></TD></TR> |
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<TD bgColor=#ffff99><B>Design Goal:</B></DIF></TD> |
<TD>Balanced</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Routing Results:</B></LI></UL></TD> |
<TD> </TD></TR> |
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<TD bgColor=#ffff99><B>Design Strategy:</B></DIF></TD> |
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HREF_DISABLED="Xilinx Default (unlocked)?&DataKey=Strategy">Xilinx |
Default (unlocked)</A></TD> |
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<LI><B>Timing Constraints:</B></LI></UL></TD> |
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<TD bgColor=#ffff99><B>Environment:</B></DIF></TD> |
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HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core_envsettings.html">System |
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<LI><B>Final Timing Score:</B></LI></UL></TD> |
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<TD><B>Report Name</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD>Platgen Log File</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Libgen Log File</TD> |
<TD> </TD> |
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<TR align=left> |
<TD>Simgen Log File</TD> |
<TD> </TD> |
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<TD>BitInit Log File</TD> |
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<TD>System Log File</TD> |
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<TD colSpan=4 align=center><B>Device Utilization Summary (estimated |
values)</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></A></TD></TR> |
<TR align=center bgColor=#ffff99> |
<TD align=left><B>Logic Utilization</B></TD> |
<TD><B>Used</B></TD> |
<TD><B>Available</B></TD> |
<TD colSpan=2><B>Utilization</B></TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice Registers</TD> |
<TD align=right>3700</TD> |
<TD align=right>301440</TD> |
<TD colSpan=2 align=right>1%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice LUTs</TD> |
<TD align=right>9954</TD> |
<TD align=right>150720</TD> |
<TD colSpan=2 align=right>6%</TD></TR> |
<TR align=right> |
<TD align=left>Number of fully used LUT-FF pairs</TD> |
<TD align=right>3559</TD> |
<TD align=right>10095</TD> |
<TD colSpan=2 align=right>35%</TD></TR> |
<TR align=right> |
<TD align=left>Number of bonded IOBs</TD> |
<TD align=right>0</TD> |
<TD align=right>600</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Block RAM/FIFO</TD> |
<TD align=right>73</TD> |
<TD align=right>416</TD> |
<TD colSpan=2 align=right>17%</TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=6 align=center><B>Detailed Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core.syr">Synthesis |
Report</A></TD> |
<TD>Current</TD> |
<TD>di 26. feb 14:55:39 2013</TD> |
<TD align=left>0</TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Warning">8 |
Warnings (0 new)</A></TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Info">10 |
Infos (0 new)</A></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core.bld">Translation |
Report</A></TD> |
<TD>Out of Date</TD> |
<TD>ma 25. feb 23:02:44 2013</TD> |
<TD align=left>0</TD> |
<TD align=left>0</TD> |
<TD colSpan=2 align=left>0</TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core_map.mrp">Map |
Report</A></TD> |
<TD>Out of Date</TD> |
<TD>ma 25. feb 23:06:51 2013</TD> |
<TD align=left>0</TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/map.xmsgs?&DataKey=Warning">1 |
Warning (1 new)</A></TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/map.xmsgs?&DataKey=Info">6 |
Infos (0 new)</A></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core.par">Place and |
Route Report</A></TD> |
<TD>Out of Date</TD> |
<TD>ma 25. feb 23:09:42 2013</TD> |
<TD align=left>0</TD> |
<TD align=left>0</TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/par.xmsgs?&DataKey=Info">4 |
Infos (0 new)</A></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core.twr">Post-PAR |
Static Timing Report</A></TD> |
<TD>Out of Date</TD> |
<TD>ma 25. feb 23:10:14 2013</TD> |
<TD align=left>0</TD> |
<TD align=left>0</TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/trce.xmsgs?&DataKey=Info">3 |
Infos (0 new)</A></TD></TR> |
<TR align=left> |
<TD>Bitgen Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=3 align=center><B>Secondary Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD colSpan=2><B>Generated</B></TD></TR></TBODY></TABLE><BR> |
<CENTER><B>Date Generated:</B> 02/26/2013 - 14:55:40</CENTER></BODY></HTML> |
/mod_sim_exp_core/ver011_msec_genRAM_syn.html
0,0 → 1,5
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<BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>di 26. feb 14:57:46 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.12 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.12 secs<BR> <BR>--> Reading design: mod_sim_exp_core.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "mod_sim_exp_core.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "mod_sim_exp_core"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : mod_sim_exp_core<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Auto<BR>Use Synchronous Set : Auto<BR>Use Synchronous Reset : Auto<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"../../SVN/mod_sim_exp/rtl/vhdl/core" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<BR>Parsing package <STD_FUNCTIONS>.<BR>Parsing package body <STD_FUNCTIONS>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp<BR>Parsing package <MOD_SIM_EXP_PKG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B_MUX>.<BR>Parsing architecture <BEHAVIORAL> of entity <CELL_1B_MUX>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B_ADDER>.<BR>Parsing architecture <BEHAVIORAL> of entity <CELL_1B_ADDER>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd" into library mod_sim_exp<BR>Parsing entity <D_FLIP_FLOP>.<BR>Parsing architecture <BEHAVORIAL> of entity <D_FLIP_FLOP>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B>.<BR>Parsing architecture <STRUCTURAL> of entity <CELL_1B>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd" into library mod_sim_exp<BR>Parsing entity <STANDARD_CELL_BLOCK>.<BR>Parsing architecture <STRUCTURAL> of entity <STANDARD_CELL_BLOCK>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_n.vhd" into library mod_sim_exp<BR>Parsing entity <REGISTER_N>.<BR>Parsing architecture <BEHAVORIAL> of entity <REGISTER_N>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_1b.vhd" into library mod_sim_exp<BR>Parsing entity <REGISTER_1B>.<BR>Parsing architecture <BEHAVORIAL> of entity <REGISTER_1B>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/adder_block.vhd" into library mod_sim_exp<BR>Parsing entity <ADDER_BLOCK>.<BR>Parsing architecture <STRUCTURAL> of entity <ADDER_BLOCK>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <TDPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <TDPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<BR>Parsing entity <DPRAM_GENERIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <DPRAM_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_STAGE>.<BR>Parsing architecture <STRUCTURAL> of entity <SYS_STAGE>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_LAST_CELL_LOGIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <SYS_LAST_CELL_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_FIRST_CELL_LOGIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <SYS_FIRST_CELL_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd" into library mod_sim_exp<BR>Parsing entity <COUNTER_SYNC>.<BR>Parsing architecture <BEHAVIORAL> of entity <COUNTER_SYNC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd" into library mod_sim_exp<BR>Parsing entity <X_SHIFT_REG>.<BR>Parsing architecture <BEHAVIORAL> of entity <X_SHIFT_REG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_PIPELINE>.<BR>Parsing architecture <STRUCTURAL> of entity <SYS_PIPELINE>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd" into library mod_sim_exp<BR>Parsing entity <STEPPING_LOGIC>.<BR>Parsing architecture <BEHAVIORAL> of entity <STEPPING_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd" into library mod_sim_exp<BR>Parsing entity <AUTORUN_CNTRL>.<BR>Parsing architecture <BEHAVIORAL> of entity <AUTORUN_CNTRL>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem_gen.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_MEM_GEN>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_MEM_GEN>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd" into library mod_sim_exp<BR>Parsing entity <MONT_MULTIPLIER>.<BR>Parsing architecture <STRUCTURAL> of entity <MONT_MULTIPLIER>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd" into library mod_sim_exp<BR>Parsing entity <MONT_CTRL>.<BR>Parsing architecture <BEHAVIORAL> of entity <MONT_CTRL>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/fifo_generic.vhd" into library mod_sim_exp<BR>Parsing entity <FIFO_GENERIC>.<BR>Parsing architecture <ARCH> of entity <FIFO_GENERIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" into library mod_sim_exp<BR>Parsing entity <MOD_SIM_EXP_CORE>.<BR>Parsing architecture <STRUCTURAL> of entity <MOD_SIM_EXP_CORE>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <MOD_SIM_EXP_CORE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <MONT_MULTIPLIER> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <D_FLIP_FLOP> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <X_SHIFT_REG> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <STEPPING_LOGIC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_PIPELINE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_STAGE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <ADDER_BLOCK> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B_ADDER> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <STANDARD_CELL_BLOCK> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B> (architecture <STRUCTURAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B_MUX> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <REGISTER_N> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <REGISTER_1B> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_FIRST_CELL_LOGIC> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_LAST_CELL_LOGIC> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <OPERAND_MEM_GEN> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <OPERAND_RAM_GEN> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <TDPRAM_GENERIC> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <MODULUS_RAM_GEN> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <DPRAM_GENERIC> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <FIFO_GENERIC> (architecture <ARCH>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <DPRAM_GENERIC> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <MONT_CTRL> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <AUTORUN_CNTRL> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <MOD_SIM_EXP_CORE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd".<BR> C_NR_BITS_TOTAL = 1536<BR> C_NR_STAGES_TOTAL = 96<BR> C_NR_STAGES_LOW = 32<BR> C_SPLIT_PIPELINE = true<BR> C_NR_OP = 4<BR> C_NR_M = 2<BR> C_FIFO_DEPTH = 32<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" line 167: Output port <NOPOP> of the instance <THE_EXPONENT_FIFO> is unconnected or connected to loadless signal.<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <MOD_SIM_EXP_CORE> synthesized.<BR><BR>Synthesizing Unit <MONT_MULTIPLIER>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> split = true<BR> Found 4x18-bit Read Only RAM for signal <_n0015><BR> Summary:<BR> inferred 1 RAM(s).<BR>Unit <MONT_MULTIPLIER> synthesized.<BR><BR>Synthesizing Unit <D_FLIP_FLOP>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd".<BR> Found 1-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 D-type flip-flop(s).<BR>Unit <D_FLIP_FLOP> synthesized.<BR><BR>Synthesizing Unit <X_SHIFT_REG>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> Found 1536-bit register for signal <X_REG>.<BR> Summary:<BR> inferred 1536 D-type flip-flop(s).<BR> inferred 1536 Multiplexer(s).<BR>Unit <X_SHIFT_REG> synthesized.<BR><BR>Synthesizing Unit <STEPPING_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd".<BR> n = 1536<BR> t = 96<BR> Summary:<BR> no macro.<BR>Unit <STEPPING_LOGIC> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_1>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 96<BR> Found 7-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 7-bit adder for signal <COUNT_PROC.STEPS_COUNTER[6]_GND_12_O_ADD_2_OUT> created at line 83.<BR> Found 32-bit subtractor for signal <RESET_VALUE[31]_GND_12_O_SUB_1_OUT<31:0>> created at line 79.<BR> Found 32-bit comparator equal for signal <RESET_VALUE[31]_GND_12_O_EQUAL_2_O> created at line 79<BR> Summary:<BR> inferred 2 Adder/Subtractor(s).<BR> inferred 8 D-type flip-flop(s).<BR> inferred 1 Comparator(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_1> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_2>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 1536<BR> Found 11-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 11-bit adder for signal <COUNT_PROC.STEPS_COUNTER[10]_GND_38_O_ADD_2_OUT> created at line 83.<BR> Found 32-bit subtractor for signal <RESET_VALUE[31]_GND_38_O_SUB_1_OUT<31:0>> created at line 79.<BR> Found 32-bit comparator equal for signal <RESET_VALUE[31]_GND_38_O_EQUAL_2_O> created at line 79<BR> Summary:<BR> inferred 2 Adder/Subtractor(s).<BR> inferred 12 D-type flip-flop(s).<BR> inferred 1 Comparator(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_2> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_3>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 2<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 1-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit adder for signal <COUNT_PROC.STEPS_COUNTER[0]_PWR_15_O_ADD_2_OUT<0>> created at line 83.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 2 D-type flip-flop(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_3> synthesized.<BR><BR>Synthesizing Unit <SYS_PIPELINE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> split = true<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <MY_COUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <XOUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <QOUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR> Found 1-bit 3-to-1 multiplexer for signal <START_STAGE<32>> created at line 270.<BR> Found 1-bit 4-to-1 multiplexer for signal <R_SEL_L> created at line 304.<BR> Summary:<BR> inferred 11 Multiplexer(s).<BR>Unit <SYS_PIPELINE> synthesized.<BR><BR>Synthesizing Unit <SYS_STAGE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd".<BR> width = 16<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <SYS_STAGE> synthesized.<BR><BR>Synthesizing Unit <ADDER_BLOCK>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/adder_block.vhd".<BR> width = 16<BR> Summary:<BR> no macro.<BR>Unit <ADDER_BLOCK> synthesized.<BR><BR>Synthesizing Unit <CELL_1B_ADDER>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd".<BR> Summary:<BR>Unit <CELL_1B_ADDER> synthesized.<BR><BR>Synthesizing Unit <STANDARD_CELL_BLOCK>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd".<BR> width = 16<BR> Summary:<BR> no macro.<BR>Unit <STANDARD_CELL_BLOCK> synthesized.<BR><BR>Synthesizing Unit <CELL_1B>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd".<BR> Summary:<BR> no macro.<BR>Unit <CELL_1B> synthesized.<BR><BR>Synthesizing Unit <CELL_1B_MUX>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd".<BR> Found 1-bit 4-to-1 multiplexer for signal <RESULT> created at line 72.<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <CELL_1B_MUX> synthesized.<BR><BR>Synthesizing Unit <REGISTER_N>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_n.vhd".<BR> width = 16<BR> Found 16-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 16 D-type flip-flop(s).<BR>Unit <REGISTER_N> synthesized.<BR><BR>Synthesizing Unit <REGISTER_1B>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_1b.vhd".<BR> Found 1-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 D-type flip-flop(s).<BR>Unit <REGISTER_1B> synthesized.<BR><BR>Synthesizing Unit <SYS_FIRST_CELL_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd".<BR> Summary:<BR>Unit <SYS_FIRST_CELL_LOGIC> synthesized.<BR><BR>Synthesizing Unit <SYS_LAST_CELL_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd".<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" line 86: Output port <R> of the instance <REDUCTION_ADDER> is unconnected or connected to loadless signal.<BR> Summary:<BR> no macro.<BR>Unit <SYS_LAST_CELL_LOGIC> synthesized.<BR><BR>Synthesizing Unit <OPERAND_MEM_GEN>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem_gen.vhd".<BR> width = 1536<BR> nr_op = 4<BR> nr_m = 2<BR> Summary:<BR> inferred 2 Multiplexer(s).<BR>Unit <OPERAND_MEM_GEN> synthesized.<BR><BR>Synthesizing Unit <OPERAND_RAM_GEN>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd".<BR> width = 1536<BR> depth = 4<BR> Found 32-bit 48-to-1 multiplexer for signal <ADDRB[5]_X_27_O_WIDE_MUX_59_OUT> created at line 174.<BR> Found 6-bit comparator greater for signal <ADDRB[5]_PWR_30_O_LESSTHAN_59_O> created at line 174<BR> Summary:<BR> inferred 1 Comparator(s).<BR> inferred 51 Multiplexer(s).<BR>Unit <OPERAND_RAM_GEN> synthesized.<BR><BR>Synthesizing Unit <TDPRAM_GENERIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd".<BR> depth = 4<BR> Set property "ram_style = block" for signal <RAM>.<BR> Found 4x32-bit dual-port RAM <MRAM_RAM> for signal <RAM>.<BR> Found 32-bit register for signal <DOUTB>.<BR> Found 32-bit register for signal <DOUTA>.<BR> Summary:<BR> inferred 1 RAM(s).<BR> inferred 64 D-type flip-flop(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <TDPRAM_GENERIC> synthesized.<BR><BR>Synthesizing Unit <MODULUS_RAM_GEN>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd".<BR> width = 1536<BR> depth = 2<BR> Summary:<BR> inferred 48 Multiplexer(s).<BR>Unit <MODULUS_RAM_GEN> synthesized.<BR><BR>Synthesizing Unit <DPRAM_GENERIC_1>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd".<BR> depth = 2<BR> Set property "ram_style = block" for signal <RAM>.<BR> Found 2x32-bit dual-port RAM <MRAM_RAM> for signal <RAM>.<BR> Found 32-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 RAM(s).<BR> inferred 32 D-type flip-flop(s).<BR>Unit <DPRAM_GENERIC_1> synthesized.<BR><BR>Synthesizing Unit <FIFO_GENERIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_generic.vhd".<BR> depth = 32<BR> Found 6-bit register for signal <RD_ADDR>.<BR> Found 1-bit register for signal <PUSH_I_D>.<BR> Found 1-bit register for signal <NOPOP>.<BR> Found 1-bit register for signal <NOPUSH>.<BR> Found 6-bit register for signal <WR_ADDR>.<BR> Found 6-bit adder for signal <WR_ADDR[5]_GND_109_O_ADD_0_OUT> created at line 95.<BR> Found 6-bit adder for signal <RD_ADDR[5]_GND_109_O_ADD_10_OUT> created at line 120.<BR> Found 6-bit comparator equal for signal <WR_ADDR[5]_RD_ADDR[5]_EQUAL_2_O> created at line 95<BR> Found 6-bit comparator equal for signal <EMPTY_I> created at line 99<BR> Summary:<BR> inferred 2 Adder/Subtractor(s).<BR> inferred 15 D-type flip-flop(s).<BR> inferred 2 Comparator(s).<BR>Unit <FIFO_GENERIC> synthesized.<BR><BR>Synthesizing Unit <DPRAM_GENERIC_2>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd".<BR> depth = 33<BR> Set property "ram_style = block" for signal <RAM>.<BR>WARNING:Xst:3035 - Index value(s) does not match array range for signal <RAM>, simulation mismatch.<BR> Found 33x32-bit dual-port RAM <MRAM_RAM> for signal <RAM>.<BR> Found 32-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 RAM(s).<BR> inferred 32 D-type flip-flop(s).<BR>Unit <DPRAM_GENERIC_2> synthesized.<BR><BR>Synthesizing Unit <MONT_CTRL>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd".<BR> Found 3-bit register for signal <START_UP_COUNTER>.<BR> Found 1-bit register for signal <CALC_TIME_I>.<BR> Found 1-bit register for signal <START_D>.<BR> Found 3-bit adder for signal <START_UP_COUNTER[2]_GND_111_O_ADD_0_OUT> created at line 128.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 5 D-type flip-flop(s).<BR> inferred 5 Multiplexer(s).<BR>Unit <MONT_CTRL> synthesized.<BR><BR>Synthesizing Unit <AUTORUN_CNTRL>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd".<BR> Found 4-bit register for signal <BIT_COUNTER_I>.<BR> Found 1-bit register for signal <RUNNING_I>.<BR> Found 1-bit register for signal <START_MULTIPLIER_DEL_I>.<BR> Found 1-bit register for signal <START_CYCLE_DEL_I>.<BR> Found 1-bit register for signal <MULT_DONE_DEL_I>.<BR> Found 1-bit register for signal <CYCLE_COUNTER_I>.<BR> Found 4-bit subtractor for signal <GND_112_O_GND_112_O_SUB_4_OUT<3:0>> created at line 113.<BR> Found 1-bit 16-to-1 multiplexer for signal <E0_BIT_I> created at line 122.<BR> Found 1-bit 16-to-1 multiplexer for signal <E1_BIT_I> created at line 123.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 9 D-type flip-flop(s).<BR> inferred 7 Multiplexer(s).<BR>Unit <AUTORUN_CNTRL> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 98<BR> 2x32-bit dual-port RAM : 48<BR> 33x32-bit dual-port RAM : 1<BR> 4x18-bit single-port Read Only RAM : 1<BR> 4x32-bit dual-port RAM : 48<BR># Adders/Subtractors : 9<BR> 1-bit adder : 1<BR> 11-bit adder : 1<BR> 3-bit adder : 1<BR> 32-bit subtractor : 2<BR> 4-bit subtractor : 1<BR> 6-bit adder : 2<BR> 7-bit adder : 1<BR># Registers : 843<BR> 1-bit register : 595<BR> 11-bit register : 1<BR> 1536-bit register : 1<BR> 16-bit register : 96<BR> 3-bit register : 1<BR> 32-bit register : 145<BR> 4-bit register : 1<BR> 6-bit register : 2<BR> 7-bit register : 1<BR># Comparators : 5<BR> 32-bit comparator equal : 2<BR> 6-bit comparator equal : 2<BR> 6-bit comparator greater : 1<BR># Multiplexers : 3397<BR> 1-bit 16-to-1 multiplexer : 2<BR> 1-bit 2-to-1 multiplexer : 1649<BR> 1-bit 3-to-1 multiplexer : 1<BR> 1-bit 4-to-1 multiplexer : 1539<BR> 11-bit 2-to-1 multiplexer : 1<BR> 16-bit 2-to-1 multiplexer : 96<BR> 2-bit 2-to-1 multiplexer : 6<BR> 3-bit 2-to-1 multiplexer : 2<BR> 32-bit 2-to-1 multiplexer : 97<BR> 32-bit 48-to-1 multiplexer : 1<BR> 4-bit 2-to-1 multiplexer : 2<BR> 7-bit 2-to-1 multiplexer : 1<BR># Xors : 9224<BR> 1-bit xor2 : 9224<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR>WARNING:Xst:1290 - Hierarchical block <CARRY_REG> is unconnected in block <MY_ADDER>.<BR> It will be removed from the design.<BR>WARNING:Xst:1290 - Hierarchical block <XOUT_REG> is unconnected in block <PIPELINE_STAGES[95].STAGE>.<BR> It will be removed from the design.<BR>WARNING:Xst:1290 - Hierarchical block <QOUT_REG> is unconnected in block <PIPELINE_STAGES[95].STAGE>.<BR> It will be removed from the design.<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_1>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER>: 1 register on signal <COUNT_PROC.STEPS_COUNTER>.<BR>Unit <COUNTER_SYNC_1> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_2>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER>: 1 register on signal <COUNT_PROC.STEPS_COUNTER>.<BR>Unit <COUNTER_SYNC_2> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_3>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER_0>: 1 register on signal <COUNT_PROC.STEPS_COUNTER_0>.<BR>Unit <COUNTER_SYNC_3> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <DPRAM_GENERIC_1>.<BR>INFO:Xst:3040 - The RAM <MRAM_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOUT><BR> -----------------------------------------------------------------------<BR> | ram_type | Block | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 2-word x 32-bit | |<BR> | mode | read-first | |<BR> | clkA | connected to signal <CLK> | rise |<BR> | weA | connected to signal <WE> | high |<BR> | addrA | connected to signal <WADDR> | |<BR> | diA | connected to signal <DIN> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR> | Port B |<BR> | aspect ratio | 2-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkB | connected to signal <CLK> | rise |<BR> | addrB | connected to signal <RADDR> | |<BR> | doB | connected to signal <DOUT> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR>Unit <DPRAM_GENERIC_1> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <DPRAM_GENERIC_2>.<BR>INFO:Xst:3040 - The RAM <MRAM_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOUT><BR> -----------------------------------------------------------------------<BR> | ram_type | Block | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 33-word x 32-bit | |<BR> | mode | read-first | |<BR> | clkA | connected to signal <CLK> | rise |<BR> | weA | connected to signal <WE> | high |<BR> | addrA | connected to signal <WADDR> | |<BR> | diA | connected to signal <DIN> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR> | Port B |<BR> | aspect ratio | 33-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkB | connected to signal <CLK> | rise |<BR> | addrB | connected to signal <RADDR> | |<BR> | doB | connected to signal <DOUT> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR>Unit <DPRAM_GENERIC_2> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <FIFO_GENERIC>.<BR>The following registers are absorbed into counter <RD_ADDR>: 1 register on signal <RD_ADDR>.<BR>The following registers are absorbed into counter <WR_ADDR>: 1 register on signal <WR_ADDR>.<BR>Unit <FIFO_GENERIC> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <MONT_MULTIPLIER>.<BR>INFO:Xst:3031 - HDL ADVISOR - The RAM <MRAM__N0015> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.<BR> -----------------------------------------------------------------------<BR> | ram_type | Distributed | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 4-word x 18-bit | |<BR> | weA | connected to signal <GND> | high |<BR> | addrA | connected to signal <P_SEL> | |<BR> | diA | connected to signal <GND> | |<BR> | doA | connected to signal <T_SEL> | |<BR> -----------------------------------------------------------------------<BR>Unit <MONT_MULTIPLIER> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <TDPRAM_GENERIC>.<BR>INFO:Xst:3040 - The RAM <MRAM_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOUTA> <DOUTB><BR> -----------------------------------------------------------------------<BR> | ram_type | Block | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 4-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkA | connected to signal <CLKA> | rise |<BR> | weA | connected to signal <WEA> | high |<BR> | addrA | connected to signal <ADDRA> | |<BR> | diA | connected to signal <DINA> | |<BR> | doA | connected to signal <DOUTA> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR> | Port B |<BR> | aspect ratio | 4-word x 32-bit | |<BR> | mode | write-first | |<BR> | clkB | connected to signal <CLKB> | rise |<BR> | weB | connected to signal <WEB> | high |<BR> | addrB | connected to signal <ADDRB> | |<BR> | diB | connected to signal <DINB> | |<BR> | doB | connected to signal <DOUTB> | |<BR> -----------------------------------------------------------------------<BR> | optimization | area | |<BR> -----------------------------------------------------------------------<BR>Unit <TDPRAM_GENERIC> synthesized (advanced).<BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 98<BR> 2x32-bit dual-port block RAM : 48<BR> 33x32-bit dual-port block RAM : 1<BR> 4x18-bit single-port distributed Read Only RAM : 1<BR> 4x32-bit dual-port block RAM : 48<BR># Adders/Subtractors : 5<BR> 3-bit adder : 1<BR> 32-bit subtractor : 2<BR> 4-bit subtractor : 1<BR> 6-bit adder : 1<BR># Counters : 5<BR> 1-bit up counter : 1<BR> 11-bit up counter : 1<BR> 6-bit up counter : 2<BR> 7-bit up counter : 1<BR># Registers : 3673<BR> Flip-Flops : 3673<BR># Comparators : 5<BR> 32-bit comparator equal : 2<BR> 6-bit comparator equal : 2<BR> 6-bit comparator greater : 1<BR># Multiplexers : 3297<BR> 1-bit 16-to-1 multiplexer : 2<BR> 1-bit 2-to-1 multiplexer : 1648<BR> 1-bit 3-to-1 multiplexer : 1<BR> 1-bit 4-to-1 multiplexer : 1539<BR> 16-bit 2-to-1 multiplexer : 96<BR> 2-bit 2-to-1 multiplexer : 5<BR> 3-bit 2-to-1 multiplexer : 2<BR> 32-bit 2-to-1 multiplexer : 1<BR> 32-bit 48-to-1 multiplexer : 1<BR> 4-bit 2-to-1 multiplexer : 2<BR># Xors : 9224<BR> 1-bit xor2 : 9224<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <MOD_SIM_EXP_CORE> ...<BR><BR>Optimizing unit <OPERAND_RAM_GEN> ...<BR><BR>Optimizing unit <MODULUS_RAM_GEN> ...<BR><BR>Optimizing unit <FIFO_GENERIC> ...<BR><BR>Optimizing unit <MONT_CTRL> ...<BR><BR>Optimizing unit <AUTORUN_CNTRL> ...<BR><BR>Optimizing unit <X_SHIFT_REG> ...<BR><BR>Optimizing unit <SYS_PIPELINE> ...<BR><BR>Optimizing unit <SYS_STAGE> ...<BR><BR>Optimizing unit <ADDER_BLOCK> ...<BR><BR>Optimizing unit <STANDARD_CELL_BLOCK> ...<BR><BR>Optimizing unit <REGISTER_N> ...<BR><BR>Optimizing unit <STEPPING_LOGIC> ...<BR>WARNING:Xst:2677 - Node <THE_EXPONENT_FIFO nopop> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout xout_reg pipeline_stages[95].stage systolic_array> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout pipeline_stages[95].stage systolic_array qout_reg> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout pipeline_stages[95].stage systolic_array carry_reg my_adder> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block mod_sim_exp_core, actual ratio is 7.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Macro Statistics<BR># Registers : 3700<BR> Flip-Flops : 3700<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : mod_sim_exp_core.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 10810<BR># GND : 1<BR># INV : 4<BR># LUT2 : 14<BR># LUT3 : 800<BR># LUT4 : 832<BR># LUT5 : 3911<BR># LUT6 : 4393<BR># MUXCY : 10<BR># MUXF7 : 829<BR># MUXF8 : 2<BR># VCC : 1<BR># XORCY : 13<BR># FlipFlops/Latches : 3700<BR># FD : 5<BR># FDC : 1832<BR># FDCE : 1845<BR># FDP : 1<BR># FDPE : 4<BR># FDR : 3<BR># FDRE : 10<BR># RAMS : 97<BR># RAMB18E1 : 49<BR># RAMB36E1 : 48<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice Registers: 3700 out of 301440 1% <BR> Number of Slice LUTs: 9954 out of 150720 6% <BR> Number used as Logic: 9954 out of 150720 6% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 10095<BR> Number with an unused Flip Flop: 6395 out of 10095 63% <BR> Number with an unused LUT: 141 out of 10095 1% <BR> Number of fully used LUT-FF pairs: 3559 out of 10095 35% <BR> Number of unique control sets: 113<BR><BR>IO Utilization: <BR> Number of IOs: 125<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 73 out of 416 17% <BR> Number using Block RAM only: 73<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+----------------------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+----------------------------------------+-------+<BR>clk | NONE(the_multiplier/delay_1_cycle/dout)| 3797 |<BR>-----------------------------------+----------------------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>No asynchronous control signals found in this design<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: 7.831ns (Maximum Frequency: 127.698MHz)<BR> Minimum input arrival time before clock: 5.973ns<BR> Maximum output required time after clock: 4.539ns<BR> Maximum combinational path delay: 2.140ns<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default period analysis for Clock 'clk'<BR> Clock period: 7.831ns (frequency: 127.698MHz)<BR> Total number of paths / destination ports: 412126 / 9739<BR>-------------------------------------------------------------------------<BR>Delay: 7.831ns (Levels of Logic = 11)<BR> Source: the_memory/xy_ram/ramblocks[16].ramblock/Mram_RAM (RAM)<BR> Destination: the_multiplier/systolic_array/pipeline_stages[32].stage/cout_reg/dout (FF)<BR> Source Clock: clk rising<BR> Destination Clock: clk rising<BR><BR> Data Path: the_memory/xy_ram/ramblocks[16].ramblock/Mram_RAM to the_multiplier/systolic_array/pipeline_stages[32].stage/cout_reg/dout<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> RAMB36E1:CLKARDCLK->DOADO0 6 2.073 0.450 the_memory/xy_ram/ramblocks[16].ramblock/Mram_RAM (xy<512>)<BR> LUT6:I5->O 25 0.068 0.929 the_multiplier/systolic_array/Mmux_qin_stage<32>11 (the_multiplier/systolic_array/qin_stage<32>)<BR> LUT6:I0->O 1 0.068 0.000 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result121 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result12)<BR> MUXF7:I1->O 2 0.248 0.423 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result12_f7 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result12_f7)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<2>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[3].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<4>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[5].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<6>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[7].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<8>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[9].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<10>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[11].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<12>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[13].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<14>)<BR> LUT5:I4->O 1 0.068 0.000 the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[15].cells/cell_adder/Mxor_r_xo<0>1 (the_multiplier/systolic_array/pipeline_stages[32].stage/cell_result<15>)<BR> FDCE:D 0.011 the_multiplier/systolic_array/pipeline_stages[32].stage/result_reg/dout_15<BR> ----------------------------------------<BR> Total 7.831ns (3.012ns logic, 4.819ns route)<BR> (38.5% logic, 61.5% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 19167 / 10478<BR>-------------------------------------------------------------------------<BR>Offset: 5.973ns (Levels of Logic = 12)<BR> Source: p_sel<0> (PAD)<BR> Destination: the_multiplier/systolic_array/pipeline_stages[0].stage/cout_reg/dout (FF)<BR> Destination Clock: clk rising<BR><BR> Data Path: p_sel<0> to the_multiplier/systolic_array/pipeline_stages[0].stage/cout_reg/dout<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT4:I1->O 29 0.068 0.927 the_multiplier/x_selection/Mmux_xi11 (the_multiplier/xi)<BR> LUT6:I1->O 1 0.068 0.000 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result111 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result11)<BR> MUXF7:I1->O 1 0.248 0.417 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result11_f7 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result1)<BR> LUT5:I4->O 2 0.068 0.423 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result12 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/mux2adder)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<2>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[3].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<4>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[5].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<6>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[7].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<8>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[9].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<10>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[11].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<12>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[13].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<14>)<BR> LUT5:I4->O 1 0.068 0.000 the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[15].cells/cell_adder/Mxor_r_xo<0>1 (the_multiplier/systolic_array/pipeline_stages[0].stage/cell_result<15>)<BR> FDCE:D 0.011 the_multiplier/systolic_array/pipeline_stages[0].stage/result_reg/dout_15<BR> ----------------------------------------<BR> Total 5.973ns (1.189ns logic, 4.784ns route)<BR> (19.9% logic, 80.1% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 2675 / 37<BR>-------------------------------------------------------------------------<BR>Offset: 4.539ns (Levels of Logic = 5)<BR> Source: the_exponent_fifo/ramblock/Mram_RAM (RAM)<BR> Destination: ready (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: the_exponent_fifo/ramblock/Mram_RAM to ready<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> RAMB18E1:CLKARDCLK->DOBDO6 1 2.073 0.638 the_exponent_fifo/ramblock/Mram_RAM (fifo_dout<22>)<BR> LUT6:I2->O 1 0.068 0.000 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51)<BR> MUXF7:I1->O 1 0.248 0.000 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7)<BR> MUXF8:I0->O 6 0.175 0.614 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_2_f8 (the_control_unit/autorun_control_logic/e1_bit_i)<BR> LUT6:I3->O 2 0.068 0.587 the_control_unit/autorun_control_logic/done_i (the_control_unit/auto_done)<BR> LUT3:I0->O 0 0.068 0.000 the_control_unit/done1 (ready)<BR> ----------------------------------------<BR> Total 4.539ns (2.700ns logic, 1.839ns route)<BR> (59.5% logic, 40.5% route)<BR><BR>=========================================================================<BR>Timing constraint: Default path analysis<BR> Total number of paths / destination ports: 1829 / 34<BR>-------------------------------------------------------------------------<BR>Delay: 2.140ns (Levels of Logic = 5)<BR> Source: rw_address<1> (PAD)<BR> Destination: data_out<31> (PAD)<BR><BR> Data Path: rw_address<1> to data_out<31><BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT6:I0->O 1 0.068 0.638 the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_111 (the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_111)<BR> LUT6:I2->O 1 0.068 0.000 the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_6 (the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_6)<BR> MUXF7:I1->O 2 0.248 0.423 the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_5_f7 (the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_5_f7)<BR> LUT6:I5->O 1 0.068 0.000 the_memory/xy_ram/Mmux_doutB110 (the_memory/xy_ram/Mmux_doutB1)<BR> MUXF7:I1->O 0 0.248 0.000 the_memory/xy_ram/Mmux_doutB1_f7 (data_out<0>)<BR> ----------------------------------------<BR> Total 2.140ns (1.079ns logic, 1.061ns route)<BR> (50.4% logic, 49.6% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>Clock to Setup on destination clock clk<BR>---------------+---------+---------+---------+---------+<BR> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<BR>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<BR>---------------+---------+---------+---------+---------+<BR>clk | 7.831| | | |<BR>---------------+---------+---------+---------+---------+<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 193.00 secs<BR>Total CPU time to Xst completion: 192.90 secs<BR> <BR>--> <BR><BR>Total memory usage is 374848 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 8 ( 0 filtered)<BR>Number of infos : 10 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML> |
/mod_sim_exp_core/ver010_msec_sum.html
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<TD colSpan=4 align=center><B>mod_sim_exp_core Project Status (02/26/2013 |
- 15:19:05)</B></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Project File:</B></TD> |
<TD>mod_exp_core.xise</TD> |
<TD bgColor=#ffff99><B>Parser Errors:</B></TD> |
<TD>No Errors </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Module Name:</B></TD> |
<TD>mod_sim_exp_core</TD> |
<TD bgColor=#ffff99><B>Implementation State:</B></TD> |
<TD>Synthesized</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Errors:</B></LI></UL></TD> |
<TD>No Errors</TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Product Version:</B></TD> |
<TD>ISE 12.4</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Warnings:</B></LI></UL></TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/*.xmsgs?&DataKey=Warning">8 |
Warnings (8 new)</A></TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Goal:</B></DIF></TD> |
<TD>Balanced</TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Routing Results:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Design Strategy:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="Xilinx Default (unlocked)?&DataKey=Strategy">Xilinx |
Default (unlocked)</A></TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD></TR> |
<TR align=left> |
<TD bgColor=#ffff99><B>Environment:</B></DIF></TD> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core_envsettings.html">System |
Settings</A> </TD> |
<TD bgColor=#ffff99> |
<UL> |
<LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=5 align=center><B>XPS Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=EDKReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD>Platgen Log File</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Libgen Log File</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>Simgen Log File</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>BitInit Log File</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR> |
<TR align=left> |
<TD>System Log File</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=4 align=center><B>Device Utilization Summary (estimated |
values)</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></A></TD></TR> |
<TR align=center bgColor=#ffff99> |
<TD align=left><B>Logic Utilization</B></TD> |
<TD><B>Used</B></TD> |
<TD><B>Available</B></TD> |
<TD colSpan=2><B>Utilization</B></TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice Registers</TD> |
<TD align=right>3689</TD> |
<TD align=right>301440</TD> |
<TD colSpan=2 align=right>1%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Slice LUTs</TD> |
<TD align=right>9349</TD> |
<TD align=right>150720</TD> |
<TD colSpan=2 align=right>6%</TD></TR> |
<TR align=right> |
<TD align=left>Number of fully used LUT-FF pairs</TD> |
<TD align=right>3548</TD> |
<TD align=right>9490</TD> |
<TD colSpan=2 align=right>37%</TD></TR> |
<TR align=right> |
<TD align=left>Number of bonded IOBs</TD> |
<TD align=right>0</TD> |
<TD align=right>600</TD> |
<TD colSpan=2 align=right>0%</TD></TR> |
<TR align=right> |
<TD align=left>Number of Block RAM/FIFO</TD> |
<TD align=right>97</TD> |
<TD align=right>416</TD> |
<TD colSpan=2 align=right>23%</TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=6 align=center><B>Detailed Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD><B>Generated</B></TD> |
<TD align=left><B>Errors</B></TD> |
<TD align=left><B>Warnings</B></TD> |
<TD colSpan=2 align=left><B>Infos</B></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core.syr">Synthesis |
Report</A></TD> |
<TD>Current</TD> |
<TD>di 26. feb 15:19:03 2013</TD> |
<TD align=left>0</TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Warning">8 |
Warnings (8 new)</A></TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/xst.xmsgs?&DataKey=Info">7 |
Infos (7 new)</A></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core.bld">Translation |
Report</A></TD> |
<TD>Out of Date</TD> |
<TD>ma 25. feb 23:02:44 2013</TD> |
<TD align=left>0</TD> |
<TD align=left>0</TD> |
<TD colSpan=2 align=left>0</TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core_map.mrp">Map |
Report</A></TD> |
<TD>Out of Date</TD> |
<TD>ma 25. feb 23:06:51 2013</TD> |
<TD align=left>0</TD> |
<TD align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/map.xmsgs?&DataKey=Warning">1 |
Warning (1 new)</A></TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/map.xmsgs?&DataKey=Info">6 |
Infos (0 new)</A></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core.par">Place and |
Route Report</A></TD> |
<TD>Out of Date</TD> |
<TD>ma 25. feb 23:09:42 2013</TD> |
<TD align=left>0</TD> |
<TD align=left>0</TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/par.xmsgs?&DataKey=Info">4 |
Infos (0 new)</A></TD></TR> |
<TR align=left> |
<TD><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\mod_sim_exp_core.twr">Post-PAR |
Static Timing Report</A></TD> |
<TD>Out of Date</TD> |
<TD>ma 25. feb 23:10:14 2013</TD> |
<TD align=left>0</TD> |
<TD align=left>0</TD> |
<TD colSpan=2 align=left><A |
HREF_DISABLED="D:/Dropbox/ISE/mod_exp_core\_xmsgs/trce.xmsgs?&DataKey=Info">3 |
Infos (0 new)</A></TD></TR> |
<TR align=left> |
<TD>Bitgen Report</TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD> </TD> |
<TD colSpan=2> </TD></TR></TBODY></TABLE> <BR> |
<TABLE border=1 cellSpacing=0 cellPadding=3 width="100%"> |
<TBODY> |
<TR align=center bgColor=#99ccff> |
<TD colSpan=3 align=center><B>Secondary Reports</B></TD> |
<TD width="10%" align=right><A |
HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></A></TD></TR> |
<TR bgColor=#ffff99> |
<TD><B>Report Name</B></TD> |
<TD><B>Status</B></TD> |
<TD colSpan=2><B>Generated</B></TD></TR></TBODY></TABLE><BR> |
<CENTER><B>Date Generated:</B> 02/26/2013 - 15:19:05</CENTER></BODY></HTML> |