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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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  • This comparison shows the changes necessary to convert path 
    /mod_sim_exp/trunk/rtl
    from Rev 55 to Rev 59
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Rev 55 → Rev 59

/vhdl/ram/dpram_generic.vhd
0,0 → 1,92
----------------------------------------------------------------------
---- dpram_generic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- behovorial description of a dual port ram with one 32-bit ----
---- write port and one 32-bit read port ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.std_functions.all;
 
-- altera infers ramblocks from a depth of 9
-- xilinx infers ramblocks from a depth of 2
entity dpram_generic is
generic (
depth : integer := 2
);
port (
clk : in std_logic;
-- write port
waddr : in std_logic_vector(log2(depth)-1 downto 0);
we : in std_logic;
din : in std_logic_vector(31 downto 0);
-- read port
raddr : in std_logic_vector(log2(depth)-1 downto 0);
dout : out std_logic_vector(31 downto 0)
);
end dpram_generic;
 
architecture behavorial of dpram_generic is
-- the memory
type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
signal ram : ram_type;
-- xilinx constraint to use blockram resources
attribute ram_style : string;
attribute ram_style of ram:signal is "block";
-- altera constraint
attribute ramstyle : string;
attribute ramstyle of ram : signal is "M9K, no_rw_check";
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
ram(conv_integer(waddr)) <= din;
end if;
dout <= ram(conv_integer(raddr));
end if;
end process;
end behavorial;
 
/vhdl/ram/tdpram_generic.vhd
0,0 → 1,108
----------------------------------------------------------------------
---- dpram_generic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- behovorial description of a dual port ram with one 32-bit ----
---- write port and one 32-bit read port ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.std_functions.all;
 
-- altera infers ramblocks from a depth of 9
-- xilinx infers ramblocks from a depth of 2
entity tdpram_generic is
generic (
depth : integer := 9
);
port (
-- port A
clkA : in std_logic;
addrA : in std_logic_vector(log2(depth)-1 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(31 downto 0);
doutA : out std_logic_vector(31 downto 0);
-- port B
clkB : in std_logic;
addrB : in std_logic_vector(log2(depth)-1 downto 0);
weB : in std_logic;
dinB : in std_logic_vector(31 downto 0);
doutB : out std_logic_vector(31 downto 0)
);
end tdpram_generic;
 
architecture behavorial of tdpram_generic is
-- the memory
type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
shared variable RAM: ram_type;
-- xilinx constraint to use blockram resources
attribute ram_style : string;
attribute ram_style of RAM:variable is "block";
-- altera constraint
--attribute ramstyle : string;
--attribute ramstyle of RAM:variable is "M9K, no_rw_check";
begin
-- port A
process (clkA)
begin
if (clkA'event and clkA = '1') then
if ( weA = '1') then
RAM(conv_integer(addrA)) := dinA ;
end if;
doutA <= RAM(conv_integer(addrA));
end if;
end process;
-- port B
process (clkB)
begin
if (clkB'event and clkB = '1') then
if ( weB = '1') then
RAM(conv_integer(addrB)) := dinB ;
end if;
doutB <= RAM(conv_integer(addrB));
end if;
end process;
end behavorial;
 
/vhdl/core/std_functions.vhd
0,0 → 1,81
----------------------------------------------------------------------
---- std_functions ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- package with standard functions used in this project ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
package std_functions is
function maxV(L, R: INTEGER) return INTEGER;
function minV(L, R: INTEGER) return INTEGER;
function log2 (val: INTEGER) return natural;
end std_functions;
 
package body std_functions is
function maxV(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
 
function minV(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
 
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
end std_functions;

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