URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/sim
- from Rev 90 to Rev 94
- ↔ Reverse comparison
Rev 90 → Rev 94
/Makefile
1,7 → 1,9
#VCOM = /usr/local/bin/vcom |
VCOMOPS = -explicit -check_synthesis -2002 -quiet |
VLOGOPS = -vopt -nocovercells |
#MAKEFLAGS = --silent |
HDL_DIR = ../rtl/vhdl/ |
VER_DIR = ../rtl/verilog/ |
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## |
# hdl files |
44,7 → 46,11
$(HDL_DIR)core/sys_first_cell_logic.vhd \ |
$(HDL_DIR)core/sys_pipeline.vhd \ |
$(HDL_DIR)core/mont_multiplier.vhd \ |
$(HDL_DIR)core/pulse_cdc.vhd \ |
$(HDL_DIR)core/clk_sync.vhd \ |
|
VER_SRC =$(VER_DIR)generic_fifo_dc.v \ |
$(VER_DIR)generic_fifo_dc_gray.v |
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## |
# Testbench HDL files |
51,7 → 57,8
## |
TB_SRC_DIR = ../bench/vhdl/ |
TB_SRC = $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd \ |
$(TB_SRC_DIR)msec_axi_tb.vhd |
$(TB_SRC_DIR)msec_axi_tb.vhd \ |
$(TB_SRC_DIR)axi_tb.vhd |
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## |
# Interface HDL files |
77,6 → 84,7
#echo -- |
#echo building Modular Exponentiation Core |
#echo -- |
vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC) |
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC) |
#echo Done! |
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