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/generic_fifo_dc_aw5_summary.html
0,0 → 1,112
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:14:37)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>msec.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>generic_fifo_dc</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT>No Warnings</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
</TABLE> |
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>46</TD> |
<TD ALIGN=RIGHT>301440</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>40</TD> |
<TD ALIGN=RIGHT>150720</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>38</TD> |
<TD ALIGN=RIGHT>48</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>79%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>600</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>416</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
</TABLE> |
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:14:37 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (1 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
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<br><center><b>Date Generated:</b> 07/03/2013 - 16:14:37</center> |
</BODY></HTML> |
/generic_fifo_dc_aw5_syr.html
0,0 → 1,112
<title>Synthesis Report</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>Synthesis Report</b></p><b><center>Wed Jul 3 16:16:06 2013</center></b><br><hr><br>Release 14.4 - xst P.49d (lin64)<br>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.<br>--> <br>Parameter TMPDIR set to xst/projnav.tmp<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Parameter xsthdpdir set to xst<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Reading design: generic_fifo_dc.prj<br><br>TABLE OF CONTENTS<br> 1) Synthesis Options Summary<br> 2) HDL Parsing<br> 3) HDL Elaboration<br> 4) HDL Synthesis<br> 4.1) HDL Synthesis Report<br> 5) Advanced HDL Synthesis<br> 5.1) Advanced HDL Synthesis Report<br> 6) Low Level Synthesis<br> 7) Partition Report<br> 8) Design Summary<br> 8.1) Primitive and Black Box Usage<br> 8.2) Device utilization summary<br> 8.3) Partition Resource Summary<br> 8.4) Timing Report<br> 8.4.1) Clock Information<br> 8.4.2) Asynchronous Control Signals Information<br> 8.4.3) Timing Summary<br> 8.4.4) Timing Details<br> 8.4.5) Cross Clock Domains Report<br><br><br>=========================================================================<br>* Synthesis Options Summary *<br>=========================================================================<br>---- Source Parameters<br>Input File Name : "generic_fifo_dc.prj"<br>Ignore Synthesis Constraint File : NO<br><br>---- Target Parameters<br>Output File Name : "generic_fifo_dc"<br>Output Format : NGC<br>Target Device : xc6vlx240t-1-ff1156<br><br>---- Source Options<br>Top Module Name : generic_fifo_dc<br>Automatic FSM Extraction : YES<br>FSM Encoding Algorithm : Auto<br>Safe Implementation : No<br>FSM Style : LUT<br>RAM Extraction : Yes<br>RAM Style : Auto<br>ROM Extraction : Yes<br>Shift Register Extraction : YES<br>ROM Style : Auto<br>Resource Sharing : YES<br>Asynchronous To Synchronous : NO<br>Shift Register Minimum Size : 2<br>Use DSP Block : Auto<br>Automatic Register Balancing : No<br><br>---- Target Options<br>LUT Combining : Auto<br>Reduce Control Sets : Auto<br>Add IO Buffers : NO<br>Global Maximum Fanout : 100000<br>Add Generic Clock Buffer(BUFG) : 32<br>Register Duplication : YES<br>Optimize Instantiated Primitives : NO<br>Use Clock Enable : Auto<br>Use Synchronous Set : Auto<br>Use Synchronous Reset : Auto<br>Pack IO Registers into IOBs : Auto<br>Equivalent register Removal : YES<br><br>---- General Options<br>Optimization Goal : Area<br>Optimization Effort : 2<br>Power Reduction : NO<br>Keep Hierarchy : No<br>Netlist Hierarchy : As_Optimized<br>RTL Output : Yes<br>Global Optimization : AllClockNets<br>Read Cores : YES<br>Write Timing Constraints : NO<br>Cross Clock Analysis : NO<br>Hierarchy Separator : /<br>Bus Delimiter : <><br>Case Specifier : Maintain<br>Slice Utilization Ratio : 100<br>BRAM Utilization Ratio : 100<br>DSP48 Utilization Ratio : 100<br>Auto BRAM Packing : NO<br>Slice Utilization Ratio Delta : 5<br><br>---- Other Options<br>Cores Search Directories : {"../../syn/xilinx/src" }<br><br>=========================================================================<br><br><br>=========================================================================<br>* HDL Parsing *<br>=========================================================================<br>Analyzing Verilog file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v" into library work<br>Parsing module <generic_fifo_dc>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<br>Parsing package <std_functions>.<br>Parsing package body <std_functions>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<br>Parsing entity <dpram_generic>.<br>Parsing architecture <behavorial> of entity <dpram_generic>.<br><br>=========================================================================<br>* HDL Elaboration *<br>=========================================================================<br><br>Elaborating module <generic_fifo_dc>.<br>Going to vhdl side to elaborate module dpram_generic<br><br>Elaborating entity <dpram_generic> (architecture <behavorial>) with generics from library <mod_sim_exp>.<br>Back to verilog to continue elaboration<br><br>=========================================================================<br>* HDL Synthesis *<br>=========================================================================<br><br>Synthesizing Unit <generic_fifo_dc>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v".<br> dw = 32<br> aw = 5<br> n = 32<br> max_size = 32<br> Found 6-bit register for signal <wp>.<br> Found 6-bit register for signal <rp>.<br> Found 6-bit register for signal <wp_s>.<br> Found 6-bit register for signal <rp_s>.<br> Found 1-bit register for signal <empty>.<br> Found 1-bit register for signal <full>.<br> Found 1-bit register for signal <re_r>.<br> Found 6-bit register for signal <diff_r1>.<br> Found 1-bit register for signal <empty_n>.<br> Found 1-bit register for signal <we_r>.<br> Found 6-bit register for signal <diff_r2>.<br> Found 1-bit register for signal <full_n>.<br> Found 2-bit register for signal <level>.<br> Found 1-bit register for signal <nopop>.<br> Found 1-bit register for signal <nopush>.<br> Found 32-bit register for signal <dout>.<br> Found 6-bit subtractor for signal <diff> created at line 254.<br> Found 6-bit adder for signal <wp_pl1> created at line 217.<br> Found 6-bit adder for signal <rp_pl1> created at line 224.<br> Found 6-bit comparator equal for signal <wp_s[5]_rp[5]_equal_19_o> created at line 243<br> Found 6-bit comparator equal for signal <wp_s[5]_rp_pl1[5]_equal_20_o> created at line 243<br> Found 5-bit comparator equal for signal <wp[4]_rp_s[4]_equal_22_o> created at line 246<br> Found 1-bit comparator not equal for signal <n0022> created at line 246<br> Found 5-bit comparator equal for signal <wp_pl1[4]_rp_s[4]_equal_24_o> created at line 247<br> Found 1-bit comparator not equal for signal <n0027> created at line 247<br> Found 6-bit comparator greater for signal <diff_r1[5]_PWR_1_o_LessThan_31_o> created at line 263<br> Found 6-bit comparator greater for signal <GND_1_o_diff_r2[5]_LessThan_37_o> created at line 272<br> Summary:<br> inferred 3 Adder/Subtractor(s).<br> inferred 78 D-type flip-flop(s).<br> inferred 8 Comparator(s).<br>Unit <generic_fifo_dc> synthesized.<br><br>Synthesizing Unit <dpram_generic>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd".<br> depth = 32<br> Set property "ram_style = block" for signal <RAM>.<br> Found 32x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.<br> Found 32-bit register for signal <doutB>.<br> Summary:<br> inferred 1 RAM(s).<br> inferred 32 D-type flip-flop(s).<br>Unit <dpram_generic> synthesized.<br><br>=========================================================================<br>HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 32x32-bit dual-port RAM : 1<br># Adders/Subtractors : 3<br> 6-bit adder : 2<br> 6-bit subtractor : 1<br># Registers : 17<br> 1-bit register : 8<br> 2-bit register : 1<br> 32-bit register : 2<br> 6-bit register : 6<br># Comparators : 8<br> 1-bit comparator not equal : 2<br> 5-bit comparator equal : 2<br> 6-bit comparator equal : 2<br> 6-bit comparator greater : 2<br><br>=========================================================================<br><br>=========================================================================<br>* Advanced HDL Synthesis *<br>=========================================================================<br><br><br>Synthesizing (advanced) Unit <generic_fifo_dc>.<br>The following registers are absorbed into counter <rp>: 1 register on signal <rp>.<br>The following registers are absorbed into counter <wp>: 1 register on signal <wp>.<br>INFO:Xst:3226 - The RAM <u0/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <u0/doutB> <dout><br> -----------------------------------------------------------------------<br> | ram_type | Block | |<br> -----------------------------------------------------------------------<br> | Port A |<br> | aspect ratio | 32-word x 32-bit | |<br> | mode | write-first | |<br> | clkA | connected to signal <wr_clk> | rise |<br> | weA | connected to internal node | high |<br> | addrA | connected to signal <wp<4:0>> | |<br> | diA | connected to signal <din> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br> | Port B |<br> | aspect ratio | 32-word x 32-bit | |<br> | mode | write-first | |<br> | clkB | connected to signal <rd_clk> | rise |<br> | addrB | connected to signal <rp<4:0>> | |<br> | doB | connected to signal <dout> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br>Unit <generic_fifo_dc> synthesized (advanced).<br><br>=========================================================================<br>Advanced HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 32x32-bit dual-port block RAM : 1<br># Adders/Subtractors : 3<br> 6-bit adder : 2<br> 6-bit subtractor : 1<br># Counters : 2<br> 6-bit up counter : 2<br># Registers : 34<br> Flip-Flops : 34<br># Comparators : 8<br> 1-bit comparator not equal : 2<br> 5-bit comparator equal : 2<br> 6-bit comparator equal : 2<br> 6-bit comparator greater : 2<br><br>=========================================================================<br><br>=========================================================================<br>* Low Level Synthesis *<br>=========================================================================<br><br>Optimizing unit <generic_fifo_dc> ...<br><br>Mapping all equations...<br>Building and optimizing final netlist ...<br>Found area constraint ratio of 100 (+ 5) on block generic_fifo_dc, actual ratio is 0.<br><br>Final Macro Processing ...<br><br>=========================================================================<br>Final Register Report<br><br>Macro Statistics<br># Registers : 46<br> Flip-Flops : 46<br><br>=========================================================================<br><br>=========================================================================<br>* Partition Report *<br>=========================================================================<br><br>Partition Implementation Status<br>-------------------------------<br><br> No Partitions were found in this design.<br><br>-------------------------------<br><br>=========================================================================<br>* Design Summary *<br>=========================================================================<br><br>Top Level Output File Name : generic_fifo_dc.ngc<br><br>Primitive and Black Box Usage:<br>------------------------------<br># BELS : 53<br># GND : 1<br># INV : 2<br># LUT2 : 14<br># LUT3 : 6<br># LUT4 : 2<br># LUT5 : 6<br># LUT6 : 10<br># MUXCY : 5<br># VCC : 1<br># XORCY : 6<br># FlipFlops/Latches : 46<br># FD : 34<br># FDRE : 12<br># RAMS : 1<br># RAMB18E1 : 1<br><br>Device utilization summary:<br>---------------------------<br><br>Selected Device : 6vlx240tff1156-1 <br><br><br>Slice Logic Utilization: <br> Number of Slice Registers: 46 out of 301440 0% <br> Number of Slice LUTs: 40 out of 150720 0% <br> Number used as Logic: 40 out of 150720 0% <br><br>Slice Logic Distribution: <br> Number of LUT Flip Flop pairs used: 48<br> Number with an unused Flip Flop: 2 out of 48 4% <br> Number with an unused LUT: 8 out of 48 16% <br> Number of fully used LUT-FF pairs: 38 out of 48 79% <br> Number of unique control sets: 4<br><br>IO Utilization: <br> Number of IOs: 77<br> Number of bonded IOBs: 0 out of 600 0% <br><br>Specific Feature Utilization:<br> Number of Block RAM/FIFO: 1 out of 416 0% <br> Number using Block RAM only: 1<br><br>---------------------------<br>Partition Resource Summary:<br>---------------------------<br><br> No Partitions were found in this design.<br><br>---------------------------<br><br><br>=========================================================================<br>Timing Report<br><br>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<br> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<br> GENERATED AFTER PLACE-and-ROUTE.<br><br>Clock Information:<br>------------------<br>-----------------------------------+------------------------+-------+<br>Clock Signal | Clock buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>rd_clk | NONE(empty) | 23 |<br>wr_clk | NONE(full) | 25 |<br>-----------------------------------+------------------------+-------+<br>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<br><br>Asynchronous Control Signals Information:<br>----------------------------------------<br>-----------------------------------+------------------------+-------+<br>Control Signal | Buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>we_full_AND_3_o(we_full_AND_3_o1:O)| NONE(u0/Mram_RAM) | 8 |<br>-----------------------------------+------------------------+-------+<br><br>Timing Summary:<br>---------------<br>Speed Grade: -1<br><br> Minimum period: 2.312ns (Maximum Frequency: 432.526MHz)<br> Minimum input arrival time before clock: 1.104ns<br> Maximum output required time after clock: 0.742ns<br> Maximum combinational path delay: No path found<br><br>Timing Details:<br>---------------<br>All values displayed in nanoseconds (ns)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'rd_clk'<br> Clock period: 2.312ns (frequency: 432.526MHz)<br> Total number of paths / destination ports: 100 / 27<br>-------------------------------------------------------------------------<br>Delay: 2.312ns (Levels of Logic = 3)<br> Source: rp_4 (FF)<br> Destination: empty (FF)<br> Source Clock: rd_clk rising<br> Destination Clock: rd_clk rising<br><br> Data Path: rp_4 to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 6 0.375 0.808 rp_4 (rp_4)<br> LUT5:I0->O 2 0.068 0.497 Result<4>2 (Result<4>)<br> LUT6:I4->O 1 0.068 0.417 wp_s[5]_re_OR_6_o4_SW0 (N13)<br> LUT5:I4->O 1 0.068 0.000 wp_s[5]_re_OR_6_o5 (wp_s[5]_re_OR_6_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 2.312ns (0.590ns logic, 1.722ns route)<br> (25.5% logic, 74.5% route)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'wr_clk'<br> Clock period: 2.312ns (frequency: 432.526MHz)<br> Total number of paths / destination ports: 152 / 28<br>-------------------------------------------------------------------------<br>Delay: 2.312ns (Levels of Logic = 3)<br> Source: wp_4 (FF)<br> Destination: full (FF)<br> Source Clock: wr_clk rising<br> Destination Clock: wr_clk rising<br><br> Data Path: wp_4 to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 6 0.375 0.808 wp_4 (wp_4)<br> LUT5:I0->O 2 0.068 0.497 Result<4>11 (Result<4>1)<br> LUT6:I4->O 1 0.068 0.417 wp[4]_we_OR_11_o4_SW0 (N11)<br> LUT5:I4->O 1 0.068 0.000 wp[4]_we_OR_11_o5 (wp[4]_we_OR_11_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 2.312ns (0.590ns logic, 1.722ns route)<br> (25.5% logic, 74.5% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'rd_clk'<br> Total number of paths / destination ports: 34 / 33<br>-------------------------------------------------------------------------<br>Offset: 1.104ns (Levels of Logic = 2)<br> Source: re (PAD)<br> Destination: empty (FF)<br> Destination Clock: rd_clk rising<br><br> Data Path: re to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT5:I0->O 1 0.068 0.581 wp_s[5]_re_OR_6_o3 (wp_s[5]_re_OR_6_o3)<br> LUT5:I2->O 1 0.068 0.000 wp_s[5]_re_OR_6_o5 (wp_s[5]_re_OR_6_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 1.104ns (0.523ns logic, 0.581ns route)<br> (47.4% logic, 52.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk'<br> Total number of paths / destination ports: 34 / 33<br>-------------------------------------------------------------------------<br>Offset: 1.104ns (Levels of Logic = 2)<br> Source: we (PAD)<br> Destination: full (FF)<br> Destination Clock: wr_clk rising<br><br> Data Path: we to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT5:I0->O 1 0.068 0.581 wp[4]_we_OR_11_o3 (wp[4]_we_OR_11_o3)<br> LUT5:I2->O 1 0.068 0.000 wp[4]_we_OR_11_o5 (wp[4]_we_OR_11_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 1.104ns (0.523ns logic, 0.581ns route)<br> (47.4% logic, 52.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'rd_clk'<br> Total number of paths / destination ports: 35 / 35<br>-------------------------------------------------------------------------<br>Offset: 0.742ns (Levels of Logic = 0)<br> Source: u0/Mram_RAM (RAM)<br> Destination: dout<31> (PAD)<br> Source Clock: rd_clk rising<br><br> Data Path: u0/Mram_RAM to dout<31><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> RAMB18E1:CLKARDCLK->DOBDO15 0 0.742 0.000 u0/Mram_RAM (dout<31>)<br> ----------------------------------------<br> Total 0.742ns (0.742ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk'<br> Total number of paths / destination ports: 5 / 5<br>-------------------------------------------------------------------------<br>Offset: 0.375ns (Levels of Logic = 0)<br> Source: level_1 (FF)<br> Destination: level<1> (PAD)<br> Source Clock: wr_clk rising<br><br> Data Path: level_1 to level<1><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 0 0.375 0.000 level_1 (level_1)<br> ----------------------------------------<br> Total 0.375ns (0.375ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br><br>Cross Clock Domains Report:<br>--------------------------<br><br>Clock to Setup on destination clock rd_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.312| | | |<br>wr_clk | 1.544| | | |<br>---------------+---------+---------+---------+---------+<br><br>Clock to Setup on destination clock wr_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.171| | | |<br>wr_clk | 2.312| | | |<br>---------------+---------+---------+---------+---------+<br><br>=========================================================================<br><br><br>Total REAL time to Xst completion: 10.00 secs<br>Total CPU time to Xst completion: 9.75 secs<br> <br>--> <br><br><br>Total memory usage is 416720 kilobytes<br><br>Number of errors : 0 ( 0 filtered)<br>Number of warnings : 0 ( 0 filtered)<br>Number of infos : 2 ( 0 filtered)<br><br></PRE></FONT> |
/generic_fifo_dc_aw7_summary.html
0,0 → 1,112
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:22:14)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>msec.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>generic_fifo_dc</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT>No Warnings</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>58</TD> |
<TD ALIGN=RIGHT>301440</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>57</TD> |
<TD ALIGN=RIGHT>150720</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>48</TD> |
<TD ALIGN=RIGHT>67</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>71%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>600</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>416</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
</TABLE> |
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:22:13 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
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<br><center><b>Date Generated:</b> 07/03/2013 - 16:22:14</center> |
</BODY></HTML> |
/generic_fifo_dc_aw7_syr.html
0,0 → 1,112
<title>Synthesis Report</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>Synthesis Report</b></p><b><center>Wed Jul 3 16:23:00 2013</center></b><br><hr><br>Release 14.4 - xst P.49d (lin64)<br>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.<br>--> <br>Parameter TMPDIR set to xst/projnav.tmp<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Parameter xsthdpdir set to xst<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Reading design: generic_fifo_dc.prj<br><br>TABLE OF CONTENTS<br> 1) Synthesis Options Summary<br> 2) HDL Parsing<br> 3) HDL Elaboration<br> 4) HDL Synthesis<br> 4.1) HDL Synthesis Report<br> 5) Advanced HDL Synthesis<br> 5.1) Advanced HDL Synthesis Report<br> 6) Low Level Synthesis<br> 7) Partition Report<br> 8) Design Summary<br> 8.1) Primitive and Black Box Usage<br> 8.2) Device utilization summary<br> 8.3) Partition Resource Summary<br> 8.4) Timing Report<br> 8.4.1) Clock Information<br> 8.4.2) Asynchronous Control Signals Information<br> 8.4.3) Timing Summary<br> 8.4.4) Timing Details<br> 8.4.5) Cross Clock Domains Report<br><br><br>=========================================================================<br>* Synthesis Options Summary *<br>=========================================================================<br>---- Source Parameters<br>Input File Name : "generic_fifo_dc.prj"<br>Ignore Synthesis Constraint File : NO<br><br>---- Target Parameters<br>Output File Name : "generic_fifo_dc"<br>Output Format : NGC<br>Target Device : xc6vlx240t-1-ff1156<br><br>---- Source Options<br>Top Module Name : generic_fifo_dc<br>Automatic FSM Extraction : YES<br>FSM Encoding Algorithm : Auto<br>Safe Implementation : No<br>FSM Style : LUT<br>RAM Extraction : Yes<br>RAM Style : Auto<br>ROM Extraction : Yes<br>Shift Register Extraction : YES<br>ROM Style : Auto<br>Resource Sharing : YES<br>Asynchronous To Synchronous : NO<br>Shift Register Minimum Size : 2<br>Use DSP Block : Auto<br>Automatic Register Balancing : No<br><br>---- Target Options<br>LUT Combining : Auto<br>Reduce Control Sets : Auto<br>Add IO Buffers : NO<br>Global Maximum Fanout : 100000<br>Add Generic Clock Buffer(BUFG) : 32<br>Register Duplication : YES<br>Optimize Instantiated Primitives : NO<br>Use Clock Enable : Auto<br>Use Synchronous Set : Auto<br>Use Synchronous Reset : Auto<br>Pack IO Registers into IOBs : Auto<br>Equivalent register Removal : YES<br><br>---- General Options<br>Optimization Goal : Area<br>Optimization Effort : 2<br>Power Reduction : NO<br>Keep Hierarchy : No<br>Netlist Hierarchy : As_Optimized<br>RTL Output : Yes<br>Global Optimization : AllClockNets<br>Read Cores : YES<br>Write Timing Constraints : NO<br>Cross Clock Analysis : NO<br>Hierarchy Separator : /<br>Bus Delimiter : <><br>Case Specifier : Maintain<br>Slice Utilization Ratio : 100<br>BRAM Utilization Ratio : 100<br>DSP48 Utilization Ratio : 100<br>Auto BRAM Packing : NO<br>Slice Utilization Ratio Delta : 5<br><br>---- Other Options<br>Cores Search Directories : {"../../syn/xilinx/src" }<br><br>=========================================================================<br><br><br>=========================================================================<br>* HDL Parsing *<br>=========================================================================<br>Analyzing Verilog file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v" into library work<br>Parsing module <generic_fifo_dc>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<br>Parsing package <std_functions>.<br>Parsing package body <std_functions>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<br>Parsing entity <dpram_generic>.<br>Parsing architecture <behavorial> of entity <dpram_generic>.<br><br>=========================================================================<br>* HDL Elaboration *<br>=========================================================================<br><br>Elaborating module <generic_fifo_dc>.<br>Going to vhdl side to elaborate module dpram_generic<br><br>Elaborating entity <dpram_generic> (architecture <behavorial>) with generics from library <mod_sim_exp>.<br>Back to verilog to continue elaboration<br><br>=========================================================================<br>* HDL Synthesis *<br>=========================================================================<br><br>Synthesizing Unit <generic_fifo_dc>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v".<br> dw = 32<br> aw = 7<br> n = 32<br> max_size = 128<br> Found 8-bit register for signal <wp>.<br> Found 8-bit register for signal <rp>.<br> Found 8-bit register for signal <wp_s>.<br> Found 8-bit register for signal <rp_s>.<br> Found 1-bit register for signal <empty>.<br> Found 1-bit register for signal <full>.<br> Found 1-bit register for signal <re_r>.<br> Found 8-bit register for signal <diff_r1>.<br> Found 1-bit register for signal <empty_n>.<br> Found 1-bit register for signal <we_r>.<br> Found 8-bit register for signal <diff_r2>.<br> Found 1-bit register for signal <full_n>.<br> Found 2-bit register for signal <level>.<br> Found 1-bit register for signal <nopop>.<br> Found 1-bit register for signal <nopush>.<br> Found 32-bit register for signal <dout>.<br> Found 8-bit subtractor for signal <diff> created at line 254.<br> Found 8-bit adder for signal <wp_pl1> created at line 217.<br> Found 8-bit adder for signal <rp_pl1> created at line 224.<br> Found 8-bit comparator equal for signal <wp_s[7]_rp[7]_equal_19_o> created at line 243<br> Found 8-bit comparator equal for signal <wp_s[7]_rp_pl1[7]_equal_20_o> created at line 243<br> Found 7-bit comparator equal for signal <wp[6]_rp_s[6]_equal_22_o> created at line 246<br> Found 1-bit comparator not equal for signal <n0022> created at line 246<br> Found 7-bit comparator equal for signal <wp_pl1[6]_rp_s[6]_equal_24_o> created at line 247<br> Found 1-bit comparator not equal for signal <n0027> created at line 247<br> Found 8-bit comparator greater for signal <diff_r1[7]_GND_1_o_LessThan_31_o> created at line 263<br> Found 8-bit comparator greater for signal <GND_1_o_diff_r2[7]_LessThan_37_o> created at line 272<br> Summary:<br> inferred 3 Adder/Subtractor(s).<br> inferred 90 D-type flip-flop(s).<br> inferred 8 Comparator(s).<br>Unit <generic_fifo_dc> synthesized.<br><br>Synthesizing Unit <dpram_generic>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd".<br> depth = 128<br> Set property "ram_style = block" for signal <RAM>.<br> Found 128x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.<br> Found 32-bit register for signal <doutB>.<br> Summary:<br> inferred 1 RAM(s).<br> inferred 32 D-type flip-flop(s).<br>Unit <dpram_generic> synthesized.<br><br>=========================================================================<br>HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 128x32-bit dual-port RAM : 1<br># Adders/Subtractors : 3<br> 8-bit adder : 2<br> 8-bit subtractor : 1<br># Registers : 17<br> 1-bit register : 8<br> 2-bit register : 1<br> 32-bit register : 2<br> 8-bit register : 6<br># Comparators : 8<br> 1-bit comparator not equal : 2<br> 7-bit comparator equal : 2<br> 8-bit comparator equal : 2<br> 8-bit comparator greater : 2<br><br>=========================================================================<br><br>=========================================================================<br>* Advanced HDL Synthesis *<br>=========================================================================<br><br><br>Synthesizing (advanced) Unit <generic_fifo_dc>.<br>The following registers are absorbed into counter <rp>: 1 register on signal <rp>.<br>The following registers are absorbed into counter <wp>: 1 register on signal <wp>.<br>INFO:Xst:3226 - The RAM <u0/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <u0/doutB> <dout><br> -----------------------------------------------------------------------<br> | ram_type | Block | |<br> -----------------------------------------------------------------------<br> | Port A |<br> | aspect ratio | 128-word x 32-bit | |<br> | mode | write-first | |<br> | clkA | connected to signal <wr_clk> | rise |<br> | weA | connected to internal node | high |<br> | addrA | connected to signal <wp<6:0>> | |<br> | diA | connected to signal <din> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br> | Port B |<br> | aspect ratio | 128-word x 32-bit | |<br> | mode | write-first | |<br> | clkB | connected to signal <rd_clk> | rise |<br> | addrB | connected to signal <rp<6:0>> | |<br> | doB | connected to signal <dout> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br>Unit <generic_fifo_dc> synthesized (advanced).<br><br>=========================================================================<br>Advanced HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 128x32-bit dual-port block RAM : 1<br># Adders/Subtractors : 3<br> 8-bit adder : 2<br> 8-bit subtractor : 1<br># Counters : 2<br> 8-bit up counter : 2<br># Registers : 42<br> Flip-Flops : 42<br># Comparators : 8<br> 1-bit comparator not equal : 2<br> 7-bit comparator equal : 2<br> 8-bit comparator equal : 2<br> 8-bit comparator greater : 2<br><br>=========================================================================<br><br>=========================================================================<br>* Low Level Synthesis *<br>=========================================================================<br><br>Optimizing unit <generic_fifo_dc> ...<br><br>Mapping all equations...<br>Building and optimizing final netlist ...<br>Found area constraint ratio of 100 (+ 5) on block generic_fifo_dc, actual ratio is 0.<br><br>Final Macro Processing ...<br><br>=========================================================================<br>Final Register Report<br><br>Macro Statistics<br># Registers : 58<br> Flip-Flops : 58<br><br>=========================================================================<br><br>=========================================================================<br>* Partition Report *<br>=========================================================================<br><br>Partition Implementation Status<br>-------------------------------<br><br> No Partitions were found in this design.<br><br>-------------------------------<br><br>=========================================================================<br>* Design Summary *<br>=========================================================================<br><br>Top Level Output File Name : generic_fifo_dc.ngc<br><br>Primitive and Black Box Usage:<br>------------------------------<br># BELS : 105<br># GND : 1<br># INV : 2<br># LUT1 : 14<br># LUT2 : 14<br># LUT3 : 3<br># LUT4 : 1<br># LUT5 : 5<br># LUT6 : 18<br># MUXCY : 21<br># MUXF7 : 1<br># VCC : 1<br># XORCY : 24<br># FlipFlops/Latches : 58<br># FD : 42<br># FDRE : 16<br># RAMS : 1<br># RAMB18E1 : 1<br><br>Device utilization summary:<br>---------------------------<br><br>Selected Device : 6vlx240tff1156-1 <br><br><br>Slice Logic Utilization: <br> Number of Slice Registers: 58 out of 301440 0% <br> Number of Slice LUTs: 57 out of 150720 0% <br> Number used as Logic: 57 out of 150720 0% <br><br>Slice Logic Distribution: <br> Number of LUT Flip Flop pairs used: 67<br> Number with an unused Flip Flop: 9 out of 67 13% <br> Number with an unused LUT: 10 out of 67 14% <br> Number of fully used LUT-FF pairs: 48 out of 67 71% <br> Number of unique control sets: 4<br><br>IO Utilization: <br> Number of IOs: 77<br> Number of bonded IOBs: 0 out of 600 0% <br><br>Specific Feature Utilization:<br> Number of Block RAM/FIFO: 1 out of 416 0% <br> Number using Block RAM only: 1<br><br>---------------------------<br>Partition Resource Summary:<br>---------------------------<br><br> No Partitions were found in this design.<br><br>---------------------------<br><br><br>=========================================================================<br>Timing Report<br><br>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<br> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<br> GENERATED AFTER PLACE-and-ROUTE.<br><br>Clock Information:<br>------------------<br>-----------------------------------+------------------------+-------+<br>Clock Signal | Clock buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>rd_clk | NONE(empty) | 29 |<br>wr_clk | NONE(full) | 31 |<br>-----------------------------------+------------------------+-------+<br>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<br><br>Asynchronous Control Signals Information:<br>----------------------------------------<br>-----------------------------------+------------------------+-------+<br>Control Signal | Buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>we_full_AND_3_o(we_full_AND_3_o1:O)| NONE(u0/Mram_RAM) | 8 |<br>-----------------------------------+------------------------+-------+<br><br>Timing Summary:<br>---------------<br>Speed Grade: -1<br><br> Minimum period: 3.177ns (Maximum Frequency: 314.762MHz)<br> Minimum input arrival time before clock: 2.111ns<br> Maximum output required time after clock: 0.742ns<br> Maximum combinational path delay: No path found<br><br>Timing Details:<br>---------------<br>All values displayed in nanoseconds (ns)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'rd_clk'<br> Clock period: 3.063ns (frequency: 326.477MHz)<br> Total number of paths / destination ports: 184 / 35<br>-------------------------------------------------------------------------<br>Delay: 3.063ns (Levels of Logic = 4)<br> Source: wp_s_7 (FF)<br> Destination: empty (FF)<br> Source Clock: rd_clk rising<br> Destination Clock: rd_clk rising<br><br> Data Path: wp_s_7 to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 2 0.375 0.784 wp_s_7 (wp_s_7)<br> LUT6:I0->O 2 0.068 0.423 wp_s[7]_re_OR_8_o81 (wp_s[7]_re_OR_8_o_bdd13)<br> LUT6:I5->O 2 0.068 0.423 wp_s[7]_re_OR_8_o51 (wp_s[7]_re_OR_8_o_bdd7)<br> LUT6:I5->O 1 0.068 0.775 wp_s[7]_re_OR_8_o28 (wp_s[7]_re_OR_8_o27)<br> LUT6:I1->O 1 0.068 0.000 wp_s[7]_re_OR_8_o210 (wp_s[7]_re_OR_8_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 3.063ns (0.658ns logic, 2.405ns route)<br> (21.5% logic, 78.5% route)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'wr_clk'<br> Clock period: 3.177ns (frequency: 314.762MHz)<br> Total number of paths / destination ports: 258 / 36<br>-------------------------------------------------------------------------<br>Delay: 3.177ns (Levels of Logic = 5)<br> Source: rp_s_5 (FF)<br> Destination: full (FF)<br> Source Clock: wr_clk rising<br> Destination Clock: wr_clk rising<br><br> Data Path: rp_s_5 to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 2 0.375 0.784 rp_s_5 (rp_s_5)<br> LUT6:I0->O 2 0.068 0.423 wp[6]_we_OR_15_o81 (wp[6]_we_OR_15_o_bdd13)<br> LUT6:I5->O 2 0.068 0.423 wp[6]_we_OR_15_o211 (wp[6]_we_OR_15_o_bdd36)<br> LUT3:I2->O 2 0.068 0.644 wp[6]_we_OR_15_o231 (wp[6]_we_OR_15_o_bdd39)<br> LUT5:I1->O 1 0.068 0.000 wp[6]_we_OR_15_o28_F (N10)<br> MUXF7:I0->O 1 0.245 0.000 wp[6]_we_OR_15_o28 (wp[6]_we_OR_15_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 3.177ns (0.903ns logic, 2.274ns route)<br> (28.4% logic, 71.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'rd_clk'<br> Total number of paths / destination ports: 43 / 37<br>-------------------------------------------------------------------------<br>Offset: 1.792ns (Levels of Logic = 3)<br> Source: re (PAD)<br> Destination: empty (FF)<br> Destination Clock: rd_clk rising<br><br> Data Path: re to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT6:I0->O 2 0.068 0.423 wp_s[7]_re_OR_8_o51 (wp_s[7]_re_OR_8_o_bdd7)<br> LUT6:I5->O 1 0.068 0.775 wp_s[7]_re_OR_8_o28 (wp_s[7]_re_OR_8_o27)<br> LUT6:I1->O 1 0.068 0.000 wp_s[7]_re_OR_8_o210 (wp_s[7]_re_OR_8_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 1.792ns (0.594ns logic, 1.198ns route)<br> (33.1% logic, 66.9% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk'<br> Total number of paths / destination ports: 43 / 37<br>-------------------------------------------------------------------------<br>Offset: 2.111ns (Levels of Logic = 4)<br> Source: we (PAD)<br> Destination: full (FF)<br> Destination Clock: wr_clk rising<br><br> Data Path: we to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT5:I0->O 1 0.068 0.491 wp[6]_we_OR_15_o51_SW0 (N6)<br> LUT4:I2->O 2 0.068 0.781 wp[6]_we_OR_15_o41 (wp[6]_we_OR_15_o_bdd5)<br> LUT6:I1->O 1 0.068 0.000 wp[6]_we_OR_15_o28_G (N11)<br> MUXF7:I1->O 1 0.248 0.000 wp[6]_we_OR_15_o28 (wp[6]_we_OR_15_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 2.111ns (0.839ns logic, 1.272ns route)<br> (39.7% logic, 60.3% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'rd_clk'<br> Total number of paths / destination ports: 35 / 35<br>-------------------------------------------------------------------------<br>Offset: 0.742ns (Levels of Logic = 0)<br> Source: u0/Mram_RAM (RAM)<br> Destination: dout<31> (PAD)<br> Source Clock: rd_clk rising<br><br> Data Path: u0/Mram_RAM to dout<31><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> RAMB18E1:CLKARDCLK->DOBDO15 0 0.742 0.000 u0/Mram_RAM (dout<31>)<br> ----------------------------------------<br> Total 0.742ns (0.742ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk'<br> Total number of paths / destination ports: 5 / 5<br>-------------------------------------------------------------------------<br>Offset: 0.375ns (Levels of Logic = 0)<br> Source: level_1 (FF)<br> Destination: level<1> (PAD)<br> Source Clock: wr_clk rising<br><br> Data Path: level_1 to level<1><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 0 0.375 0.000 level_1 (level_1)<br> ----------------------------------------<br> Total 0.375ns (0.375ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br><br>Cross Clock Domains Report:<br>--------------------------<br><br>Clock to Setup on destination clock rd_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 3.063| | | |<br>wr_clk | 1.631| | | |<br>---------------+---------+---------+---------+---------+<br><br>Clock to Setup on destination clock wr_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.136| | | |<br>wr_clk | 3.177| | | |<br>---------------+---------+---------+---------+---------+<br><br>=========================================================================<br><br><br>Total REAL time to Xst completion: 11.00 secs<br>Total CPU time to Xst completion: 11.57 secs<br> <br>--> <br><br><br>Total memory usage is 482304 kilobytes<br><br>Number of errors : 0 ( 0 filtered)<br>Number of warnings : 0 ( 0 filtered)<br>Number of infos : 2 ( 0 filtered)<br><br></PRE></FONT> |
/generic_fifo_dc_gray_aw5_summary.html
0,0 → 1,112
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:29:30)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>msec.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>generic_fifo_dc_gray</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/*.xmsgs?&DataKey=Warning'>12 Warnings (12 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
</TABLE> |
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>62</TD> |
<TD ALIGN=RIGHT>301440</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>66</TD> |
<TD ALIGN=RIGHT>150720</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>54</TD> |
<TD ALIGN=RIGHT>74</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>72%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>600</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>416</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
</TABLE> |
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:29:29 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Warning'>12 Warnings (12 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
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<br><center><b>Date Generated:</b> 07/03/2013 - 16:29:30</center> |
</BODY></HTML> |
/generic_fifo_dc_gray_aw5_syr.html
0,0 → 1,112
<title>Synthesis Report</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>Synthesis Report</b></p><b><center>Wed Jul 3 16:30:18 2013</center></b><br><hr><br>Release 14.4 - xst P.49d (lin64)<br>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.<br>--> <br>Parameter TMPDIR set to xst/projnav.tmp<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Parameter xsthdpdir set to xst<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Reading design: generic_fifo_dc_gray.prj<br><br>TABLE OF CONTENTS<br> 1) Synthesis Options Summary<br> 2) HDL Parsing<br> 3) HDL Elaboration<br> 4) HDL Synthesis<br> 4.1) HDL Synthesis Report<br> 5) Advanced HDL Synthesis<br> 5.1) Advanced HDL Synthesis Report<br> 6) Low Level Synthesis<br> 7) Partition Report<br> 8) Design Summary<br> 8.1) Primitive and Black Box Usage<br> 8.2) Device utilization summary<br> 8.3) Partition Resource Summary<br> 8.4) Timing Report<br> 8.4.1) Clock Information<br> 8.4.2) Asynchronous Control Signals Information<br> 8.4.3) Timing Summary<br> 8.4.4) Timing Details<br> 8.4.5) Cross Clock Domains Report<br><br><br>=========================================================================<br>* Synthesis Options Summary *<br>=========================================================================<br>---- Source Parameters<br>Input File Name : "generic_fifo_dc_gray.prj"<br>Ignore Synthesis Constraint File : NO<br><br>---- Target Parameters<br>Output File Name : "generic_fifo_dc_gray"<br>Output Format : NGC<br>Target Device : xc6vlx240t-1-ff1156<br><br>---- Source Options<br>Top Module Name : generic_fifo_dc_gray<br>Automatic FSM Extraction : YES<br>FSM Encoding Algorithm : Auto<br>Safe Implementation : No<br>FSM Style : LUT<br>RAM Extraction : Yes<br>RAM Style : Auto<br>ROM Extraction : Yes<br>Shift Register Extraction : YES<br>ROM Style : Auto<br>Resource Sharing : YES<br>Asynchronous To Synchronous : NO<br>Shift Register Minimum Size : 2<br>Use DSP Block : Auto<br>Automatic Register Balancing : No<br><br>---- Target Options<br>LUT Combining : Auto<br>Reduce Control Sets : Auto<br>Add IO Buffers : NO<br>Global Maximum Fanout : 100000<br>Add Generic Clock Buffer(BUFG) : 32<br>Register Duplication : YES<br>Optimize Instantiated Primitives : NO<br>Use Clock Enable : Auto<br>Use Synchronous Set : Auto<br>Use Synchronous Reset : Auto<br>Pack IO Registers into IOBs : Auto<br>Equivalent register Removal : YES<br><br>---- General Options<br>Optimization Goal : Area<br>Optimization Effort : 2<br>Power Reduction : NO<br>Keep Hierarchy : No<br>Netlist Hierarchy : As_Optimized<br>RTL Output : Yes<br>Global Optimization : AllClockNets<br>Read Cores : YES<br>Write Timing Constraints : NO<br>Cross Clock Analysis : NO<br>Hierarchy Separator : /<br>Bus Delimiter : <><br>Case Specifier : Maintain<br>Slice Utilization Ratio : 100<br>BRAM Utilization Ratio : 100<br>DSP48 Utilization Ratio : 100<br>Auto BRAM Packing : NO<br>Slice Utilization Ratio Delta : 5<br><br>---- Other Options<br>Cores Search Directories : {"../../syn/xilinx/src" }<br><br>=========================================================================<br><br><br>=========================================================================<br>* HDL Parsing *<br>=========================================================================<br>Analyzing Verilog file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v" into library work<br>Parsing module <generic_fifo_dc_gray>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<br>Parsing package <std_functions>.<br>Parsing package body <std_functions>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<br>Parsing entity <dpram_generic>.<br>Parsing architecture <behavorial> of entity <dpram_generic>.<br><br>=========================================================================<br>* HDL Elaboration *<br>=========================================================================<br><br>Elaborating module <generic_fifo_dc_gray>.<br>Going to vhdl side to elaborate module dpram_generic<br><br>Elaborating entity <dpram_generic> (architecture <behavorial>) with generics from library <mod_sim_exp>.<br>Back to verilog to continue elaboration<br><br>=========================================================================<br>* HDL Synthesis *<br>=========================================================================<br><br>Synthesizing Unit <generic_fifo_dc_gray>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v".<br> dw = 32<br> aw = 5<br> Found 1-bit register for signal <rd_clr_r>.<br> Found 1-bit register for signal <wr_clr>.<br> Found 1-bit register for signal <wr_clr_r>.<br> Found 1-bit register for signal <rd_clr>.<br> Found 32-bit register for signal <dout>.<br> Found 6-bit register for signal <wp_bin>.<br> Found 6-bit register for signal <wp_gray>.<br> Found 6-bit register for signal <rp_bin>.<br> Found 6-bit register for signal <rp_gray>.<br> Found 6-bit register for signal <wp_s>.<br> Found 6-bit register for signal <rp_s>.<br> Found 1-bit register for signal <empty>.<br> Found 1-bit register for signal <full>.<br> Found 1-bit register for signal <nopop>.<br> Found 1-bit register for signal <nopush>.<br> Found 1-bit register for signal <full_wc>.<br> Found 5-bit register for signal <rp_bin_xr>.<br> Found 5-bit register for signal <d1>.<br> Found 2-bit register for signal <wr_level>.<br> Found 5-bit register for signal <wp_bin_xr>.<br> Found 5-bit register for signal <d2>.<br> Found 1-bit register for signal <full_rc>.<br> Found 2-bit register for signal <rd_level>.<br> Found 6-bit adder for signal <wp_bin_next> created at line 242.<br> Found 6-bit adder for signal <rp_bin_next> created at line 255.<br> Found 5-bit adder for signal <rp_bin_x[4]_GND_1_o_add_42_OUT> created at line 306.<br> Found 5-bit adder for signal <wp_bin[4]_rp_bin_xr[4]_add_45_OUT> created at line 307.<br> Found 5-bit adder for signal <rp_bin[4]_wp_bin_xr[4]_add_53_OUT> created at line 312.<br> Found 6-bit comparator equal for signal <wp_s[5]_rp_gray[5]_equal_31_o> created at line 278<br> Found 6-bit comparator equal for signal <wp_s[5]_rp_gray_next[5]_equal_32_o> created at line 278<br> Found 5-bit comparator equal for signal <wp_bin[4]_rp_bin_x[4]_equal_34_o> created at line 281<br> Found 1-bit comparator not equal for signal <n0038> created at line 281<br> Found 5-bit comparator equal for signal <wp_bin_next[4]_rp_bin_x[4]_equal_36_o> created at line 282<br> Found 1-bit comparator not equal for signal <n0043> created at line 282<br> Summary:<br> inferred 5 Adder/Subtractor(s).<br> inferred 102 D-type flip-flop(s).<br> inferred 6 Comparator(s).<br>Unit <generic_fifo_dc_gray> synthesized.<br><br>Synthesizing Unit <dpram_generic>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd".<br> depth = 32<br> Set property "ram_style = block" for signal <RAM>.<br> Found 32x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.<br> Found 32-bit register for signal <doutB>.<br> Summary:<br> inferred 1 RAM(s).<br> inferred 32 D-type flip-flop(s).<br>Unit <dpram_generic> synthesized.<br><br>=========================================================================<br>HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 32x32-bit dual-port RAM : 1<br># Adders/Subtractors : 5<br> 5-bit adder : 3<br> 6-bit adder : 2<br># Registers : 24<br> 1-bit register : 10<br> 2-bit register : 2<br> 32-bit register : 2<br> 5-bit register : 4<br> 6-bit register : 6<br># Comparators : 6<br> 1-bit comparator not equal : 2<br> 5-bit comparator equal : 2<br> 6-bit comparator equal : 2<br># Xors : 4<br> 6-bit xor2 : 4<br><br>=========================================================================<br><br>=========================================================================<br>* Advanced HDL Synthesis *<br>=========================================================================<br><br>WARNING:Xst:2677 - Node <d2_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br><br>Synthesizing (advanced) Unit <generic_fifo_dc_gray>.<br>The following registers are absorbed into counter <rp_bin>: 1 register on signal <rp_bin>.<br>The following registers are absorbed into counter <wp_bin>: 1 register on signal <wp_bin>.<br>INFO:Xst:3226 - The RAM <u0/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <u0/doutB> <dout><br> -----------------------------------------------------------------------<br> | ram_type | Block | |<br> -----------------------------------------------------------------------<br> | Port A |<br> | aspect ratio | 32-word x 32-bit | |<br> | mode | write-first | |<br> | clkA | connected to signal <wr_clk> | rise |<br> | weA | connected to internal node | high |<br> | addrA | connected to signal <wp_bin<4:0>> | |<br> | diA | connected to signal <din> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br> | Port B |<br> | aspect ratio | 32-word x 32-bit | |<br> | mode | write-first | |<br> | clkB | connected to signal <rd_clk> | rise |<br> | addrB | connected to signal <rp_bin<4:0>> | |<br> | doB | connected to signal <dout> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br>Unit <generic_fifo_dc_gray> synthesized (advanced).<br>WARNING:Xst:2677 - Node <d2_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br><br>=========================================================================<br>Advanced HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 32x32-bit dual-port block RAM : 1<br># Adders/Subtractors : 5<br> 5-bit adder : 3<br> 6-bit adder : 2<br># Counters : 2<br> 6-bit up counter : 2<br># Registers : 52<br> Flip-Flops : 52<br># Comparators : 6<br> 1-bit comparator not equal : 2<br> 5-bit comparator equal : 2<br> 6-bit comparator equal : 2<br># Xors : 4<br> 6-bit xor2 : 4<br><br>=========================================================================<br><br>=========================================================================<br>* Low Level Synthesis *<br>=========================================================================<br>INFO:Xst:2261 - The FF/Latch <wp_gray_5> in Unit <generic_fifo_dc_gray> is equivalent to the following FF/Latch, which will be removed : <wp_bin_5> <br>INFO:Xst:2261 - The FF/Latch <rp_gray_5> in Unit <generic_fifo_dc_gray> is equivalent to the following FF/Latch, which will be removed : <rp_bin_5> <br><br>Optimizing unit <generic_fifo_dc_gray> ...<br><br>Mapping all equations...<br>Building and optimizing final netlist ...<br>Found area constraint ratio of 100 (+ 5) on block generic_fifo_dc_gray, actual ratio is 0.<br><br>Final Macro Processing ...<br><br>=========================================================================<br>Final Register Report<br><br>Macro Statistics<br># Registers : 62<br> Flip-Flops : 62<br><br>=========================================================================<br><br>=========================================================================<br>* Partition Report *<br>=========================================================================<br><br>Partition Implementation Status<br>-------------------------------<br><br> No Partitions were found in this design.<br><br>-------------------------------<br><br>=========================================================================<br>* Design Summary *<br>=========================================================================<br><br>Top Level Output File Name : generic_fifo_dc_gray.ngc<br><br>Primitive and Black Box Usage:<br>------------------------------<br># BELS : 80<br># GND : 1<br># INV : 4<br># LUT2 : 19<br># LUT3 : 9<br># LUT4 : 7<br># LUT5 : 10<br># LUT6 : 17<br># MUXCY : 8<br># VCC : 1<br># XORCY : 4<br># FlipFlops/Latches : 62<br># FD : 34<br># FDP : 4<br># FDR : 2<br># FDRE : 22<br># RAMS : 1<br># RAMB18E1 : 1<br><br>Device utilization summary:<br>---------------------------<br><br>Selected Device : 6vlx240tff1156-1 <br><br><br>Slice Logic Utilization: <br> Number of Slice Registers: 62 out of 301440 0% <br> Number of Slice LUTs: 66 out of 150720 0% <br> Number used as Logic: 66 out of 150720 0% <br><br>Slice Logic Distribution: <br> Number of LUT Flip Flop pairs used: 74<br> Number with an unused Flip Flop: 12 out of 74 16% <br> Number with an unused LUT: 8 out of 74 10% <br> Number of fully used LUT-FF pairs: 54 out of 74 72% <br> Number of unique control sets: 7<br><br>IO Utilization: <br> Number of IOs: 77<br> Number of bonded IOBs: 0 out of 600 0% <br><br>Specific Feature Utilization:<br> Number of Block RAM/FIFO: 1 out of 416 0% <br> Number using Block RAM only: 1<br><br>---------------------------<br>Partition Resource Summary:<br>---------------------------<br><br> No Partitions were found in this design.<br><br>---------------------------<br><br><br>=========================================================================<br>Timing Report<br><br>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<br> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<br> GENERATED AFTER PLACE-and-ROUTE.<br><br>Clock Information:<br>------------------<br>-----------------------------------+------------------------+-------+<br>Clock Signal | Clock buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>rd_clk | NONE(empty) | 32 |<br>wr_clk | NONE(full) | 32 |<br>-----------------------------------+------------------------+-------+<br>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<br><br>Asynchronous Control Signals Information:<br>----------------------------------------<br>-----------------------------------+------------------------+-------+<br>Control Signal | Buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>we_full_AND_3_o(we_full_AND_3_o1:O)| NONE(u0/Mram_RAM) | 8 |<br>-----------------------------------+------------------------+-------+<br><br>Timing Summary:<br>---------------<br>Speed Grade: -1<br><br> Minimum period: 2.974ns (Maximum Frequency: 336.247MHz)<br> Minimum input arrival time before clock: 1.508ns<br> Maximum output required time after clock: 0.742ns<br> Maximum combinational path delay: No path found<br><br>Timing Details:<br>---------------<br>All values displayed in nanoseconds (ns)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'rd_clk'<br> Clock period: 2.459ns (frequency: 406.669MHz)<br> Total number of paths / destination ports: 164 / 53<br>-------------------------------------------------------------------------<br>Delay: 2.459ns (Levels of Logic = 3)<br> Source: rp_bin_4 (FF)<br> Destination: empty (FF)<br> Source Clock: rd_clk rising<br> Destination Clock: rd_clk rising<br><br> Data Path: rp_bin_4 to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 6 0.375 0.808 rp_bin_4 (rp_bin_4)<br> LUT6:I1->O 2 0.068 0.644 Result<5>2 (Result<5>)<br> LUT6:I2->O 1 0.068 0.417 wp_s[5]_re_OR_6_o5 (wp_s[5]_re_OR_6_o5)<br> LUT5:I4->O 1 0.068 0.000 wp_s[5]_re_OR_6_o6 (wp_s[5]_re_OR_6_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 2.459ns (0.590ns logic, 1.869ns route)<br> (24.0% logic, 76.0% route)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'wr_clk'<br> Clock period: 2.974ns (frequency: 336.247MHz)<br> Total number of paths / destination ports: 202 / 51<br>-------------------------------------------------------------------------<br>Delay: 2.974ns (Levels of Logic = 4)<br> Source: wp_bin_4 (FF)<br> Destination: full (FF)<br> Source Clock: wr_clk rising<br> Destination Clock: wr_clk rising<br><br> Data Path: wp_bin_4 to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 7 0.375 0.815 wp_bin_4 (wp_bin_4)<br> LUT5:I0->O 2 0.068 0.587 Result<4>11 (Result<4>1)<br> LUT6:I3->O 2 0.068 0.423 wp_bin[4]_we_OR_11_o7 (wp_bin[4]_we_OR_11_o7)<br> LUT5:I4->O 1 0.068 0.491 wp_bin[4]_we_OR_11_o2 (wp_bin[4]_we_OR_11_o2)<br> LUT5:I3->O 1 0.068 0.000 wp_bin[4]_we_OR_11_o5 (wp_bin[4]_we_OR_11_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 2.974ns (0.658ns logic, 2.316ns route)<br> (22.1% logic, 77.9% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'rd_clk'<br> Total number of paths / destination ports: 33 / 32<br>-------------------------------------------------------------------------<br>Offset: 1.428ns (Levels of Logic = 3)<br> Source: re (PAD)<br> Destination: empty (FF)<br> Destination Clock: rd_clk rising<br><br> Data Path: re to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT6:I0->O 1 0.068 0.417 wp_s[5]_re_OR_6_o4 (wp_s[5]_re_OR_6_o4)<br> LUT6:I5->O 1 0.068 0.417 wp_s[5]_re_OR_6_o5 (wp_s[5]_re_OR_6_o5)<br> LUT5:I4->O 1 0.068 0.000 wp_s[5]_re_OR_6_o6 (wp_s[5]_re_OR_6_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 1.428ns (0.594ns logic, 0.834ns route)<br> (41.6% logic, 58.4% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk'<br> Total number of paths / destination ports: 34 / 32<br>-------------------------------------------------------------------------<br>Offset: 1.508ns (Levels of Logic = 3)<br> Source: we (PAD)<br> Destination: full (FF)<br> Destination Clock: wr_clk rising<br><br> Data Path: we to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT6:I0->O 2 0.068 0.423 wp_bin[4]_we_OR_11_o7 (wp_bin[4]_we_OR_11_o7)<br> LUT5:I4->O 1 0.068 0.491 wp_bin[4]_we_OR_11_o2 (wp_bin[4]_we_OR_11_o2)<br> LUT5:I3->O 1 0.068 0.000 wp_bin[4]_we_OR_11_o5 (wp_bin[4]_we_OR_11_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 1.508ns (0.594ns logic, 0.914ns route)<br> (39.4% logic, 60.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'rd_clk'<br> Total number of paths / destination ports: 36 / 36<br>-------------------------------------------------------------------------<br>Offset: 0.742ns (Levels of Logic = 0)<br> Source: u0/Mram_RAM (RAM)<br> Destination: dout<31> (PAD)<br> Source Clock: rd_clk rising<br><br> Data Path: u0/Mram_RAM to dout<31><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> RAMB18E1:CLKARDCLK->DOBDO15 0 0.742 0.000 u0/Mram_RAM (dout<31>)<br> ----------------------------------------<br> Total 0.742ns (0.742ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk'<br> Total number of paths / destination ports: 4 / 4<br>-------------------------------------------------------------------------<br>Offset: 0.375ns (Levels of Logic = 0)<br> Source: wr_level_1 (FF)<br> Destination: wr_level<1> (PAD)<br> Source Clock: wr_clk rising<br><br> Data Path: wr_level_1 to wr_level<1><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 0 0.375 0.000 wr_level_1 (wr_level_1)<br> ----------------------------------------<br> Total 0.375ns (0.375ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br><br>Cross Clock Domains Report:<br>--------------------------<br><br>Clock to Setup on destination clock rd_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.459| | | |<br>wr_clk | 0.818| | | |<br>---------------+---------+---------+---------+---------+<br><br>Clock to Setup on destination clock wr_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 1.572| | | |<br>wr_clk | 2.974| | | |<br>---------------+---------+---------+---------+---------+<br><br>=========================================================================<br><br><br>Total REAL time to Xst completion: 15.00 secs<br>Total CPU time to Xst completion: 15.01 secs<br> <br>--> <br><br><br>Total memory usage is 416708 kilobytes<br><br>Number of errors : 0 ( 0 filtered)<br>Number of warnings : 12 ( 0 filtered)<br>Number of infos : 4 ( 0 filtered)<br><br></PRE></FONT> |
/generic_fifo_dc_gray_aw7_summary.html
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
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<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:32:22)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>msec.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>generic_fifo_dc_gray</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/*.xmsgs?&DataKey=Warning'>20 Warnings (8 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>78</TD> |
<TD ALIGN=RIGHT>301440</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>95</TD> |
<TD ALIGN=RIGHT>150720</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>67</TD> |
<TD ALIGN=RIGHT>106</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>63%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>600</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>416</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:32:21 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Warning'>20 Warnings (8 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (2 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
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<br><center><b>Date Generated:</b> 07/03/2013 - 16:32:22</center> |
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/generic_fifo_dc_gray_aw7_syr.html
0,0 → 1,112
<title>Synthesis Report</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>Synthesis Report</b></p><b><center>Wed Jul 3 16:32:33 2013</center></b><br><hr><br>Release 14.4 - xst P.49d (lin64)<br>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.<br>--> <br>Parameter TMPDIR set to xst/projnav.tmp<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.06 secs<br> <br>--> <br>Parameter xsthdpdir set to xst<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.06 secs<br> <br>--> <br>Reading design: generic_fifo_dc_gray.prj<br><br>TABLE OF CONTENTS<br> 1) Synthesis Options Summary<br> 2) HDL Parsing<br> 3) HDL Elaboration<br> 4) HDL Synthesis<br> 4.1) HDL Synthesis Report<br> 5) Advanced HDL Synthesis<br> 5.1) Advanced HDL Synthesis Report<br> 6) Low Level Synthesis<br> 7) Partition Report<br> 8) Design Summary<br> 8.1) Primitive and Black Box Usage<br> 8.2) Device utilization summary<br> 8.3) Partition Resource Summary<br> 8.4) Timing Report<br> 8.4.1) Clock Information<br> 8.4.2) Asynchronous Control Signals Information<br> 8.4.3) Timing Summary<br> 8.4.4) Timing Details<br> 8.4.5) Cross Clock Domains Report<br><br><br>=========================================================================<br>* Synthesis Options Summary *<br>=========================================================================<br>---- Source Parameters<br>Input File Name : "generic_fifo_dc_gray.prj"<br>Ignore Synthesis Constraint File : NO<br><br>---- Target Parameters<br>Output File Name : "generic_fifo_dc_gray"<br>Output Format : NGC<br>Target Device : xc6vlx240t-1-ff1156<br><br>---- Source Options<br>Top Module Name : generic_fifo_dc_gray<br>Automatic FSM Extraction : YES<br>FSM Encoding Algorithm : Auto<br>Safe Implementation : No<br>FSM Style : LUT<br>RAM Extraction : Yes<br>RAM Style : Auto<br>ROM Extraction : Yes<br>Shift Register Extraction : YES<br>ROM Style : Auto<br>Resource Sharing : YES<br>Asynchronous To Synchronous : NO<br>Shift Register Minimum Size : 2<br>Use DSP Block : Auto<br>Automatic Register Balancing : No<br><br>---- Target Options<br>LUT Combining : Auto<br>Reduce Control Sets : Auto<br>Add IO Buffers : NO<br>Global Maximum Fanout : 100000<br>Add Generic Clock Buffer(BUFG) : 32<br>Register Duplication : YES<br>Optimize Instantiated Primitives : NO<br>Use Clock Enable : Auto<br>Use Synchronous Set : Auto<br>Use Synchronous Reset : Auto<br>Pack IO Registers into IOBs : Auto<br>Equivalent register Removal : YES<br><br>---- General Options<br>Optimization Goal : Area<br>Optimization Effort : 2<br>Power Reduction : NO<br>Keep Hierarchy : No<br>Netlist Hierarchy : As_Optimized<br>RTL Output : Yes<br>Global Optimization : AllClockNets<br>Read Cores : YES<br>Write Timing Constraints : NO<br>Cross Clock Analysis : NO<br>Hierarchy Separator : /<br>Bus Delimiter : <><br>Case Specifier : Maintain<br>Slice Utilization Ratio : 100<br>BRAM Utilization Ratio : 100<br>DSP48 Utilization Ratio : 100<br>Auto BRAM Packing : NO<br>Slice Utilization Ratio Delta : 5<br><br>---- Other Options<br>Cores Search Directories : {"../../syn/xilinx/src" }<br><br>=========================================================================<br><br><br>=========================================================================<br>* HDL Parsing *<br>=========================================================================<br>Analyzing Verilog file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v" into library work<br>Parsing module <generic_fifo_dc_gray>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<br>Parsing package <std_functions>.<br>Parsing package body <std_functions>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<br>Parsing entity <dpram_generic>.<br>Parsing architecture <behavorial> of entity <dpram_generic>.<br><br>=========================================================================<br>* HDL Elaboration *<br>=========================================================================<br><br>Elaborating module <generic_fifo_dc_gray>.<br>Going to vhdl side to elaborate module dpram_generic<br><br>Elaborating entity <dpram_generic> (architecture <behavorial>) with generics from library <mod_sim_exp>.<br>Back to verilog to continue elaboration<br><br>=========================================================================<br>* HDL Synthesis *<br>=========================================================================<br><br>Synthesizing Unit <generic_fifo_dc_gray>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v".<br> dw = 32<br> aw = 7<br> Found 1-bit register for signal <rd_clr_r>.<br> Found 1-bit register for signal <wr_clr>.<br> Found 1-bit register for signal <wr_clr_r>.<br> Found 1-bit register for signal <rd_clr>.<br> Found 32-bit register for signal <dout>.<br> Found 8-bit register for signal <wp_bin>.<br> Found 8-bit register for signal <wp_gray>.<br> Found 8-bit register for signal <rp_bin>.<br> Found 8-bit register for signal <rp_gray>.<br> Found 8-bit register for signal <wp_s>.<br> Found 8-bit register for signal <rp_s>.<br> Found 1-bit register for signal <empty>.<br> Found 1-bit register for signal <full>.<br> Found 1-bit register for signal <nopop>.<br> Found 1-bit register for signal <nopush>.<br> Found 1-bit register for signal <full_wc>.<br> Found 7-bit register for signal <rp_bin_xr>.<br> Found 7-bit register for signal <d1>.<br> Found 2-bit register for signal <wr_level>.<br> Found 7-bit register for signal <wp_bin_xr>.<br> Found 7-bit register for signal <d2>.<br> Found 1-bit register for signal <full_rc>.<br> Found 2-bit register for signal <rd_level>.<br> Found 8-bit adder for signal <wp_bin_next> created at line 242.<br> Found 8-bit adder for signal <rp_bin_next> created at line 255.<br> Found 7-bit adder for signal <rp_bin_x[6]_GND_1_o_add_42_OUT> created at line 306.<br> Found 7-bit adder for signal <wp_bin[6]_rp_bin_xr[6]_add_45_OUT> created at line 307.<br> Found 7-bit adder for signal <rp_bin[6]_wp_bin_xr[6]_add_53_OUT> created at line 312.<br> Found 8-bit comparator equal for signal <wp_s[7]_rp_gray[7]_equal_31_o> created at line 278<br> Found 8-bit comparator equal for signal <wp_s[7]_rp_gray_next[7]_equal_32_o> created at line 278<br> Found 7-bit comparator equal for signal <wp_bin[6]_rp_bin_x[6]_equal_34_o> created at line 281<br> Found 1-bit comparator not equal for signal <n0038> created at line 281<br> Found 7-bit comparator equal for signal <wp_bin_next[6]_rp_bin_x[6]_equal_36_o> created at line 282<br> Found 1-bit comparator not equal for signal <n0043> created at line 282<br> Summary:<br> inferred 5 Adder/Subtractor(s).<br> inferred 122 D-type flip-flop(s).<br> inferred 6 Comparator(s).<br>Unit <generic_fifo_dc_gray> synthesized.<br><br>Synthesizing Unit <dpram_generic>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd".<br> depth = 128<br> Set property "ram_style = block" for signal <RAM>.<br> Found 128x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.<br> Found 32-bit register for signal <doutB>.<br> Summary:<br> inferred 1 RAM(s).<br> inferred 32 D-type flip-flop(s).<br>Unit <dpram_generic> synthesized.<br><br>=========================================================================<br>HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 128x32-bit dual-port RAM : 1<br># Adders/Subtractors : 5<br> 7-bit adder : 3<br> 8-bit adder : 2<br># Registers : 24<br> 1-bit register : 10<br> 2-bit register : 2<br> 32-bit register : 2<br> 7-bit register : 4<br> 8-bit register : 6<br># Comparators : 6<br> 1-bit comparator not equal : 2<br> 7-bit comparator equal : 2<br> 8-bit comparator equal : 2<br># Xors : 4<br> 8-bit xor2 : 4<br><br>=========================================================================<br><br>=========================================================================<br>* Advanced HDL Synthesis *<br>=========================================================================<br><br>WARNING:Xst:2677 - Node <d2_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_3> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_4> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_3> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_4> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br><br>Synthesizing (advanced) Unit <generic_fifo_dc_gray>.<br>The following registers are absorbed into counter <rp_bin>: 1 register on signal <rp_bin>.<br>The following registers are absorbed into counter <wp_bin>: 1 register on signal <wp_bin>.<br>INFO:Xst:3226 - The RAM <u0/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <u0/doutB> <dout><br> -----------------------------------------------------------------------<br> | ram_type | Block | |<br> -----------------------------------------------------------------------<br> | Port A |<br> | aspect ratio | 128-word x 32-bit | |<br> | mode | write-first | |<br> | clkA | connected to signal <wr_clk> | rise |<br> | weA | connected to internal node | high |<br> | addrA | connected to signal <wp_bin<6:0>> | |<br> | diA | connected to signal <din> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br> | Port B |<br> | aspect ratio | 128-word x 32-bit | |<br> | mode | write-first | |<br> | clkB | connected to signal <rd_clk> | rise |<br> | addrB | connected to signal <rp_bin<6:0>> | |<br> | doB | connected to signal <dout> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br>Unit <generic_fifo_dc_gray> synthesized (advanced).<br>WARNING:Xst:2677 - Node <d2_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_3> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_4> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_3> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_4> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br><br>=========================================================================<br>Advanced HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 128x32-bit dual-port block RAM : 1<br># Adders/Subtractors : 5<br> 7-bit adder : 3<br> 8-bit adder : 2<br># Counters : 2<br> 8-bit up counter : 2<br># Registers : 64<br> Flip-Flops : 64<br># Comparators : 6<br> 1-bit comparator not equal : 2<br> 7-bit comparator equal : 2<br> 8-bit comparator equal : 2<br># Xors : 4<br> 8-bit xor2 : 4<br><br>=========================================================================<br><br>=========================================================================<br>* Low Level Synthesis *<br>=========================================================================<br><br>Optimizing unit <generic_fifo_dc_gray> ...<br>INFO:Xst:2261 - The FF/Latch <rp_gray_7> in Unit <generic_fifo_dc_gray> is equivalent to the following FF/Latch, which will be removed : <rp_bin_7> <br>INFO:Xst:2261 - The FF/Latch <wp_gray_7> in Unit <generic_fifo_dc_gray> is equivalent to the following FF/Latch, which will be removed : <wp_bin_7> <br><br>Mapping all equations...<br>Building and optimizing final netlist ...<br>Found area constraint ratio of 100 (+ 5) on block generic_fifo_dc_gray, actual ratio is 0.<br><br>Final Macro Processing ...<br><br>=========================================================================<br>Final Register Report<br><br>Macro Statistics<br># Registers : 78<br> Flip-Flops : 78<br><br>=========================================================================<br><br>=========================================================================<br>* Partition Report *<br>=========================================================================<br><br>Partition Implementation Status<br>-------------------------------<br><br> No Partitions were found in this design.<br><br>-------------------------------<br><br>=========================================================================<br>* Design Summary *<br>=========================================================================<br><br>Top Level Output File Name : generic_fifo_dc_gray.ngc<br><br>Primitive and Black Box Usage:<br>------------------------------<br># BELS : 139<br># GND : 1<br># INV : 4<br># LUT1 : 12<br># LUT2 : 22<br># LUT3 : 14<br># LUT4 : 12<br># LUT5 : 12<br># LUT6 : 19<br># MUXCY : 24<br># VCC : 1<br># XORCY : 18<br># FlipFlops/Latches : 78<br># FD : 42<br># FDP : 4<br># FDR : 2<br># FDRE : 30<br># RAMS : 1<br># RAMB18E1 : 1<br><br>Device utilization summary:<br>---------------------------<br><br>Selected Device : 6vlx240tff1156-1 <br><br><br>Slice Logic Utilization: <br> Number of Slice Registers: 78 out of 301440 0% <br> Number of Slice LUTs: 95 out of 150720 0% <br> Number used as Logic: 95 out of 150720 0% <br><br>Slice Logic Distribution: <br> Number of LUT Flip Flop pairs used: 106<br> Number with an unused Flip Flop: 28 out of 106 26% <br> Number with an unused LUT: 11 out of 106 10% <br> Number of fully used LUT-FF pairs: 67 out of 106 63% <br> Number of unique control sets: 7<br><br>IO Utilization: <br> Number of IOs: 77<br> Number of bonded IOBs: 0 out of 600 0% <br><br>Specific Feature Utilization:<br> Number of Block RAM/FIFO: 1 out of 416 0% <br> Number using Block RAM only: 1<br><br>---------------------------<br>Partition Resource Summary:<br>---------------------------<br><br> No Partitions were found in this design.<br><br>---------------------------<br><br><br>=========================================================================<br>Timing Report<br><br>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<br> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<br> GENERATED AFTER PLACE-and-ROUTE.<br><br>Clock Information:<br>------------------<br>-----------------------------------+------------------------+-------+<br>Clock Signal | Clock buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>rd_clk | NONE(empty) | 40 |<br>wr_clk | NONE(full) | 40 |<br>-----------------------------------+------------------------+-------+<br>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<br><br>Asynchronous Control Signals Information:<br>----------------------------------------<br>-----------------------------------+------------------------+-------+<br>Control Signal | Buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>we_full_AND_3_o(we_full_AND_3_o1:O)| NONE(u0/Mram_RAM) | 8 |<br>-----------------------------------+------------------------+-------+<br><br>Timing Summary:<br>---------------<br>Speed Grade: -1<br><br> Minimum period: 2.978ns (Maximum Frequency: 335.796MHz)<br> Minimum input arrival time before clock: 1.589ns<br> Maximum output required time after clock: 0.742ns<br> Maximum combinational path delay: No path found<br><br>Timing Details:<br>---------------<br>All values displayed in nanoseconds (ns)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'rd_clk'<br> Clock period: 2.637ns (frequency: 379.219MHz)<br> Total number of paths / destination ports: 254 / 69<br>-------------------------------------------------------------------------<br>Delay: 2.637ns (Levels of Logic = 4)<br> Source: rp_bin_2 (FF)<br> Destination: empty (FF)<br> Source Clock: rd_clk rising<br> Destination Clock: rd_clk rising<br><br> Data Path: rp_bin_2 to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 9 0.375 0.634 rp_bin_2 (rp_bin_2)<br> LUT3:I0->O 3 0.068 0.431 Madd_rp_bin_next_cy<2>11 (Madd_rp_bin_next_cy<2>)<br> LUT6:I5->O 2 0.068 0.423 Madd_rp_bin_next_xor<7>11 (rp_bin_next<7>)<br> LUT6:I5->O 1 0.068 0.491 wp_s[7]_re_OR_8_o6_SW0 (N15)<br> LUT6:I4->O 1 0.068 0.000 wp_s[7]_re_OR_8_o7 (wp_s[7]_re_OR_8_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 2.637ns (0.658ns logic, 1.979ns route)<br> (25.0% logic, 75.0% route)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'wr_clk'<br> Clock period: 2.978ns (frequency: 335.796MHz)<br> Total number of paths / destination ports: 320 / 67<br>-------------------------------------------------------------------------<br>Delay: 2.978ns (Levels of Logic = 4)<br> Source: wp_bin_4 (FF)<br> Destination: full (FF)<br> Source Clock: wr_clk rising<br> Destination Clock: wr_clk rising<br><br> Data Path: wp_bin_4 to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 9 0.375 0.828 wp_bin_4 (wp_bin_4)<br> LUT6:I1->O 4 0.068 0.437 Madd_wp_bin_next_cy<5>11 (Madd_wp_bin_next_cy<5>)<br> LUT2:I1->O 1 0.068 0.638 Madd_wp_bin_next_xor<6>11 (wp_bin_next<6>)<br> LUT6:I2->O 1 0.068 0.417 wp_bin[6]_we_OR_15_o7 (wp_bin[6]_we_OR_15_o7)<br> LUT6:I5->O 1 0.068 0.000 wp_bin[6]_we_OR_15_o8 (wp_bin[6]_we_OR_15_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 2.978ns (0.658ns logic, 2.320ns route)<br> (22.1% logic, 77.9% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'rd_clk'<br> Total number of paths / destination ports: 37 / 36<br>-------------------------------------------------------------------------<br>Offset: 1.301ns (Levels of Logic = 2)<br> Source: re (PAD)<br> Destination: empty (FF)<br> Destination Clock: rd_clk rising<br><br> Data Path: re to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT6:I0->O 1 0.068 0.775 wp_s[7]_re_OR_8_o5 (wp_s[7]_re_OR_8_o5)<br> LUT6:I1->O 1 0.068 0.000 wp_s[7]_re_OR_8_o7 (wp_s[7]_re_OR_8_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 1.301ns (0.526ns logic, 0.775ns route)<br> (40.4% logic, 59.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk'<br> Total number of paths / destination ports: 37 / 36<br>-------------------------------------------------------------------------<br>Offset: 1.589ns (Levels of Logic = 3)<br> Source: we (PAD)<br> Destination: full (FF)<br> Destination Clock: wr_clk rising<br><br> Data Path: we to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT5:I0->O 1 0.068 0.581 wp_bin[6]_we_OR_15_o5 (wp_bin[6]_we_OR_15_o5)<br> LUT6:I3->O 1 0.068 0.417 wp_bin[6]_we_OR_15_o7 (wp_bin[6]_we_OR_15_o7)<br> LUT6:I5->O 1 0.068 0.000 wp_bin[6]_we_OR_15_o8 (wp_bin[6]_we_OR_15_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 1.589ns (0.591ns logic, 0.998ns route)<br> (37.2% logic, 62.8% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'rd_clk'<br> Total number of paths / destination ports: 36 / 36<br>-------------------------------------------------------------------------<br>Offset: 0.742ns (Levels of Logic = 0)<br> Source: u0/Mram_RAM (RAM)<br> Destination: dout<31> (PAD)<br> Source Clock: rd_clk rising<br><br> Data Path: u0/Mram_RAM to dout<31><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> RAMB18E1:CLKARDCLK->DOBDO15 0 0.742 0.000 u0/Mram_RAM (dout<31>)<br> ----------------------------------------<br> Total 0.742ns (0.742ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk'<br> Total number of paths / destination ports: 4 / 4<br>-------------------------------------------------------------------------<br>Offset: 0.375ns (Levels of Logic = 0)<br> Source: wr_level_1 (FF)<br> Destination: wr_level<1> (PAD)<br> Source Clock: wr_clk rising<br><br> Data Path: wr_level_1 to wr_level<1><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 0 0.375 0.000 wr_level_1 (wr_level_1)<br> ----------------------------------------<br> Total 0.375ns (0.375ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br><br>Cross Clock Domains Report:<br>--------------------------<br><br>Clock to Setup on destination clock rd_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.637| | | |<br>wr_clk | 0.818| | | |<br>---------------+---------+---------+---------+---------+<br><br>Clock to Setup on destination clock wr_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 1.598| | | |<br>wr_clk | 2.978| | | |<br>---------------+---------+---------+---------+---------+<br><br>=========================================================================<br><br><br>Total REAL time to Xst completion: 9.00 secs<br>Total CPU time to Xst completion: 9.49 secs<br> <br>--> <br><br><br>Total memory usage is 481856 kilobytes<br><br>Number of errors : 0 ( 0 filtered)<br>Number of warnings : 20 ( 0 filtered)<br>Number of infos : 4 ( 0 filtered)<br><br></PRE></FONT> |