URL
https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk
Subversion Repositories modular_oscilloscope
Compare Revisions
- This comparison shows the changes necessary to convert path
/modular_oscilloscope/trunk/hdl/ctrl
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/generic_decoder.vhd
16,7 → 16,7
--| 0.1 | jul-2009 | First release |
--| 0.2 | jul-2009 | New output code |
---------------------------------------------------------------------------------------------------- |
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|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
/memory_writer.vhd
14,7 → 14,7
--| File history: |
--| 0.1 | jul-2009 | First release |
---------------------------------------------------------------------------------------------------- |
|
|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
/data_skipper.vhd
14,7 → 14,7
--| File history: |
--| 0.1 | jul-2009 | First testing |
---------------------------------------------------------------------------------------------------- |
|
|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
/channel_selector.vhd
16,7 → 16,7
--| 0.1 | jul-2009 | First testing |
--| 0.2 | jul-2009 | Added generic number of channel |
---------------------------------------------------------------------------------------------------- |
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|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
/output_manager.vhd
3,7 → 3,7
--| UNSL - Argentine |
--| |
--| File: output_manager.vhd |
--| Version: 0.3 |
--| Version: 0.31 |
--| Tested in: Actel A3PE1500 |
--|------------------------------------------------------------------------------------------------- |
--| Description: |
15,19 → 15,20
--| 0.1 | jun-2009 | First testing |
--| 0.2 | jul-2009 | Two levels internal buffer |
--| 0.3 | jul-2009 | One level internal buffer and only one clock |
--| 0.31 | jul-2009 | Internal WE signals |
---------------------------------------------------------------------------------------------------- |
|
|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
|
--| Wishbone Rev. B.3 compatible |
---------------------------------------------------------------------------------------------------- |
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--================================================================================================== |
-- TODO |
-- Config WE signals |
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--================================================================================================== |
|
-- This first release |
|
library ieee; |
use ieee.std_logic_1164.all; |
40,7 → 41,7
---------------------------------------------------------------------------------------------------- |
entity output_manager is |
generic( |
MEM_ADD_WIDTH: integer := 14 |
MEM_ADD_WIDTH: integer := 14 |
); |
port( |
------------------------------------------------------------------------------------------------ |
80,7 → 81,7
-- when the buffer arrives here, address is changed to 0 (buffer size) |
final_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
-- address wich is being writed by control |
-- stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
-- it is set when communication ends and remains until next restart or actual address change |
finish: out std_logic |
|
92,7 → 93,9
---------------------------------------------------------------------------------------------------- |
architecture ARCH11 of output_manager is |
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type DataStatusType is ( |
RESET, |
INIT, -- when restartet |
159,10 → 162,14
ADR_O_mem <= address_counter; |
s_finish <= '1' when address_counter = initial_address and data_status /= INIT else |
'0'; |
enable_read <= enable and not(s_finish); |
enable_read <= '1' when enable = '1' and s_finish = '0' and address_counter /= stop_address |
else '0'; |
|
finish <= s_finish; |
WE_O_mem <= '0' ; |
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P_read: process(CLK_I, data_status, initial_address, address_counter, data, enable_read, |
ACK_I_mem, WE_I_port) |
begin |
173,6 → 180,7
case data_status is |
|
when RESET => |
|
data <= (others => '0'); |
address_counter <= initial_address; |
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/generic_counter.vhd
15,7 → 15,7
--| File history: |
--| 0.1 | jul-2009 | First release |
---------------------------------------------------------------------------------------------------- |
|
|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
/trigger_manager.vhd
14,7 → 14,7
--| File history: |
--| 0.1 | jul-2009 | First release |
---------------------------------------------------------------------------------------------------- |
|
|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |