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URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

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  • This comparison shows the changes necessary to convert path 
    /modular_oscilloscope/trunk/hdl/ctrl
    from Rev 36 to Rev 37
    ↔ Reverse comparison
  •

Rev 36 → Rev 37

/generic_decoder.vhd
65,7 → 65,7
begin
P_convertion: process (data_I, enable_I)
P_main: process (data_I, enable_I)
variable i: integer range 0 to decoded_O'length-1;
begin
for i in 0 to decoded_O'length-1 loop
/memory_writer.vhd
2,7 → 2,7
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: memory_writer.vhd
--| File: ctrl_memory_writer.vhd
--| Version: 0.1
--| Tested in: Actel A3PE1500
--|-------------------------------------------------------------------------------------------------
36,7 → 36,7
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
entity memory_writer is
entity ctrl_memory_writer is
generic(
MEM_ADD_WIDTH: integer := 14
);
67,30 → 67,22
------------------------------------------------------------------------------------------------
-- Internal
-- reset counter(memory address) to 0
-- reset memory address to 0
reset_I: in std_logic;
-- read in clk edge from the actual address ('0' means pause, '1' means continue)
enable_I: in std_logic;
-- buffer starts and ends here
-- when the buffer arrives here, address is changed to 0 (buffer size)
final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
-- address wich is being writed by control
-- stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
-- it is set when communication ends and remains until next restart or actual address change
finished_O: out std_logic;
-- When counter finishes, restart
-- when counter finishes, restart
continuous_I: in std_logic;
);
end entity memory_writer;
end entity ctrl_memory_writer;
 
 
 
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
architecture ARCH11 of output_manager is
architecture ARCH11 of ctrl_output_manager is
type DataStatusType is (
INIT,
110,7 → 102,7
begin
--------------------------------------------------------------------------------------------------
-- Instantiations
-- Instances
U_COUNTER0: generic_counter
generic map(
OUTPUT_WIDTH => MEM_ADD_WIDTH -- Output width for counter.
153,7 → 145,7
P_cyc_signals: process (clk_I, enable_count, ACK_I_adc, ACK_I_mem)
begin
if CLK_I'event and CLK_I = '1' then
if enable_I /= '1' or reset_I = '1' then
if enable_I = '0' or reset_I = '1' then
CYC_O_adc <= '0'; CYC_O_mem <= '0';
else
CYC_O_adc <= '1'; CYC_O_mem <= '1';
/data_skipper.vhd
2,9 → 2,10
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: data_skipper.vhd
--| Version: 0.1
--| File: ctrl_data_skipper.vhd
--| Version: 0.12
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--| CONTROL - Data skipper
13,6 → 14,8
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.1 | jul-2009 | First testing
--| 0.11 | jul-2009 | Added input signal indicating when it's selected the first channel
--| 0.12 | jul-2009 | Optimized
----------------------------------------------------------------------------------------------------
 
--|
40,7 → 43,7
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
entity data_skipper is
entity ctrl_data_skipper is
generic(
-- max losses = 2**(2**SELECTOR_WIDTH). (i.e., if SELECTOR_WIDTH = 5: 4.2950e+09)
SELECTOR_WIDTH: integer := 5
55,19 → 58,23
-- enable from register
enable_skipper_I: in std_logic;
-- common signals
reset_I, clk_I: in std_logic
reset_I, clk_I: in std_logic;
first_channel_I: in std_logic
);
end entity data_skipper;
end ctrl_entity data_skipper;
 
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
architecture ARCH10 of data_skipper is
architecture ARCH10 of ctrl_data_skipper is
signal count: std_logic_vector( integer(2**real(SELECTOR_WIDTH))-1 downto 0);
signal decoded: std_logic_vector( integer(2**real(SELECTOR_WIDTH))-1 downto 0);
signal anded: std_logic_vector( integer(2**real(SELECTOR_WIDTH))-1 downto 0);
signal reset_count: std_logic;
signal match: std_logic;
signal enable_count: std_logic;
begin
 
U_COUNTER0: generic_counter
91,11 → 98,12
decoded_O => decoded
);
 
match <= '1' when decoded <= count else
anded <= decoded and count;
match <= '1' when anded = std_logic_vector(to_unsigned(0,integer(2**real(SELECTOR_WIDTH)))) else
'0' ;
reset_count <= match or reset_I;
enable_count <= stb_I and ack_I and enable_skipper_I;
 
reset_count <= reset_I;
enable_count <= stb_I and ack_I and enable_skipper_I and first_channel_I;
ack_O <= stb_I and ack_I and (match or not(enable_skipper_I)) and not(reset_I);
 
/output_manager.vhd
2,9 → 2,10
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: output_manager.vhd
--| File: ctrl_output_manager.vhd
--| Version: 0.5
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--| CONTROL - Output manager
26,8 → 27,8
 
 
--==================================================================================================
-- TODO
 
-- TO DO
 
 
--==================================================================================================
 
41,7 → 42,7
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
entity output_manager is
entity ctrl_output_manager is
generic(
MEM_ADD_WIDTH: integer := 14
);
84,33 → 85,32
initial_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
-- buffer starts and ends here
biggest_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
biggest_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
-- when the buffer arrives here, address is changed to 0 (buffer size)
pause_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
pause_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
-- address wich is being writed by control
finish_O: out std_logic
-- it is set when communication ends and remains until next restart or actual address change
);
end entity output_manager;
end entity ctrl_output_manager;
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
architecture ARCH20 of output_manager is
architecture ARCH20 of ctrl_output_manager is
signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
signal enable_read: std_logic;
signal enable_count: std_logic;
signal s_finish: std_logic; -- register previous (and equal) to output
signal init: std_logic; -- register
 
begin
--------------------------------------------------------------------------------------------------
-- Wishbone signals
DAT_O_port <= DAT_I_mem;
CYC_O_mem <= CYC_I_port;
STB_O_mem <= STB_I_port and enable_read;
120,11 → 120,10
--------------------------------------------------------------------------------------------------
-- Status signals
enable_read <= '1' when enable_I = '1' and s_finish = '0' and address_counter /= pause_address_I
and WE_I_port = '0'
enable_read <= '1' when enable_I = '1' and WE_I_port = '0' and s_finish = '0' and
(address_counter /= pause_address_I or init = '1')
else '0';
 
enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
finish_O <= s_finish;
131,31 → 130,33
 
P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
begin
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
if RST_I = '1' then
s_finish <= '1';
init <= '0';
elsif load_I = '1' then
s_finish <= '0';
elsif address_counter = initial_address_I then
init <= '1';
elsif address_counter + 1 = initial_address_I then
s_finish <= '1';
end if;
init <= '0';
else
init <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------
-- Address counter
P_count: process(CLK_I, address_counter, enable_count, load_I)
begin
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
if load_I = '1' then
address_counter <= initial_address_I;
elsif enable_count = '1' then
if address_counter >= biggest_address_I then
address_counter <= (others => '0');
else
address_counter <= address_counter + 1;
end if;
elsif enable_count = '1' and address_counter >= biggest_address_I then
address_counter <= (others => '0');
elsif enable_count = '1' then
address_counter <= address_counter + 1;
end if;
end if;
end process;
/trigger_manager.vhd
2,7 → 2,7
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: trigger_manager.vhd
--| File: ctrl_trigger_manager.vhd
--| Version: 0.1
--| Tested in: Actel A3PE1500
--|-------------------------------------------------------------------------------------------------
33,7 → 33,7
use IEEE.NUMERIC_STD.ALL;
 
 
entity trigger_manager is
entity ctrl_trigger_manager is
generic (
MEM_ADD_WIDTH: integer := 14;
DATA_WIDTH: integer := 10;
60,9 → 60,9
address_O: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0)
);
 
end entity trigger_manager;
end entity ctrl_trigger_manager;
 
architecture arch01_trigger of trigger_manager is
architecture arch01_trigger of ctrl_trigger_manager is
-- trigger process signals
signal higher, higher_reg: std_logic;
signal pre_trigger: std_logic;

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