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  • This comparison shows the changes necessary to convert path 
    /modular_oscilloscope/trunk/hdl/ctrl
    from Rev 52 to Rev 54
    ↔ Reverse comparison
  •

Rev 52 → Rev 54

/ctrl.vhd
340,7 → 340,7
------------------------------------------------------------------------------------------------
-- Machine
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr, reg_trigger_en,
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr,
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
begin
-- signals from output manager are described in next process
407,7 → 407,7
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
running <= '1'; -- aviod an ack if there is a read/write from port
strobe_adc <= '0';
426,7 → 426,7
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
running <= '1'; -- aviod an ack if there is a read/write from port
strobe_adc <= '1';
449,7 → 449,7
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
running <= '0';
strobe_adc <= '0';
482,10 → 482,11
------------------------------------------------------------------------------------------------
-- Output
P_OUTMGR: process (RST_I_port, stop, CLK_I_port, CLK_I_port, present_state, trigger_act,
P_OUTMGR: process (RST_I_port, stop, CLK_I_port, present_state, trigger_act,
reg_trigger_en, memwr_out_adr, outmgr_en)
begin
if RST_I_port = '1' or present_state = ST_IDLE or present_state = ST_INIT then
-- load must be '1' only for one cycle, enable must be set until the end
if RST_I_port = '1' or present_state /= ST_RUNNING then
outmgr_load <= '0';
outmgr_en <= '0';
elsif CLK_I_port'event and CLK_I_port = '1' then
492,13 → 493,13
if stop = '1' then
outmgr_load <= '0';
outmgr_en <= '0';
elsif outmgr_en = '1' then
outmgr_load <= '0';
elsif present_state = ST_RUNNING and ( trigger_act = '1' or (reg_trigger_en = '0' and
memwr_out_adr /= 0 ) ) then
outmgr_load <= '1';
outmgr_en <= '1';
-- load must be set only one cycle
elsif outmgr_en = '1' then
outmgr_load <= '0';
end if;
end if;
end process;
/ctrl_pkg.vhd
169,7 → 169,7
);
port(
channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
channel_number_O: out std_logic_vector(3 downto 0);
channel_number_O: out std_logic_vector(CHANNEL_WIDTH - 1 downto 0);
first_channel_O: out std_logic;
clk_I: in std_logic;
enable_I: in std_logic;
/channel_selector.vhd
43,7 → 43,7
----------------------------------------------------------------------------------------------------
entity ctrl_channel_selector is
generic(
CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
);
port(
channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
/address_allocation.vhd
190,7 → 190,8
--------------------------------------------------------------------------------------------------
-- Read asignments
-- if reading registers, do ack, else use internal ack
ACK_O_port <= CYC_I_port and STB_I_port and (not(ADR_I_port(3)) or ACK_I_int or not(running_I));
ACK_O_port <= (CYC_I_port and STB_I_port) and
((not(ADR_I_port(3)) or ACK_I_int or not(running_I)));
--------------------------------------------------------------------------------------------------
225,7 → 226,12
buffer_size_R <= (others => '0');
trigger_level_R <= (others => '0');
trigger_offset_R <= (others => '0');
trigger_channel_R <= (others => '0');
write_in_adc_R <= '0';
adc_conf_R <= (others => '0');
-- Assignments
elsif CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '1' and ADR_I_port(3) = '0' then
/output_manager.vhd
3,7 → 3,7
--| UNSL - Argentine
--|
--| File: ctrl_output_manager.vhd
--| Version: 0.5
--| Version: 0.54
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
18,6 → 18,7
--| 0.3 | jul-2009 | One level internal buffer and only one clock
--| 0.31 | jul-2009 | Internal WE signals
--| 0.5 | jul-2009 | Architecture completely renovated (reduced)
--| 0.54 | aug-2009 | New finish_O and init flag behavior
----------------------------------------------------------------------------------------------------
 
--|
28,8 → 29,10
 
--==================================================================================================
-- TO DO
 
 
-- NO Speed up address_counter
-- OK Full test of new architecture
-- OK Fix default value of s_finish signal
 
--==================================================================================================
 
 
99,7 → 102,7
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
architecture ARCH20 of ctrl_output_manager is
architecture ARCH22 of ctrl_output_manager is
signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
signal enable_read: std_logic;
120,6 → 123,7
--------------------------------------------------------------------------------------------------
-- Status signals
-- there is an init signal because in the first read, address_counter may be = to pause_address_I
enable_read <= '1' when enable_I = '1' and WE_I_port = '0' and s_finish = '0' and
(address_counter /= pause_address_I or init = '1')
else '0';
127,36 → 131,43
enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
finish_O <= s_finish;
s_finish <= '1' when address_counter = initial_address_I and init = '0' else
'0';
 
P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
begin
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
if RST_I = '1' then
s_finish <= '1';
init <= '0';
elsif load_I = '1' then
s_finish <= '0';
init <= '1';
elsif address_counter + 1 = initial_address_I then
s_finish <= '1';
init <= '0';
else
init <= '0';
end if;
end if;
end process;
-- P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
-- begin
-- if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
-- if RST_I = '1' then
-- --s_finish <= '0'; -- !! enable signal must be '0' until load
-- init <= '0';
-- elsif load_I = '1' then
-- --s_finish <= '0';
-- init <= '1';
-- -- elsif address_counter + 1 = initial_address_I then
-- -- s_finish <= '1';
-- -- init <= '0';
-- elsif enable_count = '1' then
-- init <= '0';
-- end if;
-- end if;
-- end process;
--------------------------------------------------------------------------------------------------
-- Address counter
P_count: process(CLK_I, address_counter, enable_count, load_I)
P_count: process(CLK_I, RST_I, address_counter, enable_count, load_I)
begin
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
if load_I = '1' then
if RST_I = '1' then
address_counter <= (others => '0');
init <= '1';
elsif load_I = '1' then
address_counter <= initial_address_I;
init <= '1';
elsif enable_count = '1' and address_counter >= biggest_address_I then
address_counter <= (others => '0');
elsif enable_count = '1' then
address_counter <= address_counter + 1;
init <= '0';
end if;
end if;
end process;

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