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https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk
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/modular_oscilloscope/trunk/hdl/ctrl
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- ↔ Reverse comparison
Rev 55 → Rev 56
/tbench/output_manager_tbench_text.vhd
0,0 → 1,357
-------------------------------------------------------------------------------------------------100 |
--| Modular Oscilloscope |
--| UNSL - Argentine |
--| |
--| File: ctrl_output_manager_tbench_text.vhd |
--| Version: 0.01 |
--| Tested in: Actel A3PE1500 |
--|------------------------------------------------------------------------------------------------- |
--| Description: |
--| This file is only for test purposes. |
--|------------------------------------------------------------------------------------------------- |
--| File history: |
--| 0.01 | jul-2009 | First release |
---------------------------------------------------------------------------------------------------- |
|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
---------------------------------------------------------------------------------------------------- |
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-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.math_real.all; |
|
entity ctrl_tb_simple_clock is |
port ( |
CLK_PERIOD: in time;-- := 20 ns; |
CLK_DUTY: in real; -- := 0.5; |
active: in boolean; |
clk_o: out std_logic |
); |
end entity ctrl_tb_simple_clock ; |
|
architecture beh of ctrl_tb_simple_clock is |
begin |
P_main: process |
begin |
wait until active; |
while (active = true) loop |
clk_o <= '0'; |
wait for CLK_PERIOD * (100.0 - clk_Duty)/100.0; |
clk_o <= '1'; |
wait for CLK_PERIOD * clk_Duty/100.0; |
end loop; |
clk_o <= '0'; |
wait; |
end process; |
end architecture beh; |
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-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> |
library ieee, std; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use IEEE.NUMERIC_STD.ALL; |
|
|
-- Additional libraries used by Model Under Test. |
use ieee.math_real.all; |
|
entity stimulus is |
generic( |
MEM_ADD_WIDTH: integer := 14 |
); |
port( |
ACK_I_mem: inout std_logic ; |
DAT_I_mem: inout std_logic_vector (15 downto 0); |
|
CYC_I_port: inout std_logic; |
STB_I_port: inout std_logic; |
WE_I_port: inout std_logic; |
RST_I: inout std_logic; |
CLK_I: inout std_logic; |
|
load_I: inout std_logic; |
enable_I: inout std_logic; |
initial_address_I: inout std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
biggest_address_I: inout std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
pause_address_I: inout std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
|
finish_O: in std_logic; |
CYC_O_mem: in std_logic; |
STB_O_mem: in std_logic; |
ADR_O_mem: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0) |
); |
|
end stimulus; |
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architecture STIMULATOR of stimulus is |
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-- Control Signal Declarations |
signal tb_InitFlag : boolean := false; |
signal tb_ParameterInitFlag : boolean := false; |
signal i: std_logic; |
|
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-- Parm Declarations |
signal clk_Duty : real := 0.0; |
signal clk_Period : time := 0 ns; |
|
|
begin |
-------------------------------------------------------------------------------------------------- |
-- Parm Assignment Block |
AssignParms : process |
variable clk_Duty_real : real; |
variable clk_Period_real : real; |
begin |
-- Basic parameters |
clk_Period_real := 20.0; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<-- |
clk_Period <= clk_Period_real * 1 ns; |
clk_Duty_real := 50.0; |
clk_Duty <= clk_Duty_real; |
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tb_ParameterInitFlag <= true; |
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wait; |
end process; |
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-------------------------------------------------------------------------------------------------- |
-- Clocks |
-- Clock Instantiation |
tb_clk: entity work.tb_simple_clock |
port map ( |
clk_Period => clk_Period, |
clk_Duty => clk_Duty, |
active => tb_InitFlag, |
clk_o => CLK_I |
); |
|
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-------------------------------------------------------------------------------------------------- |
-- Clocked Sequences |
|
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-------------------------------------------------------------------------------------------------- |
-- Sequence: Unclocked |
Unclocked : process |
|
begin |
wait until tb_ParameterInitFlag; |
tb_InitFlag <= true; |
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load_I <= '0'; |
RST_I <= '1'; |
STB_I_port <= '1'; |
CYC_I_port <= '1'; |
WE_I_port <= '0'; |
initial_address_I <= B"01_0000_0000_0000"; |
biggest_address_I <= B"11_1100_0000_0000"; |
pause_address_I <= B"00_0000_1000_0000"; |
enable_I <= '1'; |
wait for 1.5 * clk_Period; |
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RST_I <= '0'; |
wait for 1.0 * clk_Period; |
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load_I <= '1'; |
wait for 1.0 * clk_Period; |
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load_I <= '0'; |
wait until ADR_O_mem = B"00_0000_1000_0000"; |
wait for 8.0 * clk_Period; |
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pause_address_I <= B"01_0000_0000_0000"; |
wait for 20.0 * clk_Period; |
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enable_I <= '0'; |
wait for 8.0 * clk_Period; |
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enable_I <= '1'; |
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wait until finish_O = '1'; |
wait for 2.0 * clk_Period; |
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tb_InitFlag <= false; |
wait; |
|
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end process; |
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-------------------------------------------------------------------------------------------------- |
-- Conditional signals |
|
P_mem: process(STB_O_mem, DAT_I_mem, CYC_O_mem, CLK_I, RST_I,i) |
|
begin |
if STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then |
ACK_I_mem <= '1'; |
else |
ACK_I_mem <= '0'; |
end if; |
|
if CLK_I'event and CLK_I = '1' then |
if RST_I = '1' then |
DAT_I_mem <= (others => '0'); |
elsif STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then |
DAT_I_mem <= DAT_I_mem + 1; |
end if; |
end if; |
|
if CLK_I'event and CLK_I = '1' then |
if RST_I = '1' then |
i <= '0'; |
elsif STB_O_mem = '1' and CYC_O_mem = '1' then |
i <= not(i); |
end if; |
end if; |
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end process; |
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end architecture STIMULATOR; |
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-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> |
library ieee, std; |
use ieee.std_logic_1164.all; |
|
|
|
-- Additional libraries used by Model Under Test. |
-- ... |
|
entity testbench is |
generic ( |
MEM_ADD_WIDTH: integer := 14 |
); |
end testbench; |
|
architecture tbGeneratedCode of testbench is |
signal DAT_I_mem: std_logic_vector (15 downto 0); |
signal ADR_O_mem: std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
signal CYC_O_mem: std_logic; |
signal STB_O_mem: std_logic; |
signal ACK_I_mem: std_logic ; |
signal WE_O_mem: std_logic; |
signal DAT_O_port: std_logic_vector (15 downto 0); |
signal CYC_I_port: std_logic; |
signal STB_I_port: std_logic; |
signal ACK_O_port: std_logic ; |
signal WE_I_port: std_logic; |
signal RST_I: std_logic; |
signal CLK_I: std_logic; |
signal load_I: std_logic; |
signal enable_I: std_logic; |
signal initial_address_I: std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
signal biggest_address_I: std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
signal pause_address_I: std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); |
signal finish_O: std_logic; |
|
begin |
-------------------------------------------------------------------------------------------------- |
-- Instantiation of Stimulus. |
U_stimulus_0 : entity work.stimulus |
generic map ( |
MEM_ADD_WIDTH=> MEM_ADD_WIDTH |
) |
port map ( |
ACK_I_mem => ACK_I_mem, |
DAT_I_mem => DAT_I_mem, |
CYC_I_port => CYC_I_port, |
STB_I_port => STB_I_port, |
WE_I_port => WE_I_port, |
RST_I => RST_I, |
CLK_I => CLK_I, |
load_I => load_I, |
enable_I => enable_I, |
initial_address_I => initial_address_I, |
biggest_address_I => biggest_address_I, |
pause_address_I => pause_address_I, |
|
|
finish_O => finish_O, |
CYC_O_mem => CYC_O_mem, |
STB_O_mem => STB_O_mem, |
ADR_O_mem => ADR_O_mem |
); |
|
-------------------------------------------------------------------------------------------------- |
-- Instantiation of Model Under Test. |
U_outman_0 : entity work.output_manager --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<-- |
generic map ( |
|
MEM_ADD_WIDTH=> MEM_ADD_WIDTH |
) |
port map ( |
DAT_I_mem => DAT_I_mem, |
ADR_O_mem => ADR_O_mem, |
CYC_O_mem => CYC_O_mem, |
STB_O_mem => STB_O_mem, |
ACK_I_mem => ACK_I_mem, |
WE_O_mem => WE_O_mem, |
DAT_O_port => DAT_O_port, |
CYC_I_port => CYC_I_port, |
STB_I_port => STB_I_port, |
ACK_O_port => ACK_O_port, |
WE_I_port => WE_I_port, |
RST_I => RST_I, |
CLK_I => CLK_I, |
load_I => load_I, |
enable_I => enable_I, |
initial_address_I => initial_address_I, |
biggest_address_I => biggest_address_I, |
pause_address_I => pause_address_I, |
finish_O => finish_O |
); |
|
-- U_mem0: entity work.dual_port_memory_wb |
-- port map( |
-- -- Port A (Higer prioriry) |
-- RST_I_a => '0', |
-- CLK_I_a => '0', |
-- DAT_I_a => (others => '0'), |
-- DAT_O_a => open, |
-- ADR_I_a => '0', |
-- CYC_I_a => '0', |
-- STB_I_a => '0', |
-- ACK_O_a => open, |
-- WE_I_a => '0', |
-- |
-- -- Port B (Lower prioriry) |
-- RST_I_b => RST_I, |
-- CLK_I_b => CLK_I, |
-- DAT_I_b => (others => '0'), |
-- DAT_O_b => DAT_I_mem, |
-- ADR_I_b => ADR_O_mem, |
-- CYC_I_b => CYC_O_mem, |
-- STB_I_b => STB_O_mem, |
-- ACK_O_b => ACK_I_mem, |
-- WE_I_b => WE_O_mem |
-- ); |
|
end tbGeneratedCode; |
---------------------------------------------------------------------------------------------------- |
tbench/output_manager_tbench_text.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ctrl.vhd
===================================================================
--- ctrl.vhd (revision 55)
+++ ctrl.vhd (revision 56)
@@ -158,7 +158,8 @@
--------------------------------------------------------------------------------------------------
-- Flags
- signal running: std_logic;
+ signal status: std_logic_vector(1 downto 0);
+ signal next_status1: std_logic;
signal stop: std_logic;
signal start: std_logic;
signal continuous: std_logic;
@@ -314,13 +315,12 @@
trigger_channel_O => reg_trigger_channel,
error_number_I => "000", -- not implemented yet
- error_flag_I => '0', -- not implemented yet
adc_conf_O => dat_to_adc,
start_O => start,
continuous_O => continuous,
- running_I => running,
+ status_I => status,
write_in_adc_O => write_in_adc,
stop_O => stop
);
@@ -360,12 +360,14 @@
trigger_reset <= '1';
trigger_en <= '-';
- running <= '1';
+ status(0) <= '1';
+ next_status1 <= not(next_status1); -- will be changed every buffer full read
strobe_adc <= '0';
-- -- -- --
next_state <= ST_RUNNING;
+ -- if there is an error manager, influde an if for errors in parameters
when ST_RUNNING =>
@@ -384,11 +386,13 @@
trigger_reset <= '0';
trigger_en <= reg_trigger_en and memwr_in_ack_mem;
- running <= '1';
+ status(0) <= '1';
+ next_status1 <= status(1);
strobe_adc <= '0';
-- -- -- --
+ -- if there is an error manager, influde an if for errors in running, etc...
if outmgr_finish = '1' then
if continuous = '1' then
next_state <= ST_INIT;
@@ -410,7 +414,8 @@
trigger_reset <= '1';
trigger_en <= '-';
- running <= '1'; -- aviod an ack if there is a read/write from port
+ status(0) <= '1'; -- aviod an ack if there is a read/write from port
+ next_status1 <= status(1);
strobe_adc <= '0';
@@ -429,7 +434,8 @@
trigger_reset <= '1';
trigger_en <= '-';
- running <= '1'; -- aviod an ack if there is a read/write from port
+ status(0) <= '1'; -- aviod an ack if there is a read/write from port
+ next_status1 <= status(1);
strobe_adc <= '1';
@@ -452,7 +458,8 @@
trigger_reset <= '1';
trigger_en <= '-';
- running <= '0';
+ status(0) <= '0';
+ next_status1 <= '0'; -- or error when there is an error manager
strobe_adc <= '0';
@@ -467,8 +474,11 @@
P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc)
begin
- if RST_I_daq = '1' or stop = '1' then
+ if RST_I_daq = '1' then
present_state <= ST_IDLE;
+ status(1) <= '0';
+ elsif stop = '1' then
+ present_state <= ST_IDLE;
elsif write_in_adc = '1' then
present_state <= ST_ADCWRITE_INIT;
elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
@@ -475,6 +485,7 @@
present_state <= ST_INIT;
elsif CLK_I_daq'event and CLK_I_daq = '1' then
present_state <= next_state;
+ status(1) <= next_status1;
end if;
/ctrl_pkg.vhd
244,8 → 244,7
adc_conf_O: out std_logic_vector(15 downto 0); |
|
error_number_I: in std_logic_vector (2 downto 0); |
running_I: in std_logic; |
error_flag_I: in std_logic; |
status_I: in std_logic_vector(1 downto 0); |
|
write_in_adc_O: out std_logic; |
stop_O: out std_logic |
/address_allocation.vhd
14,6 → 14,7
--|------------------------------------------------------------------------------------------------- |
--| File history: |
--| 0.1 | jul-2009 | First testing |
--| 0.2 | aug-2009 | New status flag |
---------------------------------------------------------------------------------------------------- |
|
--| |
51,7 → 52,7
-- 05 ADCConf RW [ | | | | ADCS|ADSleep| ADPSEn| ADPS08| |
-- ADPS07| ADPS06| ADPS05| ADPS04| ADPS03| ADPS02| ADPS01| ADPS00] |
-- |
-- 08 Data_O R [ErrFlag|RunFlag| | | | DCh00| Dat09| Dat08| |
-- 08 Data_O R [StatF01|StatF00| | | | DCh00| Dat09| Dat08| |
-- Dat07| Dat06| Dat05| Dat04| Dat03| Dat02| Dat01| Dat00] |
-- |
-- 09 Error_O R [ | | | | | | | | |
60,7 → 61,11
-- |
-- |
-- Description |
-- |
-- StatF01|StatF00| |
-- 00 Stoped |
-- 01 Running, odd buffer |
-- 11 Running, pair buffer |
-- 10 Stoped, with error |
--================================================================================================== |
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|
121,8 → 126,7
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error_number_I: in std_logic_vector (2 downto 0); |
--data_channel_I: in std_logic; |
running_I: in std_logic; |
error_flag_I: in std_logic; |
status_I: in std_logic_vector(1 downto 0); |
|
write_in_adc_O: out std_logic; |
stop_O: out std_logic |
181,7 → 185,7
o_selector(7) <= (others => '0'); |
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o_selector(8) <= error_flag_I & running_I & (13 downto 11 => '0') & data_channel & data; |
o_selector(8) <= status_I & (13 downto 11 => '0') & data_channel & data; |
o_selector(9) <= (15 downto 3 => '0') & error_number_I; |
|
DAT_O_port <= o_selector(conv_integer(ADR_I_port)); |
191,7 → 195,7
-- Read asignments |
-- if reading registers, do ack, else use internal ack |
ACK_O_port <= (CYC_I_port and STB_I_port) and |
((not(ADR_I_port(3)) or ACK_I_int or not(running_I))); |
((not(ADR_I_port(3)) or ACK_I_int or not(status_I(0)))); |
|
|
-------------------------------------------------------------------------------------------------- |