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  • This comparison shows the changes necessary to convert path 
    /modular_oscilloscope/trunk/hdl/ctrl
    from Rev 56 to Rev 57
    ↔ Reverse comparison
  •

Rev 56 → Rev 57

/ctrl.vhd
24,7 → 24,7
 
--==================================================================================================
-- TO DO
 
 
--==================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
173,7 → 173,7
--------------------------------------------------------------------------------------------------
-- Instances
U_OUTMGR0: ctrl_output_manager
U_CTRL_OUTMGR0: ctrl_output_manager
generic map(
MEM_ADD_WIDTH => 14 --: integer := 14
)
344,7 → 344,7
------------------------------------------------------------------------------------------------
-- Machine
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr,
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq,next_status1,trigger_act)
begin
-- signals from output manager are described in next process
case present_state is
361,13 → 361,20
trigger_en <= '-';
status(0) <= '1';
next_status1 <= not(next_status1); -- will be changed every buffer full read
-- next_status1: above
strobe_adc <= '0';
-- -- -- --
next_state <= ST_RUNNING;
-- if there is an error manager, influde an if for errors in parameters
if outmgr_finish = '0' then
next_state <= ST_RUNNING;
next_status1 <= not(status(1)); -- will be changed every buffer full read
else
next_state <= ST_INIT;
next_status1 <= status(1);
end if;
-- if there is an error manager, include "if" for errors in parameters
when ST_RUNNING =>
471,7 → 478,7
 
P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc)
P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc,next_status1)
begin
if RST_I_daq = '1' then
479,10 → 486,13
status(1) <= '0';
elsif stop = '1' then
present_state <= ST_IDLE;
status(1) <= '0';
elsif write_in_adc = '1' then
present_state <= ST_ADCWRITE_INIT;
status(1) <= next_status1;
elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
present_state <= ST_INIT;
status(1) <= next_status1;
elsif CLK_I_daq'event and CLK_I_daq = '1' then
present_state <= next_state;
status(1) <= next_status1;
/address_allocation.vhd
3,29 → 3,34
--| UNSL - Argentine
--|
--| File: ctrl_address_allocation.vhd
--| Version: 0.1
--| Version: 0.21
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--| CONTROL - Address allocations
--| Registers and intercomunications.
--|
--|
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.1 | jul-2009 | First testing
--| 0.2 | aug-2009 | New status flag
--| 0.21 | sep-2009 | Smarter stop signal
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
--| Wishbone Rev. B.3 compatible
----------------------------------------------------------------------------------------------------
 
 
 
--==================================================================================================
-- TO DO
 
-- [OK] Finish ADC conf write
 
--==================================================================================================
 
 
205,7 → 210,17
--------------------------------------------------------------------------------------------------
-- Stop signal
stop_O <= CYC_I_port and STB_I_port and WE_I_port;
-- It asserts when there is a write in the confing registers
P_stop: process (CLK_I, STB_I_port, WE_I_port, status_I, ADR_I_port)
begin
if CLK_I'event and CLK_I = '1' then
if status_I(0) = '0' then
stop_O <= '0';
elsif CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '1' and ADR_I_port(3) = '0' then
stop_O <= '1';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------
-- DAT_I

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