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Rev 15 → Rev 16

/eppwbn_ctrl.vhd
0,0 → 1,190
--|------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.20
--| Targeted device: Actel A3PE1500
--|-----------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| This module controls the negotiation (IEEE Std. 1284-2000).
--| This can be easily modified to control other modes besides the EPP.
-------------------------------------------------------------------------------
--| File history:
--| 0.01 | nov-2008 | First testing release
--| 0.20 | dic-2008 | Customs signals without tri-state
--| 0.21 | jan-2009 | Sinc reset
--------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity eppwbn_ctrl is
port(
 
-- salida al puerto epp
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284-2000,
-- Negotiation/ECP/EPP (Compatibiliy)
-- HostClk/nWrite
Data: in std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
-- Busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select). Select no puede usarse
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- HostLogicH: in std_logic; -- (Host Logic High)
 
-- salida a la interface wishbone
RST_I: in std_logic;
CLK_I: in std_logic;
 
 
rst_pp: out std_logic; -- generador de reset desde la interfaz del puerto paralelo
epp_mode: out std_logic_vector (1 downto 0) -- indicador de modo de comunicaci?n epp
-- "00" deshabilitado
-- "01" inicial (se?ales de usuario e interrupciones deshabilitadas)
-- "10" sin definir
-- "11" modo EPP normal
);
end entity eppwbn_ctrl;
 
 
architecture state_machines of eppwbn_ctrl is
type StateType is (
st_compatibility_idle, -- Los estados corresponden a los especificados
st_negotiation2, -- por el est?ndar.
-- Los n?meros de los estados negotiation corresponden
-- a las fases del est?ndar.
st_initial_epp,
st_epp_mode
-- otros modos
);
signal next_state, present_state: StateType;
signal ext_req_val: std_logic_vector (7 downto 0);
begin
----------------------------------------------------------------------------------------
 
rst_pp <= not(nInit) and not(nSelectIn); -- (nInit = '0') and (nSelectIn = '0');
PeriphLogicH <= '1';
----------------------------------------------------------------------------------------
 
P_data_store: process(nStrobe, present_state, Data, RST_I, nInit, nSelectIn)
begin
if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then
ext_req_val <= (others => '0');
elsif (present_state = st_negotiation2 and nStrobe'event and nStrobe = '0') then
ext_req_val <= Data;
end if;
end process P_data_store;
----------------------------------------------------------------------------------------
-- estado siguiente
P_state_comb: process(present_state, next_state, RST_I, nSelectIn, nAutoFd, ext_req_val, nInit, nStrobe) begin
if RST_I = '1' then
next_state <= st_compatibility_idle;
else
case present_state is
when st_compatibility_idle =>
PError <= '0';
nFault <= '1';
Sel <= '1';
nAck <= '1';
epp_mode <= "00";
 
if (nAutoFd = '0' and nSelectIn = '1') then
next_state <= st_negotiation2;
else
next_state <= st_compatibility_idle;
end if;
when st_negotiation2 =>
PError <= '1';
nFault <= '1';
Sel <= '1';
nAck <= '0';
epp_mode <= "00";
-- Reconocimiento del host
if (nStrobe = '1' and
nAutoFd = '1') then
-- Pedido de modo EPP
if (ext_req_val = "01000000") then
next_state <= st_initial_epp;
-- Otros modos
else
next_state <= st_compatibility_idle;
end if;
else
next_state <= st_negotiation2;
end if;
when st_initial_epp =>
Sel <= '1';
PError <= '1';
nFault <= '1';
nAck <= '1';
epp_mode <= "01";
-- Finalizaci?n del modo EPP
if nInit = '0' then
next_state <= st_compatibility_idle;
-- Comienzo del primer ciclo EPP
elsif (nSelectIn = '0' or nAutoFd = '0') then
next_state <= st_epp_mode;
else
next_state <= st_initial_epp;
end if;
when st_epp_mode =>
Sel <= '0'; -- El bus debe asegurar que se puedan usar
 
nFault <= '0'; -- EPP.
nAck <= '0';
epp_mode <= "11";
-- Finalizaci?n del modo EPP
next_state <= st_epp_mode;
 
end case; -- no tiene handshake.
end if;
end process P_state_comb;
 
----------------------------------------------------------------------------------------
-- estado actual
P_state_clocked: process(CLK_I, nInit, nSelectIn) begin
if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then
present_state <= st_compatibility_idle;
elsif present_state = st_epp_mode and nInit = '0' then
present_state <= st_compatibility_idle;
elsif (CLK_I'event and CLK_I='1') then
present_state <= next_state;
end if;
end process P_state_clocked;
end architecture state_machines;
/memory_8bit_reset.vhd
0,0 → 1,392
-------------------------------------------------------------------------------
-- Title : Single port RAM
-- Project : Memory Cores
-------------------------------------------------------------------------------
-- File : spmem.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 1999/5/14
-- Last update : 2000/12/19
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned
-------------------------------------------------------------------------------
-- Description: Single Port memory
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 12 May 1999
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 19 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : General review
-- Two versions are now available with reset and without
-- Default output can can be defined
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 5 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Registered Read Address feature is added to make use of
-- Altera's FPGAs memory bits
-- This feature was added from Richard Herveille's
-- contribution and his memory core
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
 
-- (!)
-- Original file modified to reduce code and make WR and reset signals
-- positive and make Reset sincronous
 
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_unsigned.all;
 
-------------------------------------------------------------------------------
-- Single port Memory core with reset
-- To make use of on FPGA memory bits do not use the RESET option
-- For Altera's FPGA you have to use also OPTION := 1
 
entity mem_8bit_reset is
 
generic ( --USE_RESET : boolean := false; -- use system reset
 
--USE_CS : boolean := false; -- use chip select signal
 
DEFAULT_OUT : std_logic := '0'; -- Default output
--OPTION : integer := 1; -- 1: Registered read Address(suitable
-- for Altera's FPGAs
-- 0: non registered read address
ADD_WIDTH : integer := 8;
WIDTH : integer := 8);
 
port (
cs : in std_logic; -- chip select
clk : in std_logic; -- write clock
reset : in std_logic; -- System Reset
add : in std_logic_vector(add_width -1 downto 0); -- Address
Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data
Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data
WR : in std_logic); -- Read Write Enable
end mem_8bit_reset;
 
 
 
architecture spmem_beh of mem_8bit_reset is
 
type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
-- Memory Type
signal data : data_array(0 to (2** add_width-1) ); -- Local data
 
-- FLEX/APEX devices require address to be registered with inclock for read operations
-- This signal is used only when OPTION = 1
-- signal regA : std_logic_vector( (add_width -1) downto 0);
procedure init_mem(signal memory_cell : inout data_array ) is
 
begin
 
for i in 0 to (2** add_width-1) loop
memory_cell(i) <= (others => '0');
end loop;
 
end init_mem;
 
begin -- spmem_beh
-- -------------------------------------------------------------------------------
-- -- Non Registered Read Address
-- -------------------------------------------------------------------------------
-- NON_REG : if OPTION = 0 generate
-- -------------------------------------------------------------------------------
-- -- Clocked Process with Reset
-- -------------------------------------------------------------------------------
-- Reset_ENABLED : if USE_RESET = true generate
 
-- -------------------------------------------------------------------------------
-- CS_ENABLED : if USE_CS = true generate
 
process (clk, reset)
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
if reset = '1' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
else
if CS = '1' then
if WR = '1' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
end if;
end if;
end process;
-- end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- CS_DISABLED : if USE_CS = false generate
 
-- process (clk, reset)
 
 
-- begin -- PROCESS
-- -- activities triggered by asynchronous reset (active low)
 
-- if reset = '0' then
-- data_out <= (others => DEFAULT_OUT);
-- init_mem ( data);
 
-- -- activities triggered by rising edge of clock
-- elsif clk'event and clk = '1' then
-- if WR = '0' then
-- data(conv_integer(add)) <= data_in;
-- data_out <= (others => DEFAULT_OUT);
-- else
-- data_out <= data(conv_integer(add));
-- end if;
 
-- end if;
 
-- end process;
-- end generate CS_DISABLED;
 
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- end generate Reset_ENABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- -- Clocked Process without Reset
-- -------------------------------------------------------------------------------
-- Reset_DISABLED : if USE_RESET = false generate
 
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- CS_ENABLED : if USE_CS = true generate
 
-- process (clk)
-- begin -- PROCESS
 
-- -- activities triggered by rising edge of clock
-- if clk'event and clk = '1' then
-- if cs = '1' then
-- if WR = '0' then
-- data(conv_integer(add)) <= data_in;
-- data_out <= (others => DEFAULT_OUT);
-- else
-- data_out <= data(conv_integer(add));
-- end if;
-- else
-- data_out <= (others => DEFAULT_OUT);
-- end if;
 
 
-- end if;
 
-- end process;
-- end generate CS_ENABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- CS_DISABLED : if USE_CS = false generate
 
-- process (clk)
-- begin -- PROCESS
 
-- -- activities triggered by rising edge of clock
-- if clk'event and clk = '1' then
-- if WR = '0' then
-- data(conv_integer(add)) <= data_in;
-- data_out <= (others => DEFAULT_OUT);
-- else
-- data_out <= data(conv_integer(add));
-- end if;
 
-- end if;
 
-- end process;
-- end generate CS_DISABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- end generate Reset_DISABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- end generate NON_REG;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- REG: if OPTION = 1 generate
-- -------------------------------------------------------------------------------
-- -- Clocked Process with Reset
-- -------------------------------------------------------------------------------
-- Reset_ENABLED : if USE_RESET = true generate
 
-- -------------------------------------------------------------------------------
-- CS_ENABLED : if USE_CS = true generate
 
-- process (clk, reset)
 
-- begin -- PROCESS
-- -- activities triggered by asynchronous reset (active low)
 
-- if reset = '0' then
-- data_out <= (others => DEFAULT_OUT);
-- init_mem ( data);
 
-- -- activities triggered by rising edge of clock
-- elsif clk'event and clk = '1' then
 
-- regA <= add;
-- if CS = '1' then
-- if WR = '0' then
-- data(conv_integer(add)) <= data_in;
-- data_out <= (others => DEFAULT_OUT);
-- else
-- data_out <= data(conv_integer(regA));
-- end if;
-- else
-- data_out <= (others => DEFAULT_OUT);
-- end if;
 
-- end if;
 
-- end process;
-- end generate CS_ENABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- CS_DISABLED : if USE_CS = false generate
 
-- process (clk, reset)
 
 
-- begin -- PROCESS
-- -- activities triggered by asynchronous reset (active low)
 
-- if reset = '0' then
-- data_out <= (others => DEFAULT_OUT);
-- init_mem ( data);
 
-- -- activities triggered by rising edge of clock
-- elsif clk'event and clk = '1' then
-- regA <= add;
-- if WR = '0' then
-- data(conv_integer(add)) <= data_in;
-- data_out <= (others => DEFAULT_OUT);
-- else
-- data_out <= data(conv_integer(regA));
-- end if;
 
-- end if;
 
-- end process;
-- end generate CS_DISABLED;
 
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- end generate Reset_ENABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- -- Clocked Process without Reset
-- -------------------------------------------------------------------------------
-- Reset_DISABLED : if USE_RESET = false generate
 
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- CS_ENABLED : if USE_CS = true generate
 
-- process (clk)
-- begin -- PROCESS
 
-- -- activities triggered by rising edge of clock
-- if clk'event and clk = '1' then
 
-- regA <= add;
-- if cs = '1' then
-- if WR = '0' then
-- data(conv_integer(add)) <= data_in;
-- data_out <= (others => DEFAULT_OUT);
-- else
-- data_out <= data(conv_integer(regA));
-- end if;
-- else
-- data_out <= (others => DEFAULT_OUT);
-- end if;
 
 
-- end if;
 
-- end process;
-- end generate CS_ENABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- CS_DISABLED : if USE_CS = false generate
 
-- process (clk)
-- begin -- PROCESS
 
-- -- activities triggered by rising edge of clock
-- if clk'event and clk = '1' then
-- regA <= add;
-- if WR = '0' then
-- data(conv_integer(add)) <= data_in;
-- data_out <= (others => DEFAULT_OUT);
-- else
-- data_out <= data(conv_integer(regA));
-- end if;
 
-- end if;
 
-- end process;
-- end generate CS_DISABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- end generate Reset_DISABLED;
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------
-- end generate REG;
 
end spmem_beh;
-------------------------------------------------------------------------------
/eppwbn_wbn_side.vhd
0,0 → 1,141
--|------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.20
--| Targeted device: Actel A3PE1500
--|------------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| This module is in the wishbone side (IEEE Std. 1284-2000).
-------------------------------------------------------------------------------
--| File history:
--| 0.01 | nov-2008 | First release
--| 0.1 | jan-2009 | Sinc reset
--------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
 
 
entity eppwbn_wbn_side is
port(
 
-- al puerto epp
inStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284, Negotiation/ECP/EPP (Compatibiliy)
-- HostClk/nWrite
iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
-- inAck: out std_logic; -- PtrClk/PeriphClk/Intr
iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
-- iPError: out std_logic; -- AckData/nAckReverse
-- iSel: out std_logic; -- XFlag (Select)
inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
-- iPeriphLogicH: out std_logic; -- (Periph Logic High)
-- inInit: in std_logic; -- nReverseRequest
-- inFault: out std_logic; -- nDataAvail/nPeriphRequest
inSelectIn: in std_logic; -- 1284 Active/nAStrb
-- iHostLogicH: in std_logic; -- (Host Logic High)
-- i indica interna en el core y controlada por el bloque de control
-- a la interface wishbone
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic;
rst_pp: in std_logic -- reset desde la interfaz del puerto paralelo
 
 
);
end eppwbn_wbn_side;
 
architecture con_registro of eppwbn_wbn_side is -- El dato es registrado en el core.
 
signal adr_ack,data_ack: std_logic;
signal adr_reg,data_reg: std_logic_vector (7 downto 0); -- deben crearse dos registros de lectrura/escritura
 
 
begin
 
 
-- Data R/W
data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_pp)
begin
if (rst_pp = '1' or RST_I = '1') then -- Reset de interfaz EPP
data_reg <= (others => '0');
pre_STB_O <= '0';
data_ack <= '0';
elsif (CLK_I'event and CLK_I = '1') then
if RST_I = '1' then
data_reg <= (others => '0');
pre_STB_O <= '0';
data_ack <= '0';
else
if (inAutoFd = '0' and data_ack = '0') then -- Data strobe
pre_STB_O <= '1';
if (inStrobe = '0') then -- Escritura EPP
data_reg <= iData;
end if;
end if;
 
pre_STB_O <= '0';
data_ack <= '1';
if (inStrobe = '1') then -- Lectura EPP
data_reg <= DAT_I;
end if;
end if;
end if;
end if;
 
data_ack <= '0'; -- una vez que haya respuesta desde la PC
end if;
end process;
STB_O <= pre_STB_O;
CYC_O <= pre_STB_O;
DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos
-- a wishbone, lectura y escritura de datos desde epp
 
-- Adr R/W
 
adr_strobing: process (inSelectIn, RST_I, rst_pp)
begin
if (RST_I = '1' or rst_pp = '1') then
adr_reg <= (others => '0');
elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe
if inStrobe = '0' then
adr_reg <= iData;
end if;
end if;
end process;
ADR_O <= adr_reg;
-- Puerto bidireccional
iData <= data_reg when (inStrobe = '1' and data_ack = '1') else
adr_reg when (inStrobe = '1' and adr_ack = '1') else
(others => 'Z');
end con_registro;
/eppwbn_test_wb_side.vhd
0,0 → 1,61
--|-----------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_test_wb_side.vhd
--| Version: 0.10
--| Targeted device: Actel A3PE1500
--|-----------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| This file is only for test purposes
--| It only stores data in regiters with wishbone interconect
--------------------------------------------------------------------------------
--| File history:
--| 0.10 | dic-2008 | First release
--------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.eppwbn_pgk.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
 
 
entity eppwbn_test_wb_side is
port(
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_I: in std_logic_vector (7 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
ACK_O: out std_logic ;
WE_I: in std_logic
);
end eppwbn_test_wb_side;
 
architecture eppwbn_test_wb_arch0 of eppwbn_test_wb_side is
signal auto_ack: std_logic;
begin
MEM1: mem_8bit_reset
port map (
cs => auto_ack,
clk => CLK_I,
reset => RST_I,
add => ADR_I,
Data_In => DAT_I,
Data_Out => DAT_O,
WR => WE_I
);
auto_ack <= CYC_I and STB_I;
ACK_O <= auto_ack;
end architecture eppwbn_test_wb_arch0;
/eppwbn_test.vhd
0,0 → 1,102
--|-----------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_test.vhd
--| Version: 0.10
--| Targeted device: Actel A3PE1500
--|-----------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| This file is only for test purposes
--|
--------------------------------------------------------------------------------
--| File history:
--| 0.10 | jan-2008 | First release
--------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.eppwbn_pgk.all;
 
 
 
entity eppwbn_test is
port(
-- al puerto EPP
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
-- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- a los switches
rst: in std_logic;
-- al clock
clk: in std_logic
);
end eppwbn_test;
 
architecture eppwbn_test_arch0 of eppwbn_test is
signal DAT_I_master: std_logic_vector (7 downto 0);
signal DAT_O_master: std_logic_vector (7 downto 0);
signal ADR_O_master: std_logic_vector (7 downto 0);
signal CYC_O_master: std_logic;
signal STB_O_master: std_logic;
signal ACK_I_master: std_logic;
signal WE_O_master: std_logic;
begin
SL_MEM1: eppwbn_test_wb_side port map(
RST_I => rst,
CLK_I => clk,
DAT_I => DAT_O_master,
DAT_O => DAT_I_master,
ADR_I => ADR_O_master,
CYC_I => CYC_O_master,
STB_I => STB_O_master,
ACK_O => ACK_I_master,
WE_I => WE_O_master
);
 
MA_EPP: eppwbn port map(
-- Externo
nStrobe => nStrobe,
Data => Data,
nAck => nAck,
busy => busy,
PError => PError,
Sel => Sel,
nAutoFd => nAutoFd,
PeriphLogicH => PeriphLogicH,
nInit => nInit,
nFault => nFault,
nSelectIn => nSelectIn,
-- Interno
RST_I => rst,
CLK_I => clk,
DAT_I => DAT_I_master,
DAT_O => DAT_O_master,
ADR_O => ADR_O_master,
CYC_O => CYC_O_master,
STB_O => STB_O_master,
ACK_I => ACK_I_master,
WE_O => WE_O_master
);
end architecture eppwbn_test_arch0;
/eppwbn_pkg.vhd
0,0 → 1,164
--|-----------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.10
--| Targeted device: Actel A3PE1500
--|-----------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| Package for instantiate all EPP-WBN modules.
--------------------------------------------------------------------------------
--| File history:
--| 0.01 | dic-2008 | First release
--| 0.10 | jan-2008 | Added testing memory
--------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package eppwbn_pgk is
------------------------------------------------------------------------------
-- Componentes
-- Bridge control
component eppwbn_ctrl is
port(
nStrobe: in std_logic;
Data: in std_logic_vector (7 downto 0);
nAck: out std_logic;
PError: out std_logic;
Sel: out std_logic;
nAutoFd: in std_logic;
PeriphLogicH: out std_logic;
nInit: in std_logic;
nFault: out std_logic;
nSelectIn: in std_logic;
RST_I: in std_logic;
CLK_I: in std_logic;
 
rst_pp: out std_logic;
epp_mode: out std_logic_vector (1 downto 0)
);
end component eppwbn_ctrl;
-- Comunication with EPP interface
component eppwbn_epp_side is
port(
epp_mode: in std_logic_vector (1 downto 0);
 
ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic;
ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic;
wb_Busy: in std_logic;
wb_nAutoFd: out std_logic;
wb_nSelectIn: out std_logic;
wb_nStrobe: out std_logic;
 
nAck, PError, Sel, nFault: out std_logic;
Busy: out std_logic;
nAutoFd: in std_logic;
nSelectIn: in std_logic;
nStrobe: in std_logic
);
end component eppwbn_epp_side;
-- Comunication with WB interface
component eppwbn_wbn_side is
port(
inStrobe: in std_logic;
iData: inout std_logic_vector (7 downto 0);
iBusy: out std_logic;
inAutoFd: in std_logic;
inSelectIn: in std_logic;
RST_I, CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O, STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic;
 
rst_pp: in std_logic
);
end component eppwbn_wbn_side;
-- Testing memory
component mem_8bit_reset is
generic ( --USE_RESET : boolean := false; -- use system reset
 
--USE_CS : boolean := false; -- use chip select signal
 
DEFAULT_OUT : std_logic := '0'; -- Default output
--OPTION : integer := 1; -- 1: Registered read Address(suitable
-- for Altera's FPGAs
-- 0: non registered read address
ADD_WIDTH : integer := 8;
WIDTH : integer := 8);
 
port (
cs : in std_logic; -- chip select
clk : in std_logic; -- write clock
reset : in std_logic; -- System Reset
add : in std_logic_vector(add_width -1 downto 0); -- Address
Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data
Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data
WR : in std_logic); -- Read Write Enable
end component mem_8bit_reset;
component eppwbn is
port(
-- Externo
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
-- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic
);
end component eppwbn;
component eppwbn_test_wb_side is
port(
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_I: in std_logic_vector (7 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
ACK_O: out std_logic ;
WE_I: in std_logic
);
end component eppwbn_test_wb_side;
end package eppwbn_pgk;
/eppwbn_epp_side.vhd
0,0 → 1,125
--|------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_epp_side.vhd
--| Version: 0.01
--| Targeted device: Actel A3PE1500
--|------------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| EPP module output control (IEEE Std. 1284-2000).
-------------------------------------------------------------------------------
--| File history:
--| 0.01 | nov-2008 | First release
--------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity eppwbn_epp_side is
port(
 
 
 
-- "00" deshabilitado
 
-- "10" sin definir
-- "11" modo EPP normal
 
-- CTRL signals
ctr_nAck: in std_logic; -- PtrClk/PeriphClk/Intr
ctr_PError: in std_logic; -- AckData/nAckReverse
ctr_Sel: in std_logic; -- XFlag (Select). Select no puede usarse
ctr_nFault: in std_logic; -- nDataAvail/nPeriphRequest
 
ctr_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb
ctr_nSelectIn: out std_logic; -- 1284 Active/nAStrb
ctr_nStrobe: out std_logic; -- HostClk/nWrite
-- WB-side signals
wb_Busy: in std_logic; -- PtrBusy/PeriphAck/nWait
wb_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb
wb_nSelectIn: out std_logic; -- 1284 Active/nAStrb
wb_nStrobe: out std_logic; -- HostClk/nWrite
 
 
-- To EPP port
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select). Select no puede usarse
nFault: out std_logic; -- nDataAvail/nPeriphRequest
Busy: out std_logic; -- PtrBusy/PeriphAck/nWait
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
nSelectIn: in std_logic; -- 1284 Active/nAStrb
nStrobe: in std_logic -- HostClk/nWrite
 
);
end entity eppwbn_epp_side;
 
architecture multiplexor of eppwbn_epp_side is
 
begin
 
-- Puentes
 
Busy <= wb_Busy;
 
ctr_nAutoFd <= nAutoFd;
ctr_nSelectIn <= nSelectIn;
ctr_nStrobe <= nStrobe;
 
 
 
multiplexing: process (epp_mode ,ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault,
nAutoFd, nSelectIn, nStrobe) begin
case epp_mode is
 
when "11" =>
-- Hacia el host
 
PError <= '0';
Sel <= '0';
nFault <= '0';
 
wb_nAutoFd <= nAutoFd;
wb_nSelectIn <= nSelectIn;
wb_nStrobe <= nStrobe;
when "01" =>
-- Hacia el host
nAck <= ctr_nAck;
PError <= ctr_PError;
Sel <= ctr_Sel;
nFault <= ctr_nFault;
 
wb_nAutoFd <= nAutoFd;
wb_nSelectIn <= nSelectIn;
wb_nStrobe <= nStrobe;
when others =>
-- Hacia el host
nAck <= ctr_nAck;
PError <= ctr_PError;
Sel <= ctr_Sel;
nFault <= ctr_nFault;
 
wb_nAutoFd <= '1';
wb_nSelectIn <= '1';
wb_nStrobe <= '1';
end case;
end process;
 
end architecture multiplexor;
 
 
 
 
/eppwbn.vhd
0,0 → 1,155
--|-----------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.01
--| Targeted device: Actel A3PE1500
--|-----------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| Instantiate all the other modules. The TOP file.
--------------------------------------------------------------------------------
--| File history:
--| 0.01 | dic-2008 | First release
--------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
 
-- Bloque completo
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.eppwbn_pgk.all;
 
entity eppwbn is
port(
-- Externo
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
-- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic
);
end eppwbn;
architecture structural of eppwbn is
------------------------------------------------------------------------------
 
signal s_epp_mode: std_logic_vector (1 downto 0);
signal s_rst_pp: std_logic;
signal s_wb_Busy: std_logic;
signal s_wb_nAutoFd: std_logic;
signal s_wb_nSelectIn: std_logic;
signal s_wb_nStrobe: std_logic;
signal s_ctr_nAck: std_logic;
signal s_ctr_PError: std_logic;
signal s_ctr_Sel: std_logic;
signal s_ctr_nFault: std_logic;
 
signal s_ctr_nAutoFd: std_logic;
signal s_ctr_nSelectIn: std_logic;
signal s_ctr_nStrobe: std_logic;
 
begin
 
 
U1: eppwbn_ctrl
port map (
nStrobe => s_ctr_nStrobe,
Data => Data,
nAck => s_ctr_nAck,
PError => s_ctr_PError,
Sel => s_ctr_Sel,
nAutoFd => s_ctr_nAutoFd,
PeriphLogicH => PeriphLogicH,
nInit => nInit,
nFault => s_ctr_nFault,
nSelectIn => s_ctr_nSelectIn,
RST_I => RST_I,
CLK_I => CLK_I,
rst_pp => s_rst_pp,
epp_mode => s_epp_mode
);
 
 
U2: eppwbn_epp_side
port map (
epp_mode => s_epp_mode,
 
ctr_nAck => s_ctr_nAck,
ctr_PError => s_ctr_PError,
ctr_Sel => s_ctr_Sel,
ctr_nFault => s_ctr_nFault,
 
ctr_nAutoFd => s_ctr_nAutoFd,
ctr_nSelectIn => s_ctr_nSelectIn,
ctr_nStrobe=> s_ctr_nStrobe,
wb_Busy => s_wb_Busy,
wb_nAutoFd => s_wb_nAutoFd,
wb_nSelectIn => s_wb_nSelectIn,
wb_nStrobe => s_wb_nStrobe,
 
nAck => nAck,
PError => PError,
Sel => Sel,
nFault => nFault,
Busy => Busy,
nAutoFd => nAutoFd,
nSelectIn => nSelectIn,
nStrobe => nStrobe
);
 
 
U3: eppwbn_wbn_side
port map(
inStrobe => s_wb_nStrobe,
iData => Data,
iBusy => s_wb_Busy,
inAutoFd => s_wb_nAutoFd,
inSelectIn => s_wb_nSelectIn,
RST_I => RST_I,
CLK_I => CLK_I,
DAT_I => DAT_I,
DAT_O => DAT_O,
ADR_O => ADR_O,
CYC_O => CYC_O,
STB_O => STB_O,
ACK_I => ACK_I,
WE_O => WE_O,
rst_pp => s_rst_pp
);
end architecture;
/memory_original.vhd
0,0 → 1,391
-------------------------------------------------------------------------------
-- Title : Single port RAM
-- Project : Memory Cores
-------------------------------------------------------------------------------
-- File : spmem.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 1999/5/14
-- Last update : 2000/12/19
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned
-------------------------------------------------------------------------------
-- Description: Single Port memory
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 12 May 1999
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 19 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : General review
-- Two versions are now available with reset and without
-- Default output can can be defined
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 5 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Registered Read Address feature is added to make use of
-- Altera's FPGAs memory bits
-- This feature was added from Richard Herveille's
-- contribution and his memory core
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
 
 
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_unsigned.all;
 
-------------------------------------------------------------------------------
-- Single port Memory core with reset
-- To make use of on FPGA memory bits do not use the RESET option
-- For Altera's FPGA you have to use also OPTION := 1
 
entity Spmem_ent is
 
generic ( USE_RESET : boolean := false; -- use system reset
 
USE_CS : boolean := false; -- use chip select signal
 
DEFAULT_OUT : std_logic := '1'; -- Default output
OPTION : integer := 1; -- 1: Registered read Address(suitable
-- for Altera's FPGAs
-- 0: non registered read address
ADD_WIDTH : integer := 3;
WIDTH : integer := 8);
 
port (
cs : std_logic; -- chip select
clk : in std_logic; -- write clock
reset : in std_logic; -- System Reset
add : in std_logic_vector(add_width -1 downto 0); -- Address
Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data
Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data
WR : in std_logic); -- Read Write Enable
end Spmem_ent;
 
 
 
architecture spmem_beh of Spmem_ent is
 
type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
-- Memory Type
signal data : data_array(0 to (2** add_width-1) ); -- Local data
 
-- FLEX/APEX devices require address to be registered with inclock for read operations
-- This signal is used only when OPTION = 1
signal regA : std_logic_vector( (add_width -1) downto 0);
procedure init_mem(signal memory_cell : inout data_array ) is
 
begin
 
for i in 0 to (2** add_width-1) loop
memory_cell(i) <= (others => '0');
end loop;
 
end init_mem;
 
begin -- spmem_beh
-------------------------------------------------------------------------------
-- Non Registered Read Address
-------------------------------------------------------------------------------
NON_REG : if OPTION = 0 generate
-------------------------------------------------------------------------------
-- Clocked Process with Reset
-------------------------------------------------------------------------------
Reset_ENABLED : if USE_RESET = true generate
 
-------------------------------------------------------------------------------
CS_ENABLED : if USE_CS = true generate
 
process (clk, reset)
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
if reset = '0' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
 
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
if CS = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
 
end if;
 
end process;
end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_DISABLED : if USE_CS = false generate
 
process (clk, reset)
 
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
if reset = '0' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
 
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
 
end if;
 
end process;
end generate CS_DISABLED;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate Reset_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Clocked Process without Reset
-------------------------------------------------------------------------------
Reset_DISABLED : if USE_RESET = false generate
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_ENABLED : if USE_CS = true generate
 
process (clk)
begin -- PROCESS
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
if cs = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
 
 
end if;
 
end process;
end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_DISABLED : if USE_CS = false generate
 
process (clk)
begin -- PROCESS
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
 
end if;
 
end process;
end generate CS_DISABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate Reset_DISABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate NON_REG;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REG: if OPTION = 1 generate
-------------------------------------------------------------------------------
-- Clocked Process with Reset
-------------------------------------------------------------------------------
Reset_ENABLED : if USE_RESET = true generate
 
-------------------------------------------------------------------------------
CS_ENABLED : if USE_CS = true generate
 
process (clk, reset)
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
if reset = '0' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
 
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
 
regA <= add;
if CS = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(regA));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
 
end if;
 
end process;
end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_DISABLED : if USE_CS = false generate
 
process (clk, reset)
 
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
if reset = '0' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
 
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
regA <= add;
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(regA));
end if;
 
end if;
 
end process;
end generate CS_DISABLED;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate Reset_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Clocked Process without Reset
-------------------------------------------------------------------------------
Reset_DISABLED : if USE_RESET = false generate
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_ENABLED : if USE_CS = true generate
 
process (clk)
begin -- PROCESS
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
 
regA <= add;
if cs = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(regA));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
 
 
end if;
 
end process;
end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_DISABLED : if USE_CS = false generate
 
process (clk)
begin -- PROCESS
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
regA <= add;
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(regA));
end if;
 
end if;
 
end process;
end generate CS_DISABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate Reset_DISABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate REG;
 
end spmem_beh;
-------------------------------------------------------------------------------
 
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