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/eppwbn_16bit_test.vhd

eppwbn_16bit_test.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: memory_8bit_reset.vhd =================================================================== --- memory_8bit_reset.vhd (revision 16) +++ memory_8bit_reset.vhd (revision 19) @@ -1,392 +1,391 @@ -------------------------------------------------------------------------------- --- Title : Single port RAM --- Project : Memory Cores -------------------------------------------------------------------------------- --- File : spmem.vhd --- Author : Jamil Khatib (khatib@ieee.org) --- Organization: OpenIPCore Project --- Created : 1999/5/14 --- Last update : 2000/12/19 --- Platform : --- Simulators : Modelsim 5.3XE/Windows98 --- Synthesizers: Leonardo/WindowsNT --- Target : --- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned -------------------------------------------------------------------------------- --- Description: Single Port memory -------------------------------------------------------------------------------- --- Copyright (c) 2000 Jamil Khatib --- --- This VHDL design file is an open design; you can redistribute it and/or --- modify it and/or implement it after contacting the author --- You can check the draft license at --- http://www.opencores.org/OIPC/license.shtml - -------------------------------------------------------------------------------- --- Revisions : --- Revision Number : 1 --- Version : 0.1 --- Date : 12 May 1999 --- Modifier : Jamil Khatib (khatib@ieee.org) --- Desccription : Created --- Known bugs : --- To Optimze : -------------------------------------------------------------------------------- --- Revisions : --- Revision Number : 2 --- Version : 0.2 --- Date : 19 Dec 2000 --- Modifier : Jamil Khatib (khatib@ieee.org) --- Desccription : General review --- Two versions are now available with reset and without --- Default output can can be defined --- Known bugs : --- To Optimze : -------------------------------------------------------------------------------- --- Revisions : --- Revision Number : 3 --- Version : 0.3 --- Date : 5 Jan 2001 --- Modifier : Jamil Khatib (khatib@ieee.org) --- Desccription : Registered Read Address feature is added to make use of --- Altera's FPGAs memory bits --- This feature was added from Richard Herveille's --- contribution and his memory core --- Known bugs : --- To Optimze : -------------------------------------------------------------------------------- - --- (!) --- Original file modified to reduce code and make WR and reset signals --- positive and make Reset sincronous - - -library ieee; - -use ieee.std_logic_1164.all; - -use ieee.std_logic_unsigned.all; - -------------------------------------------------------------------------------- --- Single port Memory core with reset --- To make use of on FPGA memory bits do not use the RESET option --- For Altera's FPGA you have to use also OPTION := 1 - -entity mem_8bit_reset is - - generic ( --USE_RESET : boolean := false; -- use system reset - - --USE_CS : boolean := false; -- use chip select signal - - DEFAULT_OUT : std_logic := '0'; -- Default output - --OPTION : integer := 1; -- 1: Registered read Address(suitable - -- for Altera's FPGAs - -- 0: non registered read address - ADD_WIDTH : integer := 8; - WIDTH : integer := 8); - - port ( - cs : in std_logic; -- chip select - clk : in std_logic; -- write clock - reset : in std_logic; -- System Reset - add : in std_logic_vector(add_width -1 downto 0); -- Address - Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data - Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data - WR : in std_logic); -- Read Write Enable -end mem_8bit_reset; - - - -architecture spmem_beh of mem_8bit_reset is - - type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0); - -- Memory Type - signal data : data_array(0 to (2** add_width-1) ); -- Local data - - -- FLEX/APEX devices require address to be registered with inclock for read operations - -- This signal is used only when OPTION = 1 - -- signal regA : std_logic_vector( (add_width -1) downto 0); - - procedure init_mem(signal memory_cell : inout data_array ) is - - begin - - for i in 0 to (2** add_width-1) loop - memory_cell(i) <= (others => '0'); - end loop; - - end init_mem; - -begin -- spmem_beh --- ------------------------------------------------------------------------------- --- -- Non Registered Read Address --- ------------------------------------------------------------------------------- - -- NON_REG : if OPTION = 0 generate --- ------------------------------------------------------------------------------- --- -- Clocked Process with Reset --- ------------------------------------------------------------------------------- - -- Reset_ENABLED : if USE_RESET = true generate - --- ------------------------------------------------------------------------------- --- CS_ENABLED : if USE_CS = true generate - - process (clk, reset) - - begin -- PROCESS - -- activities triggered by asynchronous reset (active low) - - -- activities triggered by rising edge of clock - if clk'event and clk = '1' then - - if reset = '1' then - data_out <= (others => DEFAULT_OUT); - init_mem ( data); - else - if CS = '1' then - if WR = '1' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(add)); - end if; - else - data_out <= (others => DEFAULT_OUT); - end if; - end if; - end if; - end process; --- end generate CS_ENABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - -- CS_DISABLED : if USE_CS = false generate - - -- process (clk, reset) - - - -- begin -- PROCESS - -- -- activities triggered by asynchronous reset (active low) - - -- if reset = '0' then - -- data_out <= (others => DEFAULT_OUT); - -- init_mem ( data); - - -- -- activities triggered by rising edge of clock - -- elsif clk'event and clk = '1' then - -- if WR = '0' then - -- data(conv_integer(add)) <= data_in; - -- data_out <= (others => DEFAULT_OUT); - -- else - -- data_out <= data(conv_integer(add)); - -- end if; - - -- end if; - - -- end process; - -- end generate CS_DISABLED; - --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- end generate Reset_ENABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- --- -- Clocked Process without Reset --- ------------------------------------------------------------------------------- - -- Reset_DISABLED : if USE_RESET = false generate - --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- CS_ENABLED : if USE_CS = true generate - - -- process (clk) - -- begin -- PROCESS - - -- -- activities triggered by rising edge of clock - -- if clk'event and clk = '1' then - -- if cs = '1' then - -- if WR = '0' then - -- data(conv_integer(add)) <= data_in; - -- data_out <= (others => DEFAULT_OUT); - -- else - -- data_out <= data(conv_integer(add)); - -- end if; - -- else - -- data_out <= (others => DEFAULT_OUT); - -- end if; - - - -- end if; - - -- end process; - -- end generate CS_ENABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- CS_DISABLED : if USE_CS = false generate - - -- process (clk) - -- begin -- PROCESS - - -- -- activities triggered by rising edge of clock - -- if clk'event and clk = '1' then - -- if WR = '0' then - -- data(conv_integer(add)) <= data_in; - -- data_out <= (others => DEFAULT_OUT); - -- else - -- data_out <= data(conv_integer(add)); - -- end if; - - -- end if; - - -- end process; - -- end generate CS_DISABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- end generate Reset_DISABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- end generate NON_REG; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --- REG: if OPTION = 1 generate --- ------------------------------------------------------------------------------- --- -- Clocked Process with Reset --- ------------------------------------------------------------------------------- - -- Reset_ENABLED : if USE_RESET = true generate - --- ------------------------------------------------------------------------------- - -- CS_ENABLED : if USE_CS = true generate - - -- process (clk, reset) - - -- begin -- PROCESS - -- -- activities triggered by asynchronous reset (active low) - - -- if reset = '0' then - -- data_out <= (others => DEFAULT_OUT); - -- init_mem ( data); - - -- -- activities triggered by rising edge of clock - -- elsif clk'event and clk = '1' then - - -- regA <= add; - - -- if CS = '1' then - -- if WR = '0' then - -- data(conv_integer(add)) <= data_in; - -- data_out <= (others => DEFAULT_OUT); - -- else - -- data_out <= data(conv_integer(regA)); - -- end if; - -- else - -- data_out <= (others => DEFAULT_OUT); - -- end if; - - -- end if; - - -- end process; - -- end generate CS_ENABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- CS_DISABLED : if USE_CS = false generate - - -- process (clk, reset) - - - -- begin -- PROCESS - -- -- activities triggered by asynchronous reset (active low) - - -- if reset = '0' then - -- data_out <= (others => DEFAULT_OUT); - -- init_mem ( data); - - -- -- activities triggered by rising edge of clock - -- elsif clk'event and clk = '1' then - -- regA <= add; - - -- if WR = '0' then - -- data(conv_integer(add)) <= data_in; - -- data_out <= (others => DEFAULT_OUT); - -- else - -- data_out <= data(conv_integer(regA)); - -- end if; - - -- end if; - - -- end process; - -- end generate CS_DISABLED; - --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- end generate Reset_ENABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- --- -- Clocked Process without Reset --- ------------------------------------------------------------------------------- - -- Reset_DISABLED : if USE_RESET = false generate - --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- CS_ENABLED : if USE_CS = true generate - - -- process (clk) - -- begin -- PROCESS - - -- -- activities triggered by rising edge of clock - -- if clk'event and clk = '1' then - - -- regA <= add; - - -- if cs = '1' then - -- if WR = '0' then - -- data(conv_integer(add)) <= data_in; - -- data_out <= (others => DEFAULT_OUT); - -- else - -- data_out <= data(conv_integer(regA)); - -- end if; - -- else - -- data_out <= (others => DEFAULT_OUT); - -- end if; - - - -- end if; - - -- end process; - -- end generate CS_ENABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- CS_DISABLED : if USE_CS = false generate - - -- process (clk) - -- begin -- PROCESS - - -- -- activities triggered by rising edge of clock - -- if clk'event and clk = '1' then - - -- regA <= add; - - -- if WR = '0' then - -- data(conv_integer(add)) <= data_in; - -- data_out <= (others => DEFAULT_OUT); - -- else - -- data_out <= data(conv_integer(regA)); - -- end if; - - -- end if; - - -- end process; - -- end generate CS_DISABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - -- end generate Reset_DISABLED; --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- - --- end generate REG; - -end spmem_beh; -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Title : Single port RAM +-- Project : Memory Cores +------------------------------------------------------------------------------- +-- File : spmem.vhd +-- Author : Jamil Khatib (khatib@ieee.org) +-- Organization: OpenIPCore Project +-- Created : 1999/5/14 +-- Last update : 2000/12/19 +-- Platform : +-- Simulators : Modelsim 5.3XE/Windows98 +-- Synthesizers: Leonardo/WindowsNT +-- Target : +-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned +------------------------------------------------------------------------------- +-- Description: Single Port memory +------------------------------------------------------------------------------- +-- Copyright (c) 2000 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml + +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 12 May 1999 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : Created +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 2 +-- Version : 0.2 +-- Date : 19 Dec 2000 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : General review +-- Two versions are now available with reset and without +-- Default output can can be defined +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 3 +-- Version : 0.3 +-- Date : 5 Jan 2001 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : Registered Read Address feature is added to make use of +-- Altera's FPGAs memory bits +-- This feature was added from Richard Herveille's +-- contribution and his memory core +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- + +-- (!) +-- Original file modified to reduce code and make WR and reset signals +-- positive, make Reset sincronous, make data transfer asinc. + + +library ieee; + +use ieee.std_logic_1164.all; + +use ieee.std_logic_unsigned.all; + +------------------------------------------------------------------------------- +-- Single port Memory core with reset +-- To make use of on FPGA memory bits do not use the RESET option +-- For Altera's FPGA you have to use also OPTION := 1 + +entity mem_8bit_reset is + + generic ( --USE_RESET : boolean := false; -- use system reset + + --USE_CS : boolean := false; -- use chip select signal + + DEFAULT_OUT : std_logic := '0'; -- Default output + --OPTION : integer := 1; -- 1: Registered read Address(suitable + -- for Altera's FPGAs + -- 0: non registered read address + ADD_WIDTH : integer := 8; + WIDTH : integer := 8); + + port ( + cs : in std_logic; -- chip select + clk : in std_logic; -- write clock + reset : in std_logic; -- System Reset + add : in std_logic_vector(add_width -1 downto 0); -- Address + Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data + Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data + WR : in std_logic); -- Read Write Enable +end mem_8bit_reset; + + + +architecture spmem_beh of mem_8bit_reset is + + type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0); + -- signal s_reset: std_logic; + -- Memory Type + signal data : data_array(0 to (2** add_width-1) ); -- Local data + + + -- FLEX/APEX devices require address to be registered with inclock for read operations + -- This signal is used only when OPTION = 1 + -- signal regA : std_logic_vector( (add_width -1) downto 0); + + procedure init_mem(signal memory_cell : inout data_array ) is + + begin + + for i in 0 to (2** add_width-1) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + +begin -- spmem_beh +-- ------------------------------------------------------------------------------- +-- -- Non Registered Read Address +-- ------------------------------------------------------------------------------- + -- NON_REG : if OPTION = 0 generate +-- ------------------------------------------------------------------------------- +-- -- Clocked Process with Reset +-- ------------------------------------------------------------------------------- + -- Reset_ENABLED : if USE_RESET = true generate + +-- ------------------------------------------------------------------------------- +-- CS_ENABLED : if USE_CS = true generate + + process (clk, reset,CS,WR, add) + + begin -- PROCESS + -- activities triggered by asynchronous reset (active low) + + -- activities triggered by rising edge of clock + + data_out <= data(conv_integer(add)); + + + if clk'event and clk = '1' then + if reset = '1' then + init_mem (data); + elsif CS = '1' then + if WR = '1' then + data(conv_integer(add)) <= Data_In; + end if; + end if; + end if; + + + end process; +-- end generate CS_ENABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + -- CS_DISABLED : if USE_CS = false generate + + -- process (clk, reset) + + + -- begin -- PROCESS + -- -- activities triggered by asynchronous reset (active low) + + -- if reset = '0' then + -- data_out <= (others => DEFAULT_OUT); + -- init_mem ( data); + + -- -- activities triggered by rising edge of clock + -- elsif clk'event and clk = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(add)); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_DISABLED; + +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate Reset_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- -- Clocked Process without Reset +-- ------------------------------------------------------------------------------- + -- Reset_DISABLED : if USE_RESET = false generate + +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_ENABLED : if USE_CS = true generate + + -- process (clk) + -- begin -- PROCESS + + -- -- activities triggered by rising edge of clock + -- if clk'event and clk = '1' then + -- if cs = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(add)); + -- end if; + -- else + -- data_out <= (others => DEFAULT_OUT); + -- end if; + + + -- end if; + + -- end process; + -- end generate CS_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_DISABLED : if USE_CS = false generate + + -- process (clk) + -- begin -- PROCESS + + -- -- activities triggered by rising edge of clock + -- if clk'event and clk = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(add)); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_DISABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate Reset_DISABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate NON_REG; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- REG: if OPTION = 1 generate +-- ------------------------------------------------------------------------------- +-- -- Clocked Process with Reset +-- ------------------------------------------------------------------------------- + -- Reset_ENABLED : if USE_RESET = true generate + +-- ------------------------------------------------------------------------------- + -- CS_ENABLED : if USE_CS = true generate + + -- process (clk, reset) + + -- begin -- PROCESS + -- -- activities triggered by asynchronous reset (active low) + + -- if reset = '0' then + -- data_out <= (others => DEFAULT_OUT); + -- init_mem ( data); + + -- -- activities triggered by rising edge of clock + -- elsif clk'event and clk = '1' then + + -- regA <= add; + + -- if CS = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(regA)); + -- end if; + -- else + -- data_out <= (others => DEFAULT_OUT); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_DISABLED : if USE_CS = false generate + + -- process (clk, reset) + + + -- begin -- PROCESS + -- -- activities triggered by asynchronous reset (active low) + + -- if reset = '0' then + -- data_out <= (others => DEFAULT_OUT); + -- init_mem ( data); + + -- -- activities triggered by rising edge of clock + -- elsif clk'event and clk = '1' then + -- regA <= add; + + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(regA)); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_DISABLED; + +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate Reset_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- -- Clocked Process without Reset +-- ------------------------------------------------------------------------------- + -- Reset_DISABLED : if USE_RESET = false generate + +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_ENABLED : if USE_CS = true generate + + -- process (clk) + -- begin -- PROCESS + + -- -- activities triggered by rising edge of clock + -- if clk'event and clk = '1' then + + -- regA <= add; + + -- if cs = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(regA)); + -- end if; + -- else + -- data_out <= (others => DEFAULT_OUT); + -- end if; + + + -- end if; + + -- end process; + -- end generate CS_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_DISABLED : if USE_CS = false generate + + -- process (clk) + -- begin -- PROCESS + + -- -- activities triggered by rising edge of clock + -- if clk'event and clk = '1' then + + -- regA <= add; + + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(regA)); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_DISABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate Reset_DISABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + +-- end generate REG; + +end spmem_beh; +------------------------------------------------------------------------------- Index: eppwbn_16bit.vhd =================================================================== --- eppwbn_16bit.vhd (nonexistent) +++ eppwbn_16bit.vhd (revision 19) @@ -0,0 +1,134 @@ +---------------------------------------------------------------------------------------------------- +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| File: eppwbn_16 bit.vhd +--| Version: 0.01 +--| Tested in: Actel APA300 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| EPP - Wishbone bridge. +--| The top module for 16 bit wisbone data bus. +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | dic-2008 | First release +---------------------------------------------------------------------------------------------------- +--| Copyright ® 2009, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. + +--| Wishbone Rev. B.3 compatible +---------------------------------------------------------------------------------------------------- + + + +-- Bloque completo 16 bit + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use work.eppwbn_pgk.all; + +entity eppwbn_16bit is +port( + -- Externo + nStrobe: in std_logic; -- HostClk/nWrite + Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select) + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + + + -- Interno + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (15 downto 0); + DAT_O: out std_logic_vector (15 downto 0); + ADR_O: out std_logic_vector (7 downto 0); + CYC_O: out std_logic; + STB_O: out std_logic; + ACK_I: in std_logic ; + WE_O: out std_logic + ); +end eppwbn_16bit; + + + +architecture structural of eppwbn_16bit is + -- Seńales + signal s_DAT_I: std_logic_vector (7 downto 0); + signal s_DAT_O: std_logic_vector (7 downto 0); + signal s_ADR_O: std_logic_vector (7 downto 0); + signal s_CYC_O: std_logic; + signal s_STB_O: std_logic; + signal s_ACK_I: std_logic; + signal s_WE_O: std_logic; +begin + + + U_EPPWBN8: eppwbn + port map( + -- To EPP interface + nStrobe => nStrobe, + Data => Data, + nAck => nAck, + busy => busy, + PError => PError, + Sel => Sel, + nAutoFd => nAutoFd, + PeriphLogicH => PeriphLogicH, + nInit => nInit, + nFault => nFault, + nSelectIn => nSelectIn, + + -- Common signals + RST_I => RST_I, + CLK_I => CLK_I, + + -- Master EPP to slave width exteneder + DAT_I => s_DAT_I, + DAT_O => s_DAT_O, + ADR_O => s_ADR_O, + CYC_O => s_CYC_O, + STB_O => s_STB_O, + ACK_I => s_ACK_I, + WE_O => s_WE_O + ); + + U_EPPWBN_8TO16: eppwbn_width_extension + generic map( + TIME_OUT_VALUE => 255, + TIME_OUT_WIDTH => 8 + ) + port map( + -- Master EPP to slave width exteneder + DAT_I_sl => s_DAT_O, + DAT_O_sl => s_DAT_I, + ADR_I_sl => s_ADR_O, + CYC_I_sl => s_CYC_O, + STB_I_sl => s_STB_O, + ACK_O_sl => s_ACK_I, + WE_I_sl => s_WE_O, + + -- Master width exteneder to TOP + DAT_I_ma => DAT_I, + DAT_O_ma => DAT_O, + ADR_O_ma => ADR_O, + CYC_O_ma => CYC_O, + STB_O_ma => STB_O, + ACK_I_ma => ACK_I, + WE_O_ma => WE_O, + + -- Common signals + RST_I => RST_I, + CLK_I => CLK_I + ); + + +end architecture; \ No newline at end of file

eppwbn_16bit.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: eppwbn_epp_side.vhd =================================================================== --- eppwbn_epp_side.vhd (revision 16) +++ eppwbn_epp_side.vhd (revision 19) @@ -1,125 +1,125 @@ ---|------------------------------------------------------------------------------ ---| UNSL - Modular Oscilloscope ---| ---| File: eppwbn_epp_side.vhd ---| Version: 0.01 ---| Targeted device: Actel A3PE1500 ---|------------------------------------------------------------------------------ ---| Description: ---| EPP - Wishbone bridge. ---| EPP module output control (IEEE Std. 1284-2000). -------------------------------------------------------------------------------- ---| File history: ---| 0.01 | nov-2008 | First release --------------------------------------------------------------------------------- ---| Copyright ® 2008, Facundo Aguilera. ---| ---| This VHDL design file is an open design; you can redistribute it and/or ---| modify it and/or implement it after contacting the author. - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity eppwbn_epp_side is -port( - - -- Selección de modo - epp_mode: in std_logic_vector (1 downto 0);-- indicador de modo de comunicación epp - -- "00" deshabilitado - -- "01" inicial (seńales de usuario e interrupciones deshabilitadas) - -- "10" sin definir - -- "11" modo EPP normal - - -- CTRL signals - ctr_nAck: in std_logic; -- PtrClk/PeriphClk/Intr - ctr_PError: in std_logic; -- AckData/nAckReverse - ctr_Sel: in std_logic; -- XFlag (Select). Select no puede usarse - ctr_nFault: in std_logic; -- nDataAvail/nPeriphRequest - - ctr_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb - ctr_nSelectIn: out std_logic; -- 1284 Active/nAStrb - ctr_nStrobe: out std_logic; -- HostClk/nWrite - - -- WB-side signals - wb_Busy: in std_logic; -- PtrBusy/PeriphAck/nWait - wb_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb - wb_nSelectIn: out std_logic; -- 1284 Active/nAStrb - wb_nStrobe: out std_logic; -- HostClk/nWrite - -- No están implementadas las seńales personalizadas - - -- To EPP port - nAck: out std_logic; -- PtrClk/PeriphClk/Intr - PError: out std_logic; -- AckData/nAckReverse - Sel: out std_logic; -- XFlag (Select). Select no puede usarse - nFault: out std_logic; -- nDataAvail/nPeriphRequest - - Busy: out std_logic; -- PtrBusy/PeriphAck/nWait - nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb - nSelectIn: in std_logic; -- 1284 Active/nAStrb - nStrobe: in std_logic -- HostClk/nWrite - -); -end entity eppwbn_epp_side; - -architecture multiplexor of eppwbn_epp_side is - -begin - - -- Puentes - -- Son incorporados en un módulo para facilitar modificaciones - Busy <= wb_Busy; - - ctr_nAutoFd <= nAutoFd; - ctr_nSelectIn <= nSelectIn; - ctr_nStrobe <= nStrobe; - - -- Selección de salidas desde el módulo EPP cuando epp_mode = "11" - -- Como no están implementadas las seńales personalizadas se escribe "0000" - multiplexing: process (epp_mode ,ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault, - nAutoFd, nSelectIn, nStrobe) begin - case epp_mode is - - when "11" => - -- Hacia el host - nAck <= '0'; -- No están implementadas las seńales personalizadas - PError <= '0'; - Sel <= '0'; - nFault <= '0'; - - -- Hacia el módulo EPP - wb_nAutoFd <= nAutoFd; - wb_nSelectIn <= nSelectIn; - wb_nStrobe <= nStrobe; - - when "01" => - -- Hacia el host - nAck <= ctr_nAck; - PError <= ctr_PError; - Sel <= ctr_Sel; - nFault <= ctr_nFault; - - -- Hacia el módulo EPP - wb_nAutoFd <= nAutoFd; - wb_nSelectIn <= nSelectIn; - wb_nStrobe <= nStrobe; - - when others => - -- Hacia el host - nAck <= ctr_nAck; - PError <= ctr_PError; - Sel <= ctr_Sel; - nFault <= ctr_nFault; - - -- Hacia el módulo EPP - wb_nAutoFd <= '1'; - wb_nSelectIn <= '1'; - wb_nStrobe <= '1'; - end case; - end process; - -end architecture multiplexor; - - - - +--|------------------------------------------------------------------------------ +--| UNSL - Modular Oscilloscope +--| +--| File: eppwbn_epp_side.vhd +--| Version: 0.01 +--| Targeted device: Actel A3PE1500 +--|------------------------------------------------------------------------------ +--| Description: +--| EPP - Wishbone bridge. +--| EPP module output control (IEEE Std. 1284-2000). +------------------------------------------------------------------------------- +--| File history: +--| 0.01 | nov-2008 | First release +-------------------------------------------------------------------------------- +--| Copyright ® 2008, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity eppwbn_epp_side is +port( + + -- Selección de modo + epp_mode: in std_logic_vector (1 downto 0);-- indicador de modo de comunicación epp + -- "00" deshabilitado + -- "01" inicial (seńales de usuario e interrupciones deshabilitadas) + -- "10" sin definir + -- "11" modo EPP normal + + -- CTRL signals + ctr_nAck: in std_logic; -- PtrClk/PeriphClk/Intr + ctr_PError: in std_logic; -- AckData/nAckReverse + ctr_Sel: in std_logic; -- XFlag (Select). Select no puede usarse + ctr_nFault: in std_logic; -- nDataAvail/nPeriphRequest + + ctr_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb + ctr_nSelectIn: out std_logic; -- 1284 Active/nAStrb + ctr_nStrobe: out std_logic; -- HostClk/nWrite + + -- WB-side signals + wb_Busy: in std_logic; -- PtrBusy/PeriphAck/nWait + wb_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb + wb_nSelectIn: out std_logic; -- 1284 Active/nAStrb + wb_nStrobe: out std_logic; -- HostClk/nWrite + -- No están implementadas las seńales personalizadas + + -- To EPP port + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select). Select no puede usarse + nFault: out std_logic; -- nDataAvail/nPeriphRequest + + Busy: out std_logic; -- PtrBusy/PeriphAck/nWait + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + nSelectIn: in std_logic; -- 1284 Active/nAStrb + nStrobe: in std_logic -- HostClk/nWrite + +); +end entity eppwbn_epp_side; + +architecture multiplexor of eppwbn_epp_side is + +begin + + -- Puentes + -- Son incorporados en un módulo para facilitar modificaciones + Busy <= wb_Busy; + + ctr_nAutoFd <= nAutoFd; + ctr_nSelectIn <= nSelectIn; + ctr_nStrobe <= nStrobe; + + -- Selección de salidas desde el módulo EPP cuando epp_mode = "11" + -- Como no están implementadas las seńales personalizadas se escribe "0000" + multiplexing: process (epp_mode ,ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault, + nAutoFd, nSelectIn, nStrobe) begin + case epp_mode is + + when "11" => + -- Hacia el host + nAck <= '1'; -- No están implementadas las seńales personalizadas + PError <= '0'; + Sel <= '0'; + nFault <= '0'; + + -- Hacia el módulo EPP + wb_nAutoFd <= nAutoFd; + wb_nSelectIn <= nSelectIn; + wb_nStrobe <= nStrobe; + + when "01" => + -- Hacia el host + nAck <= ctr_nAck; + PError <= ctr_PError; + Sel <= ctr_Sel; + nFault <= ctr_nFault; + + -- Hacia el módulo EPP + wb_nAutoFd <= nAutoFd; + wb_nSelectIn <= nSelectIn; + wb_nStrobe <= nStrobe; + + when others => + -- Hacia el host + nAck <= ctr_nAck; + PError <= ctr_PError; + Sel <= ctr_Sel; + nFault <= ctr_nFault; + + -- Hacia el módulo EPP + wb_nAutoFd <= '1'; + wb_nSelectIn <= '1'; + wb_nStrobe <= '1'; + end case; + end process; + +end architecture multiplexor; + + + + Index: eppwbn_wbn_side.vhd =================================================================== --- eppwbn_wbn_side.vhd (revision 16) +++ eppwbn_wbn_side.vhd (revision 19) @@ -1,141 +1,147 @@ ---|------------------------------------------------------------------------------ ---| UNSL - Modular Oscilloscope ---| ---| File: eppwbn_wbn_side.vhd ---| Version: 0.20 ---| Targeted device: Actel A3PE1500 ---|------------------------------------------------------------------------------ ---| Description: ---| EPP - Wishbone bridge. ---| This module is in the wishbone side (IEEE Std. 1284-2000). -------------------------------------------------------------------------------- ---| File history: ---| 0.01 | nov-2008 | First release ---| 0.1 | jan-2009 | Sinc reset --------------------------------------------------------------------------------- ---| Copyright ® 2008, Facundo Aguilera. ---| ---| This VHDL design file is an open design; you can redistribute it and/or ---| modify it and/or implement it after contacting the author. - - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; ---use IEEE.STD_LOGIC_ARITH.ALL; - - -entity eppwbn_wbn_side is -port( - - -- al puerto epp - inStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284, Negotiation/ECP/EPP (Compatibiliy) - -- HostClk/nWrite - iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8) - -- inAck: out std_logic; -- PtrClk/PeriphClk/Intr - iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait - -- iPError: out std_logic; -- AckData/nAckReverse - -- iSel: out std_logic; -- XFlag (Select) - inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb - -- iPeriphLogicH: out std_logic; -- (Periph Logic High) - -- inInit: in std_logic; -- nReverseRequest - -- inFault: out std_logic; -- nDataAvail/nPeriphRequest - inSelectIn: in std_logic; -- 1284 Active/nAStrb - -- iHostLogicH: in std_logic; -- (Host Logic High) - -- i indica interna en el core y controlada por el bloque de control - - -- a la interface wishbone - RST_I: in std_logic; - CLK_I: in std_logic; - DAT_I: in std_logic_vector (7 downto 0); - DAT_O: out std_logic_vector (7 downto 0); - ADR_O: out std_logic_vector (7 downto 0); - CYC_O: out std_logic; - STB_O: out std_logic; - ACK_I: in std_logic ; - WE_O: out std_logic; - - - rst_pp: in std_logic -- reset desde la interfaz del puerto paralelo - - -); - -end eppwbn_wbn_side; - -architecture con_registro of eppwbn_wbn_side is -- El dato es registrado en el core. - - - signal adr_ack,data_ack: std_logic; - signal adr_reg,data_reg: std_logic_vector (7 downto 0); -- deben crearse dos registros de lectrura/escritura - signal pre_STB_O: std_logic; -- seńal previa a STB_O - -begin - - iBusy <= adr_ack or data_ack; -- nWait. Se utiliza para confirmación de lectuira/escritura de datos/direcciones - WE_O <= not(inStrobe); -- Ambas seńales tienen la misma utilidad, habilitan escritura - - - -- Data R/W - data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_pp) - begin - - if (rst_pp = '1' or RST_I = '1') then -- Reset de interfaz EPP - data_reg <= (others => '0'); - pre_STB_O <= '0'; - data_ack <= '0'; - elsif (CLK_I'event and CLK_I = '1') then - if RST_I = '1' then - data_reg <= (others => '0'); - pre_STB_O <= '0'; - data_ack <= '0'; - else - if (inAutoFd = '0' and data_ack = '0') then -- Data strobe - pre_STB_O <= '1'; - if (inStrobe = '0') then -- Escritura EPP - data_reg <= iData; - end if; - end if; - if (ACK_I = '1' and pre_STB_O = '1') then -- Dato escrito o leído - pre_STB_O <= '0'; - data_ack <= '1'; - if (inStrobe = '1') then -- Lectura EPP - data_reg <= DAT_I; - end if; - end if; - end if; - end if; - if (inAutoFd = '1' and data_ack = '1') then -- iBusy solo se pondrá a cero - data_ack <= '0'; -- una vez que haya respuesta desde la PC - end if; - - end process; - STB_O <= pre_STB_O; - CYC_O <= pre_STB_O; - DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos - -- a wishbone, lectura y escritura de datos desde epp - - - -- Adr R/W - adr_ack <= not(inSelectIn); -- Autoconfirmación de estado. - adr_strobing: process (inSelectIn, RST_I, rst_pp) - begin - if (RST_I = '1' or rst_pp = '1') then - adr_reg <= (others => '0'); - elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe - if inStrobe = '0' then - adr_reg <= iData; - end if; - end if; - end process; - ADR_O <= adr_reg; - - - -- Puerto bidireccional - iData <= data_reg when (inStrobe = '1' and data_ack = '1') else - adr_reg when (inStrobe = '1' and adr_ack = '1') else - (others => 'Z'); - - - +---------------------------------------------------------------------------------------------------- +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| File: eppwbn_wbn_side.vhd +--| Version: 0.2 +--| Tested in: Actel APA300 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| EPP - Wishbone bridge. +--| This module is in the wishbone side (IEEE Std. 1284-2000). +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | nov-2008 | First release +--| 0.1 | jan-2009 | Sinc reset +--| 0.2 | feb-2009 | Some improvements +---------------------------------------------------------------------------------------------------- +--| Copyright ® 2008, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; + + +entity eppwbn_wbn_side is +port( + + -- al puerto epp + -- Nomenclatura IEEE Std. 1284-2000 + -- Negotiation/ECP/EPP (Compatibiliy) + inStrobe: in std_logic; -- HostClk/nWrite + iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8) + -- inAck: out std_logic; -- PtrClk/PeriphClk/Intr + iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait + -- iPError: out std_logic; -- AckData/nAckReverse + -- iSel: out std_logic; -- XFlag (Select) + inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + -- iPeriphLogicH: out std_logic; -- (Periph Logic High) + -- inInit: in std_logic; -- nReverseRequest + -- inFault: out std_logic; -- nDataAvail/nPeriphRequest + inSelectIn: in std_logic; -- 1284 Active/nAStrb + -- iHostLogicH: in std_logic; -- (Host Logic High) + -- i indica interna en el core y controlada por el bloque de control + + -- a la interface wishbone + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (7 downto 0); + DAT_O: out std_logic_vector (7 downto 0); + ADR_O: out std_logic_vector (7 downto 0); + CYC_O: out std_logic; + STB_O: out std_logic; + ACK_I: in std_logic ; + WE_O: out std_logic; + + + rst_pp: in std_logic -- reset desde la interfaz del puerto paralelo +); + +end eppwbn_wbn_side; + +architecture con_registro of eppwbn_wbn_side is + + + signal adr_ack,data_ack: std_logic; + signal adr_reg,data_reg: std_logic_vector (7 downto 0); -- registros internos temporales + signal pre_STB_O: std_logic; -- registro que maneja a STB_O + +begin + + iBusy <= adr_ack or data_ack; -- nWait. Se utiliza para confirmación de lectura/escritura de datos/direcciones + WE_O <= not(inStrobe); -- Ambas seńales tienen la misma utilidad, habilitan escritura + STB_O <= pre_STB_O ; + CYC_O <= pre_STB_O; + DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos + -- a wishbone, lectura y escritura de datos desde epp + + -- Data R/W + data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_pp, data_ack,inStrobe,iData) + begin + + if (rst_pp = '1') then -- Reset de desde interfaz EPP asíncrono + data_reg <= (others => '0'); + pre_STB_O <= '0'; + data_ack <= '0'; + + elsif inAutoFd = '0' and data_ack = '0' and pre_STB_O = '0' then -- Data strobe + if (inStrobe = '0') then -- Escritura EPP + data_reg <= iData; + end if; + pre_STB_O <= '1'; + elsif inAutoFd = '1' and data_ack = '1' then -- iBusy solo se pondrá a cero + data_ack <= '0'; + -- Se indica el la comprobación de data_ack = '1' para forzar a la herramienta + -- de síntesis a crear un registro. + + elsif (CLK_I'event and CLK_I = '1') then + if RST_I = '1' then + data_reg <= (others => '0'); + pre_STB_O <= '0'; + data_ack <= '0'; + else + if (ACK_I = '1' and pre_STB_O = '1') then -- Dato escrito o leído + pre_STB_O <= '0'; + data_ack <= '1'; + if (inStrobe = '1') then -- Lectura EPP + data_reg <= DAT_I; + end if; + end if; + end if; + end if; + + + + end process; + + + + -- Adr R/W + adr_ack <= not(inSelectIn); -- Autoconfirmación de estado. + adr_strobing: process (inSelectIn, RST_I, rst_pp,inStrobe,iData) + begin + if (RST_I = '1' or rst_pp = '1') then + adr_reg <= (others => '0'); + elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe + if inStrobe = '0' then + adr_reg <= iData; + end if; + end if; + end process; + ADR_O <= adr_reg; + + + -- Puerto bidireccional + iData <= data_reg when (inStrobe = '1' and data_ack = '1') else + adr_reg when (inStrobe = '1' and adr_ack = '1') else + (others => 'Z'); + + + end con_registro; \ No newline at end of file Index: test_memory.vhd =================================================================== --- test_memory.vhd (nonexistent) +++ test_memory.vhd (revision 19) @@ -0,0 +1,399 @@ +------------------------------------------------------------------------------- +-- Title : Single port RAM +-- Project : Memory Cores +------------------------------------------------------------------------------- +-- File : spmem.vhd +-- Author : Jamil Khatib (khatib@ieee.org) +-- Organization: OpenIPCore Project +-- Created : 1999/5/14 +-- Last update : 2000/12/19 +-- Platform : +-- Simulators : Modelsim 5.3XE/Windows98 +-- Synthesizers: Leonardo/WindowsNT +-- Target : +-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned +------------------------------------------------------------------------------- +-- Description: Single Port memory +------------------------------------------------------------------------------- +-- Copyright (c) 2000 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml + +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 12 May 1999 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : Created +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 2 +-- Version : 0.2 +-- Date : 19 Dec 2000 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : General review +-- Two versions are now available with reset and without +-- Default output can can be defined +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 3 +-- Version : 0.3 +-- Date : 5 Jan 2001 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : Registered Read Address feature is added to make use of +-- Altera's FPGAs memory bits +-- This feature was added from Richard Herveille's +-- contribution and his memory core +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1asinc +-- Version : 0.1asinc +-- Date : 13 Mar 2009 +-- Modifier : Aguilera Facundo (afacu@ieee.org) +-- Desccription : Original file modified to reduce code and to make WR and +-- reset signals positive, Reset sincronous, data transfer +-- asinc. +------------------------------------------------------------------------------- + +-- (!) +-- Original file modified to reduce code and to make WR and reset signals +-- positive, Reset sincronous, data transfer asinc. + + +library ieee; + +use ieee.std_logic_1164.all; + +use ieee.std_logic_unsigned.all; + +------------------------------------------------------------------------------- +-- Single port Memory core with reset +-- To make use of on FPGA memory bits do not use the RESET option +-- For Altera's FPGA you have to use also OPTION := 1 + +entity test_memory is + + generic ( --USE_RESET : boolean := false; -- use system reset + + --USE_CS : boolean := false; -- use chip select signal + + DEFAULT_OUT : std_logic := '0'; -- Default output + --OPTION : integer := 1; -- 1: Registered read Address(suitable + -- for Altera's FPGAs + -- 0: non registered read address + ADD_WIDTH : integer := 8; + WIDTH : integer := 8); + port ( + cs : in std_logic; -- chip select + clk : in std_logic; -- write clock + reset : in std_logic; -- System Reset + add : in std_logic_vector(add_width -1 downto 0); -- Address + Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data + Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data + WR : in std_logic); -- Read Write Enable +end test_memory; + + + +architecture spmem_beh of test_memory is + + type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0); + -- signal s_reset: std_logic; + -- Memory Type + signal data : data_array(0 to (2** add_width-1) ); -- Local data + + + -- FLEX/APEX devices require address to be registered with inclock for read operations + -- This signal is used only when OPTION = 1 + -- signal regA : std_logic_vector( (add_width -1) downto 0); + + procedure init_mem(signal memory_cell : inout data_array ) is + + begin + + for i in 0 to (2** add_width-1) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + +begin -- spmem_beh +-- ------------------------------------------------------------------------------- +-- -- Non Registered Read Address +-- ------------------------------------------------------------------------------- + -- NON_REG : if OPTION = 0 generate +-- ------------------------------------------------------------------------------- +-- -- Clocked Process with Reset +-- ------------------------------------------------------------------------------- + -- Reset_ENABLED : if USE_RESET = true generate + +-- ------------------------------------------------------------------------------- +-- CS_ENABLED : if USE_CS = true generate + + process (clk, reset,CS,WR, add) + + begin -- PROCESS + -- activities triggered by asynchronous reset (active low) + + -- activities triggered by rising edge of clock + + data_out <= data(conv_integer(add)); + + + if clk'event and clk = '1' then + if reset = '1' then + init_mem (data); + elsif CS = '1' then + if WR = '1' then + data(conv_integer(add)) <= Data_In; + end if; + end if; + end if; + + + end process; +-- end generate CS_ENABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + -- CS_DISABLED : if USE_CS = false generate + + -- process (clk, reset) + + + -- begin -- PROCESS + -- -- activities triggered by asynchronous reset (active low) + + -- if reset = '0' then + -- data_out <= (others => DEFAULT_OUT); + -- init_mem ( data); + + -- -- activities triggered by rising edge of clock + -- elsif clk'event and clk = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(add)); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_DISABLED; + +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate Reset_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- -- Clocked Process without Reset +-- ------------------------------------------------------------------------------- + -- Reset_DISABLED : if USE_RESET = false generate + +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_ENABLED : if USE_CS = true generate + + -- process (clk) + -- begin -- PROCESS + + -- -- activities triggered by rising edge of clock + -- if clk'event and clk = '1' then + -- if cs = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(add)); + -- end if; + -- else + -- data_out <= (others => DEFAULT_OUT); + -- end if; + + + -- end if; + + -- end process; + -- end generate CS_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_DISABLED : if USE_CS = false generate + + -- process (clk) + -- begin -- PROCESS + + -- -- activities triggered by rising edge of clock + -- if clk'event and clk = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(add)); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_DISABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate Reset_DISABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate NON_REG; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- REG: if OPTION = 1 generate +-- ------------------------------------------------------------------------------- +-- -- Clocked Process with Reset +-- ------------------------------------------------------------------------------- + -- Reset_ENABLED : if USE_RESET = true generate + +-- ------------------------------------------------------------------------------- + -- CS_ENABLED : if USE_CS = true generate + + -- process (clk, reset) + + -- begin -- PROCESS + -- -- activities triggered by asynchronous reset (active low) + + -- if reset = '0' then + -- data_out <= (others => DEFAULT_OUT); + -- init_mem ( data); + + -- -- activities triggered by rising edge of clock + -- elsif clk'event and clk = '1' then + + -- regA <= add; + + -- if CS = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(regA)); + -- end if; + -- else + -- data_out <= (others => DEFAULT_OUT); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_DISABLED : if USE_CS = false generate + + -- process (clk, reset) + + + -- begin -- PROCESS + -- -- activities triggered by asynchronous reset (active low) + + -- if reset = '0' then + -- data_out <= (others => DEFAULT_OUT); + -- init_mem ( data); + + -- -- activities triggered by rising edge of clock + -- elsif clk'event and clk = '1' then + -- regA <= add; + + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(regA)); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_DISABLED; + +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate Reset_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- -- Clocked Process without Reset +-- ------------------------------------------------------------------------------- + -- Reset_DISABLED : if USE_RESET = false generate + +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_ENABLED : if USE_CS = true generate + + -- process (clk) + -- begin -- PROCESS + + -- -- activities triggered by rising edge of clock + -- if clk'event and clk = '1' then + + -- regA <= add; + + -- if cs = '1' then + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(regA)); + -- end if; + -- else + -- data_out <= (others => DEFAULT_OUT); + -- end if; + + + -- end if; + + -- end process; + -- end generate CS_ENABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- CS_DISABLED : if USE_CS = false generate + + -- process (clk) + -- begin -- PROCESS + + -- -- activities triggered by rising edge of clock + -- if clk'event and clk = '1' then + + -- regA <= add; + + -- if WR = '0' then + -- data(conv_integer(add)) <= data_in; + -- data_out <= (others => DEFAULT_OUT); + -- else + -- data_out <= data(conv_integer(regA)); + -- end if; + + -- end if; + + -- end process; + -- end generate CS_DISABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + -- end generate Reset_DISABLED; +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- + +-- end generate REG; + +end spmem_beh; +-------------------------------------------------------------------------------

test_memory.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: eppwbn_ctrl.vhd =================================================================== --- eppwbn_ctrl.vhd (revision 16) +++ eppwbn_ctrl.vhd (revision 19) @@ -1,190 +1,208 @@ ---|------------------------------------------------------------------------------ ---| UNSL - Modular Oscilloscope ---| ---| File: eppwbn_wbn_side.vhd ---| Version: 0.20 ---| Targeted device: Actel A3PE1500 ---|----------------------------------------------------------------------------- ---| Description: ---| EPP - Wishbone bridge. ---| This module controls the negotiation (IEEE Std. 1284-2000). ---| This can be easily modified to control other modes besides the EPP. -------------------------------------------------------------------------------- ---| File history: ---| 0.01 | nov-2008 | First testing release ---| 0.20 | dic-2008 | Customs signals without tri-state ---| 0.21 | jan-2009 | Sinc reset --------------------------------------------------------------------------------- ---| Copyright ® 2008, Facundo Aguilera. ---| ---| This VHDL design file is an open design; you can redistribute it and/or ---| modify it and/or implement it after contacting the author. - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity eppwbn_ctrl is -port( - - -- salida al puerto epp - nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284-2000, - -- Negotiation/ECP/EPP (Compatibiliy) - -- HostClk/nWrite - Data: in std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8) - nAck: out std_logic; -- PtrClk/PeriphClk/Intr - -- Busy: out std_logic; -- PtrBusy/PeriphAck/nWait - PError: out std_logic; -- AckData/nAckReverse - Sel: out std_logic; -- XFlag (Select). Select no puede usarse - nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb - PeriphLogicH: out std_logic; -- (Periph Logic High) - nInit: in std_logic; -- nReverseRequest - nFault: out std_logic; -- nDataAvail/nPeriphRequest - nSelectIn: in std_logic; -- 1284 Active/nAStrb - -- HostLogicH: in std_logic; -- (Host Logic High) - -- i indica misma seńal de salida al puerto, aunque interna en el core y controlada por el bloque de control - - -- salida a la interface wishbone - RST_I: in std_logic; - CLK_I: in std_logic; - - -- seńales internas - rst_pp: out std_logic; -- generador de reset desde la interfaz del puerto paralelo - epp_mode: out std_logic_vector (1 downto 0) -- indicador de modo de comunicaci?n epp - -- "00" deshabilitado - -- "01" inicial (se?ales de usuario e interrupciones deshabilitadas) - -- "10" sin definir - -- "11" modo EPP normal -); -end entity eppwbn_ctrl; - - -architecture state_machines of eppwbn_ctrl is - type StateType is ( - st_compatibility_idle, -- Los estados corresponden a los especificados - st_negotiation2, -- por el est?ndar. - -- Los n?meros de los estados negotiation corresponden - -- a las fases del est?ndar. - st_initial_epp, - st_epp_mode - -- otros modos - ); - signal next_state, present_state: StateType; - signal ext_req_val: std_logic_vector (7 downto 0); -begin - - ---------------------------------------------------------------------------------------- - -- generación de seńal de reset para otros módulos y seńal de encendido hacia el host - rst_pp <= not(nInit) and not(nSelectIn); -- (nInit = '0') and (nSelectIn = '0'); - - PeriphLogicH <= '1'; - - ---------------------------------------------------------------------------------------- - -- almacenamiento de Extensibility Request Value (asíncrono) - P_data_store: process(nStrobe, present_state, Data, RST_I, nInit, nSelectIn) - begin - if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then - ext_req_val <= (others => '0'); - elsif (present_state = st_negotiation2 and nStrobe'event and nStrobe = '0') then - ext_req_val <= Data; - end if; - end process P_data_store; - - ---------------------------------------------------------------------------------------- - -- estado siguiente - P_state_comb: process(present_state, next_state, RST_I, nSelectIn, nAutoFd, ext_req_val, nInit, nStrobe) begin - - if RST_I = '1' then - next_state <= st_compatibility_idle; - else - case present_state is - - when st_compatibility_idle => - PError <= '0'; - nFault <= '1'; - Sel <= '1'; - nAck <= '1'; - - epp_mode <= "00"; - - -- verificación de compatibilidad con 1284 - if (nAutoFd = '0' and nSelectIn = '1') then - next_state <= st_negotiation2; - else - next_state <= st_compatibility_idle; - end if; - - when st_negotiation2 => - PError <= '1'; - nFault <= '1'; - Sel <= '1'; - nAck <= '0'; - - epp_mode <= "00"; - - -- Reconocimiento del host - if (nStrobe = '1' and - nAutoFd = '1') then - - -- Pedido de modo EPP - if (ext_req_val = "01000000") then - next_state <= st_initial_epp; - - -- Otros modos - - else - next_state <= st_compatibility_idle; - end if; - else - next_state <= st_negotiation2; - end if; - - when st_initial_epp => - Sel <= '1'; - PError <= '1'; - nFault <= '1'; - nAck <= '1'; - - epp_mode <= "01"; - - -- Finalizaci?n del modo EPP - if nInit = '0' then - next_state <= st_compatibility_idle; - -- Comienzo del primer ciclo EPP - elsif (nSelectIn = '0' or nAutoFd = '0') then - next_state <= st_epp_mode; - else - next_state <= st_initial_epp; - end if; - - when st_epp_mode => - Sel <= '0'; -- El bus debe asegurar que se puedan usar - PError <= '0'; -- las seńales definidas por el usuario en el módulo - nFault <= '0'; -- EPP. - nAck <= '0'; - - epp_mode <= "11"; - - -- Finalizaci?n del modo EPP - - next_state <= st_epp_mode; - -- Se sale de este estado en forma asíncrona ya que esta acción - end case; -- no tiene handshake. - end if; - - end process P_state_comb; - - - - ---------------------------------------------------------------------------------------- - -- estado actual - P_state_clocked: process(CLK_I, nInit, nSelectIn) begin - if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then - present_state <= st_compatibility_idle; - elsif present_state = st_epp_mode and nInit = '0' then - present_state <= st_compatibility_idle; - elsif (CLK_I'event and CLK_I='1') then - present_state <= next_state; - end if; - end process P_state_clocked; - +---------------------------------------------------------------------------------------------------- +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| File: eppwbn_wbn_side.vhd +--| Version: 0.21 +--| Tested in: Actel APA300 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| EPP - Wishbone bridge. +--| This module controls the negotiation (IEEE Std. 1284-2000). +--| This can be easily modified to control other modes besides the EPP. +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | nov-2008 | First testing release +--| 0.20 | dic-2008 | Custom signals without tri-state +--| 0.21 | jan-2009 | Sinc reset +---------------------------------------------------------------------------------------------------- +--| Copyright ® 2008, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity eppwbn_ctrl is +port( + + -- salida al puerto epp + nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284-2000, + -- Negotiation/ECP/EPP (Compatibiliy) + -- HostClk/nWrite + Data: in std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + -- Busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select). Select no puede usarse + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + -- HostLogicH: in std_logic; -- (Host Logic High) + -- i indica misma seńal de salida al puerto, aunque interna en el core y controlada por el bloque de control + + -- salida a la interface wishbone + RST_I: in std_logic; + CLK_I: in std_logic; + + -- seńales internas + rst_pp: out std_logic; -- generador de reset desde la interfaz del puerto paralelo + epp_mode: out std_logic_vector (1 downto 0) -- indicador de modo de comunicaci?n epp + -- "00" deshabilitado + -- "01" inicial (se?ales de usuario e interrupciones deshabilitadas) + -- "10" sin definir + -- "11" modo EPP normal +); +end entity eppwbn_ctrl; + + +architecture state_machines of eppwbn_ctrl is + type StateType is ( + st_compatibility_idle, -- Los estados corresponden a los especificados + st_negotiation2, -- por el est?ndar. + -- Los n?meros de los estados negotiation corresponden + -- a las fases del est?ndar. + st_initial_epp, + st_epp_mode + -- otros modos + ); + signal next_state, present_state: StateType; + signal ext_req_val: std_logic_vector (7 downto 0); +begin + + ---------------------------------------------------------------------------------------- + -- generación de seńal de reset para otros módulos y seńal de encendido hacia el host + rst_pp <= not(nInit); -- (nInit = '0') and (nSelectIn = '0'); + + PeriphLogicH <= '1'; + + ---------------------------------------------------------------------------------------- + -- almacenamiento de Extensibility Request Value (asíncrono) + P_data_store: process(nStrobe, present_state, Data, RST_I, nInit, nSelectIn) + begin + if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then + ext_req_val <= (others => '0'); + elsif (present_state = st_negotiation2 and nStrobe = '0') then + ext_req_val <= Data; + end if; + end process P_data_store; + + ---------------------------------------------------------------------------------------- + -- estado siguiente + P_state_comb: process(present_state, next_state, RST_I, nSelectIn, nAutoFd, ext_req_val, nInit, nStrobe) begin + + if RST_I = '1' then + PError <= '0'; + nFault <= '1'; + Sel <= '1'; + nAck <= '1'; + + epp_mode <= "00"; + + next_state <= st_compatibility_idle; + else + case present_state is + + when st_compatibility_idle => + PError <= '0'; + nFault <= '1'; + Sel <= '1'; + nAck <= '1'; + + epp_mode <= "00"; + + -- verificación de compatibilidad con 1284 + if (nAutoFd = '0' and nSelectIn = '1') then + next_state <= st_negotiation2; + else + next_state <= st_compatibility_idle; + end if; + + when st_negotiation2 => + PError <= '1'; + nFault <= '1'; + Sel <= '1'; + nAck <= '0'; + + epp_mode <= "00"; + + -- Respuesta según modo solicitado + if (nStrobe = '1' and + nAutoFd = '1') then + if (ext_req_val = "01000000") then + next_state <= st_initial_epp; + + -- Otros modos + + else + next_state <= st_compatibility_idle; + end if; + else + next_state <= st_negotiation2; + end if; + + when st_initial_epp => + Sel <= '1'; + PError <= '1'; + nFault <= '1'; + nAck <= '1'; + + epp_mode <= "01"; + + + -- Finalizacón del modo EPP o cambio a EPP idle + if nInit = '0' then + next_state <= st_compatibility_idle; + elsif (nSelectIn = '0' or nAutoFd = '0') then + next_state <= st_epp_mode; + else + next_state <= st_initial_epp; + end if; + + when st_epp_mode => + Sel <= '0'; -- El bus debe asegurar que se puedan usar + PError <= '0'; -- las seńales definidas por el usuario en el módulo + nFault <= '0'; -- EPP. + nAck <= '0'; + + epp_mode <= "11"; + + -- Finalización del modo EPP + if nInit = '0' then + next_state <= st_compatibility_idle; + else + next_state <= st_epp_mode; + end if; + -- Se sale de este estado en forma asíncrona ya que esta acción + end case; -- no tiene handshake. + end if; + + end process P_state_comb; + + + + ---------------------------------------------------------------------------------------- + -- estado actual + P_state_clocked: process(CLK_I, nInit, nSelectIn,RST_I) begin + -- if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then + -- present_state <= st_compatibility_idle; + -- elsif present_state = st_epp_mode and nInit = '0' then + -- present_state <= st_compatibility_idle; + -- elsif (CLK_I'event and CLK_I='1') then + -- present_state <= next_state; + -- end if; + + + if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then + present_state <= st_compatibility_idle; + elsif (CLK_I'event and CLK_I='1') then + present_state <= next_state; + end if; + end process P_state_clocked; + end architecture state_machines; \ No newline at end of file Index: eppwbm_width_extension.vhd =================================================================== --- eppwbm_width_extension.vhd (nonexistent) +++ eppwbm_width_extension.vhd (revision 19) @@ -0,0 +1,162 @@ +---------------------------------------------------------------------------------------------------- +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| eppwbn_16bit_test.vhd +--| Version: 0.01 +--| Tested in: Actel APA300 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| EPP - Wishbone bridge. +--| Convert 8 to 16 bits width data bus +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | mar-2009 | First release +---------------------------------------------------------------------------------------------------- +--| Copyright ® 2008, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. + +--| Wishbone Rev. B.3 compatible +---------------------------------------------------------------------------------------------------- + + +-- COMO USAR: +-- Puente entre un bus de datos de 8 bit (esclavo) y otro de 16 bit (maestro). cada dos acciones del +-- lado de 8 bit realiza una en en lado de 16. Posee un timer configurable con el que vuelve al +-- estado inicial luego de sierto tiempo (ningun byte leido). También vuelve al estado inicial al +-- hacer un cambio de dirección, por lo que puede realizarse una sincronización inicial haciendo un +-- cambio de dirección de escritura. + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use work.eppwbn_pgk.all; + +entity eppwbn_width_extension is + generic ( + TIME_OUT_VALUE: integer := 255; + TIME_OUT_WIDTH: integer := 8; + ); + port( + -- Slave signals + DAT_I_sl: in std_logic_vector (7 downto 0); + DAT_O_sl: out std_logic_vector (7 downto 0); + ADR_I_sl: in std_logic_vector (7 downto 0); + CYC_I_sl: in std_logic; + STB_I_sl: in std_logic; + ACK_O_sl: out std_logic ; + WE_I_sl: in std_logic; + + + -- Master signals + DAT_I_ma: in std_logic_vector (15 downto 0); + DAT_O_ma: out std_logic_vector (15 downto 0); + ADR_O_ma: out std_logic_vector (7 downto 0); + CYC_O_ma: out std_logic; + STB_O_ma: out std_logic; + ACK_I_ma: in std_logic ; + WE_O_ma: out std_logic; + + -- Common signals + RST_I: in std_logic; + CLK_I: in std_logic; + ); +end entity eppwbn_width_extension; + + +architecture arch_0 of eppwbn_width_extension is + type StateType is ( + st_low, + st_high + ); + signal next_state, present_state: StateType; + + signal dat_reg, adr_reg: std_logic_vector (7 downto 0); -- Almacena temporalmente las entradas + signal timer, time_out_ref: std_logic_vector (TIME_OUT_WIDTH - 1 downto 0); + +begin + + ADR_O_ma <= ADR_I_sl; + time_out_ref <= TIME_OUT_VALUE; + + P_state_comb: process(DAT_I_sl,CYC_I_sl,STB_I_sl,WE_I_sl,ACK_I_ma,present_state) + begin + case present_state is + + -- Escritura: Seńales de hadshake provistas por el módulo. Se guarda byte bajo. + -- Lectura: Seńales de hadshake provistas por fuente. Se guarda byte alto. + when st_low => + WE_O_ma <= '0'; + DAT_O_ma <= (others => '0'); + DAT_O_sl <= DAT_I_ma(7 downto 0); + adr_reg <= ADR_I_sl; + + if WE_I_sl = '1' then + CYC_O_ma <= '0'; -- Esperar hasta recibir el proximo byte + STB_O_ma <= '0'; + ACK_O_sl <= CYC_I_sl & STB_I_sl; -- Genera autorespuesta + dat_reg <= DAT_I_sl; -- Guarda byte bajo + else + CYC_O_ma <= CYC_I_sl; + STB_O_ma <= STB_I_sl; + ACK_O_sl <= ACK_I_ma; + dat_reg <= DAT_I_ma(15 downto 8); + end if; + + + + if (CYC_I_sl = '1' and STB_I_sl = '1') and (WE_I_sl = '1' or ACK_I_ma = '1') then + next_state <= st_high; + else + next_state <= st_low; + end if; + + -- Escritura: Seńales de hadshake provistas por fuentepor el módulo. + -- Lectura: Seńales de hadshake provistas por el módulo. + when st_high => + WE_O_ma <= WE_I_sl; + DAT_O_ma <= (DAT_I_sl, dat_reg); + DAT_O_sl <= dat_reg; + dat_reg <= dat_reg; + adr_reg <= adr_reg; + if adr_reg = ADR_I_sl then + if WE_I_sl = '1' then + CYC_O_ma <= CYC_I_sl; -- Usa seńales de la fuente + STB_O_ma <= STB_I_sl; + ACK_O_sl <= ACK_I_sl; + else + CYC_O_ma <= '0'; + STB_O_ma <= '0'; + ACK_O_sl <= CYC_I_sl & STB_I_sl; -- Genera autorespuesta + end if; + else + CYC_O_ma <= 0; + STB_O_ma <= 0; + ACK_O_sl <= 0; + end if; + + if ((CYC_I_sl and STB_I_sl) and (WE_I_sl != '1' or ACK_I_ma = '1')) + or ((CYC_I_sl and STB_I_sl) and (ADR_I_sl != adr_reg)) + or (timer >= time_out_ref) then + next_state <= st_low; + else + next_state <= st_high; + end + + + P_state_clocked: process(RST_I,CLK_I) + begin + if RST_I = '1' then + present_state <= st_low; + dat_reg <= (others => '0'); + adr_reg <= (others => '0'); + timer <= (others => '0'); + elsif CLK_I'event and CLK_I = '1' then + present_state <= next_state; + timer = timer + '1'; + end if; + end process; + +end architecture arch_0;

eppwbm_width_extension.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: eppwbn_test_wb_side.vhd =================================================================== --- eppwbn_test_wb_side.vhd (revision 16) +++ eppwbn_test_wb_side.vhd (revision 19) @@ -13,7 +13,7 @@ --| File history: --| 0.10 | dic-2008 | First release -------------------------------------------------------------------------------- ---| Copyright ® 2008, Facundo Aguilera. +--| Copyright ® 2008, Facundo Aguilera. --| --| This VHDL design file is an open design; you can redistribute it and/or --| modify it and/or implement it after contacting the author. @@ -43,7 +43,11 @@ signal auto_ack: std_logic; begin - MEM1: mem_8bit_reset + MEM1: test_memory + generic map( + DEFAULT_OUT => '0'; + ADD_WIDTH => 8; + WIDTH => 8 port map ( cs => auto_ack, clk => CLK_I,

/eppwbn_16bit_test_tbench_text.vhd

eppwbn_16bit_test_tbench_text.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: eppwbn_width_extension.vhd =================================================================== --- eppwbn_width_extension.vhd (nonexistent) +++ eppwbn_width_extension.vhd (revision 19) @@ -0,0 +1,181 @@ +---------------------------------------------------------------------------------------------------- +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| Version: 0.01 +--| Tested in: Actel APA300 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| EPP - Wishbone bridge. +--| Convert 8 to 16 bits width data bus +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | mar-2009 | First release +---------------------------------------------------------------------------------------------------- +--| Copyright ® 2008, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. + +--| Wishbone Rev. B.3 compatible +---------------------------------------------------------------------------------------------------- + + +-- COMO USAR: +-- Puente entre un bus de datos de 8 bit (esclavo) y otro de 16 bit (maestro). cada dos acciones del +-- lado de 8 bit realiza una en en lado de 16. Posee un timer configurable con el que vuelve al +-- estado inicial luego de sierto tiempo (ningun byte leido). También vuelve al estado inicial al +-- hacer un cambio de dirección, por lo que puede realizarse una sincronización inicial haciendo un +-- cambio de dirección de escritura. + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.std_logic_unsigned.all; +use IEEE.numeric_std.all; +use work.eppwbn_pgk.all; + +entity eppwbn_width_extension is + generic ( + TIME_OUT_VALUE: integer := 255; + TIME_OUT_WIDTH: integer := 8 + ); + port( + -- Slave signals + DAT_I_sl: in std_logic_vector (7 downto 0); + DAT_O_sl: out std_logic_vector (7 downto 0); + ADR_I_sl: in std_logic_vector (7 downto 0); + CYC_I_sl: in std_logic; + STB_I_sl: in std_logic; + ACK_O_sl: out std_logic ; + WE_I_sl: in std_logic; + + + -- Master signals + DAT_I_ma: in std_logic_vector (15 downto 0); + DAT_O_ma: out std_logic_vector (15 downto 0); + ADR_O_ma: out std_logic_vector (7 downto 0); + CYC_O_ma: out std_logic; + STB_O_ma: out std_logic; + ACK_I_ma: in std_logic ; + WE_O_ma: out std_logic; + + -- Common signals + RST_I: in std_logic; + CLK_I: in std_logic + ); +end entity eppwbn_width_extension; + + +architecture arch_0 of eppwbn_width_extension is + type StateType is ( + st_low, + st_high + ); + signal next_state, present_state: StateType; + + signal dat_reg, adr_reg: std_logic_vector (7 downto 0); -- Almacena temporalmente las entradas + signal timer, time_out_ref: std_logic_vector (TIME_OUT_WIDTH - 1 downto 0); + +begin + + ADR_O_ma <= ADR_I_sl; + time_out_ref <= conv_std_logic_vector(TIME_OUT_VALUE, TIME_OUT_WIDTH); + + P_state_comb: process(DAT_I_sl,CYC_I_sl,STB_I_sl,WE_I_sl,ACK_I_ma,present_state,ADR_I_sl, + DAT_I_ma,dat_reg,adr_reg,timer,time_out_ref) + begin + + case present_state is + + -- Escritura: Seńales de hadshake provistas por el módulo. Se guarda byte bajo. + -- Lectura: Seńales de hadshake provistas por fuente. Se guarda byte alto. + when st_low => + WE_O_ma <= '0'; + DAT_O_ma <= (others => '0'); + DAT_O_sl <= DAT_I_ma(7 downto 0); + if WE_I_sl = '1' then + CYC_O_ma <= '0'; -- Esperar hasta recibir el proximo byte + STB_O_ma <= '0'; + ACK_O_sl <= CYC_I_sl and STB_I_sl; -- Genera autorespuesta + else + CYC_O_ma <= CYC_I_sl; + STB_O_ma <= STB_I_sl; + ACK_O_sl <= ACK_I_ma; + end if; + + + + if (CYC_I_sl = '1' and STB_I_sl = '1') and (WE_I_sl = '1' or ACK_I_ma = '1') then + next_state <= st_high; + else + next_state <= st_low; + end if; + + -- Escritura: Seńales de hadshake provistas por fuentepor el módulo. + -- Lectura: Seńales de hadshake provistas por el módulo. + when others => + WE_O_ma <= WE_I_sl; + DAT_O_ma <= DAT_I_sl & dat_reg; + DAT_O_sl <= dat_reg; + if adr_reg = ADR_I_sl then + if WE_I_sl = '1' then + CYC_O_ma <= CYC_I_sl; -- Usa seńales de la fuente + STB_O_ma <= STB_I_sl; + ACK_O_sl <= ACK_I_ma; + else + CYC_O_ma <= '0'; + STB_O_ma <= '0'; + ACK_O_sl <= CYC_I_sl and STB_I_sl; -- Genera autorespuesta + end if; + else + CYC_O_ma <= '0'; + STB_O_ma <= '0'; + ACK_O_sl <= '0'; + end if; + + if ((CYC_I_sl = '1' and STB_I_sl = '1') and (WE_I_sl /= '1' or ACK_I_ma = '1')) + or ((CYC_I_sl = '1' and STB_I_sl = '1') and (ADR_I_sl /= adr_reg)) + or (timer >= time_out_ref) then + next_state <= st_low; + else + next_state <= st_high; + end if; + end case; + + end process; + + + P_state_clocked: process(RST_I,CLK_I,next_state,timer) + begin + if RST_I = '1' then + present_state <= st_low; + + timer <= (others => '0'); + dat_reg <= (others => '0'); + adr_reg <= (others => '0'); + elsif CLK_I'event and CLK_I = '1' then + -- Resgistrar los valores si va a cambir al estado st_high + if next_state = st_high and present_state = st_low then + adr_reg <= ADR_I_sl; + if WE_I_sl = '1' then + dat_reg <= DAT_I_sl; -- Guarda byte bajo + else + dat_reg <= DAT_I_ma(15 downto 8); + end if; + end if; + + -- Configuración del timer + if present_state = st_high then + timer <= timer + 1; + else + timer <= (others => '0'); + end if; + + -- Cambio de estado + present_state <= next_state; + end if; + end process; + +end architecture arch_0;

eppwbn_width_extension.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: pll.vhd =================================================================== --- pll.vhd (nonexistent) +++ pll.vhd (revision 19) @@ -0,0 +1,59 @@ +-- Version: 8.5 8.5.0.34 + +library ieee; +use ieee.std_logic_1164.all; +library APA; +use APA.all; + +entity pll is + port(GLB, LOCK : out std_logic; CLK : in std_logic) ; +end pll; + + +architecture DEF_ARCH of pll is + + component PLLCORE + port(SDOUT : out std_logic; SCLK, SDIN, SSHIFT, SUPDATE : + in std_logic := 'U'; GLB : out std_logic; CLK : in + std_logic := 'U'; GLA : out std_logic; CLKA : in + std_logic := 'U'; LOCK : out std_logic; MODE, FBDIV5, + EXTFB, FBSEL0, FBSEL1, FINDIV0, FINDIV1, FINDIV2, FINDIV3, + FINDIV4, FBDIV0, FBDIV1, FBDIV2, FBDIV3, FBDIV4, STATBSEL, + DLYB0, DLYB1, OBDIV0, OBDIV1, STATASEL, DLYA0, DLYA1, + OADIV0, OADIV1, OAMUX0, OAMUX1, OBMUX0, OBMUX1, OBMUX2, + FBDLY0, FBDLY1, FBDLY2, FBDLY3, XDLYSEL : in std_logic := + 'U') ; + end component; + + component PWR + port( Y : out std_logic); + end component; + + component GND + port( Y : out std_logic); + end component; + + signal VCC, GND_1_net : std_logic ; + begin + + PWR_1_net : PWR port map(Y => VCC); + GND_2_net : GND port map(Y => GND_1_net); + Core : PLLCORE + port map(SDOUT => OPEN , SCLK => GND_1_net, SDIN => + GND_1_net, SSHIFT => GND_1_net, SUPDATE => GND_1_net, + GLB => GLB, CLK => CLK, GLA => OPEN , CLKA => GND_1_net, + LOCK => LOCK, MODE => GND_1_net, FBDIV5 => GND_1_net, + EXTFB => GND_1_net, FBSEL0 => VCC, FBSEL1 => GND_1_net, + FINDIV0 => GND_1_net, FINDIV1 => GND_1_net, FINDIV2 => + GND_1_net, FINDIV3 => GND_1_net, FINDIV4 => GND_1_net, + FBDIV0 => GND_1_net, FBDIV1 => GND_1_net, FBDIV2 => + GND_1_net, FBDIV3 => GND_1_net, FBDIV4 => GND_1_net, + STATBSEL => GND_1_net, DLYB0 => GND_1_net, DLYB1 => + GND_1_net, OBDIV0 => VCC, OBDIV1 => VCC, STATASEL => + GND_1_net, DLYA0 => GND_1_net, DLYA1 => GND_1_net, + OADIV0 => GND_1_net, OADIV1 => GND_1_net, OAMUX0 => + GND_1_net, OAMUX1 => GND_1_net, OBMUX0 => GND_1_net, + OBMUX1 => GND_1_net, OBMUX2 => VCC, FBDLY0 => GND_1_net, + FBDLY1 => GND_1_net, FBDLY2 => GND_1_net, FBDLY3 => + GND_1_net, XDLYSEL => GND_1_net); +end DEF_ARCH;

pll.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: eppwbn_test.vhd =================================================================== --- eppwbn_test.vhd (revision 16) +++ eppwbn_test.vhd (revision 19) @@ -1,102 +1,123 @@ ---|----------------------------------------------------------------------------- ---| UNSL - Modular Oscilloscope ---| ---| File: eppwbn_test.vhd ---| Version: 0.10 ---| Targeted device: Actel A3PE1500 ---|----------------------------------------------------------------------------- ---| Description: ---| EPP - Wishbone bridge. ---| This file is only for test purposes ---| --------------------------------------------------------------------------------- ---| File history: ---| 0.10 | jan-2008 | First release --------------------------------------------------------------------------------- ---| Copyright ® 2008, Facundo Aguilera. ---| ---| This VHDL design file is an open design; you can redistribute it and/or ---| modify it and/or implement it after contacting the author. - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.eppwbn_pgk.all; - - - -entity eppwbn_test is - port( - -- al puerto EPP - nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284 - -- HostClk/nWrite - Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8) - nAck: out std_logic; -- PtrClk/PeriphClk/Intr - busy: out std_logic; -- PtrBusy/PeriphAck/nWait - PError: out std_logic; -- AckData/nAckReverse - Sel: out std_logic; -- XFlag (Select) - nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb - PeriphLogicH: out std_logic; -- (Periph Logic High) - nInit: in std_logic; -- nReverseRequest - nFault: out std_logic; -- nDataAvail/nPeriphRequest - nSelectIn: in std_logic; -- 1284 Active/nAStrb - - -- a los switches - rst: in std_logic; - - -- al clock - clk: in std_logic - - ); -end eppwbn_test; - -architecture eppwbn_test_arch0 of eppwbn_test is - - signal DAT_I_master: std_logic_vector (7 downto 0); - signal DAT_O_master: std_logic_vector (7 downto 0); - signal ADR_O_master: std_logic_vector (7 downto 0); - signal CYC_O_master: std_logic; - signal STB_O_master: std_logic; - signal ACK_I_master: std_logic; - signal WE_O_master: std_logic; - -begin - - SL_MEM1: eppwbn_test_wb_side port map( - RST_I => rst, - CLK_I => clk, - DAT_I => DAT_O_master, - DAT_O => DAT_I_master, - ADR_I => ADR_O_master, - CYC_I => CYC_O_master, - STB_I => STB_O_master, - ACK_O => ACK_I_master, - WE_I => WE_O_master - ); - - MA_EPP: eppwbn port map( - -- Externo - nStrobe => nStrobe, - Data => Data, - nAck => nAck, - busy => busy, - PError => PError, - Sel => Sel, - nAutoFd => nAutoFd, - PeriphLogicH => PeriphLogicH, - nInit => nInit, - nFault => nFault, - nSelectIn => nSelectIn, - -- Interno - RST_I => rst, - CLK_I => clk, - DAT_I => DAT_I_master, - DAT_O => DAT_O_master, - ADR_O => ADR_O_master, - CYC_O => CYC_O_master, - STB_O => STB_O_master, - ACK_I => ACK_I_master, - WE_O => WE_O_master - ); - +--|----------------------------------------------------------------------------- +--| UNSL - Modular Oscilloscope +--| +--| File: eppwbn_test.vhd +--| Version: 0.10 +--| Targeted device: Actel A3PE1500 +--|----------------------------------------------------------------------------- +--| Description: +--| EPP - Wishbone bridge. +--| This file is only for test purposes +--| +-------------------------------------------------------------------------------- +--| File history: +--| 0.10 | jan-2008 | First release +-------------------------------------------------------------------------------- +--| Copyright ® 2008, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.eppwbn_pgk.all; + + + +entity eppwbn_test is + port( + -- al puerto EPP + nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284 + -- HostClk/nWrite + Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select) + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + + -- a los switches + rst: in std_logic; + + -- al clock + clk: in std_logic + + -- a los leds + --epp_mode: out std_logic_vector(1 downto 0); + --nAck_monitor: out std_logic; + --busy_monitor: out std_logic; + --PError_monitor: out std_logic; + --Sel_monitor: out std_logic; + --nFault_monitor: out std_logic; + -- nAutoFd_monitor: out std_logic; + -- nInit_monitor: out std_logic; + -- nSelectIn_monitor: out std_logic; + -- nStrobe_monitor: out std_logic + --PeriphLogicH_monitor: out std_logic; + ); +end eppwbn_test; + +architecture eppwbn_test_arch0 of eppwbn_test is + + signal DAT_I_master: std_logic_vector (7 downto 0); + signal DAT_O_master: std_logic_vector (7 downto 0); + signal ADR_O_master: std_logic_vector (7 downto 0); + signal CYC_O_master: std_logic; + signal STB_O_master: std_logic; + signal ACK_I_master: std_logic; + signal WE_O_master: std_logic; + signal clk_pll: std_logic; + +begin + + SL_MEM1: eppwbn_test_wb_side + port map( + RST_I => rst, + CLK_I => clk_pll, + DAT_I => DAT_O_master, + DAT_O => DAT_I_master, + ADR_I => ADR_O_master, + CYC_I => CYC_O_master, + STB_I => STB_O_master, + ACK_O => ACK_I_master, + WE_I => WE_O_master + ); + + + + MA_EPP: eppwbn port map( + -- Externo + nStrobe => nStrobe, + Data => Data, + nAck => nAck, + busy => busy, + PError => PError, + Sel => Sel, + nAutoFd => nAutoFd, + PeriphLogicH => PeriphLogicH, + nInit => nInit, + nFault => nFault, + nSelectIn => nSelectIn, + -- Interno + RST_I => rst, + CLK_I => clk_pll, + DAT_I => DAT_I_master, + DAT_O => DAT_O_master, + ADR_O => ADR_O_master, + CYC_O => CYC_O_master, + STB_O => STB_O_master, + ACK_I => ACK_I_master, + WE_O => WE_O_master + ); + + PLL_0: pll port map( + GLB => clk_pll, + CLK => clk + ); + end architecture eppwbn_test_arch0; \ No newline at end of file Index: eppwbn.vhd =================================================================== --- eppwbn.vhd (revision 16) +++ eppwbn.vhd (revision 19) @@ -1,23 +1,29 @@ ---|----------------------------------------------------------------------------- ---| UNSL - Modular Oscilloscope +---------------------------------------------------------------------------------------------------- +--| Modular Oscilloscope +--| UNSL - Argentine --| ---| File: eppwbn_wbn_side.vhd ---| Version: 0.01 ---| Targeted device: Actel A3PE1500 ---|----------------------------------------------------------------------------- +--| File: eppwbn.vhd +--| Version: 0.1 +--| Tested in: Actel APA300 +--|------------------------------------------------------------------------------------------------- --| Description: --| EPP - Wishbone bridge. ---| Instantiate all the other modules. The TOP file. --------------------------------------------------------------------------------- +--| The top module for 8 bit wisbone data bus. +--|------------------------------------------------------------------------------------------------- --| File history: --| 0.01 | dic-2008 | First release --------------------------------------------------------------------------------- +--| 0.10 | feb-2009 | Working +---------------------------------------------------------------------------------------------------- --| Copyright ® 2008, Facundo Aguilera. --| --| This VHDL design file is an open design; you can redistribute it and/or --| modify it and/or implement it after contacting the author. +--| Wishbone Rev. B.3 compatible +---------------------------------------------------------------------------------------------------- + + -- Bloque completo library IEEE; @@ -39,6 +45,7 @@ nInit: in std_logic; -- nReverseRequest nFault: out std_logic; -- nDataAvail/nPeriphRequest nSelectIn: in std_logic; -- 1284 Active/nAStrb + -- Interno RST_I: in std_logic; @@ -49,7 +56,7 @@ CYC_O: out std_logic; STB_O: out std_logic; ACK_I: in std_logic ; - WE_O: out std_logic + WE_O: out std_logic ); end eppwbn; @@ -79,7 +86,6 @@ begin - -- Conexión del módulo de control U1: eppwbn_ctrl port map (

/eppwbn_16bit_test_wb_side.vhd

eppwbn_16bit_test_wb_side.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: memory_original.vhd =================================================================== --- memory_original.vhd (revision 16) +++ memory_original.vhd (revision 19) @@ -1,391 +1,391 @@ -------------------------------------------------------------------------------- --- Title : Single port RAM --- Project : Memory Cores -------------------------------------------------------------------------------- --- File : spmem.vhd --- Author : Jamil Khatib (khatib@ieee.org) --- Organization: OpenIPCore Project --- Created : 1999/5/14 --- Last update : 2000/12/19 --- Platform : --- Simulators : Modelsim 5.3XE/Windows98 --- Synthesizers: Leonardo/WindowsNT --- Target : --- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned -------------------------------------------------------------------------------- --- Description: Single Port memory -------------------------------------------------------------------------------- --- Copyright (c) 2000 Jamil Khatib --- --- This VHDL design file is an open design; you can redistribute it and/or --- modify it and/or implement it after contacting the author --- You can check the draft license at --- http://www.opencores.org/OIPC/license.shtml - -------------------------------------------------------------------------------- --- Revisions : --- Revision Number : 1 --- Version : 0.1 --- Date : 12 May 1999 --- Modifier : Jamil Khatib (khatib@ieee.org) --- Desccription : Created --- Known bugs : --- To Optimze : -------------------------------------------------------------------------------- --- Revisions : --- Revision Number : 2 --- Version : 0.2 --- Date : 19 Dec 2000 --- Modifier : Jamil Khatib (khatib@ieee.org) --- Desccription : General review --- Two versions are now available with reset and without --- Default output can can be defined --- Known bugs : --- To Optimze : -------------------------------------------------------------------------------- --- Revisions : --- Revision Number : 3 --- Version : 0.3 --- Date : 5 Jan 2001 --- Modifier : Jamil Khatib (khatib@ieee.org) --- Desccription : Registered Read Address feature is added to make use of --- Altera's FPGAs memory bits --- This feature was added from Richard Herveille's --- contribution and his memory core --- Known bugs : --- To Optimze : -------------------------------------------------------------------------------- - - - -library ieee; - -use ieee.std_logic_1164.all; - -use ieee.std_logic_unsigned.all; - -------------------------------------------------------------------------------- --- Single port Memory core with reset --- To make use of on FPGA memory bits do not use the RESET option --- For Altera's FPGA you have to use also OPTION := 1 - -entity Spmem_ent is - - generic ( USE_RESET : boolean := false; -- use system reset - - USE_CS : boolean := false; -- use chip select signal - - DEFAULT_OUT : std_logic := '1'; -- Default output - OPTION : integer := 1; -- 1: Registered read Address(suitable - -- for Altera's FPGAs - -- 0: non registered read address - ADD_WIDTH : integer := 3; - WIDTH : integer := 8); - - port ( - cs : std_logic; -- chip select - clk : in std_logic; -- write clock - reset : in std_logic; -- System Reset - add : in std_logic_vector(add_width -1 downto 0); -- Address - Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data - Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data - WR : in std_logic); -- Read Write Enable -end Spmem_ent; - - - -architecture spmem_beh of Spmem_ent is - - type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0); - -- Memory Type - signal data : data_array(0 to (2** add_width-1) ); -- Local data - - -- FLEX/APEX devices require address to be registered with inclock for read operations - -- This signal is used only when OPTION = 1 - signal regA : std_logic_vector( (add_width -1) downto 0); - - procedure init_mem(signal memory_cell : inout data_array ) is - - begin - - for i in 0 to (2** add_width-1) loop - memory_cell(i) <= (others => '0'); - end loop; - - end init_mem; - -begin -- spmem_beh -------------------------------------------------------------------------------- --- Non Registered Read Address -------------------------------------------------------------------------------- - NON_REG : if OPTION = 0 generate -------------------------------------------------------------------------------- --- Clocked Process with Reset -------------------------------------------------------------------------------- - Reset_ENABLED : if USE_RESET = true generate - -------------------------------------------------------------------------------- - CS_ENABLED : if USE_CS = true generate - - process (clk, reset) - - begin -- PROCESS - -- activities triggered by asynchronous reset (active low) - - if reset = '0' then - data_out <= (others => DEFAULT_OUT); - init_mem ( data); - - -- activities triggered by rising edge of clock - elsif clk'event and clk = '1' then - if CS = '1' then - if WR = '0' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(add)); - end if; - else - data_out <= (others => DEFAULT_OUT); - end if; - - end if; - - end process; - end generate CS_ENABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - CS_DISABLED : if USE_CS = false generate - - process (clk, reset) - - - begin -- PROCESS - -- activities triggered by asynchronous reset (active low) - - if reset = '0' then - data_out <= (others => DEFAULT_OUT); - init_mem ( data); - - -- activities triggered by rising edge of clock - elsif clk'event and clk = '1' then - if WR = '0' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(add)); - end if; - - end if; - - end process; - end generate CS_DISABLED; - -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - end generate Reset_ENABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --- Clocked Process without Reset -------------------------------------------------------------------------------- - Reset_DISABLED : if USE_RESET = false generate - -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - CS_ENABLED : if USE_CS = true generate - - process (clk) - begin -- PROCESS - - -- activities triggered by rising edge of clock - if clk'event and clk = '1' then - if cs = '1' then - if WR = '0' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(add)); - end if; - else - data_out <= (others => DEFAULT_OUT); - end if; - - - end if; - - end process; - end generate CS_ENABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - CS_DISABLED : if USE_CS = false generate - - process (clk) - begin -- PROCESS - - -- activities triggered by rising edge of clock - if clk'event and clk = '1' then - if WR = '0' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(add)); - end if; - - end if; - - end process; - end generate CS_DISABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - end generate Reset_DISABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - end generate NON_REG; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -REG: if OPTION = 1 generate -------------------------------------------------------------------------------- --- Clocked Process with Reset -------------------------------------------------------------------------------- - Reset_ENABLED : if USE_RESET = true generate - -------------------------------------------------------------------------------- - CS_ENABLED : if USE_CS = true generate - - process (clk, reset) - - begin -- PROCESS - -- activities triggered by asynchronous reset (active low) - - if reset = '0' then - data_out <= (others => DEFAULT_OUT); - init_mem ( data); - - -- activities triggered by rising edge of clock - elsif clk'event and clk = '1' then - - regA <= add; - - if CS = '1' then - if WR = '0' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(regA)); - end if; - else - data_out <= (others => DEFAULT_OUT); - end if; - - end if; - - end process; - end generate CS_ENABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - CS_DISABLED : if USE_CS = false generate - - process (clk, reset) - - - begin -- PROCESS - -- activities triggered by asynchronous reset (active low) - - if reset = '0' then - data_out <= (others => DEFAULT_OUT); - init_mem ( data); - - -- activities triggered by rising edge of clock - elsif clk'event and clk = '1' then - regA <= add; - - if WR = '0' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(regA)); - end if; - - end if; - - end process; - end generate CS_DISABLED; - -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - end generate Reset_ENABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --- Clocked Process without Reset -------------------------------------------------------------------------------- - Reset_DISABLED : if USE_RESET = false generate - -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - CS_ENABLED : if USE_CS = true generate - - process (clk) - begin -- PROCESS - - -- activities triggered by rising edge of clock - if clk'event and clk = '1' then - - regA <= add; - - if cs = '1' then - if WR = '0' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(regA)); - end if; - else - data_out <= (others => DEFAULT_OUT); - end if; - - - end if; - - end process; - end generate CS_ENABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - CS_DISABLED : if USE_CS = false generate - - process (clk) - begin -- PROCESS - - -- activities triggered by rising edge of clock - if clk'event and clk = '1' then - - regA <= add; - - if WR = '0' then - data(conv_integer(add)) <= data_in; - data_out <= (others => DEFAULT_OUT); - else - data_out <= data(conv_integer(regA)); - end if; - - end if; - - end process; - end generate CS_DISABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - end generate Reset_DISABLED; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - -end generate REG; - -end spmem_beh; -------------------------------------------------------------------------------- - +------------------------------------------------------------------------------- +-- Title : Single port RAM +-- Project : Memory Cores +------------------------------------------------------------------------------- +-- File : spmem.vhd +-- Author : Jamil Khatib (khatib@ieee.org) +-- Organization: OpenIPCore Project +-- Created : 1999/5/14 +-- Last update : 2000/12/19 +-- Platform : +-- Simulators : Modelsim 5.3XE/Windows98 +-- Synthesizers: Leonardo/WindowsNT +-- Target : +-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned +------------------------------------------------------------------------------- +-- Description: Single Port memory +------------------------------------------------------------------------------- +-- Copyright (c) 2000 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml + +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 12 May 1999 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : Created +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 2 +-- Version : 0.2 +-- Date : 19 Dec 2000 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : General review +-- Two versions are now available with reset and without +-- Default output can can be defined +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 3 +-- Version : 0.3 +-- Date : 5 Jan 2001 +-- Modifier : Jamil Khatib (khatib@ieee.org) +-- Desccription : Registered Read Address feature is added to make use of +-- Altera's FPGAs memory bits +-- This feature was added from Richard Herveille's +-- contribution and his memory core +-- Known bugs : +-- To Optimze : +------------------------------------------------------------------------------- + + + +library ieee; + +use ieee.std_logic_1164.all; + +use ieee.std_logic_unsigned.all; + +------------------------------------------------------------------------------- +-- Single port Memory core with reset +-- To make use of on FPGA memory bits do not use the RESET option +-- For Altera's FPGA you have to use also OPTION := 1 + +entity Spmem_ent is + + generic ( USE_RESET : boolean := false; -- use system reset + + USE_CS : boolean := false; -- use chip select signal + + DEFAULT_OUT : std_logic := '1'; -- Default output + OPTION : integer := 1; -- 1: Registered read Address(suitable + -- for Altera's FPGAs + -- 0: non registered read address + ADD_WIDTH : integer := 3; + WIDTH : integer := 8); + + port ( + cs : std_logic; -- chip select + clk : in std_logic; -- write clock + reset : in std_logic; -- System Reset + add : in std_logic_vector(add_width -1 downto 0); -- Address + Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data + Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data + WR : in std_logic); -- Read Write Enable +end Spmem_ent; + + + +architecture spmem_beh of Spmem_ent is + + type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0); + -- Memory Type + signal data : data_array(0 to (2** add_width-1) ); -- Local data + + -- FLEX/APEX devices require address to be registered with inclock for read operations + -- This signal is used only when OPTION = 1 + signal regA : std_logic_vector( (add_width -1) downto 0); + + procedure init_mem(signal memory_cell : inout data_array ) is + + begin + + for i in 0 to (2** add_width-1) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + +begin -- spmem_beh +------------------------------------------------------------------------------- +-- Non Registered Read Address +------------------------------------------------------------------------------- + NON_REG : if OPTION = 0 generate +------------------------------------------------------------------------------- +-- Clocked Process with Reset +------------------------------------------------------------------------------- + Reset_ENABLED : if USE_RESET = true generate + +------------------------------------------------------------------------------- + CS_ENABLED : if USE_CS = true generate + + process (clk, reset) + + begin -- PROCESS + -- activities triggered by asynchronous reset (active low) + + if reset = '0' then + data_out <= (others => DEFAULT_OUT); + init_mem ( data); + + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + if CS = '1' then + if WR = '0' then + data(conv_integer(add)) <= data_in; + data_out <= (others => DEFAULT_OUT); + else + data_out <= data(conv_integer(add)); + end if; + else + data_out <= (others => DEFAULT_OUT); + end if; + + end if; + + end process; + end generate CS_ENABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + CS_DISABLED : if USE_CS = false generate + + process (clk, reset) + + + begin -- PROCESS + -- activities triggered by asynchronous reset (active low) + + if reset = '0' then + data_out <= (others => DEFAULT_OUT); + init_mem ( data); + + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + if WR = '0' then + data(conv_integer(add)) <= data_in; + data_out <= (others => DEFAULT_OUT); + else + data_out <= data(conv_integer(add)); + end if; + + end if; + + end process; + end generate CS_DISABLED; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + end generate Reset_ENABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Clocked Process without Reset +------------------------------------------------------------------------------- + Reset_DISABLED : if USE_RESET = false generate + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + CS_ENABLED : if USE_CS = true generate + + process (clk) + begin -- PROCESS + + -- activities triggered by rising edge of clock + if clk'event and clk = '1' then + if cs = '1' then + if WR = '0' then + data(conv_integer(add)) <= data_in; + data_out <= (others => DEFAULT_OUT); + else + data_out <= data(conv_integer(add)); + end if; + else + data_out <= (others => DEFAULT_OUT); + end if; + + + end if; + + end process; + end generate CS_ENABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + CS_DISABLED : if USE_CS = false generate + + process (clk) + begin -- PROCESS + + -- activities triggered by rising edge of clock + if clk'event and clk = '1' then + if WR = '0' then + data(conv_integer(add)) <= data_in; + data_out <= (others => DEFAULT_OUT); + else + data_out <= data(conv_integer(add)); + end if; + + end if; + + end process; + end generate CS_DISABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + end generate Reset_DISABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + end generate NON_REG; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +REG: if OPTION = 1 generate +------------------------------------------------------------------------------- +-- Clocked Process with Reset +------------------------------------------------------------------------------- + Reset_ENABLED : if USE_RESET = true generate + +------------------------------------------------------------------------------- + CS_ENABLED : if USE_CS = true generate + + process (clk, reset) + + begin -- PROCESS + -- activities triggered by asynchronous reset (active low) + + if reset = '0' then + data_out <= (others => DEFAULT_OUT); + init_mem ( data); + + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + + regA <= add; + + if CS = '1' then + if WR = '0' then + data(conv_integer(add)) <= data_in; + data_out <= (others => DEFAULT_OUT); + else + data_out <= data(conv_integer(regA)); + end if; + else + data_out <= (others => DEFAULT_OUT); + end if; + + end if; + + end process; + end generate CS_ENABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + CS_DISABLED : if USE_CS = false generate + + process (clk, reset) + + + begin -- PROCESS + -- activities triggered by asynchronous reset (active low) + + if reset = '0' then + data_out <= (others => DEFAULT_OUT); + init_mem ( data); + + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + regA <= add; + + if WR = '0' then + data(conv_integer(add)) <= data_in; + data_out <= (others => DEFAULT_OUT); + else + data_out <= data(conv_integer(regA)); + end if; + + end if; + + end process; + end generate CS_DISABLED; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + end generate Reset_ENABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Clocked Process without Reset +------------------------------------------------------------------------------- + Reset_DISABLED : if USE_RESET = false generate + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + CS_ENABLED : if USE_CS = true generate + + process (clk) + begin -- PROCESS + + -- activities triggered by rising edge of clock + if clk'event and clk = '1' then + + regA <= add; + + if cs = '1' then + if WR = '0' then + data(conv_integer(add)) <= data_in; + data_out <= (others => DEFAULT_OUT); + else + data_out <= data(conv_integer(regA)); + end if; + else + data_out <= (others => DEFAULT_OUT); + end if; + + + end if; + + end process; + end generate CS_ENABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + CS_DISABLED : if USE_CS = false generate + + process (clk) + begin -- PROCESS + + -- activities triggered by rising edge of clock + if clk'event and clk = '1' then + + regA <= add; + + if WR = '0' then + data(conv_integer(add)) <= data_in; + data_out <= (others => DEFAULT_OUT); + else + data_out <= data(conv_integer(regA)); + end if; + + end if; + + end process; + end generate CS_DISABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + end generate Reset_DISABLED; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +end generate REG; + +end spmem_beh; +------------------------------------------------------------------------------- + 1 \ No newline at end of file Index: eppwbn_pkg.vhd =================================================================== --- eppwbn_pkg.vhd (revision 16) +++ eppwbn_pkg.vhd (revision 19) @@ -1,164 +1,281 @@ ---|----------------------------------------------------------------------------- ---| UNSL - Modular Oscilloscope ---| ---| File: eppwbn_wbn_side.vhd ---| Version: 0.10 ---| Targeted device: Actel A3PE1500 ---|----------------------------------------------------------------------------- ---| Description: ---| EPP - Wishbone bridge. ---| Package for instantiate all EPP-WBN modules. --------------------------------------------------------------------------------- ---| File history: ---| 0.01 | dic-2008 | First release ---| 0.10 | jan-2008 | Added testing memory --------------------------------------------------------------------------------- ---| Copyright ® 2008, Facundo Aguilera. ---| ---| This VHDL design file is an open design; you can redistribute it and/or ---| modify it and/or implement it after contacting the author. - - --- Bloque completo -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -package eppwbn_pgk is - ------------------------------------------------------------------------------ - -- Componentes - - -- Bridge control - component eppwbn_ctrl is - port( - nStrobe: in std_logic; - - Data: in std_logic_vector (7 downto 0); - nAck: out std_logic; - PError: out std_logic; - Sel: out std_logic; - nAutoFd: in std_logic; - PeriphLogicH: out std_logic; - nInit: in std_logic; - nFault: out std_logic; - nSelectIn: in std_logic; - - RST_I: in std_logic; - CLK_I: in std_logic; - - rst_pp: out std_logic; - epp_mode: out std_logic_vector (1 downto 0) - ); - end component eppwbn_ctrl; - - -- Comunication with EPP interface - component eppwbn_epp_side is - port( - epp_mode: in std_logic_vector (1 downto 0); - - ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic; - - ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic; - - wb_Busy: in std_logic; - wb_nAutoFd: out std_logic; - wb_nSelectIn: out std_logic; - wb_nStrobe: out std_logic; - - nAck, PError, Sel, nFault: out std_logic; - - Busy: out std_logic; - nAutoFd: in std_logic; - nSelectIn: in std_logic; - nStrobe: in std_logic - ); - end component eppwbn_epp_side; - - -- Comunication with WB interface - component eppwbn_wbn_side is - port( - inStrobe: in std_logic; - iData: inout std_logic_vector (7 downto 0); - iBusy: out std_logic; - inAutoFd: in std_logic; - inSelectIn: in std_logic; - - RST_I, CLK_I: in std_logic; - DAT_I: in std_logic_vector (7 downto 0); - DAT_O: out std_logic_vector (7 downto 0); - ADR_O: out std_logic_vector (7 downto 0); - CYC_O, STB_O: out std_logic; - ACK_I: in std_logic ; - WE_O: out std_logic; - - rst_pp: in std_logic - ); - end component eppwbn_wbn_side; - - -- Testing memory - component mem_8bit_reset is - generic ( --USE_RESET : boolean := false; -- use system reset - - --USE_CS : boolean := false; -- use chip select signal - - DEFAULT_OUT : std_logic := '0'; -- Default output - --OPTION : integer := 1; -- 1: Registered read Address(suitable - -- for Altera's FPGAs - -- 0: non registered read address - ADD_WIDTH : integer := 8; - WIDTH : integer := 8); - - port ( - cs : in std_logic; -- chip select - clk : in std_logic; -- write clock - reset : in std_logic; -- System Reset - add : in std_logic_vector(add_width -1 downto 0); -- Address - Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data - Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data - WR : in std_logic); -- Read Write Enable - end component mem_8bit_reset; - - component eppwbn is - port( - -- Externo - nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284 - -- HostClk/nWrite - Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8) - nAck: out std_logic; -- PtrClk/PeriphClk/Intr - busy: out std_logic; -- PtrBusy/PeriphAck/nWait - PError: out std_logic; -- AckData/nAckReverse - Sel: out std_logic; -- XFlag (Select) - nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb - PeriphLogicH: out std_logic; -- (Periph Logic High) - nInit: in std_logic; -- nReverseRequest - nFault: out std_logic; -- nDataAvail/nPeriphRequest - nSelectIn: in std_logic; -- 1284 Active/nAStrb - - -- Interno - RST_I: in std_logic; - CLK_I: in std_logic; - DAT_I: in std_logic_vector (7 downto 0); - DAT_O: out std_logic_vector (7 downto 0); - ADR_O: out std_logic_vector (7 downto 0); - CYC_O: out std_logic; - STB_O: out std_logic; - ACK_I: in std_logic ; - WE_O: out std_logic - ); - end component eppwbn; - - component eppwbn_test_wb_side is - port( - RST_I: in std_logic; - CLK_I: in std_logic; - DAT_I: in std_logic_vector (7 downto 0); - DAT_O: out std_logic_vector (7 downto 0); - ADR_I: in std_logic_vector (7 downto 0); - CYC_I: in std_logic; - STB_I: in std_logic; - ACK_O: out std_logic ; - WE_I: in std_logic - ); - end component eppwbn_test_wb_side; - -end package eppwbn_pgk; - +---------------------------------------------------------------------------------------------------- +--| UNSL - Modular Oscilloscope +--| +--| File: eppwbn_wbn_side.vhd +--| Version: 0.2 +--| Tested in: Actel APA300 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| EPP - Wishbone bridge. +--| Package for instantiate all EPP-WBN modules. +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | dic-2008 | First release +--| 0.10 | jan-2009 | Added testing memory +--| 0.20 | mar-2009 | Added extension module +--| 0.30 | apr-2009 | Added pll +---------------------------------------------------------------------------------------------------- +--| Copyright ® 2008, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + +-- El módulo PLL solo funcionará con FPGAs de Actel + + +-- Bloque completo +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +package eppwbn_pgk is + -------------------------------------------------------------------------------------------------- + -- Componentes + + -- Bridge control + component eppwbn_ctrl is + port( + nStrobe: in std_logic; + + Data: in std_logic_vector (7 downto 0); + nAck: out std_logic; + PError: out std_logic; + Sel: out std_logic; + nAutoFd: in std_logic; + PeriphLogicH: out std_logic; + nInit: in std_logic; + nFault: out std_logic; + nSelectIn: in std_logic; + + RST_I: in std_logic; + CLK_I: in std_logic; + + rst_pp: out std_logic; + epp_mode: out std_logic_vector (1 downto 0) + ); + end component eppwbn_ctrl; + + -- Comunication with EPP interface + component eppwbn_epp_side is + port( + epp_mode: in std_logic_vector (1 downto 0); + + ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic; + + ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic; + + wb_Busy: in std_logic; + wb_nAutoFd: out std_logic; + wb_nSelectIn: out std_logic; + wb_nStrobe: out std_logic; + + nAck, PError, Sel, nFault: out std_logic; + + Busy: out std_logic; + nAutoFd: in std_logic; + nSelectIn: in std_logic; + nStrobe: in std_logic + ); + end component eppwbn_epp_side; + + -- Comunication with WB interface + component eppwbn_wbn_side is + port( + inStrobe: in std_logic; + iData: inout std_logic_vector (7 downto 0); + iBusy: out std_logic; + inAutoFd: in std_logic; + inSelectIn: in std_logic; + + RST_I, CLK_I: in std_logic; + DAT_I: in std_logic_vector (7 downto 0); + DAT_O: out std_logic_vector (7 downto 0); + ADR_O: out std_logic_vector (7 downto 0); + CYC_O, STB_O: out std_logic; + ACK_I: in std_logic ; + WE_O: out std_logic; + + rst_pp: in std_logic + ); + end component eppwbn_wbn_side; + + -- Testing memory + component test_memory is + generic ( --USE_RESET : boolean := false; -- use system reset + + --USE_CS : boolean := false; -- use chip select signal + + DEFAULT_OUT : std_logic; -- Default output + --OPTION : integer := 1; -- 1: Registered read Address(suitable + -- for Altera's FPGAs + -- 0: non registered read address + ADD_WIDTH : integer; + WIDTH : integer); + + port ( + cs: in std_logic; -- chip select + clk: in std_logic; -- write clock + reset: in std_logic; -- System Reset + add: in std_logic_vector(add_width -1 downto 0); -- Address + Data_In: in std_logic_vector(WIDTH -1 downto 0); -- input data + Data_Out: out std_logic_vector(WIDTH -1 downto 0); -- Output Data + WR: in std_logic); -- Read Write Enable + end component test_memory; + + -- Epp-wishbone bridge + component eppwbn is + port( + -- Externo + nStrobe: in std_logic; -- HostClk/nWrite + Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select) + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + + -- Interno + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (7 downto 0); + DAT_O: out std_logic_vector (7 downto 0); + ADR_O: out std_logic_vector (7 downto 0); + CYC_O: out std_logic; + STB_O: out std_logic; + ACK_I: in std_logic ; + WE_O: out std_logic + ); + end component eppwbn; + + -- Testing component + component eppwbn_test_wb_side is + port( + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (7 downto 0); + DAT_O: out std_logic_vector (7 downto 0); + ADR_I: in std_logic_vector (7 downto 0); + CYC_I: in std_logic; + STB_I: in std_logic; + ACK_O: out std_logic ; + WE_I: in std_logic + ); + end component eppwbn_test_wb_side; + + + -- Width extension + component eppwbn_width_extension is + generic ( + TIME_OUT_VALUE: integer; + TIME_OUT_WIDTH: integer + ); + port( + -- Slave signals + DAT_I_sl: in std_logic_vector (7 downto 0); + DAT_O_sl: out std_logic_vector (7 downto 0); + ADR_I_sl: in std_logic_vector (7 downto 0); + CYC_I_sl: in std_logic; + STB_I_sl: in std_logic; + ACK_O_sl: out std_logic ; + WE_I_sl: in std_logic; + + + -- Master signals + DAT_I_ma: in std_logic_vector (15 downto 0); + DAT_O_ma: out std_logic_vector (15 downto 0); + ADR_O_ma: out std_logic_vector (7 downto 0); + CYC_O_ma: out std_logic; + STB_O_ma: out std_logic; + ACK_I_ma: in std_logic ; + WE_O_ma: out std_logic; + + -- Common signals + RST_I: in std_logic; + CLK_I: in std_logic + ); + end component eppwbn_width_extension; + + component eppwbn_16bit is + port( + -- Externo + nStrobe: in std_logic; -- HostClk/nWrite + Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select) + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + + + -- Interno + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (15 downto 0); + DAT_O: out std_logic_vector (15 downto 0); + ADR_O: out std_logic_vector (7 downto 0); + CYC_O: out std_logic; + STB_O: out std_logic; + ACK_I: in std_logic ; + WE_O: out std_logic + ); + end component eppwbn_16bit; + + component eppwbn_16bit_test is + port( + -- al puerto EPP + nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284 + -- HostClk/nWrite + Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select) + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + + -- a los switches + rst: in std_logic; + + -- al clock + clk: in std_logic + + ); + end component eppwbn_16bit_test; + + component eppwbn_16bit_test_wb_side is + generic ( + ADD_WIDTH : integer ; + WIDTH : integer + ); + port( + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (WIDTH-1 downto 0); + DAT_O: out std_logic_vector (WIDTH-1 downto 0); + ADR_I: in std_logic_vector (7 downto 0); + CYC_I: in std_logic; + STB_I: in std_logic; + ACK_O: out std_logic ; + WE_I: in std_logic + ); + end component eppwbn_16bit_test_wb_side; + + -- Clock (Actel specific) + component pll is + port(GLB, LOCK : out std_logic; CLK : in std_logic) ; + end component pll; + + +end package eppwbn_pgk; + \ No newline at end of file