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Rev 19 → Rev 22

/eppwbn_16bit_test.vhd
1,115 → 1,203
--|-----------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_test.vhd
--| Version: 0.10
--| Targeted device: Actel A3PE1500
--|-----------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| This file is only for test purposes
--|
--------------------------------------------------------------------------------
--| File history:
--| 0.10 | jan-2008 | First release
--------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.eppwbn_pgk.all;
 
 
 
entity eppwbn_16bit_test is
port(
-- al puerto EPP
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
-- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- a los switches
rst: in std_logic;
-- al clock
clk: in std_logic
);
end eppwbn_16bit_test;
 
architecture eppwbn_test_arch0 of eppwbn_16bit_test is
signal DAT_I_master: std_logic_vector (15 downto 0);
signal DAT_O_master: std_logic_vector (15 downto 0);
signal ADR_O_master: std_logic_vector (7 downto 0);
signal CYC_O_master: std_logic;
signal STB_O_master: std_logic;
signal ACK_I_master: std_logic;
signal WE_O_master: std_logic;
signal clk_pll: std_logic;
begin
SL_MEM1: eppwbn_16bit_test_wb_side
generic map(
ADD_WIDTH => 8 ,
WIDTH => 16
)
port map(
RST_I => rst,
CLK_I => clk_pll,
DAT_I => DAT_O_master,
DAT_O => DAT_I_master,
ADR_I => ADR_O_master,
CYC_I => CYC_O_master,
STB_I => STB_O_master,
ACK_O => ACK_I_master,
WE_I => WE_O_master
);
 
MA_EPP: eppwbn_16bit port map(
-- Externo
nStrobe => nStrobe,
Data => Data,
nAck => nAck,
busy => busy,
PError => PError,
Sel => Sel,
nAutoFd => nAutoFd,
PeriphLogicH => PeriphLogicH,
nInit => nInit,
nFault => nFault,
nSelectIn => nSelectIn,
-- Interno
RST_I => rst,
CLK_I => clk_pll,
DAT_I => DAT_I_master,
DAT_O => DAT_O_master,
ADR_O => ADR_O_master,
CYC_O => CYC_O_master,
STB_O => STB_O_master,
ACK_I => ACK_I_master,
WE_O => WE_O_master
);
PLL_0: pll port map(
GLB => clk_pll,
CLK => clk
);
-------------------------------------------------------------------------------------------------100
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: eppwbn_test.vhd
--| Version: 0.60
--| Tested in: Actel APA300, Actel A3PE1500
--|-------------------------------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| This file is only for test purposes
--|
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.10 | jan-2008 | First release
--| 0.50 | jun-2009 | Sample testing signals
--| 0.60 | jun-2009 | Sample testing instance for a dual port memory
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.eppwbn_pkg.all;
 
 
 
entity eppwbn_16bit_test is
generic(
 
 
 
);
port(
-- al puerto EPP
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
-- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- a los switches
 
-- al clock
clk: in std_logic;
-- monitores
display_cat: out std_logic;
data_monitor: out std_logic_vector (3 downto 0);
select_nibble: in std_logic; -- Select data nibble. High: high nibble, low: ...
epp_mode_monitor: out std_logic_vector (1 downto 0);
nSelectIn_monitor:out std_logic;
nAutoFd_monitor: out std_logic;
nStrobe_monitor: out std_logic
);
end eppwbn_16bit_test;
 
architecture eppwbn_test_arch0 of eppwbn_16bit_test is
signal DAT_I_master: std_logic_vector (15 downto 0);
signal DAT_O_master: std_logic_vector (15 downto 0);
signal ADR_O_master: std_logic_vector (7 downto 0);
signal CYC_O_master: std_logic;
signal STB_O_master: std_logic;
signal ACK_I_master: std_logic;
signal WE_O_master: std_logic;
signal clk_pll: std_logic;
signal gnd: std_logic;
signal s_not_rst: std_logic;
signal s_not_epp_mode: std_logic_vector (1 downto 0);
signal s_to_mem_ADR_I_a: std_logic_vector(13 downto 0);
begin
gnd <= '0';
s_not_rst <= not(rst);
data_monitor <= Data(7 downto 4) when select_nibble = '1' else
Data(3 downto 0);
display_cat <= '0';
epp_mode_monitor <= not(s_not_epp_mode);
nSelectIn_monitor <= nSelectIn;
nAutoFd_monitor <= nAutoFd;
nStrobe_monitor <= nStrobe;
 
-- SL_MEM1: eppwbn_16bit_test_wb_side
-- generic map(
-- ADD_WIDTH => ADD_WIDTH ,
-- WIDTH => 16
-- )
-- port map(
-- RST_I => s_not_rst,
-- CLK_I => clk_pll,
-- DAT_I => DAT_O_master,
-- DAT_O => DAT_I_master,
-- ADR_I => ADR_O_master(ADD_WIDTH - 1 downto 0),
-- CYC_I => CYC_O_master,
-- STB_I => STB_O_master,
-- ACK_O => ACK_I_master,
-- WE_I => WE_O_master
-- );
 
 
s_to_mem_ADR_I_a <= (13 downto 8 => '0') & ADR_O_master;
SL_MEM2: dual_port_memory_wb port map(
-- Puerto A
RST_I_a => s_not_rst,
CLK_I_a => clk_pll,
DAT_I_a => DAT_O_master,
DAT_O_a => DAT_I_master,
ADR_I_a => s_to_mem_ADR_I_a,
CYC_I_a => CYC_O_master,
STB_I_a => STB_O_master,
ACK_O_a => ACK_I_master,
WE_I_a => WE_O_master,
-- Puerto B
RST_I_b => s_not_rst,
CLK_I_b => '0',
DAT_I_b => (others => '0'),
ADR_I_b => (others => '0'),
CYC_I_b => '0',
STB_I_b => '0',
WE_I_b => '0'
);
 
MA_EPP: eppwbn_16bit port map(
-- Externo
nStrobe => nStrobe,
Data => Data,
nAck => nAck,
busy => busy,
PError => PError,
Sel => Sel,
nAutoFd => nAutoFd,
PeriphLogicH => PeriphLogicH,
nInit => nInit,
nFault => nFault,
nSelectIn => nSelectIn,
-- Interno
RST_I => s_not_rst,
CLK_I => clk_pll,
DAT_I => DAT_I_master,
DAT_O => DAT_O_master,
ADR_O => ADR_O_master,
CYC_O => CYC_O_master,
STB_O => STB_O_master,
ACK_I => ACK_I_master,
WE_O => WE_O_master,
-- MONITORES
-- TEMPORAL
epp_mode_monitor => s_not_epp_mode
);
 
PLL_0: component A3PE_pll
port map(
POWERDOWN => '0',
CLKA => clk,
LOCK => open,
--SDIN => '0',
--SCLK => '0',
--SSHIFT => '0',
--SUPDATE => '0',
--MODE => '0',
GLA => clk_pll
--SDOUT => open
);
 
end architecture eppwbn_test_arch0;
/eppwbn_16bit.vhd
27,7 → 27,7
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.eppwbn_pgk.all;
use work.eppwbn_pkg.all;
 
entity eppwbn_16bit is
port(
54,7 → 54,11
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic
WE_O: out std_logic;
-- TEMPORAL monitores
epp_mode_monitor: out std_logic_vector(1 downto 0)
);
end eppwbn_16bit;
74,6 → 78,10
U_EPPWBN8: eppwbn
port map(
-- TEMPORAL
epp_mode_monitor => epp_mode_monitor,
-- To EPP interface
nStrobe => nStrobe,
Data => Data,
/eppwbn_epp_side.vhd
15,7 → 15,7
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
--| modify it and/or implement it after contacting the author.
 
 
library IEEE;
68,7 → 68,7
 
-- Puentes
 
Busy <= wb_Busy;
 
ctr_nAutoFd <= nAutoFd;
ctr_nSelectIn <= nSelectIn;
77,7 → 77,7
 
 
multiplexing: process (epp_mode ,ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault,
nAutoFd, nSelectIn, nStrobe) begin
nAutoFd, nSelectIn, nStrobe, wb_Busy) begin
case epp_mode is
 
when "11" =>
91,6 → 91,7
wb_nAutoFd <= nAutoFd;
wb_nSelectIn <= nSelectIn;
wb_nStrobe <= nStrobe;
Busy <= wb_Busy;
when "01" =>
-- Hacia el host
103,6 → 104,7
wb_nAutoFd <= nAutoFd;
wb_nSelectIn <= nSelectIn;
wb_nStrobe <= nStrobe;
Busy <= wb_Busy;
when others =>
-- Hacia el host
115,6 → 117,7
wb_nAutoFd <= '1';
wb_nSelectIn <= '1';
wb_nStrobe <= '1';
Busy <= '0';
end case;
end process;
 
/eppwbn_ctrl.vhd
87,8 → 87,10
begin
if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then
ext_req_val <= (others => '0');
elsif (present_state = st_negotiation2 and nStrobe = '0') then
elsif (nStrobe = '0') and present_state = st_negotiation2 then
ext_req_val <= Data;
else
ext_req_val <= ext_req_val;
end if;
end process P_data_store;
188,7 → 190,7
----------------------------------------------------------------------------------------
-- estado actual
P_state_clocked: process(CLK_I, nInit, nSelectIn,RST_I) begin
P_state_clocked: process(CLK_I, nInit, nSelectIn) begin
-- if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then
-- present_state <= st_compatibility_idle;
-- elsif present_state = st_epp_mode and nInit = '0' then
198,7 → 200,7
-- end if;
if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then
if (nInit = '0' and nSelectIn = '0') then
present_state <= st_compatibility_idle;
elsif (CLK_I'event and CLK_I='1') then
present_state <= next_state;
/eppwbn_test_wb_side.vhd
13,7 → 13,7
--| File history:
--| 0.10 | dic-2008 | First release
--------------------------------------------------------------------------------
--| Copyright ® 2008, Facundo Aguilera.
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
21,7 → 21,7
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.eppwbn_pgk.all;
use work.eppwbn_pkg.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
 
 
/eppwbn_width_extension.vhd
34,7 → 34,7
use IEEE.STD_LOGIC_ARITH.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.eppwbn_pgk.all;
use work.eppwbn_pkg.all;
 
entity eppwbn_width_extension is
generic (
/eppwbn_test.vhd
21,7 → 21,7
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.eppwbn_pgk.all;
use work.eppwbn_pkg.all;
 
 
 
88,7 → 88,7
WE_I => WE_O_master
);
 
MA_EPP: eppwbn port map(
-- Externo
/eppwbn.vhd
28,10 → 28,16
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.eppwbn_pgk.all;
use work.eppwbn_pkg.all;
 
entity eppwbn is
port(
 
-- TEMPORAL
epp_mode_monitor: out std_logic_vector (1 downto 0);
 
 
 
-- Externo
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
-- HostClk/nWrite
86,6 → 92,11
begin
-- TEMPORAL
epp_mode_monitor <= s_epp_mode;
 
U1: eppwbn_ctrl
port map (
/eppwbn_16bit_test_wb_side.vhd
21,7 → 21,7
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.eppwbn_pgk.all;
use work.eppwbn_pkg.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
 
 
37,7 → 37,7
CLK_I: in std_logic;
DAT_I: in std_logic_vector (WIDTH-1 downto 0);
DAT_O: out std_logic_vector (WIDTH-1 downto 0);
ADR_I: in std_logic_vector (7 downto 0);
ADR_I: in std_logic_vector (ADD_WIDTH-1 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
ACK_O: out std_logic ;
52,7 → 52,7
MEM1: test_memory
generic map(
DEFAULT_OUT => '0',
ADD_WIDTH => 8,
ADD_WIDTH => ADD_WIDTH,
WIDTH => WIDTH
)
port map (
/eppwbn_pkg.vhd
1,281 → 1,316
----------------------------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.2
--| Tested in: Actel APA300
--|-------------------------------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| Package for instantiate all EPP-WBN modules.
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.01 | dic-2008 | First release
--| 0.10 | jan-2009 | Added testing memory
--| 0.20 | mar-2009 | Added extension module
--| 0.30 | apr-2009 | Added pll
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package eppwbn_pgk is
--------------------------------------------------------------------------------------------------
-- Componentes
-- Bridge control
component eppwbn_ctrl is
port(
nStrobe: in std_logic;
Data: in std_logic_vector (7 downto 0);
nAck: out std_logic;
PError: out std_logic;
Sel: out std_logic;
nAutoFd: in std_logic;
PeriphLogicH: out std_logic;
nInit: in std_logic;
nFault: out std_logic;
nSelectIn: in std_logic;
RST_I: in std_logic;
CLK_I: in std_logic;
 
rst_pp: out std_logic;
epp_mode: out std_logic_vector (1 downto 0)
);
end component eppwbn_ctrl;
-- Comunication with EPP interface
component eppwbn_epp_side is
port(
epp_mode: in std_logic_vector (1 downto 0);
 
ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic;
ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic;
wb_Busy: in std_logic;
wb_nAutoFd: out std_logic;
wb_nSelectIn: out std_logic;
wb_nStrobe: out std_logic;
 
nAck, PError, Sel, nFault: out std_logic;
Busy: out std_logic;
nAutoFd: in std_logic;
nSelectIn: in std_logic;
nStrobe: in std_logic
);
end component eppwbn_epp_side;
-- Comunication with WB interface
component eppwbn_wbn_side is
port(
inStrobe: in std_logic;
iData: inout std_logic_vector (7 downto 0);
iBusy: out std_logic;
inAutoFd: in std_logic;
inSelectIn: in std_logic;
RST_I, CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O, STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic;
 
rst_pp: in std_logic
);
end component eppwbn_wbn_side;
-- Testing memory
component test_memory is
generic ( --USE_RESET : boolean := false; -- use system reset
 
--USE_CS : boolean := false; -- use chip select signal
 
DEFAULT_OUT : std_logic; -- Default output
--OPTION : integer := 1; -- 1: Registered read Address(suitable
-- for Altera's FPGAs
-- 0: non registered read address
ADD_WIDTH : integer;
WIDTH : integer);
 
port (
cs: in std_logic; -- chip select
clk: in std_logic; -- write clock
reset: in std_logic; -- System Reset
add: in std_logic_vector(add_width -1 downto 0); -- Address
Data_In: in std_logic_vector(WIDTH -1 downto 0); -- input data
Data_Out: out std_logic_vector(WIDTH -1 downto 0); -- Output Data
WR: in std_logic); -- Read Write Enable
end component test_memory;
-- Epp-wishbone bridge
component eppwbn is
port(
-- Externo
nStrobe: in std_logic; -- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic
);
end component eppwbn;
-- Testing component
component eppwbn_test_wb_side is
port(
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_I: in std_logic_vector (7 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
ACK_O: out std_logic ;
WE_I: in std_logic
);
end component eppwbn_test_wb_side;
-- Width extension
component eppwbn_width_extension is
generic (
TIME_OUT_VALUE: integer;
TIME_OUT_WIDTH: integer
);
port(
-- Slave signals
DAT_I_sl: in std_logic_vector (7 downto 0);
DAT_O_sl: out std_logic_vector (7 downto 0);
ADR_I_sl: in std_logic_vector (7 downto 0);
CYC_I_sl: in std_logic;
STB_I_sl: in std_logic;
ACK_O_sl: out std_logic ;
WE_I_sl: in std_logic;
-- Master signals
DAT_I_ma: in std_logic_vector (15 downto 0);
DAT_O_ma: out std_logic_vector (15 downto 0);
ADR_O_ma: out std_logic_vector (7 downto 0);
CYC_O_ma: out std_logic;
STB_O_ma: out std_logic;
ACK_I_ma: in std_logic ;
WE_O_ma: out std_logic;
-- Common signals
RST_I: in std_logic;
CLK_I: in std_logic
);
end component eppwbn_width_extension;
 
component eppwbn_16bit is
port(
-- Externo
nStrobe: in std_logic; -- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (15 downto 0);
DAT_O: out std_logic_vector (15 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic
);
end component eppwbn_16bit;
component eppwbn_16bit_test is
port(
-- al puerto EPP
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
-- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- a los switches
rst: in std_logic;
-- al clock
clk: in std_logic
);
end component eppwbn_16bit_test;
component eppwbn_16bit_test_wb_side is
generic (
ADD_WIDTH : integer ;
WIDTH : integer
);
port(
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (WIDTH-1 downto 0);
DAT_O: out std_logic_vector (WIDTH-1 downto 0);
ADR_I: in std_logic_vector (7 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
ACK_O: out std_logic ;
WE_I: in std_logic
);
end component eppwbn_16bit_test_wb_side;
-- Clock (Actel specific)
component pll is
port(GLB, LOCK : out std_logic; CLK : in std_logic) ;
end component pll;
 
end package eppwbn_pgk;
----------------------------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.2
--| Tested in: Actel APA300
--|-------------------------------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| Package for instantiate all EPP-WBN modules.
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.01 | dic-2008 | First release
--| 0.10 | jan-2009 | Added testing memory
--| 0.20 | mar-2009 | Added extension module
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package eppwbn_pkg is
--------------------------------------------------------------------------------------------------
-- Componentes
-- Bridge control
component eppwbn_ctrl is
port(
nStrobe: in std_logic;
Data: in std_logic_vector (7 downto 0);
nAck: out std_logic;
PError: out std_logic;
Sel: out std_logic;
nAutoFd: in std_logic;
PeriphLogicH: out std_logic;
nInit: in std_logic;
nFault: out std_logic;
nSelectIn: in std_logic;
RST_I: in std_logic;
CLK_I: in std_logic;
 
rst_pp: out std_logic;
epp_mode: out std_logic_vector (1 downto 0)
);
end component eppwbn_ctrl;
-- Comunication with EPP interface
component eppwbn_epp_side is
port(
epp_mode: in std_logic_vector (1 downto 0);
 
ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic;
ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic;
wb_Busy: in std_logic;
wb_nAutoFd: out std_logic;
wb_nSelectIn: out std_logic;
wb_nStrobe: out std_logic;
 
nAck, PError, Sel, nFault: out std_logic;
Busy: out std_logic;
nAutoFd: in std_logic;
nSelectIn: in std_logic;
nStrobe: in std_logic
);
end component eppwbn_epp_side;
-- Comunication with WB interface
component eppwbn_wbn_side is
port(
inStrobe: in std_logic;
iData: inout std_logic_vector (7 downto 0);
iBusy: out std_logic;
inAutoFd: in std_logic;
inSelectIn: in std_logic;
RST_I, CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O, STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic;
 
rst_pp: in std_logic
);
end component eppwbn_wbn_side;
-- Testing memory
component test_memory is
generic ( --USE_RESET : boolean := false; -- use system reset
 
--USE_CS : boolean := false; -- use chip select signal
 
DEFAULT_OUT : std_logic; -- Default output
--OPTION : integer := 1; -- 1: Registered read Address(suitable
-- for Altera's FPGAs
-- 0: non registered read address
ADD_WIDTH : integer;
WIDTH : integer);
 
port (
cs: in std_logic; -- chip select
clk: in std_logic; -- write clock
reset: in std_logic; -- System Reset
add: in std_logic_vector(add_width -1 downto 0); -- Address
Data_In: in std_logic_vector(WIDTH -1 downto 0); -- input data
Data_Out: out std_logic_vector(WIDTH -1 downto 0); -- Output Data
WR: in std_logic); -- Read Write Enable
end component test_memory;
-- Epp-wishbone bridge
component eppwbn is
port(
-- TEMPORAL
epp_mode_monitor: out std_logic_vector (1 downto 0);
-- Externo
nStrobe: in std_logic; -- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic
);
end component eppwbn;
-- Testing component
component eppwbn_test_wb_side is
port(
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_I: in std_logic_vector (7 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
ACK_O: out std_logic ;
WE_I: in std_logic
);
end component eppwbn_test_wb_side;
-- Width extension
component eppwbn_width_extension is
generic (
TIME_OUT_VALUE: integer;
TIME_OUT_WIDTH: integer
);
port(
-- Slave signals
DAT_I_sl: in std_logic_vector (7 downto 0);
DAT_O_sl: out std_logic_vector (7 downto 0);
ADR_I_sl: in std_logic_vector (7 downto 0);
CYC_I_sl: in std_logic;
STB_I_sl: in std_logic;
ACK_O_sl: out std_logic ;
WE_I_sl: in std_logic;
-- Master signals
DAT_I_ma: in std_logic_vector (15 downto 0);
DAT_O_ma: out std_logic_vector (15 downto 0);
ADR_O_ma: out std_logic_vector (7 downto 0);
CYC_O_ma: out std_logic;
STB_O_ma: out std_logic;
ACK_I_ma: in std_logic ;
WE_O_ma: out std_logic;
-- Common signals
RST_I: in std_logic;
CLK_I: in std_logic
);
end component eppwbn_width_extension;
 
component eppwbn_16bit is
port(
-- TEMPORAL
epp_mode_monitor: out std_logic_vector (1 downto 0);
-- Externo
nStrobe: in std_logic; -- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (15 downto 0);
DAT_O: out std_logic_vector (15 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic
);
end component eppwbn_16bit;
component eppwbn_16bit_test is
port(
-- al puerto EPP
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
-- HostClk/nWrite
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
busy: out std_logic; -- PtrBusy/PeriphAck/nWait
PError: out std_logic; -- AckData/nAckReverse
Sel: out std_logic; -- XFlag (Select)
nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
PeriphLogicH: out std_logic; -- (Periph Logic High)
nInit: in std_logic; -- nReverseRequest
nFault: out std_logic; -- nDataAvail/nPeriphRequest
nSelectIn: in std_logic; -- 1284 Active/nAStrb
-- a los switches
rst: in std_logic;
-- al clock
clk: in std_logic;
-- monitores
data_monitor: out std_logic_vector (7 downto 0);
epp_mode_monitor: out std_logic_vector (1 downto 0)
);
end component eppwbn_16bit_test;
component eppwbn_16bit_test_wb_side is
generic (
ADD_WIDTH : integer ;
WIDTH : integer
);
port(
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (WIDTH-1 downto 0);
DAT_O: out std_logic_vector (WIDTH-1 downto 0);
ADR_I: in std_logic_vector (7 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
ACK_O: out std_logic ;
WE_I: in std_logic
);
end component eppwbn_16bit_test_wb_side;
-- Clock (Actel specific)
component A3PE_pll is
port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out
std_logic) ;
end component A3PE_pll;
 
component dual_port_memory_wb is
port(
-- Puerto A (Higer prioriry)
RST_I_a: in std_logic;
CLK_I_a: in std_logic;
DAT_I_a: in std_logic_vector (15 downto 0);
DAT_O_a: out std_logic_vector (15 downto 0);
ADR_I_a: in std_logic_vector (13 downto 0);
CYC_I_a: in std_logic;
STB_I_a: in std_logic;
ACK_O_a: out std_logic ;
WE_I_a: in std_logic;
-- Puerto B (Lower prioriry)
RST_I_b: in std_logic;
CLK_I_b: in std_logic;
DAT_I_b: in std_logic_vector (15 downto 0);
DAT_O_b: out std_logic_vector (15 downto 0);
ADR_I_b: in std_logic_vector (13 downto 0);
CYC_I_b: in std_logic;
STB_I_b: in std_logic;
ACK_O_b: out std_logic ;
WE_I_b: in std_logic
);
end component dual_port_memory_wb;
end package eppwbn_pkg;

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