URL
https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk
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- This comparison shows the changes necessary to convert path
/modular_oscilloscope/trunk/hdl/epp
- from Rev 34 to Rev 41
- ↔ Reverse comparison
Rev 34 → Rev 41
/eppwbn_16bit_test.vhd
4,17 → 4,19
--| |
--| File: eppwbn_test.vhd |
--| Version: 0.60 |
--| Tested in: Actel APA300, Actel A3PE1500 |
--| Tested in: Actel APA300 |
--| Tested in: Actel A3PE1500 |
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board |
--|------------------------------------------------------------------------------------------------- |
--| Description: |
--| EPP - Wishbone bridge. |
--| This file is only for test purposes |
--| This file is only for test purposes |
--| |
--|------------------------------------------------------------------------------------------------- |
--| File history: |
--| 0.10 | jan-2008 | First release |
--| 0.50 | jun-2009 | Sample testing signals |
--| 0.60 | jun-2009 | Sample testing instance for a dual port memory |
--| 0.50 | jun-2009 | Testing signals |
--| 0.60 | jun-2009 | Testing instance for the dual port memory |
---------------------------------------------------------------------------------------------------- |
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--| |
/eppwbn_ctrl.vhd
16,7 → 16,7
--| 0.20 | dic-2008 | Custom signals without tri-state |
--| 0.21 | jan-2009 | Sinc reset |
---------------------------------------------------------------------------------------------------- |
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|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
44,8 → 44,8
nFault: out std_logic; -- nDataAvail/nPeriphRequest |
nSelectIn: in std_logic; -- 1284 Active/nAStrb |
-- HostLogicH: in std_logic; -- (Host Logic High) |
|
|
|
-- salida a la interface wishbone |
RST_I: in std_logic; |
CLK_I: in std_logic; |
62,7 → 62,7
|
|
architecture state_machines of eppwbn_ctrl is |
type StateType is ( |
type StateType is ( |
st_compatibility_idle, -- Los estados corresponden a los especificados |
st_negotiation2, -- por el est?ndar. |
-- Los n?meros de los estados negotiation corresponden |
69,10 → 69,10
-- a las fases del est?ndar. |
st_initial_epp, |
st_epp_mode |
-- otros modos |
-- otros modos |
); |
signal next_state, present_state: StateType; |
signal ext_req_val: std_logic_vector (7 downto 0); |
signal next_state, present_state: StateType; |
signal ext_req_val: std_logic_vector (7 downto 0); |
begin |
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---------------------------------------------------------------------------------------- |
/eppwbn_pkg.vhd
14,7 → 14,7
--| 0.10 | jan-2009 | Added testing memory |
--| 0.20 | mar-2009 | Added extension module |
---------------------------------------------------------------------------------------------------- |
|
|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |