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URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

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    /modular_oscilloscope/trunk
    from Rev 37 to Rev 38
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Rev 37 → Rev 38

/hdl/ctrl/tbench/channel_selector_tbench_text.vhd
233,6 → 233,7
signal clk_I: std_logic;
signal enable_I: std_logic;
signal reset_I: std_logic;
signal first_channel_O: std_logic;
 
begin
--------------------------------------------------------------------------------------------------
247,13 → 248,14
 
--------------------------------------------------------------------------------------------------
-- Instantiation of Model Under Test.
daq_0 : entity work.channel_selector
chsel_0 : entity work.channel_selector
port map (
channels_I => channels_I,
channel_number_O => channel_number_O,
clk_I => clk_I,
enable_I => enable_I,
reset_I => reset_I
reset_I => reset_I,
first_channel_O => first_channel_O
);
end tbGeneratedCode;
----------------------------------------------------------------------------------------------------
/hdl/ctrl/tbench/data_skipper_tbench_text.vhd
53,7 → 53,8
-- enable from register
enable_skipper_I: inout std_logic;
-- common signals
reset_I, clk_I: inout std_logic
reset_I, clk_I: inout std_logic;
first_channel_I: inout std_logic
);
 
end stimulus;
80,17 → 81,6
 
begin
--------------------------------------------------------------------------------------------------
-- Status Control block.
process
-- variable good : boolean;
begin
wait until tb_ParameterInitFlag;
tb_status <= TB_ONCE;
wait for 50000 ns;
tb_status <= TB_DONE; -- End of simulation
wait;
end process;
 
--------------------------------------------------------------------------------------------------
-- Parm Assignment Block
160,16 → 150,34
 
--<===============================================================================================
-- Sequence: Unclocked
Unclocked : process
P_FirstCh: process
begin
wait until tb_ParameterInitFlag;
first_channel_I <= '0';
wait for T*1.5 ns;
while tb_status = TB_ONCE loop
first_channel_I <= '1';
wait for T * 1 ns; --<delay>
first_channel_I <= '0';
wait for 4.0 * T * 1 ns;
end loop;
wait;
end process;
P_Unclocked : process
variable i: natural range 0 to 500;
begin
wait until tb_ParameterInitFlag;
tb_status <= TB_ONCE;
 
 
-- Initial
reset_I <= '1' ;
enable_skipper_I <= '0';
ack_I <= '0'; stb_I <= '0';
enable_skipper_I <= '1';
selector_I <= (others => '0');
wait for 15 ns; --<delay>
wait for T*1.5 ns; --<delay>
-- w/o en_skip
reset_I <= '0';
192,20 → 200,20
wait for 4.0 * T * 1 ns; --<delay>
ack_I <= '0'; stb_I <= '1';
wait for 4.0*T * 1 ns; --<delay>
wait for 4.0*T *4.0* 1 ns; --<delay>
-- selector_I /= 0
ack_I <= '1'; stb_I <= '1'; selector_I <= std_logic_vector(unsigned(selector_I) + 1);
wait for 20.0*T * 1 ns; --<delay>
wait for 20.0*T*4.0 * 1 ns; --<delay>
selector_I <= std_logic_vector(to_unsigned( integer(2**real(selector_I'length )/10.0), selector_I'length ));
wait for 1000.0*T * 1 ns; --<delay>
wait for 4000.0*T*4.0 * 1 ns;
selector_I <= std_logic_vector(to_unsigned( integer(2**real(selector_I'length )/4.0), selector_I'length ));
wait for 2000.0*T * 1 ns; --<delay>
wait for 4000.0*T*4.0 * 1 ns; --<delay>
selector_I <= std_logic_vector(to_unsigned( integer(2**real(selector_I'length )-1.0), selector_I'length ));
wait for 100000.0*T * 1 ns; --<delay>
wait for 100000.0*T *4.0* 1 ns; --<delay>
 
212,9 → 220,8
tb_status <= TB_DONE; -- End of simulation
wait;
 
end process;
--===============================================================================================>
253,6 → 260,7
signal enable_skipper_I: std_logic;
-- common signals
signal reset_I, clk_I: std_logic;
signal first_channel_I: std_logic;
 
begin
--------------------------------------------------------------------------------------------------
267,7 → 275,8
selector_I => selector_I,
enable_skipper_I => enable_skipper_I,
reset_I => reset_I,
clk_I => clk_I
clk_I => clk_I,
first_channel_I => first_channel_I
);
 
--------------------------------------------------------------------------------------------------
283,6 → 292,7
selector_I => selector_I,
enable_skipper_I => enable_skipper_I,
reset_I => reset_I,
first_channel_I => first_channel_I,
clk_I => clk_I
);
end tbGeneratedCode;
/hdl/ctrl/ctrl.vhd
1,6 → 431,7
-- ctrl.vhd
-------------------------------------------------------------------------------------------------100
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: ctrl.vhd
--| Version: 0.1
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--| CONTROL - Control system
--| This is the tom modules in the folder.
--|
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.1 | aug-2009 | First testing
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
--==================================================================================================
-- TO DO
 
--==================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
 
use work.ctrl_pkg.all;
 
entity ctrl is
port(
------------------------------------------------------------------------------------------------
-- From port
DAT_I_port: in std_logic_vector (15 downto 0);
DAT_O_port: out std_logic_vector (15 downto 0);
ADR_I_port: in std_logic_vector (3 downto 0);
CYC_I_port: in std_logic;
STB_I_port: in std_logic;
ACK_O_port: out std_logic ;
WE_I_port: in std_logic;
CLK_I_port: in std_logic;
RST_I_port: in std_logic;
------------------------------------------------------------------------------------------------
-- To ADC
DAT_I_daq: in std_logic_vector (15 downto 0);
DAT_O_daq: out std_logic_vector (15 downto 0);
ADR_O_daq: out std_logic_vector (3 downto 0);
CYC_O_daq: out std_logic;
STB_O_daq: out std_logic;
ACK_I_daq: in std_logic ;
WE_O_daq: out std_logic;
CLK_I_daq: in std_logic;
RST_I_daq: in std_logic;
------------------------------------------------------------------------------------------------
-- To memory, A (writing) interface (Higer prioriry)
--DAT_I_memw: in std_logic_vector (15 downto 0);
DAT_O_memw: out std_logic_vector (15 downto 0);
ADR_O_memw: out std_logic_vector (13 downto 0);
CYC_O_memw: out std_logic;
STB_O_memw: out std_logic;
ACK_I_memw: in std_logic ;
WE_O_memw: out std_logic;
------------------------------------------------------------------------------------------------
-- To memory, B (reading) interface
DAT_I_memr: in std_logic_vector (15 downto 0);
--DAT_O_memr: out std_logic_vector (15 downto 0);
ADR_O_memr: out std_logic_vector (13 downto 0);
CYC_O_memr: out std_logic;
STB_O_memr: out std_logic;
ACK_I_memr: in std_logic ;
WE_O_memr: out std_logic
 
);
end entity ctrl;
 
 
 
architecture WSM of ctrl is
type StateType is (
ST_IDLE,
ST_INIT,
ST_RUNNING
);
signal next_state, present_state: StateType;
--------------------------------------------------------------------------------------------------
-- Interconnections
 
-- internal wb
signal cyc_to_outmgr: std_logic;
signal stb_to_outmgr: std_logic;
signal ack_from_outmgr: std_logic;
signal dat_from_outmgr: std_logic_vector(15 downto 0);
 
-- trigger
signal trigger_reset: std_logic;
signal trigger_en: std_logic;
signal trigger_out_adr: std_logic;
signal reg_trigger_en: std_logic;
signal reg_trigger_edge: std_logic;
signal reg_trigger_level: std_logic_vector(9 downto 0);
signal reg_trigger_offset: std_logic_vector(14 downto 0);
signal reg_trigger_channel: std_logic;
-- channels
signal reg_channels_selection: std_logic_vector(1 downto 0);
signal chsel_first_channel: std_logic;
signal chsel_channel: std_logic_vector(3 downto 0);
signal chsel_reset: std_logic;
signal chsel_en: std_logic;
-- address
signal buffer_size: std_logic_vector(13 downto 0);
-- skipper
signal dskip_en: std_logic;
signal dskip_reset: std_logic;
signal dskip_out_ack: std_logic;
signal dskip_in_stb: std_logic;
-- Memory writer
signal memwr_en: std_logic;
signal memwr_reset: std_logic;
signal memwr_stb: std_logic;
signal memwr_ack: std_logic;
signal memwr_continuous: std_logic;
signal memwr_out_adr: std_logic_vector (14 downto 0);
signal memwr_in_dat: std_logic_vector (15 downto 0);
-- outmgr
signal outmgr_reset: std_logic;
signal outmgr_en: std_logic;
signal outmgr_load: std_logic;
signal outmgr_initial_adr: std_logic;
--signal outmgr_pause_adr: std_logic; -- ??
signal outmgr_finish: std_logic;
signal time_scale: std_logic_vector(4 downto 0);
signal time_scale_en: std_logic;
--------------------------------------------------------------------------------------------------
-- Flags
signal running: std_logic;
signal stop: std_logic;
signal start: std_logic;
signal continuous: std_logic;
 
 
begin
--------------------------------------------------------------------------------------------------
-- Instances
U_OUTMGR0: ctrl_output_manager
generic map(
MEM_ADD_WIDTH => 14 --: integer := 14
)
port map(
----------------------------------------------------------------------------------------------
-- MASTER (to memory)
DAT_I_mem => DAT_I_memr, -- direct
ADR_O_mem => ADR_O_memr, -- direct
CYC_O_mem => CYC_O_memr, -- direct
STB_O_mem => STB_O_memr, -- direct
ACK_I_mem => ACK_I_memr, -- direct
WE_O_mem => WE_O_memr, -- direct
----------------------------------------------------------------------------------------------
-- SLAVE (to I/O ports)
DAT_O_port => dat_from_outmgr,
CYC_I_port => cyc_to_outmgr,
STB_I_port => stb_to_outmgr,
ACK_O_port => ack_from_outmgr,
WE_I_port => '0',
------------------------------------------------------------------------------------------------
-- Common signals
RST_I => RST_I_port, -- direct
CLK_I => CLK_I_port, -- direct
------------------------------------------------------------------------------------------------
-- Internal
load_I => outmgr_load,
enable_I => outmgr_en,
initial_address_I => outmgr_initial_adr,
biggest_address_I => buffer_size,
pause_address_I => memwr_out_adr, -- define
finish_O => outmgr_finish
);
 
U_CTRL_MEMWR0: ctrl_memory_writer
generic map(
MEM_ADD_WIDTH => 14--: integer := 14
)
port map(
-- to memory
DAT_O_mem => DAT_O_memw, -- direct
ADR_O_mem => memwr_out_adr, --!
CYC_O_mem => CYC_O_memw, -- direct
STB_O_mem => STB_O_memw, -- direct
ACK_I_mem => ACK_I_memw, -- direct
WE_O_mem => WE_O_memw, -- direct
-- to acquistion module
DAT_I_adc => memwr_in_dat, --!
CYC_O_adc => CYC_O_adc, -- direct
STB_O_adc => memwr_stb,
ACK_I_adc => memwr_ack,
WE_O_adc => WE_O_adc, -- direct
-- Common signals
RST_I => RST_I_daq, -- direct
CLK_I => CLK_I_daq, -- direct
-- Internal
reset_I => memwr_reset,
enable_I => memwr_en,
final_address_I => buffer_size,
finished_O => memwr_finish,
continuous_I => memwr_continuous
);
U_CTRL_DSKIP0: ctrl_data_skipper
generic map(
SELECTOR_WIDTH => 5,--: integer := 5
)
port map(
ack_O => dskip_out_ack,
ack_I => ACK_I_daq,
stb_I => dskip_in_stb,
selector_I => reg_time_scale,
enable_skipper_I => reg_time_scale_en,
reset_I => RST_I_daq,
clk_I => CLK_I_daq,
first_channel_I => chsel_first_channel
);
U_CTRL_CHSEL0: ctrl_channel_selector
generic map(
CHANNEL_WIDTH => 4 --: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
)
port map(
channels_I => reg_channels_selection,
channel_number_O => chsel_channel,
first_channel_O => chsel_first_channel,
clk_I => CLK_I_daq,
enable_I => chsel_en,
reset_I => chsel_reset
);
U_CTRL_TRIGGER0: ctrl_trigger_manager
generic map(
MEM_ADD_WIDTH => 14,--: integer := 14;
DATA_WIDTH => 10,--: integer := 10;
CHANNELS_WIDTH => 1--: integer := 4
)
port map(
data_I => DAT_I_daq,
channel_I => chsel_channel,
trig_channel_I => reg_trigger_channel,
address_I => memwr_out_adr,
final_address_I => reg_buffer_size,
offset_I => reg_trigger_offset,
level_I => reg_trigger_level,
falling_I => reg_trigger_edge,
clk_I => CLK_I_daq,
reset_I => trigger_reset,
enable_I => trigger_en,
trigger_O => trigger_act,
address_O => trigger_out_adr
);
-- reg_: signals from conf registers
U_CTRL_ADDASSMNT0: ctrl_address_assignments
port map(
-- From port
DAT_I_port => DAT_I_port,
DAT_O_port => DAT_O_port,
ADR_I_port => ADR_I_port,
CYC_I_port => CYC_I_port,
STB_I_port => STB_I_port,
ACK_O_port => ACK_O_port,
WE_I_port => WE_I_port,
RST_I => RST_I_port,
CLK_I => CLK_I_port,
-- To internal
CYC_O_int => cyc_to_outmgr,
STB_O_int => stb_to_outmgr,
ACK_I_int => ack_from_outmgr,
DAT_I_int => dat_from_outmgr,
-- Internal
time_scale_O => reg_time_scale,
time_scale_en_O => reg_time_scale_en,
channels_sel_O => reg_channels_selection,
buffer_size_O => reg_buffer_size,
 
trigger_en_O => reg_trigger_en,
trigger_edge_O => reg_trigger_edge,
trigger_level_O => reg_trigger_level,
trigger_offset_O => reg_trigger_offset,
trigger_channel_O => reg_trigger_channel,
 
error_number_I => "0000", -- not implemented yet
data_channel_I => data_channel_r,
error_flag_I => '0', -- not implemented yet
 
start_O => start,
continuous_O => continuous,
running_I => running,
stop_O => stop
);
 
------------------------------------------------------------------------------------------------
-- Machine
P_sm_comb: process ()
begin
case present_state is
when ST_INIT =>
memwr_reset <= '1';
memwr_en <= '0';
memwr_continuous <= '-';
dskip_reset <= '1';
dskip_en <= '0';
chsel_reset <= '1';
chsel_en <= '0';
trigger_reset <= '1';
trigger_en <= '0';
next_state <= ST_RUNNING;
when ST_RUNNING =>
memwr_reset <= '0';
memwr_en <= ;
memwr_continuous <= ;
dskip_reset <= '0';
dskip_en <= reg_time_scale_en;
chsel_reset <= '0';
chsel_en <= dskip_out_ack;
trigger_reset <= '0';
trigger_en <= reg_trigger_en and memwr_ack;
 
 
when others => --ST_IDLE
 
end case;
end process;
 
P_sm_clkd: process ()
begin
if RST_I_daq = '1' or stop = '1' then
present_state <= ST_IDLE;
elsif start = '1' then
present_state <= ST_INIT;
elsif CLK_I_daq'ecent and clk_I = '1' then
present_state <= next_state;
end if;
end process;
------------------------------------------------------------------------------------------------
-- Output
P_OUTMGR: process (RST_I_port, stop, CLK_I_port, CLK_I_port, present_state, trigger_act,
reg_trigger_en, memwr_out_adr, outmgr_en)
if RST_I_port = '1' or present_state = IDLE or present_state = INIT then
outmgr_load <= '0';
outmgr_en <= '0';
elsif CLK_I_port'event and CLK_I_port = '1' then
if present_state = ST_RUNNING and trigger_act = '1' or (reg_trigger_en = '0' and
memwr_out_adr != conv_integer(0) ) then
outmgr_load <= '1';
outmgr_en <= '1';
-- load must be set only one cycle
elsif outmgr_en = '1' then
load <= '0';
end if;
end if;
end process;
outmgr_initial_adr <= trigger_out_adr when reg_trigger_en = '1' else
(others => '0');
 
end architecture;
/hdl/ctrl/channel_selector.vhd
2,8 → 2,8
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: channel_selector.vhd
--| Version: 0.2
--| File: ctrl_channel_selector.vhd
--| Version: 0.3
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
15,6 → 15,7
--| File history:
--| 0.1 | jul-2009 | First testing
--| 0.2 | jul-2009 | Added generic number of channel
--| 0.3 | jul-2009 | Added signal indicating when it's selecting the first channel
----------------------------------------------------------------------------------------------------
 
--|
25,7 → 26,8
 
--==================================================================================================
-- TODO
 
 
 
--==================================================================================================
 
 
36,16 → 38,16
use ieee.math_real.all;
 
 
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
entity channel_selector is
entity ctrl_channel_selector is
generic(
N_CHANNELS: integer := 16 -- number of channels
CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
);
port(
channels_I: in std_logic_vector(N_CHANNELS-1 downto 0);
channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
channel_number_O: out std_logic_vector(3 downto 0);
first_channel_O: out std_logic;
clk_I: in std_logic;
enable_I: in std_logic;
reset_I: in std_logic
55,13 → 57,16
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
architecture ARCH01 of channel_selector is
constant CHANNEL_WIDTH: integer := integer(ceil(log2(real(N_CHANNELS))));
signal channel: unsigned(CHANNEL_WIDTH-1 downto 0);
signal next_channel: unsigned(CHANNEL_WIDTH-1 downto 0);
architecture ARCH01 of ctrl_channel_selector is
constant N_CHANNELS: integer := integer(2**real(CHANNEL_WIDTH));
-- signal channel: unsigned(CHANNEL_WIDTH-1 downto 0);
-- signal next_channel: unsigned(CHANNEL_WIDTH-1 downto 0);
-- signal next_is_first_channel: std_logic;
signal channel: unsigned(CHANNEL_WIDTH-1 downto 0);
signal next_channel: unsigned(CHANNEL_WIDTH downto 0);
signal next_is_first_channel: std_logic;
signal rotated: unsigned(N_CHANNELS-1 downto 0);
signal plus: unsigned(CHANNEL_WIDTH downto 0);
begin
--------------------------------------------------------------------------------------------------
69,85 → 74,86
channel_number_O <= (3 downto CHANNEL_WIDTH => '0') & std_logic_vector(channel);
--channel_number_O <= std_logic_vector(channel);
--------------------------------------------------------------------------------------------------
-- Combinational selection
-- Combinational selection of next channel
P_comb: process(channel,channels_I)
variable j : integer range 0 to N_CHANNELS-1;
variable index: integer range 0 to N_CHANNELS-1;
begin
-- P_comb: process(channel,channels_I)
-- variable j : integer range 0 to N_CHANNELS-1;
-- variable index: integer range 0 to N_CHANNELS-1;
-- begin
 
-- -- for i in 0 to N_CHANNELS loop
-- if i = to_integer(channel) then
-- exit;
-- end if;
-- end loop;
-- for i in 0 to N_CHANNELS loop
--i := to_natural(channel);
for j in 0 to N_CHANNELS-1 loop
-- for j in 0 to N_CHANNELS-1 loop
if (j + to_integer(channel) + 1) > (N_CHANNELS - 1) then
index := j + to_integer(channel) + 1 - N_CHANNELS;
else
index := j + to_integer(channel) + 1;
end if;
-- if (j + to_integer(channel) + 1) > (N_CHANNELS - 1) then
-- index := j + to_integer(channel) + 1 - N_CHANNELS;
-- next_is_first_channel <= '1';
-- else
-- index := j + to_integer(channel) + 1;
-- next_is_first_channel <= '0';
-- end if;
if channels_I(index) = '1' then
next_channel <= to_unsigned(index, CHANNEL_WIDTH);
exit;
else
next_channel <= channel;
end if;
end loop;
-- if channels_I(index) = '1' then
-- next_channel <= to_unsigned(index, CHANNEL_WIDTH);
-- exit;
-- else
-- next_channel <= channel;
-- end if;
-- end loop;
-- end process;
--100.0 MHz 67.1 MHz (N_CHANNELS = 16)
-- 271 of 38400 (1%)
rotated <= unsigned(channels_I) ror (to_integer(channel));
next_channel <= ('0' & channel) + plus;
--next_channel <= channel + plus;
next_is_first_channel <= next_channel (CHANNEL_WIDTH);
P_coder: process(rotated)
variable i: integer range 1 to N_CHANNELS-1;
begin
for i in 1 to N_CHANNELS-1 loop
if rotated(i) = '1' then
plus <= to_unsigned(i, CHANNEL_WIDTH+1);
exit;
else
plus <= (CHANNEL_WIDTH =>'1') & (CHANNEL_WIDTH - 1 downto 0 => '0');
end if;
end loop;
end process;
-- for i in 0 to N_CHANNELS loop
-- if channel = to_unsigned(i, 4) then
-- for j in i+1 to (2*N_CHANNELS)-1 loop
-- if j > N_CHANNELS-1 then
-- index := j - N_CHANNELS;
-- else
-- index := j;
-- end if;
--
-- if channels_I(index) = '1' then
-- next_channel <= to_unsigned(index, CHANNEL_WIDTH);
-- exit;
-- else
-- next_channel <= channel;
-- end if;
-- end loop;
-- exit;
-- else
-- next_channel <= channel;
-- end if;
-- end loop;
end process;
--100.0 MHz 70.6 MHz (N_CHANNELS = 16)
-- 137 of 38400 (0%)
--------------------------------------------------------------------------------------------------
-- Clocked
-- Clocked selection of actual channel
P_clock: process(enable_I, reset_I, next_channel, clk_I)
-- P_clock: process(enable_I, reset_I, next_channel, clk_I)
-- begin
-- if clk_I'event and clk_I = '1' then
-- if reset_I = '1' then
-- channel <= (others => '0');
-- first_channel_O <= '1';
-- elsif enable_I = '1' then
-- channel <= next_channel;
-- first_channel_O <= next_is_first_channel;
-- end if;
-- end if;
-- end process;
P_clock: process(enable_I, reset_I, next_channel, clk_I)
begin
if clk_I'event and clk_I = '1' then
if reset_I = '1' then
channel <= (others => '0');
first_channel_O <= '1';
elsif enable_I = '1' then
channel <= next_channel;
channel <= next_channel(CHANNEL_WIDTH-1 downto 0);
first_channel_O <= next_is_first_channel;
end if;
end if;
end process;
 
end architecture;

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