OpenCores
URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /modular_oscilloscope/trunk
    from Rev 47 to Rev 48
    ↔ Reverse comparison
  •

Rev 47 → Rev 48

/hdl/ctrl/ctrl.vhd
15,7 → 15,7
--| File history:
--| 0.1 | aug-2009 | First testing
----------------------------------------------------------------------------------------------------
 
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
24,10 → 24,11
 
--==================================================================================================
-- TO DO
 
 
--==================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;
 
use work.ctrl_pkg.all;
50,7 → 51,7
-- To ADC
DAT_I_daq: in std_logic_vector (15 downto 0);
DAT_O_daq: out std_logic_vector (15 downto 0);
ADR_O_daq: out std_logic_vector (3 downto 0);
ADR_O_daq: out std_logic_vector (1 downto 0);
CYC_O_daq: out std_logic;
STB_O_daq: out std_logic;
ACK_I_daq: in std_logic ;
85,79 → 86,75
 
 
architecture WSM of ctrl is
-- machine
type StateType is (
ST_IDLE,
ST_INIT,
ST_RUNNING
ST_RUNNING,
ST_ADCWRITE_INIT,
ST_ADCWRITE
);
signal next_state, present_state: StateType;
--------------------------------------------------------------------------------------------------
-- Interconnections
 
-- internal wb
signal cyc_to_outmgr: std_logic;
signal stb_to_outmgr: std_logic;
signal ack_from_outmgr: std_logic;
signal dat_from_outmgr: std_logic_vector(15 downto 0);
 
-- trigger
signal trigger_reset: std_logic;
signal trigger_en: std_logic;
signal trigger_out_adr: std_logic;
signal trigger_out_adr: std_logic_vector(13 downto 0);
signal trigger_act: std_logic;
signal reg_trigger_en: std_logic;
signal reg_trigger_edge: std_logic;
signal reg_trigger_level: std_logic_vector(9 downto 0);
signal reg_trigger_offset: std_logic_vector(14 downto 0);
signal reg_trigger_channel: std_logic;
signal reg_trigger_channel: std_logic_vector(0 downto 0);
-- channels
signal reg_channels_selection: std_logic_vector(1 downto 0);
signal chsel_first_channel: std_logic;
signal chsel_channel: std_logic_vector(3 downto 0);
signal chsel_channel: std_logic_vector(0 downto 0);
signal chsel_reset: std_logic;
signal chsel_en: std_logic;
--signal chsel_en: std_logic;
-- address
signal buffer_size: std_logic_vector(13 downto 0);
signal reg_buffer_size: std_logic_vector(13 downto 0);
-- skipper
signal dskip_en: std_logic;
signal dskip_reset: std_logic;
--signal dskip_en: std_logic;
signal dskip_reset: std_logic;
signal dskip_out_ack: std_logic;
signal dskip_in_stb: std_logic;
signal reg_time_scale: std_logic_vector(4 downto 0);
signal reg_time_scale_en: std_logic;
-- Memory writer
signal memwr_en: std_logic;
signal memwr_reset: std_logic;
signal memwr_stb: std_logic;
signal memwr_ack: std_logic;
signal memwr_continuous: std_logic;
signal memwr_out_adr: std_logic_vector (14 downto 0);
--signal memwr_ack: std_logic;
--signal memwr_continuous: std_logic;
signal memwr_out_stb_daq: std_logic;
signal memwr_in_ack_mem: std_logic;
signal memwr_out_cyc_daq: std_logic;
signal memwr_out_adr: std_logic_vector (13 downto 0);
signal memwr_in_dat: std_logic_vector (15 downto 0);
-- outmgr
signal outmgr_reset: std_logic;
signal outmgr_en: std_logic;
signal outmgr_load: std_logic;
signal outmgr_initial_adr: std_logic;
-- Outmgr
--signal outmgr_reset: std_logic;
signal outmgr_en: std_logic;
signal outmgr_load: std_logic;
signal outmgr_initial_adr: std_logic_vector(13 downto 0);
--signal outmgr_pause_adr: std_logic; -- ??
signal outmgr_finish: std_logic;
signal outmgr_finish: std_logic;
signal outmgr_in_cyc: std_logic;
signal outmgr_in_stb: std_logic;
signal outmgr_out_akc: std_logic;
signal outmgr_out_dat: std_logic_vector(15 downto 0);
--------------------------------------------------------------------------------------------------
-- DAQ config
signal dat_to_adc: std_logic_vector(15 downto 0);
signal strobe_adc: std_logic;
signal write_in_adc: std_logic;
signal time_scale: std_logic_vector(4 downto 0);
signal time_scale_en: std_logic;
--------------------------------------------------------------------------------------------------
-- Flags
signal running: std_logic;
164,6 → 161,8
signal stop: std_logic;
signal start: std_logic;
signal continuous: std_logic;
 
177,7 → 176,6
MEM_ADD_WIDTH => 14 --: integer := 14
)
port map(
----------------------------------------------------------------------------------------------
-- MASTER (to memory)
DAT_I_mem => DAT_I_memr, -- direct
ADR_O_mem => ADR_O_memr, -- direct
185,24 → 183,21
STB_O_mem => STB_O_memr, -- direct
ACK_I_mem => ACK_I_memr, -- direct
WE_O_mem => WE_O_memr, -- direct
----------------------------------------------------------------------------------------------
-- SLAVE (to I/O ports)
DAT_O_port => dat_from_outmgr,
CYC_I_port => cyc_to_outmgr,
STB_I_port => stb_to_outmgr,
ACK_O_port => ack_from_outmgr,
DAT_O_port => outmgr_out_dat,
CYC_I_port => outmgr_in_cyc,
STB_I_port => outmgr_in_stb,
ACK_O_port => outmgr_out_akc,
WE_I_port => '0',
------------------------------------------------------------------------------------------------
-- Common signals
RST_I => RST_I_port, -- direct
CLK_I => CLK_I_port, -- direct
------------------------------------------------------------------------------------------------
-- Internal
load_I => outmgr_load,
enable_I => outmgr_en,
initial_address_I => outmgr_initial_adr,
biggest_address_I => buffer_size,
pause_address_I => memwr_out_adr, -- define
biggest_address_I => reg_buffer_size,
pause_address_I => memwr_out_adr,
finish_O => outmgr_finish
);
 
212,42 → 207,41
)
port map(
-- to memory
DAT_O_mem => DAT_O_memw, -- direct
ADR_O_mem => memwr_out_adr, --!
CYC_O_mem => CYC_O_memw, -- direct
STB_O_mem => STB_O_memw, -- direct
ACK_I_mem => ACK_I_memw, -- direct
WE_O_mem => WE_O_memw, -- direct
DAT_O_mem => DAT_O_memw, -- direct
ADR_O_mem => memwr_out_adr,
CYC_O_mem => CYC_O_memw, -- direct
STB_O_mem => STB_O_memw, -- direct
ACK_I_mem => memwr_in_ack_mem, -- direct
WE_O_mem => WE_O_memw, -- direct
-- to acquistion module
DAT_I_adc => memwr_in_dat, --!
CYC_O_adc => CYC_O_adc, -- direct
STB_O_adc => memwr_stb,
ACK_I_adc => memwr_ack,
WE_O_adc => WE_O_adc, -- direct
DAT_I_adc => memwr_in_dat,
CYC_O_adc => memwr_out_cyc_daq, -- direct
STB_O_adc => memwr_out_stb_daq, -- direct
ACK_I_adc => dskip_out_ack,
-- Common signals
RST_I => RST_I_daq, -- direct
CLK_I => CLK_I_daq, -- direct
RST_I => RST_I_daq, -- direct
CLK_I => CLK_I_daq, -- direct
-- Internal
reset_I => memwr_reset,
enable_I => memwr_en,
final_address_I => buffer_size,
finished_O => memwr_finish,
continuous_I => memwr_continuous
final_address_I => reg_buffer_size,
finished_O => open, -- !
continuous_I => reg_trigger_en
);
U_CTRL_DSKIP0: ctrl_data_skipper
generic map(
SELECTOR_WIDTH => 5,--: integer := 5
SELECTOR_WIDTH => 5--: integer := 5
)
port map(
ack_O => dskip_out_ack,
ack_I => ACK_I_daq,
stb_I => dskip_in_stb,
ack_I => ACK_I_daq, -- direct
stb_I => memwr_out_stb_daq,
selector_I => reg_time_scale,
enable_skipper_I => reg_time_scale_en,
reset_I => RST_I_daq,
clk_I => CLK_I_daq,
reset_I => dskip_reset,
clk_I => CLK_I_daq, -- direct
first_channel_I => chsel_first_channel
);
254,7 → 248,7
U_CTRL_CHSEL0: ctrl_channel_selector
generic map(
CHANNEL_WIDTH => 4 --: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
CHANNEL_WIDTH => 1 -- number of channels 2**CHANNEL_WIDTH, max. 4
)
port map(
channels_I => reg_channels_selection,
261,20 → 255,19
channel_number_O => chsel_channel,
first_channel_O => chsel_first_channel,
clk_I => CLK_I_daq,
enable_I => chsel_en,
enable_I => '1',
reset_I => chsel_reset
);
U_CTRL_TRIGGER0: ctrl_trigger_manager
generic map(
MEM_ADD_WIDTH => 14,--: integer := 14;
DATA_WIDTH => 10,--: integer := 10;
CHANNELS_WIDTH => 1--: integer := 4
DATA_WIDTH => 10,--: integer := 10;
CHANNELS_WIDTH => 1 --: integer := 4
)
port map(
data_I => DAT_I_daq,
data_I => DAT_I_daq(9 downto 0),
channel_I => chsel_channel,
trig_channel_I => reg_trigger_channel,
address_I => memwr_out_adr,
290,7 → 283,7
);
-- reg_: signals from conf registers
U_CTRL_ADDASSMNT0: ctrl_address_assignments
U_CTRL_ADDALLOC0: ctrl_address_allocation
port map(
-- From port
DAT_I_port => DAT_I_port,
303,11 → 296,11
RST_I => RST_I_port,
CLK_I => CLK_I_port,
-- To internal
CYC_O_int => cyc_to_outmgr,
STB_O_int => stb_to_outmgr,
ACK_I_int => ack_from_outmgr,
DAT_I_int => dat_from_outmgr,
-- Internal
CYC_O_int => outmgr_in_cyc,
STB_O_int => outmgr_in_stb,
ACK_I_int => outmgr_out_akc,
DAT_I_int => outmgr_out_dat,
-- Internal
time_scale_O => reg_time_scale,
time_scale_en_O => reg_time_scale_en,
channels_sel_O => reg_channels_selection,
319,68 → 312,149
trigger_offset_O => reg_trigger_offset,
trigger_channel_O => reg_trigger_channel,
 
error_number_I => "0000", -- not implemented yet
data_channel_I => data_channel_r,
error_number_I => "000", -- not implemented yet
error_flag_I => '0', -- not implemented yet
 
adc_conf_O => dat_to_adc,
start_O => start,
continuous_O => continuous,
running_I => running,
write_in_adc_O => write_in_adc,
stop_O => stop
);
 
------------------------------------------------------------------------------------------------
-- Assignments
ADR_O_memw <= memwr_out_adr;
ADR_O_daq <= '0' & chsel_channel(0) when strobe_adc = '0'
else "10";
DAT_O_daq <= dat_to_adc;
CYC_O_daq <= strobe_adc or memwr_out_cyc_daq;
STB_O_daq <= strobe_adc or memwr_out_stb_daq;
WE_O_daq <= strobe_adc ;
memwr_in_dat <= (15 downto 11 => '0') & chsel_channel & DAT_I_daq(9 downto 0);
memwr_in_ack_mem <= ACK_I_memw;
------------------------------------------------------------------------------------------------
-- Machine
P_sm_comb: process ()
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr, reg_trigger_en,
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
begin
-- signals from output manager are described in next process
case present_state is
when ST_INIT =>
memwr_reset <= '1';
memwr_en <= '0';
memwr_continuous <= '-';
memwr_en <= '-';
dskip_reset <= '1';
dskip_en <= '0';
chsel_reset <= '1';
chsel_en <= '0';
chsel_reset <= '0';
trigger_reset <= '1';
trigger_en <= '0';
trigger_en <= '-';
running <= '1';
strobe_adc <= '0';
-- -- -- --
next_state <= ST_RUNNING;
when ST_RUNNING =>
when ST_RUNNING =>
 
memwr_reset <= '0';
memwr_en <= ;
memwr_continuous <= ;
if reg_trigger_en = '1' and trigger_out_adr = memwr_out_adr then
memwr_en <= '0';
else
memwr_en <= '1';
end if;
dskip_reset <= '0';
dskip_en <= reg_time_scale_en;
chsel_reset <= '0';
chsel_en <= dskip_out_ack;
trigger_reset <= '0';
trigger_en <= reg_trigger_en and memwr_ack;
trigger_en <= reg_trigger_en and memwr_in_ack_mem;
running <= '1';
 
 
strobe_adc <= '0';
-- -- -- --
if outmgr_finish = '1' then
if continuous = '1' then
next_state <= ST_INIT;
else
next_state <= ST_IDLE;
end if;
else
next_state <= ST_RUNNING;
end if;
when ST_ADCWRITE_INIT =>
memwr_reset <= '1';
memwr_en <= '-';
dskip_reset <= '1';
chsel_reset <= '1';
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
strobe_adc <= '0';
-- -- -- --
next_state <= ST_ADCWRITE;
when ST_ADCWRITE =>
memwr_reset <= '1';
memwr_en <= '-';
dskip_reset <= '1';
chsel_reset <= '1';
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
strobe_adc <= '1';
-- -- -- --
if ACK_I_daq = '1' then
next_state <= ST_IDLE;
else
next_state <= ST_ADCWRITE;
end if;
when others => --ST_IDLE
 
memwr_reset <= '1';
memwr_en <= '-';
dskip_reset <= '1';
chsel_reset <= '1';
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
strobe_adc <= '0';
-- -- -- --
next_state <= ST_IDLE;
end case;
end process;
387,14 → 461,16
 
P_sm_clkd: process ()
P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc)
begin
if RST_I_daq = '1' or stop = '1' then
present_state <= ST_IDLE;
elsif start = '1' then
elsif write_in_adc = '1' then
present_state <= ST_ADCWRITE_INIT;
elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
present_state <= ST_INIT;
elsif CLK_I_daq'ecent and clk_I = '1' then
elsif CLK_I_daq'event and CLK_I_daq = '1' then
present_state <= next_state;
end if;
403,23 → 479,26
------------------------------------------------------------------------------------------------
-- Output
P_OUTMGR: process (RST_I_port, stop, CLK_I_port, CLK_I_port, present_state, trigger_act,
reg_trigger_en, memwr_out_adr, outmgr_en)
if RST_I_port = '1' or present_state = IDLE or present_state = INIT then
begin
if RST_I_port = '1' or present_state = ST_IDLE or present_state = ST_INIT then
outmgr_load <= '0';
outmgr_en <= '0';
elsif CLK_I_port'event and CLK_I_port = '1' then
if present_state = ST_RUNNING and trigger_act = '1' or (reg_trigger_en = '0' and
memwr_out_adr != conv_integer(0) ) then
if stop = '1' then
outmgr_load <= '0';
outmgr_en <= '0';
elsif present_state = ST_RUNNING and ( trigger_act = '1' or (reg_trigger_en = '0' and
memwr_out_adr /= 0 ) ) then
outmgr_load <= '1';
outmgr_en <= '1';
-- load must be set only one cycle
elsif outmgr_en = '1' then
load <= '0';
outmgr_load <= '0';
end if;
end if;
end process;
/hdl/ctrl/memory_writer.vhd
13,6 → 13,8
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.1 | jul-2009 | First release
--| 0.12 | aug-2009 | Disable strobe output when enable = '0'
--| 0.13 | aug-2009 | End in 0 when continuous (better integration)
----------------------------------------------------------------------------------------------------
 
--|
23,7 → 25,8
 
--==================================================================================================
-- TODO
 
 
 
--==================================================================================================
 
 
32,8 → 35,8
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
 
use work.ctrl_pkg.all;
 
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
entity ctrl_memory_writer is
58,7 → 61,7
CYC_O_adc: out std_logic;
STB_O_adc: out std_logic;
ACK_I_adc: in std_logic ;
WE_O_adc: out std_logic;
--WE_O_adc: out std_logic;
------------------------------------------------------------------------------------------------
-- Common signals
75,7 → 78,7
-- it is set when communication ends and remains until next restart or actual address change
finished_O: out std_logic;
-- when counter finishes, restart
continuous_I: in std_logic;
continuous_I: in std_logic
);
end entity ctrl_memory_writer;
 
82,22 → 85,21
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
architecture ARCH11 of ctrl_output_manager is
architecture ARCH12 of ctrl_memory_writer is
type DataStatusType is (
FINISHED,
INIT,
WORKING
);
signal data_status: DataStatusType; -- comunicates status between both ports
signal data_status: DataStatusType;
signal count: std_logic_vector(MEM_ADD_WIDTH-1 downto 0);
signal enable_count:std_logic;
signal reset_count: std_logic;
signal data: std_logic_vector(15 downto 0);
signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
signal s_finished, s_STB_adc, s_STB_mem: std_logic; -- previous to outputs
begin
119,23 → 121,24
-- Combinational
-- counter
s_finished <= '1' when count >= final_address_I;
s_finished <= '1' when count >= final_address_I else '0';
enable_count <= '1' when enable_I = '1' and
data_status = WORKING and
s_STB_mem = '1' and
ACK_I_mem = '1' and
s_finished = '0'
ACK_I_mem = '1'
else
'0';
reset_count <= '1' when reset_I = '1' or (s_finished = '1' and continuous_I = '1') else
reset_count <= '1' when reset_I = '1' or s_finished = '1' else
'0';
 
-- outputs
finished_O <= s_finished;
STB_O_adc <= s_STB_adc;
STB_O_mem <= s_STB_mem;
STB_O_adc <= s_STB_adc and enable_I; -- !
STB_O_mem <= s_STB_mem and enable_I; -- !
DAT_O_mem <= data;
ADR_O_mem <= count;
--WE_O_adc <= '0';
WE_O_mem <= '1';
--------------------------------------------------------------------------------------------------
-- Clocked
142,7 → 145,7
-- Lock interface when working
P_cyc_signals: process (clk_I, enable_count, ACK_I_adc, ACK_I_mem)
P_cyc_signals: process (CLK_I, enable_I, reset_I)
begin
if CLK_I'event and CLK_I = '1' then
if enable_I = '0' or reset_I = '1' then
153,48 → 156,55
end if;
end process;
 
P_stb_signals: process (CLK_I, reset_I, data_status, s_STB_adc, s_STB_mem, ACK_I_adc, ACK_I_mem)
begin
 
if CLK_I'event and CLK_I = '1' then
if reset_I = '1' then
if reset_I = '1' or RST_I = '1' then
data_status <= INIT;
s_STB_adc <= '0';
s_STB_mem <= '0';
data <= (others => '0');
elsif enable_I = '1' then
if data_status = INIT and s_STB_adc = '0' or s_STB_mem = '0' then
-- this state is only necessary when there are adc convertions in every clock
-- (for the first convertion)
s_STB_adc <= '1';
s_STB_mem <= '1';
else
data_status <= WORKING;
case data_status is
when INIT =>
-- this state is only necessary when there are adc convertions in every clock
-- (for the first convertion)
s_STB_adc <= '1';
s_STB_mem <= '1';
data_status <= WORKING;
if s_STB_adc = '1' and ACK_I_adc = '1' then
s_STB_mem <= '1'; -- strobe when adc ack
data <= DAT_I_adc; -- save data
elsif s_STB_mem = '1' and ACK_I_mem = '1' then
s_STB_mem <= '0';
end if;
when WORKING =>
if s_STB_adc = '1' and ACK_I_adc = '1' then
s_STB_mem <= '1'; -- strobe when adc ack
data <= DAT_I_adc; -- save data
elsif s_STB_mem = '1' and ACK_I_mem = '1' then
s_STB_mem <= '0';
end if;
if s_STB_mem = '1' and ACK_I_mem = '1' then
s_STB_adc <= '1'; -- strobe when mem ack
elsif s_STB_adc = '1' and ACK_I_adc = '1' then
s_STB_adc <= '0';
end if;
if s_STB_mem = '1' and ACK_I_mem = '1' then
s_STB_adc <= '1'; -- strobe when mem ack
elsif s_STB_adc = '1' and ACK_I_adc = '1' then
if continuous_I = '0' and s_finished = '1' then
data_status <= FINISHED;
end if;
when others => -- FINISHED
s_STB_adc <= '0';
end if;
s_STB_mem <= '0';
end if;
else
s_STB_adc <= '0';
s_STB_mem <= '0';
end case;
end if;
end if;
end if;
end process;
 
 
 
end architecture;
/hdl/ctrl/ctrl_pkg.vhd
121,7 → 121,7
CYC_O_adc: out std_logic;
STB_O_adc: out std_logic;
ACK_I_adc: in std_logic ;
WE_O_adc: out std_logic;
--WE_O_adc: out std_logic;
----------------------------------------------------------------------------------------------
-- Common signals
RST_I: in std_logic;
136,7 → 136,7
-- it is set when communication ends and remains until next restart or actual address change
finished_O: out std_logic;
-- when counter finishes, restart
continuous_I: in std_logic;
continuous_I: in std_logic
);
end component ctrl_memory_writer;
208,7 → 208,7
end component ctrl_trigger_manager;
component ctrl_address_assignments is
component ctrl_address_allocation is
port(
----------------------------------------------------------------------------------------------
-- From port
231,9 → 231,9
-- Internal
start_O: out std_logic;
continuous_O: out std_logic;
trigger_en_O: out std_losugic;
trigger_en_O: out std_logic;
trigger_edge_O: out std_logic;
trigger_channel_O:out std_logic;
trigger_channel_O:out std_logic_vector(0 downto 0);
time_scale_O: out std_logic_vector(4 downto 0);
time_scale_en_O: out std_logic;
channels_sel_O: out std_logic_vector(1 downto 0);
241,15 → 241,67
trigger_level_O: out std_logic_vector(9 downto 0);
trigger_offset_O: out std_logic_vector(14 downto 0);
adc_conf_O: out std_logic_vector(15 downto 0);
error_number_I: in std_logic_vector (2 downto 0);
data_channel_I: in std_logic;
running_I: in std_logic;
error_flag_I: in std_logic;
write_in_adc_O: out std_logic;
stop_O: out std_logic
);
end component ctrl_address_assignments;
end component ctrl_address_allocation;
component ctrl is
port(
------------------------------------------------------------------------------------------------
-- From port
DAT_I_port: in std_logic_vector (15 downto 0);
DAT_O_port: out std_logic_vector (15 downto 0);
ADR_I_port: in std_logic_vector (3 downto 0);
CYC_I_port: in std_logic;
STB_I_port: in std_logic;
ACK_O_port: out std_logic ;
WE_I_port: in std_logic;
CLK_I_port: in std_logic;
RST_I_port: in std_logic;
------------------------------------------------------------------------------------------------
-- To ADC
DAT_I_daq: in std_logic_vector (15 downto 0);
DAT_O_daq: out std_logic_vector (15 downto 0);
ADR_O_daq: out std_logic_vector (1 downto 0);
CYC_O_daq: out std_logic;
STB_O_daq: out std_logic;
ACK_I_daq: in std_logic ;
WE_O_daq: out std_logic;
CLK_I_daq: in std_logic;
RST_I_daq: in std_logic;
------------------------------------------------------------------------------------------------
-- To memory, A (writing) interface (Higer prioriry)
--DAT_I_memw: in std_logic_vector (15 downto 0);
DAT_O_memw: out std_logic_vector (15 downto 0);
ADR_O_memw: out std_logic_vector (13 downto 0);
CYC_O_memw: out std_logic;
STB_O_memw: out std_logic;
ACK_I_memw: in std_logic ;
WE_O_memw: out std_logic;
------------------------------------------------------------------------------------------------
-- To memory, B (reading) interface
DAT_I_memr: in std_logic_vector (15 downto 0);
--DAT_O_memr: out std_logic_vector (15 downto 0);
ADR_O_memr: out std_logic_vector (13 downto 0);
CYC_O_memr: out std_logic;
STB_O_memr: out std_logic;
ACK_I_memr: in std_logic ;
WE_O_memr: out std_logic
 
);
end component ctrl;
end package ctrl_pkg;
/hdl/ctrl/data_skipper.vhd
62,7 → 62,7
first_channel_I: in std_logic
);
end ctrl_entity data_skipper;
end entity ctrl_data_skipper;
 
 
----------------------------------------------------------------------------------------------------
/hdl/ctrl/channel_selector.vhd
3,7 → 3,7
--| UNSL - Argentine
--|
--| File: ctrl_channel_selector.vhd
--| Version: 0.3
--| Version: 0.31
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
16,6 → 16,7
--| 0.1 | jul-2009 | First testing
--| 0.2 | jul-2009 | Added generic number of channel
--| 0.3 | jul-2009 | Added signal indicating when it's selecting the first channel
--| 0.31 | aug-2009 | Generic width in channel_number
----------------------------------------------------------------------------------------------------
 
--|
27,7 → 28,7
--==================================================================================================
-- TODO
 
 
-- OK Generic width in channel_number_O
--==================================================================================================
 
 
46,13 → 47,13
);
port(
channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
channel_number_O: out std_logic_vector(3 downto 0);
channel_number_O: out std_logic_vector(CHANNEL_WIDTH-1 downto 0);
first_channel_O: out std_logic;
clk_I: in std_logic;
enable_I: in std_logic;
reset_I: in std_logic
);
end entity channel_selector;
end entity ctrl_channel_selector;
 
 
----------------------------------------------------------------------------------------------------
71,7 → 72,7
--------------------------------------------------------------------------------------------------
-- Output
channel_number_O <= (3 downto CHANNEL_WIDTH => '0') & std_logic_vector(channel);
channel_number_O <= std_logic_vector(channel);
--channel_number_O <= std_logic_vector(channel);
--------------------------------------------------------------------------------------------------
-- Combinational selection of next channel
/hdl/ctrl/trigger_manager.vhd
25,6 → 25,7
-- TODO
 
 
 
--==================================================================================================
 
library ieee;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.