URL
https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk
Subversion Repositories modular_oscilloscope
Compare Revisions
- This comparison shows the changes necessary to convert path
/modular_oscilloscope/trunk
- from Rev 49 to Rev 50
- ↔ Reverse comparison
Rev 49 → Rev 50
/hdl/epp/eppwbn_16bit.vhd
54,10 → 54,10
CYC_O: out std_logic; |
STB_O: out std_logic; |
ACK_I: in std_logic ; |
WE_O: out std_logic; |
WE_O: out std_logic |
|
-- TEMPORAL monitores |
epp_mode_monitor: out std_logic_vector(1 downto 0) |
--epp_mode_monitor: out std_logic_vector(1 downto 0) |
|
); |
end eppwbn_16bit; |
79,7 → 79,7
U_EPPWBN8: eppwbn |
port map( |
-- TEMPORAL |
epp_mode_monitor => epp_mode_monitor, |
--epp_mode_monitor => epp_mode_monitor, |
|
|
-- To EPP interface |
/hdl/epp/eppwbn.vhd
13,7 → 13,6
--| The top module for 8 bit wisbone data bus. |
--|------------------------------------------------------------------------------------------------- |
--| File history: |
--| 0.01 | dic-2008 | First release |
--| 0.10 | feb-2009 | Working |
---------------------------------------------------------------------------------------------------- |
|
36,10 → 35,8
port( |
|
-- TEMPORAL |
epp_mode_monitor: out std_logic_vector (1 downto 0); |
--epp_mode_monitor: out std_logic_vector (1 downto 0); |
|
|
|
-- Externo |
nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284 |
-- HostClk/nWrite |
54,7 → 51,6
nFault: out std_logic; -- nDataAvail/nPeriphRequest |
nSelectIn: in std_logic; -- 1284 Active/nAStrb |
|
|
-- Interno |
RST_I: in std_logic; |
CLK_I: in std_logic; |
89,14 → 85,10
signal s_ctr_nSelectIn: std_logic; |
signal s_ctr_nStrobe: std_logic; |
|
|
|
|
|
begin |
|
-- TEMPORAL |
epp_mode_monitor <= s_epp_mode; |
--epp_mode_monitor <= s_epp_mode; |
|
|
|