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/trunk/hdl/adq/adq_tbench_text.vhd
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trunk/hdl/adq/adq_tbench_text.vhd
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Index: trunk/hdl/adq/adq_pkg.vhd
===================================================================
--- trunk/hdl/adq/adq_pkg.vhd (revision 25)
+++ trunk/hdl/adq/adq_pkg.vhd (nonexistent)
@@ -1,69 +0,0 @@
-----------------------------------------------------------------------------------------------------
---| Modular Oscilloscope
---| UNSL - Argentine
---|
---| File: adq_pkg.vhd
---| Version: 0.01
---| Tested in: Actel A3PE1500
---|-------------------------------------------------------------------------------------------------
---| Description:
---| Adquisition control module.
---| Package for instantiate all adq modules.
---|-------------------------------------------------------------------------------------------------
---| File history:
---| 0.01 | apr-2009 | First release
-----------------------------------------------------------------------------------------------------
---| Copyright ® 2009, Facundo Aguilera.
---|
---| This VHDL design file is an open design; you can redistribute it and/or
---| modify it and/or implement it after contacting the author.
-----------------------------------------------------------------------------------------------------
-
-
--- Bloque completo
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-package adq_pkg is
- --------------------------------------------------------------------------------------------------
- -- Componentes
-
- component adq is
- generic (
- DEFALT_CONFIG : std_logic_vector
- -- bits 8 a 0 clk_pre_scaler
- -- bits 9 clk_pre_scaler_ena
- -- bit 10 adc_sleep
- -- bit 11 adc_chip_sel
- -- bits 12 a 15 sin usar
-
- -- si clk_pre_scaler_ena = 1
- -- frecuencia_adc = frecuencia_wbn / (clk_pre_scaler + 2)
- -- sino frecuencia_adc = frecuencia_wbn
- );
- port(
- -- Externo
- adc_data: in std_logic_vector (9 downto 0);
- adc_sel: out std_logic;
- adc_clk: out std_logic;
- adc_sleep: out std_logic;
- adc_chip_sel: out std_logic;
-
-
- -- Interno
- RST_I: in std_logic;
- CLK_I: in std_logic;
- DAT_I: in std_logic_vector (15 downto 0);
- ADR_I: in std_logic_vector (1 downto 0);
- CYC_I: in std_logic;
- STB_I: in std_logic;
- WE_I: in std_logic;
- DAT_O: out std_logic_vector (15 downto 0);
- ACK_O: out std_logic
- );
- end component adq;
-
-
-
-end package adq_pkg;
-
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trunk/hdl/adq/adq_pkg.vhd
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