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URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

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    /modular_oscilloscope
    from Rev 55 to Rev 56
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Rev 55 → Rev 56

/trunk/hdl/tbench/modullar_oscilloscope_tbench_text.vhd
160,7 → 160,7
-- Control Signal Declarations
signal tb_InitFlag : boolean := false;
signal tb_ParameterInitFlag : boolean := false;
signal i: std_logic;
signal runflag: std_logic;
-- Parm Declarations
211,6 → 211,8
--------------------------------------------------------------------------------------------------
-- Main process
P_Unclocked : process
variable i: integer range 0 to 1200;
------------------------------------------------------------------------------------------------
-- Procedure for write in epp port
procedure WriteData(
423,41 → 425,69
-- -- 101010110 1 342 32
--
--
--
-- wait for 50 ns;
--
-- ------------------------------------------------------------------------------------------------
-- -- Test 5 - Trigger - one shot
-- -- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, not continuous, skipper = 5,
-- -- channels 1 and 2, buffer size = 100h, rissing edge, trigg offset = 0
-- test_number <= 5;
--
-- WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"0100", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"0133", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
-- WriteData(X"00", B"00000_00101_1_1_0_1_0_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
--
--
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- while (runflag = '1') loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- end loop;
wait for 50 ns;
------------------------------------------------------------------------------------------------
-- Test 5 - Trigger - one shot
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, not continuous, skipper = 5,
-- channels 1 and 2, buffer size = 100h, rissing edge, trigg offset = 0
test_number <= 5;
-- Test 6 - Trigger
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 70 %, continuous, skipper = 3,
-- channels 1, buffer size = 150h, falling edge, full negative trigger offset
test_number <= 6;
WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
WriteData(X"02", X"0100", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
WriteData(X"03", X"0133", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
WriteData(X"00", B"00000_00101_1_1_0_1_0_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
WriteData(X"02", X"0150", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
WriteData(X"03", X"02CD", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
WriteData(X"04", X"FF6A", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R -150
WriteData(X"00", B"00000_00011_1_1_1_1_1_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
while (runflag = '1') loop
i := 0;
while (i <= 200) loop
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
i := i + 1;
end loop;
------------------------------------------------------------------------------------------------
-- Test 6 - Trigger
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
-- channels 1, buffer size = 50
------------------------------------------------------------------------------------------------
-- Test 7 - One channel
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
-- channels 1, buffer size = 50
-- daq freq = ctrl freq/2 (default), trigger channel 0, level 30 %, continuous, skipper = 5,
-- channels 1, buffer size = 30, trigger offset 29, skipper = 10
--11101101010
-- test_number <= 7;
--
-- WriteData(X"01", X"0001", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"0030", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"0010", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"0029", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R -150
-- WriteData(X"00", B"00000_01010_1_0_1_1_1_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
--
--
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- while (i <= 1200) loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i = i + 1;
-- end loop;
------------------------------------------------------------------------------------------------
-- Test 8 - Test write while working
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
/trunk/hdl/ctrl/tbench/output_manager_tbench_text.vhd
0,0 → 1,357
-------------------------------------------------------------------------------------------------100
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: ctrl_output_manager_tbench_text.vhd
--| Version: 0.01
--| Tested in: Actel A3PE1500
--|-------------------------------------------------------------------------------------------------
--| Description:
--| This file is only for test purposes.
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.01 | jul-2009 | First release
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
 
 
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity ctrl_tb_simple_clock is
port (
CLK_PERIOD: in time;-- := 20 ns;
CLK_DUTY: in real; -- := 0.5;
active: in boolean;
clk_o: out std_logic
);
end entity ctrl_tb_simple_clock ;
architecture beh of ctrl_tb_simple_clock is
begin
P_main: process
begin
wait until active;
while (active = true) loop
clk_o <= '0';
wait for CLK_PERIOD * (100.0 - clk_Duty)/100.0;
clk_o <= '1';
wait for CLK_PERIOD * clk_Duty/100.0;
end loop;
clk_o <= '0';
wait;
end process;
end architecture beh;
 
 
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
 
 
-- Additional libraries used by Model Under Test.
use ieee.math_real.all;
 
entity stimulus is
generic(
MEM_ADD_WIDTH: integer := 14
);
port(
ACK_I_mem: inout std_logic ;
DAT_I_mem: inout std_logic_vector (15 downto 0);
CYC_I_port: inout std_logic;
STB_I_port: inout std_logic;
WE_I_port: inout std_logic;
RST_I: inout std_logic;
CLK_I: inout std_logic;
load_I: inout std_logic;
enable_I: inout std_logic;
initial_address_I: inout std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
biggest_address_I: inout std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
pause_address_I: inout std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
finish_O: in std_logic;
CYC_O_mem: in std_logic;
STB_O_mem: in std_logic;
ADR_O_mem: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0)
);
 
end stimulus;
 
architecture STIMULATOR of stimulus is
 
-- Control Signal Declarations
signal tb_InitFlag : boolean := false;
signal tb_ParameterInitFlag : boolean := false;
signal i: std_logic;
 
-- Parm Declarations
signal clk_Duty : real := 0.0;
signal clk_Period : time := 0 ns;
 
begin
--------------------------------------------------------------------------------------------------
-- Parm Assignment Block
AssignParms : process
variable clk_Duty_real : real;
variable clk_Period_real : real;
begin
-- Basic parameters
clk_Period_real := 20.0; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
clk_Period <= clk_Period_real * 1 ns;
clk_Duty_real := 50.0;
clk_Duty <= clk_Duty_real;
 
tb_ParameterInitFlag <= true;
wait;
end process;
--------------------------------------------------------------------------------------------------
-- Clocks
-- Clock Instantiation
tb_clk: entity work.tb_simple_clock
port map (
clk_Period => clk_Period,
clk_Duty => clk_Duty,
active => tb_InitFlag,
clk_o => CLK_I
);
--------------------------------------------------------------------------------------------------
-- Clocked Sequences
 
 
--------------------------------------------------------------------------------------------------
-- Sequence: Unclocked
Unclocked : process
begin
wait until tb_ParameterInitFlag;
tb_InitFlag <= true;
load_I <= '0';
RST_I <= '1';
STB_I_port <= '1';
CYC_I_port <= '1';
WE_I_port <= '0';
initial_address_I <= B"01_0000_0000_0000";
biggest_address_I <= B"11_1100_0000_0000";
pause_address_I <= B"00_0000_1000_0000";
enable_I <= '1';
wait for 1.5 * clk_Period;
RST_I <= '0';
wait for 1.0 * clk_Period;
load_I <= '1';
wait for 1.0 * clk_Period;
load_I <= '0';
wait until ADR_O_mem = B"00_0000_1000_0000";
wait for 8.0 * clk_Period;
pause_address_I <= B"01_0000_0000_0000";
wait for 20.0 * clk_Period;
enable_I <= '0';
wait for 8.0 * clk_Period;
enable_I <= '1';
wait until finish_O = '1';
wait for 2.0 * clk_Period;
tb_InitFlag <= false;
wait;
end process;
--------------------------------------------------------------------------------------------------
-- Conditional signals
P_mem: process(STB_O_mem, DAT_I_mem, CYC_O_mem, CLK_I, RST_I,i)
begin
if STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
ACK_I_mem <= '1';
else
ACK_I_mem <= '0';
end if;
if CLK_I'event and CLK_I = '1' then
if RST_I = '1' then
DAT_I_mem <= (others => '0');
elsif STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
DAT_I_mem <= DAT_I_mem + 1;
end if;
end if;
if CLK_I'event and CLK_I = '1' then
if RST_I = '1' then
i <= '0';
elsif STB_O_mem = '1' and CYC_O_mem = '1' then
i <= not(i);
end if;
end if;
end process;
end architecture STIMULATOR;
 
 
 
 
 
 
 
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
library ieee, std;
use ieee.std_logic_1164.all;
 
-- Additional libraries used by Model Under Test.
-- ...
 
entity testbench is
generic (
MEM_ADD_WIDTH: integer := 14
);
end testbench;
 
architecture tbGeneratedCode of testbench is
signal DAT_I_mem: std_logic_vector (15 downto 0);
signal ADR_O_mem: std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
signal CYC_O_mem: std_logic;
signal STB_O_mem: std_logic;
signal ACK_I_mem: std_logic ;
signal WE_O_mem: std_logic;
signal DAT_O_port: std_logic_vector (15 downto 0);
signal CYC_I_port: std_logic;
signal STB_I_port: std_logic;
signal ACK_O_port: std_logic ;
signal WE_I_port: std_logic;
signal RST_I: std_logic;
signal CLK_I: std_logic;
signal load_I: std_logic;
signal enable_I: std_logic;
signal initial_address_I: std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
signal biggest_address_I: std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
signal pause_address_I: std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
signal finish_O: std_logic;
 
begin
--------------------------------------------------------------------------------------------------
-- Instantiation of Stimulus.
U_stimulus_0 : entity work.stimulus
generic map (
MEM_ADD_WIDTH=> MEM_ADD_WIDTH
)
port map (
ACK_I_mem => ACK_I_mem,
DAT_I_mem => DAT_I_mem,
CYC_I_port => CYC_I_port,
STB_I_port => STB_I_port,
WE_I_port => WE_I_port,
RST_I => RST_I,
CLK_I => CLK_I,
load_I => load_I,
enable_I => enable_I,
initial_address_I => initial_address_I,
biggest_address_I => biggest_address_I,
pause_address_I => pause_address_I,
finish_O => finish_O,
CYC_O_mem => CYC_O_mem,
STB_O_mem => STB_O_mem,
ADR_O_mem => ADR_O_mem
);
 
--------------------------------------------------------------------------------------------------
-- Instantiation of Model Under Test.
U_outman_0 : entity work.output_manager --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
generic map (
MEM_ADD_WIDTH=> MEM_ADD_WIDTH
)
port map (
DAT_I_mem => DAT_I_mem,
ADR_O_mem => ADR_O_mem,
CYC_O_mem => CYC_O_mem,
STB_O_mem => STB_O_mem,
ACK_I_mem => ACK_I_mem,
WE_O_mem => WE_O_mem,
DAT_O_port => DAT_O_port,
CYC_I_port => CYC_I_port,
STB_I_port => STB_I_port,
ACK_O_port => ACK_O_port,
WE_I_port => WE_I_port,
RST_I => RST_I,
CLK_I => CLK_I,
load_I => load_I,
enable_I => enable_I,
initial_address_I => initial_address_I,
biggest_address_I => biggest_address_I,
pause_address_I => pause_address_I,
finish_O => finish_O
);
-- U_mem0: entity work.dual_port_memory_wb
-- port map(
-- -- Port A (Higer prioriry)
-- RST_I_a => '0',
-- CLK_I_a => '0',
-- DAT_I_a => (others => '0'),
-- DAT_O_a => open,
-- ADR_I_a => '0',
-- CYC_I_a => '0',
-- STB_I_a => '0',
-- ACK_O_a => open,
-- WE_I_a => '0',
--
-- -- Port B (Lower prioriry)
-- RST_I_b => RST_I,
-- CLK_I_b => CLK_I,
-- DAT_I_b => (others => '0'),
-- DAT_O_b => DAT_I_mem,
-- ADR_I_b => ADR_O_mem,
-- CYC_I_b => CYC_O_mem,
-- STB_I_b => STB_O_mem,
-- ACK_O_b => ACK_I_mem,
-- WE_I_b => WE_O_mem
-- );
end tbGeneratedCode;
----------------------------------------------------------------------------------------------------
trunk/hdl/ctrl/tbench/output_manager_tbench_text.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/ctrl/ctrl.vhd =================================================================== --- trunk/hdl/ctrl/ctrl.vhd (revision 55) +++ trunk/hdl/ctrl/ctrl.vhd (revision 56) @@ -158,7 +158,8 @@ -------------------------------------------------------------------------------------------------- -- Flags - signal running: std_logic; + signal status: std_logic_vector(1 downto 0); + signal next_status1: std_logic; signal stop: std_logic; signal start: std_logic; signal continuous: std_logic; @@ -314,13 +315,12 @@ trigger_channel_O => reg_trigger_channel, error_number_I => "000", -- not implemented yet - error_flag_I => '0', -- not implemented yet adc_conf_O => dat_to_adc, start_O => start, continuous_O => continuous, - running_I => running, + status_I => status, write_in_adc_O => write_in_adc, stop_O => stop ); @@ -360,12 +360,14 @@ trigger_reset <= '1'; trigger_en <= '-'; - running <= '1'; + status(0) <= '1'; + next_status1 <= not(next_status1); -- will be changed every buffer full read strobe_adc <= '0'; -- -- -- -- next_state <= ST_RUNNING; + -- if there is an error manager, influde an if for errors in parameters when ST_RUNNING => @@ -384,11 +386,13 @@ trigger_reset <= '0'; trigger_en <= reg_trigger_en and memwr_in_ack_mem; - running <= '1'; + status(0) <= '1'; + next_status1 <= status(1); strobe_adc <= '0'; -- -- -- -- + -- if there is an error manager, influde an if for errors in running, etc... if outmgr_finish = '1' then if continuous = '1' then next_state <= ST_INIT; @@ -410,7 +414,8 @@ trigger_reset <= '1'; trigger_en <= '-'; - running <= '1'; -- aviod an ack if there is a read/write from port + status(0) <= '1'; -- aviod an ack if there is a read/write from port + next_status1 <= status(1); strobe_adc <= '0'; @@ -429,7 +434,8 @@ trigger_reset <= '1'; trigger_en <= '-'; - running <= '1'; -- aviod an ack if there is a read/write from port + status(0) <= '1'; -- aviod an ack if there is a read/write from port + next_status1 <= status(1); strobe_adc <= '1'; @@ -452,7 +458,8 @@ trigger_reset <= '1'; trigger_en <= '-'; - running <= '0'; + status(0) <= '0'; + next_status1 <= '0'; -- or error when there is an error manager strobe_adc <= '0'; @@ -467,8 +474,11 @@ P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc) begin - if RST_I_daq = '1' or stop = '1' then + if RST_I_daq = '1' then present_state <= ST_IDLE; + status(1) <= '0'; + elsif stop = '1' then + present_state <= ST_IDLE; elsif write_in_adc = '1' then present_state <= ST_ADCWRITE_INIT; elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then @@ -475,6 +485,7 @@ present_state <= ST_INIT; elsif CLK_I_daq'event and CLK_I_daq = '1' then present_state <= next_state; + status(1) <= next_status1; end if;
/trunk/hdl/ctrl/ctrl_pkg.vhd
244,8 → 244,7
adc_conf_O: out std_logic_vector(15 downto 0);
error_number_I: in std_logic_vector (2 downto 0);
running_I: in std_logic;
error_flag_I: in std_logic;
status_I: in std_logic_vector(1 downto 0);
write_in_adc_O: out std_logic;
stop_O: out std_logic
/trunk/hdl/ctrl/address_allocation.vhd
14,6 → 14,7
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.1 | jul-2009 | First testing
--| 0.2 | aug-2009 | New status flag
----------------------------------------------------------------------------------------------------
 
--|
51,7 → 52,7
-- 05 ADCConf RW [ | | | | ADCS|ADSleep| ADPSEn| ADPS08|
-- ADPS07| ADPS06| ADPS05| ADPS04| ADPS03| ADPS02| ADPS01| ADPS00]
--
-- 08 Data_O R [ErrFlag|RunFlag| | | | DCh00| Dat09| Dat08|
-- 08 Data_O R [StatF01|StatF00| | | | DCh00| Dat09| Dat08|
-- Dat07| Dat06| Dat05| Dat04| Dat03| Dat02| Dat01| Dat00]
--
-- 09 Error_O R [ | | | | | | | |
60,7 → 61,11
--
--
-- Description
--
-- StatF01|StatF00|
-- 00 Stoped
-- 01 Running, odd buffer
-- 11 Running, pair buffer
-- 10 Stoped, with error
--==================================================================================================
 
 
121,8 → 126,7
error_number_I: in std_logic_vector (2 downto 0);
--data_channel_I: in std_logic;
running_I: in std_logic;
error_flag_I: in std_logic;
status_I: in std_logic_vector(1 downto 0);
write_in_adc_O: out std_logic;
stop_O: out std_logic
181,7 → 185,7
o_selector(7) <= (others => '0');
o_selector(8) <= error_flag_I & running_I & (13 downto 11 => '0') & data_channel & data;
o_selector(8) <= status_I & (13 downto 11 => '0') & data_channel & data;
o_selector(9) <= (15 downto 3 => '0') & error_number_I;
DAT_O_port <= o_selector(conv_integer(ADR_I_port));
191,7 → 195,7
-- Read asignments
-- if reading registers, do ack, else use internal ack
ACK_O_port <= (CYC_I_port and STB_I_port) and
((not(ADR_I_port(3)) or ACK_I_int or not(running_I)));
((not(ADR_I_port(3)) or ACK_I_int or not(status_I(0))));
--------------------------------------------------------------------------------------------------
/trunk/hdl/daq/daq_pkg.vhd
0,0 → 1,69
----------------------------------------------------------------------------------------------------
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: daq_pkg.vhd
--| Version: 0.01
--| Tested in: Actel A3PE1500
--|-------------------------------------------------------------------------------------------------
--| Description:
--| Adquisition control module.
--| Package for instantiate all adq modules.
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.01 | apr-2009 | First release
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package daq_pkg is
--------------------------------------------------------------------------------------------------
-- Componentes
component daq is
generic (
DEFALT_CONFIG : std_logic_vector := "0000100000000000"
-- bits 8 a 0 clk_pre_scaler
-- bits 9 clk_pre_scaler_ena
-- bit 10 adc sleep
-- bit 11 adc_chip_sel
-- bits 12 a 15 sin usar
-- si clk_pre_scaler_ena = 1
-- frecuencia_adc = frecuencia_wbn / ((clk_pre_scaler+1)*2)
-- sino frecuencia_adc = frecuencia_wbn
);
port(
-- Externo
adc_data_I: in std_logic_vector (9 downto 0);
adc_sel_O: out std_logic;
adc_clk_O: out std_logic;
adc_sleep_O: out std_logic;
adc_chip_sel_O: out std_logic;
 
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (15 downto 0);
ADR_I: in std_logic_vector (1 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
DAT_O: out std_logic_vector (15 downto 0);
ACK_O: out std_logic;
adc_clk_I: std_logic
);
end component daq;
end package daq_pkg;
trunk/hdl/daq/daq_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/memory/memory_pkg.vhd =================================================================== --- trunk/hdl/memory/memory_pkg.vhd (nonexistent) +++ trunk/hdl/memory/memory_pkg.vhd (revision 56) @@ -0,0 +1,63 @@ +-------------------------------------------------------------------------------------------------100 +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| File: memory_pkg.vhd +--| Version: 0.1 +--| Tested in: Actel A3PE1500 +--| Board: RVI Prototype Board + LP Data Conversion Daughter Board +--|------------------------------------------------------------------------------------------------- +--| Description: +--| Memories - Package +--| Package for instantiate Control modules. +--| +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.1 | aug-2009 | First release +---------------------------------------------------------------------------------------------------- +--| Copyright © 2009, Facundo Aguilera (budinero at gmail.com). +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + + + +-- Bloque completo +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.math_real.all; + +package memory_pkg is + -------------------------------------------------------------------------------------------------- + -- Componentes + + component dual_port_memory_wb is + port( + -- Puerto A (Higer prioriry) + RST_I_a: in std_logic; + CLK_I_a: in std_logic; + DAT_I_a: in std_logic_vector (15 downto 0); + DAT_O_a: out std_logic_vector (15 downto 0); + ADR_I_a: in std_logic_vector (13 downto 0); + CYC_I_a: in std_logic; + STB_I_a: in std_logic; + ACK_O_a: out std_logic ; + WE_I_a: in std_logic; + + + -- Puerto B (Lower prioriry) + RST_I_b: in std_logic; + CLK_I_b: in std_logic; + DAT_I_b: in std_logic_vector (15 downto 0); + DAT_O_b: out std_logic_vector (15 downto 0); + ADR_I_b: in std_logic_vector (13 downto 0); + CYC_I_b: in std_logic; + STB_I_b: in std_logic; + ACK_O_b: out std_logic ; + WE_I_b: in std_logic + ); + end component dual_port_memory_wb; + +end package memory_pkg; + \ No newline at end of file
trunk/hdl/memory/memory_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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