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URL https://opencores.org/ocsvn/mpmc8/mpmc8/trunk

Subversion Repositories mpmc8

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  • This comparison shows the changes necessary to convert path 
    /mpmc8
    from Rev 9 to Rev 10
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  •

Rev 9 → Rev 10

/trunk/rtl/mpmc10/mpcm10_cache_wb.sv
373,6 → 373,7
ldcycd1 <= ld.cyc;
always_ff @(posedge wclk)
ldcycd2 <= ldcycd1;
 
always_ff @(posedge wclk)
if (rst) begin
for (n = 0; n < 4; n = n + 1)
/trunk/rtl/mpmc10/mpmc10_addr_gen.sv
39,7 → 39,7
module mpmc10_addr_gen(rst, clk, state, rdy, num_strips, strip_cnt, addr_base, addr);
input rst;
input clk;
input [3:0] state;
input mpmc10_state_t state;
input rdy;
input [5:0] num_strips;
input [5:0] strip_cnt;
50,9 → 50,9
if (rst)
addr <= 32'h1FFFFFFF;
else begin
if (state==mpmc10_pkg::PRESET2)
addr <= addr_base;
else if (state==mpmc10_pkg::READ_DATA1 && rdy && strip_cnt != num_strips)
if (state==PRESET2)
addr <= {addr_base[31:4],4'h0};
else if (state==READ_DATA1 && rdy && strip_cnt != num_strips)
addr[31:4] <= addr[31:4] + 2'd1;
// Increment the address if we had to start a new burst.
// else if (state==WRITE_DATA3 && req_strip_cnt!=num_strips)
/trunk/rtl/mpmc10/mpmc10_app_en_gen.sv
48,7 → 48,7
// is not true, the command must be retried.
always_ff @(posedge clk)
begin
en <= mpmc10_pkg::FALSE;
en <= FALSE;
if (state==WRITE_DATA1)
en <= TRUE;
else if (state==WRITE_DATA2 && !en)
/trunk/rtl/mpmc10/mpmc10_app_wdf_end_gen.sv
38,7 → 38,7
 
module mpmc10_app_wdf_end_gen(clk, state, rdy, strip_cnt, num_strips, wend);
input clk;
input [3:0] state;
input mpmc10_state_t state;
input rdy;
input [5:0] strip_cnt;
input [5:0] num_strips;
48,8 → 48,8
// true.
always_ff @(posedge clk)
begin
wend <= mpmc10_pkg::FALSE;
if (state==mpmc10_pkg::WRITE_DATA0 && rdy)
wend <= FALSE;
if (state==WRITE_DATA3)
wend <= strip_cnt==num_strips;
end
 
/trunk/rtl/mpmc10/mpmc10_app_wdf_wren_gen.sv
46,9 → 46,9
// true. It must be after en is asserted to set the command and address.
always_ff @(posedge clk)
begin
wren <= mpmc10_pkg::FALSE;
wren <= FALSE;
if (state==WRITE_DATA3)// WRITE_DATA0 && rdy)
wren <= mpmc10_pkg::TRUE;
wren <= TRUE;
end
 
endmodule
/trunk/rtl/mpmc10/mpmc10_mask_select.sv
36,10 → 36,11
//
import mpmc10_pkg::*;
 
module mpmc10_mask_select(rst, clk, state, wmask, mask, mask2);
module mpmc10_mask_select(rst, clk, state, we, wmask, mask, mask2);
input rst;
input clk;
input mpmc10_state_t state;
input we;
input [15:0] wmask;
output reg [15:0] mask;
output reg [15:0] mask2;
50,7 → 51,7
mask2 <= 16'h0000;
else begin
if (state==PRESET2)
mask2 <= wmask;
mask2 <= we ? ~wmask : 16'h0000;
// For RMW cycle all bytes are writtten.
else if (state==WRITE_TRAMP1)
mask2 <= 16'h0000;
/trunk/rtl/mpmc10/mpmc10_set_write_mask_wb.sv
46,21 → 46,12
output reg [WID-1:0] mask;
 
always_ff @(posedge clk)
tMask(256,we,sel,adr[4:0],mask);
 
task tMask;
input [7:0] widi;
input wei;
input [WID-1:0] seli;
input [4:0] adri;
output [15:0] masko;
begin
if (state==PRESET1)
if (wei)
masko <= ~seli;
if (we)
mask <= ~sel;
else
masko <= 16'h0000; // read all bytes
mask <= 16'h0000; // read all bytes
end
endtask
 
endmodule
/trunk/rtl/mpmc10/mpmc10_wb.sv
163,6 → 163,7
wire ch0_hit_ne, ch5_hit_ne;
 
always_ff @(posedge mem_ui_clk)
if (app_rd_data_valid)
rd_data_r <= app_rd_data;
always_ff @(posedge mem_ui_clk)
rd_data_valid_r <= app_rd_data_valid;
398,12 → 399,12
ld.bte <= wishbone_pkg::LINEAR;
ld.cti <= wishbone_pkg::CLASSIC;
ld.blen <= 'd0;
ld.cyc <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
ld.cyc <= fifoo.cyc && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
ld.stb <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
ld.we <= 1'b0;
ld.adr <= {app_waddr[31:4],4'h0};
ld.dat <= {app_waddr[31:14],8'h00,rd_data_r}; // modified=false,tag = high order address bits
ld.sel <= {36{1'b1}}; // update all bytes
ld.dat <= rd_data_r;
ld.sel <= {16{1'b1}}; // update all bytes
end
 
reg ch0wack;
697,22 → 698,13
.addr(app_waddr)
);
 
mpmc10_set_write_mask_wb uswm1
(
.clk(mem_ui_clk),
.state(state),
.we(fifoo.we),
.sel(req_fifoo.sel[15:0]),
.adr(adr|{req_strip_cnt[0],4'h0}),
.mask(wmask)
);
 
mpmc10_mask_select unsks1
(
.rst(mem_ui_rst),
.clk(mem_ui_clk),
.state(state),
.wmask(wmask),
.we(fifoo.we),
.wmask(req_fifoo.sel[15:0]),
.mask(app_wdf_mask),
.mask2(mem_wdf_mask2)
);

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