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trunk/doc/MPMC9.docx Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/MPMC9.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/MPMC9.pdf =================================================================== --- trunk/doc/MPMC9.pdf (nonexistent) +++ trunk/doc/MPMC9.pdf (revision 4)

trunk/doc/MPMC9.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/mpcm9_read_cache.sv =================================================================== --- trunk/rtl/mpcm9_read_cache.sv (nonexistent) +++ trunk/rtl/mpcm9_read_cache.sv (revision 4) @@ -0,0 +1,213 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_read_cache(rst, wclk, wr, wadr, wdat, inv, + rclk0, radr0, rdat0, hit0, + rclk1, radr1, rdat1, hit1, + rclk2, radr2, rdat2, hit2, + rclk3, radr3, rdat3, hit3, + rclk4, radr4, rdat4, hit4, + rclk5, radr5, rdat5, hit5, + rclk6, radr6, rdat6, hit6, + rclk7, radr7, rdat7, hit7 +); +input rst; +input wclk; +input wr; +input [31:0] wadr; +input [127:0] wdat; +input inv; +input rclk0; +input [31:0] radr0; +output reg [127:0] rdat0; +output reg hit0; +input rclk1; +input [31:0] radr1; +output reg [127:0] rdat1; +output reg hit1; +input rclk2; +input [31:0] radr2; +output reg [127:0] rdat2; +output reg hit2; +input rclk3; +input [31:0] radr3; +output reg [127:0] rdat3; +output reg hit3; +input rclk4; +input [31:0] radr4; +output reg [127:0] rdat4; +output reg hit4; +input rclk5; +input [31:0] radr5; +output reg [127:0] rdat5; +output reg hit5; +input rclk6; +input [31:0] radr6; +output reg [127:0] rdat6; +output reg hit6; +input rclk7; +input [31:0] radr7; +output reg [127:0] rdat7; +output reg hit7; + +(* ram_style="block" *) +reg [127:0] lines [0:1023]; +(* ram_style="block" *) +reg [27:0] tags [0:1023]; +(* ram_style="distributed" *) +reg [1023:0] vbit; +reg [31:0] radrr0; +reg [31:0] radrr1; +reg [31:0] radrr2; +reg [31:0] radrr3; +reg [31:0] radrr4; +reg [31:0] radrr5; +reg [31:0] radrr6; +reg [31:0] radrr7; +reg [27:0] tago0; +reg [27:0] tago1; +reg [27:0] tago2; +reg [27:0] tago3; +reg [27:0] tago4; +reg [27:0] tago5; +reg [27:0] tago6; +reg [27:0] tago7; +reg vbito0; +reg vbito1; +reg vbito2; +reg vbito3; +reg vbito4; +reg vbito5; +reg vbito6; +reg vbito7; + +always_ff @(posedge rclk0) + radrr0 <= radr0; +always_ff @(posedge rclk1) + radrr1 <= radr1; +always_ff @(posedge rclk2) + radrr2 <= radr2; +always_ff @(posedge rclk3) + radrr3 <= radr3; +always_ff @(posedge rclk4) + radrr4 <= radr4; +always_ff @(posedge rclk5) + radrr5 <= radr5; +always_ff @(posedge rclk6) + radrr6 <= radr6; +always_ff @(posedge rclk7) + radrr7 <= radr7; +always_ff @(posedge wclk) + if (wr) lines[wadr[13:4]] <= wdat; +always_ff @(posedge rclk0) + rdat0 <= lines[radrr0[13:4]]; +always_ff @(posedge rclk1) + rdat1 <= lines[radrr1[13:4]]; +always_ff @(posedge rclk2) + rdat2 <= lines[radrr2[13:4]]; +always_ff @(posedge rclk3) + rdat3 <= lines[radrr3[13:4]]; +always_ff @(posedge rclk4) + rdat4 <= lines[radrr4[13:4]]; +always_ff @(posedge rclk5) + rdat5 <= lines[radrr5[13:4]]; +always_ff @(posedge rclk6) + rdat6 <= lines[radrr6[13:4]]; +always_ff @(posedge rclk7) + rdat7 <= lines[radrr7[13:4]]; +always_ff @(posedge rclk0) + tago0 <= tags[radrr0[13:4]]; +always_ff @(posedge rclk1) + tago1 <= tags[radrr1[13:4]]; +always_ff @(posedge rclk2) + tago2 <= tags[radrr2[13:4]]; +always_ff @(posedge rclk3) + tago3 <= tags[radrr3[13:4]]; +always_ff @(posedge rclk4) + tago4 <= tags[radrr4[13:4]]; +always_ff @(posedge rclk5) + tago5 <= tags[radrr5[13:4]]; +always_ff @(posedge rclk6) + tago6 <= tags[radrr6[13:4]]; +always_ff @(posedge rclk7) + tago7 <= tags[radrr7[13:4]]; +always_ff @(posedge rclk0) + vbito0 <= vbit[radrr0[13:4]]; +always_ff @(posedge rclk1) + vbito1 <= vbit[radrr1[13:4]]; +always_ff @(posedge rclk2) + vbito2 <= vbit[radrr2[13:4]]; +always_ff @(posedge rclk3) + vbito3 <= vbit[radrr3[13:4]]; +always_ff @(posedge rclk4) + vbito4 <= vbit[radrr4[13:4]]; +always_ff @(posedge rclk5) + vbito5 <= vbit[radrr5[13:4]]; +always_ff @(posedge rclk6) + vbito6 <= vbit[radrr6[13:4]]; +always_ff @(posedge rclk7) + vbito7 <= vbit[radrr7[13:4]]; +always_ff @(posedge wclk) + if (wr) tags[wadr[13:4]] <= wadr[31:4]; +always_ff @(posedge wclk) +if (rst) + vbit <= 'b0; +else begin + if (wr) + vbit[wadr[13:4]] <= 1'b1; + else if (inv) + vbit[wadr[13:4]] <= 1'b0; +end +always_comb + hit0 = (tago0==radrr0[31:4]) && (vbito0==1'b1); +always_comb + hit1 = (tago1==radrr1[31:4]) && (vbito1==1'b1); +always_comb + hit2 = (tago2==radrr2[31:4]) && (vbito2==1'b1); +always_comb + hit3 = (tago3==radrr3[31:4]) && (vbito3==1'b1); +always_comb + hit4 = (tago4==radrr4[31:4]) && (vbito4==1'b1); +always_comb + hit5 = (tago5==radrr5[31:4]) && (vbito5==1'b1); +always_comb + hit6 = (tago6==radrr6[31:4]) && (vbito6==1'b1); +always_comb + hit7 = (tago7==radrr7[31:4]) && (vbito7==1'b1); + +endmodule Index: trunk/rtl/mpcm9_spr_read_cache.sv =================================================================== --- trunk/rtl/mpcm9_spr_read_cache.sv (nonexistent) +++ trunk/rtl/mpcm9_spr_read_cache.sv (revision 4) @@ -0,0 +1,90 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_spr_read_cache(rst, wclk, spr_num, wr, wadr, wdat, inv, + rclk, radr, rdat, hit +); +input rst; +input wclk; +input [4:0] spr_num; +input wr; +input [31:0] wadr; +input [127:0] wdat; +input inv; +input rclk; +input [31:0] radr; +output reg [127:0] rdat; +output reg hit; + +(* ram_style="block" *) +reg [127:0] lines [0:511]; +(* ram_style="block" *) +reg [27:0] tags [0:511]; +(* ram_style="distributed" *) +reg [511:0] vbit; +reg [31:0] radrr; +reg [27:0] tago; +reg vbito; +wire [8:0] wadrs = {spr_num,wadr[7:4]}; +wire [8:0] radrs = {spr_num,radrr[7:4]}; + +always_ff @(posedge rclk) + radrr <= radr; +always_ff @(posedge wclk) + if (wr) lines[wadrs] <= wdat; +always_ff @(posedge rclk) + rdat <= lines[radrs]; +always_ff @(posedge rclk) + tago <= tags[radrs]; +always_ff @(posedge rclk) + vbito <= vbit[radrs]; +always_ff @(posedge wclk) + if (wr) tags[wadrs] <= wadr[31:4]; +always_ff @(posedge wclk) +if (rst) + vbit <= 'b0; +else begin + if (wr) + vbit[wadrs] <= 1'b1; + else if (inv) + vbit[wadrs] <= 1'b0; +end +always_comb + hit = (tago==radrr[31:4]) && (vbito==1'b1); + +endmodule Index: trunk/rtl/mpcm9_strm_read_cache.sv =================================================================== --- trunk/rtl/mpcm9_strm_read_cache.sv (nonexistent) +++ trunk/rtl/mpcm9_strm_read_cache.sv (revision 4) @@ -0,0 +1,86 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_strm_read_cache(rst, wclk, wr, wadr, wdat, inv, + rclk, radr, rdat, hit +); +input rst; +input wclk; +input wr; +input [31:0] wadr; +input [127:0] wdat; +input inv; +input rclk; +input [31:0] radr; +output reg [127:0] rdat; +output reg hit; + +(* ram_style="block" *) +reg [127:0] lines [0:255]; +reg [27:0] tags [0:255]; +(* ram_style="distributed" *) +reg [255:0] vbit; +reg [31:0] radrr; +reg [27:0] tago; +reg vbito; + +always_ff @(posedge rclk) + radrr <= radr; +always_ff @(posedge wclk) + if (wr) lines[wadr[11:4]] <= wdat; +always_ff @(posedge rclk) + rdat <= lines[radrr[11:4]]; +always_ff @(posedge rclk) + tago <= tags[radrr[11:4]]; +always_ff @(posedge rclk) + vbito <= vbit[radrr[11:4]]; +always_ff @(posedge wclk) + if (wr) tags[wadr[11:4]] <= wadr[31:4]; +always_ff @(posedge wclk) +if (rst) + vbit <= 'b0; +else begin + if (wr) + vbit[wadr[11:4]] <= 1'b1; + else if (inv) + vbit[wadr[11:4]] <= 1'b0; +end +always_comb + hit = (tago==radrr[31:4]) && (vbito==1'b1); + +endmodule Index: trunk/rtl/mpmc9.sv =================================================================== --- trunk/rtl/mpmc9.sv (nonexistent) +++ trunk/rtl/mpmc9.sv (revision 4) @@ -0,0 +1,1437 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// 5000 LUTs, 28 BRAM +// ============================================================================ +// +//`define RED_SCREEN 1'b1 +import mpmc9_pkg::*; + +module mpmc9( +rst_i, clk100MHz, +clk0, cyc0, stb0, ack0, we0, sel0, adr0, dati0, dato0, +clk1, cs1, cyc1, stb1, ack1, we1, sel1, adr1, dati1, dato1, sr1, cr1, rb1, +clk2, cyc2, stb2, ack2, we2, sel2, adr2, dati2, dato2, +clk3, cyc3, stb3, ack3, we3, sel3, adr3, dati3, dato3, +clk4, cyc4, stb4, ack4, we4, sel4, adr4, dati4, dato4, +clk5, cyc5, stb5, ack5, sel5, adr5, dato5, spriteno, +clk6, cyc6, stb6, ack6, we6, sel6, adr6, dati6, dato6, +clk7, cs7, cyc7, stb7, ack7, we7, sel7, adr7, dati7, dato7, sr7, cr7, rb7, +mem_ui_rst, mem_ui_clk, calib_complete, +rstn, app_addr, app_cmd, app_en, app_wdf_data, app_wdf_end, app_wdf_mask, app_wdf_wren, +app_rd_data, app_rd_data_valid, app_rd_data_end, app_rdy, app_wdf_rdy, +ch, state +); +input rst_i; +input clk100MHz; + +// Channel 0 is reserved for bitmapped graphics display. +// +parameter C0W = 128; // Channel zero width +parameter STREAM0 = TRUE; +parameter STRIPS0 = 6'd63; +input clk0; +input cyc0; +input stb0; +output ack0; +input [C0W/8-1:0] sel0; +input we0; +input [31:0] adr0; +input [C0W-1:0] dati0; +output reg [C0W-1:0] dato0; +reg [C0W-1:0] dato0n; + +// Channel 1 is reserved for cpu1 +parameter C1W = 128; +parameter STREAM1 = FALSE; +parameter STRIPS1 = 6'd0; +input clk1; +input cs1; +input cyc1; +input stb1; +output ack1; +input we1; +input [C1W/8-1:0] sel1; +input [31:0] adr1; +input [C1W-1:0] dati1; +output reg [C1W-1:0] dato1; +input sr1; +input cr1; +output rb1; + +// Channel 2 is reserved for the ethernet controller +parameter C2W = 32; +parameter STREAM2 = FALSE; +parameter STRIPS2 = 6'd31; +input clk2; +input cyc2; +input stb2; +output ack2; +input we2; +input [C2W/8-1:0] sel2; +input [31:0] adr2; +input [C2W-1:0] dati2; +output reg [C2W-1:0] dato2; + +// Channel 3 is reserved for the audio controller +parameter C3W = 16; +parameter STREAM3 = TRUE; +parameter STRIPS3 = 6'd63; +input clk3; +input cyc3; +input stb3; +output ack3; +input we3; +input [C3W/8-1:0] sel3; +input [31:0] adr3; +input [C3W-1:0] dati3; +output reg [C3W-1:0] dato3; + +// Channel 4 is reserved for the graphics controller +parameter C4W = 128; +parameter STREAM4 = FALSE; +parameter STRIPS4 = 6'd0; +input clk4; +input cyc4; +input stb4; +output ack4; +input we4; +input [C4W/8-1:0] sel4; +input [31:0] adr4; +input [C4W-1:0] dati4; +output reg [C4W-1:0] dato4; + +// Channel 5 is reserved for sprite DMA, which is read-only +parameter C5W = 64; +parameter STREAM5 = TRUE; +parameter STRIPS5 = 6'd15; +input clk5; +input cyc5; +input stb5; +output ack5; +input [C5W/8-1:0] sel5; +input [5:0] spriteno; +input [31:0] adr5; +output reg [C5W-1:0] dato5; + +// Channel 6 is reserved for the SD/MMC controller +parameter C6W = 128; +parameter STREAM6 = FALSE; +parameter STRIPS6 = 6'd63; +input clk6; +input cyc6; +input stb6; +output ack6; +input we6; +input [C6W/8-1:0] sel6; +input [31:0] adr6; +input [C6W-1:0] dati6; +output reg [C6W-1:0] dato6; + +// Channel 7 is reserved for the cpu +parameter C7W = 16; +parameter C7R = 16; +parameter STREAM7 = FALSE; +parameter STRIPS7 = 6'd3; +input clk7; +input cs7; +input cyc7; +input stb7; +output ack7; +input we7; +input [C7W/8-1:0] sel7; +input [31:0] adr7; +input [C7W-1:0] dati7; +output reg [C7R-1:0] dato7; +input sr7; +input cr7; +output rb7; + +// MIG interface signals +input mem_ui_rst; +input mem_ui_clk; +input calib_complete; +output rstn; +output [AMSB:0] app_addr; +output [2:0] app_cmd; +output reg app_en; +output reg [127:0] app_wdf_data; +output [15:0] app_wdf_mask; +output app_wdf_end; +output app_wdf_wren; +input [127:0] app_rd_data; +input app_rd_data_valid; +input app_rd_data_end; +input app_rdy; +input app_wdf_rdy; + +// Debugging +output reg [3:0] ch; +output [3:0] state; + +integer n; +integer n1; +integer n2; + +wire [31:0] app_waddr; +wire [31:0] adr; +wire [127:0] dat128; +reg [15:0] wmask; +reg [127:0] rmw_data; + +reg [3:0] nch; +reg [5:0] sreg; +reg rstn; +reg [5:0] nack_to = 6'd0; +reg [5:0] spriteno_r; + +wire cs0 = cyc0 && stb0 && adr0[31:29]==3'h0; +wire ics1 = cyc1 & stb1 & cs1; +wire cs2 = cyc2 && stb2 && adr2[31:29]==3'h0; +wire cs3 = cyc3 && stb3 && adr3[31:29]==3'h0; +wire cs4 = cyc4 && stb4 && adr4[31:29]==3'h0; +wire cs5 = cyc5 && stb5 && adr5[31:29]==3'h0; +wire cs6 = cyc6 && stb6 && adr6[31:29]==3'h0; +wire ics7 = cyc7 & stb7 & cs7; + +reg acki0,acki1,acki2,acki3,acki4,acki5,acki6,acki7; +wire do_wr; +wire do_wr0; +wire do_wr1; +wire do_wr2; +wire do_wr3; +wire do_wr4; +wire do_wr5; +wire do_wr6; +wire do_wr7; + +reg [5:0] num_strips; +wire [5:0] req_strip_cnt; // count of requested strips +wire [5:0] resp_strip_cnt; // count of response strips +reg [AMSB:0] app_addr; + +reg [15:0] refcnt; // refreshing not used, its automnatic +reg refreq; +wire refack; +wire [15:0] tocnt; // memory access timeout counter + +reg [3:0] resv_ch [0:NAR-1]; +reg [31:0] resv_adr [0:NAR-1]; + +// Cross clock domain signals +wire cs0xx; +wire we0xx; +wire [C0W/8-1:0] sel0xx; +wire [31:0] adr0xx; +wire [C0W-1:0] dati0xx; + +wire cs1xx; +wire we1xx; +wire [15:0] sel1xx; +wire [31:0] adr1xx; +wire [127:0] dati1xx; +wire sr1xx; +wire cr1xx; + +wire cs2xx; +wire we2xx; +wire [C2W/8-1:0] sel2xx; +wire [31:0] adr2xx; +wire [C2W-1:0] dati2xx; + +wire cs3xx; +wire we3xx; +wire [C3W/8-1:0] sel3xx; +wire [31:0] adr3xx; +wire [C3W-1:0] dati3xx; + +wire cs4xx; +wire we4xx; +wire [C4W/8-1:0] sel4xx; +wire [31:0] adr4xx; +wire [C4W-1:0] dati4xx; + +wire cs5xx; +wire we5xx; +wire [C5W/8-1:0] sel5xx; +wire [31:0] adr5xx; +wire [C5W-1:0] dati5xx; +wire [5:0] spritenoxx; + +wire cs6xx; +wire we6xx; +wire [C6W/8-1:0] sel6xx; +wire [31:0] adr6xx; +wire [C6W-1:0] dati6xx; + +wire cs7xx; +wire we7xx; +wire [C7W/8-1:0] sel7xx; +wire [31:0] adr7xx; +wire [C7W-1:0] dati7xx; +wire sr7xx; +wire cr7xx; + +reg [7:0] to_cnt; + +// Terminate the ack signal as soon as the circuit select goes away. +assign ack0 = acki0 & cs0; +assign ack1 = acki1 & ics1; +assign ack2 = acki2 & cs2; +assign ack3 = acki3 & cs3; +assign ack4 = acki4 & cs4; +assign ack5 = acki5 & cs5; +assign ack6 = acki6 & cs6; +assign ack7 = acki7 & ics7; + +wire pre_ack0; +wire pre_ack1; +wire pre_ack2; +wire pre_ack3; +wire pre_ack4; +wire pre_ack5; +wire pre_ack6; +wire pre_ack7; + +// Used to transition state to IDLE at end of access +// We dont transition to idle until a negative edge is seen on ack +wire ne_acki0; +wire ne_acki1; +wire ne_acki2; +wire ne_acki3; +wire ne_acki4; +wire ne_acki5; +wire ne_acki6; +wire ne_acki7; +wire pe_acki0; +wire pe_acki1; +wire pe_acki2; +wire pe_acki3; +wire pe_acki4; +wire pe_acki5; +wire pe_acki6; +wire pe_acki7; +edge_det ed_acki0 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki0), .pe(pe_acki0), .ne(ne_acki0), .ee()); +edge_det ed_acki1 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki1), .pe(pe_acki1), .ne(ne_acki1), .ee()); +edge_det ed_acki2 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki2), .pe(pe_acki2), .ne(ne_acki2), .ee()); +edge_det ed_acki3 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki3), .pe(pe_acki3), .ne(ne_acki3), .ee()); +edge_det ed_acki4 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki4), .pe(pe_acki4), .ne(ne_acki4), .ee()); +edge_det ed_acki5 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki5), .pe(pe_acki5), .ne(ne_acki5), .ee()); +edge_det ed_acki6 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki6), .pe(pe_acki6), .ne(ne_acki6), .ee()); +edge_det ed_acki7 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki7), .pe(pe_acki7), .ne(ne_acki7), .ee()); + +wire [127:0] ch0_rdat_c, ch0_rdat_s, ch0_rdat; +wire [127:0] ch1_rdat, ch1_rdat_c, ch1_rdat_s; +wire [127:0] ch2_rdat, ch2_rdat_c, ch2_rdat_s; +wire [127:0] ch3_rdat, ch3_rdat_c, ch3_rdat_s; +wire [127:0] ch4_rdat, ch4_rdat_c, ch4_rdat_s; +wire [127:0] ch5_rdat, ch5_rdat_c, ch5_rdat_s; +wire [127:0] ch6_rdat, ch6_rdat_c, ch6_rdat_s; +wire [127:0] ch7_rdat, ch7_rdat_c, ch7_rdat_s; +reg [127:0] ch0_rdatr; +reg [127:0] ch1_rdatr; +reg [127:0] ch2_rdatr; +reg [127:0] ch3_rdatr; +reg [127:0] ch4_rdatr; +reg [127:0] ch5_rdatr; +reg [127:0] ch6_rdatr; +reg [127:0] ch7_rdatr; +wire ch0_hit_c, ch0_hit_s; +wire ch1_hit_c, ch1_hit_s; +wire ch2_hit_c, ch2_hit_s; +wire ch3_hit_c, ch3_hit_s; +wire ch4_hit_c, ch4_hit_s; +wire ch5_hit_c, ch5_hit_s; +wire ch6_hit_c, ch6_hit_s; +wire ch7_hit_c, ch7_hit_s; +wire ch0_hit, ch1_hit, ch2_hit, ch3_hit; +wire ch4_hit, ch5_hit, ch6_hit, ch7_hit; + +mpmc9_read_cache rc0 ( + .rst(rst_i), + .wclk(mem_ui_clk), + .wr(app_rd_data_valid && !( + (STREAM0 && ch==4'd0) || + (STREAM1 && ch==4'd1) || + (STREAM2 && ch==4'd2) || + (STREAM3 && ch==4'd3) || + (STREAM4 && ch==4'd4) || + (STREAM5 && ch==4'd5) || + (STREAM6 && ch==4'd6) || + (STREAM7 && ch==4'd7) + )), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(state==WRITE_DATA0), + .rclk0(STREAM0 ? 1'b0 : clk0), + .radr0(STREAM0 ? 32'h0 : {adr0xx[31:4],4'h0}), + .rdat0(ch0_rdat_c), + .hit0(ch0_hit_c), + .rclk1(STREAM1 ? 1'b0 : mem_ui_clk), + .radr1(STREAM1 ? 32'h0 : {adr1xx[31:4],4'h0}), + .rdat1(ch1_rdat_c), + .hit1(ch1_hit_c), + .rclk2(STREAM2 ? 1'b0 : mem_ui_clk), + .radr2(STREAM2 ? 32'h0 : {adr2xx[31:4],4'h0}), + .rdat2(ch2_rdat_c), + .hit2(ch2_hit_c), + .rclk3(STREAM3 ? 1'b0 : mem_ui_clk), + .radr3(STREAM3 ? 32'h0 : {adr3xx[31:4],4'h0}), + .rdat3(ch3_rdat_c), + .hit3(ch3_hit_c), + .rclk4(STREAM4 ? 1'b0 : mem_ui_clk), + .radr4(STREAM4 ? 32'h0 : {adr4xx[31:4],4'h0}), + .rdat4(ch4_rdat_c), + .hit4(ch4_hit_c), + .rclk5(STREAM5 ? 1'b0 : mem_ui_clk), + .radr5(STREAM5 ? 32'h0 : {adr5xx[31:4],4'h0}), + .rdat5(ch5_rdat_c), + .hit5(ch5_hit_c), + .rclk6(STREAM6 ? 1'b0 : mem_ui_clk), + .radr6(STREAM6 ? 32'h0 : {adr6xx[31:4],4'h0}), + .rdat6(ch6_rdat_c), + .hit6(ch6_hit_c), + .rclk7(STREAM7 ? 1'b0 : mem_ui_clk), + .radr7(STREAM7 ? 32'h0 : {adr7xx[31:4],4'h0}), + .rdat7(ch7_rdat_c), + .hit7(ch7_hit_c) +); + +mpmc9_strm_read_cache ustrm0 +( + .rst(rst_i), + .wclk(mem_ui_clk), + .wr(ch==4'd0 && app_rd_data_valid), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(1'b0), + .rclk(mem_ui_clk), + .radr({adr0xx[31:4],4'h0}), + .rdat(ch0_rdat_s), + .hit(ch0_hit_s) +); + +mpmc9_strm_read_cache ustrm1 +( + .rst(rst_i), + .wclk(mem_ui_clk), + .wr(ch==4'd1 && app_rd_data_valid), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(1'b0), + .rclk(mem_ui_clk), + .radr({adr1xx[31:4],4'h0}), + .rdat(ch1_rdat_s), + .hit(ch1_hit_s) +); + +mpmc9_strm_read_cache ustrm2 +( + .rst(rst_i), + .wclk(mem_ui_clk), + .wr(ch==4'd2 && app_rd_data_valid), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(1'b0), + .rclk(mem_ui_clk), + .radr({adr2xx[31:4],4'h0}), + .rdat(ch2_rdat_s), + .hit(ch2_hit_s) +); + +mpmc9_strm_read_cache ustrm3 +( + .rst(rst_i), + .wclk(mem_ui_clk), + .wr(ch==4'd3 && app_rd_data_valid), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(1'b0), + .rclk(mem_ui_clk), + .radr({adr3xx[31:4],4'h0}), + .rdat(ch3_rdat_s), + .hit(ch3_hit_s) +); + +mpmc9_strm_read_cache ustrm4 +( + .rst(rst_i), + .wclk(mem_ui_clk), + .wr(ch==4'd4 && app_rd_data_valid), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(1'b0), + .rclk(mem_ui_clk), + .radr({adr4xx[31:4],4'h0}), + .rdat(ch4_rdat_s), + .hit(ch4_hit_s) +); + +mpmc9_spr_read_cache usprrc5 +( + .rst(rst_i), + .wclk(mem_ui_clk), + .spr_num(spriteno[4:0]), + .wr(ch==4'd5 && app_rd_data_valid), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(1'b0), + .rclk(mem_ui_clk), + .radr({adr5xx[31:4],4'h0}), + .rdat(ch5_rdat_s), + .hit(ch5_hit_s) +); + +mpmc9_strm_read_cache ustrm6 +( + .rst(rst_i), + .wclk(mem_ui_clk), + .wr(ch==4'd6 && app_rd_data_valid), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(1'b0), + .rclk(mem_ui_clk), + .radr({adr6xx[31:4],4'h0}), + .rdat(ch6_rdat_s), + .hit(ch6_hit_s) +); + +mpmc9_strm_read_cache ustrm7 +( + .rst(rst_i), + .wclk(mem_ui_clk), + .wr(ch==4'd7 && app_rd_data_valid), + .wadr({app_waddr[31:4],4'h0}), + .wdat(app_rd_data), + .inv(1'b0), + .rclk(mem_ui_clk), + .radr({adr7xx[31:4],4'h0}), + .rdat(ch7_rdat_s), + .hit(ch7_hit_s) +); + +// These muxes will be reduced to wires. +assign ch0_hit = STREAM0 ? ch0_hit_s : ch0_hit_c; +assign ch0_rdat = STREAM0 ? ch0_rdat_s : ch0_rdat_c; +assign ch1_hit = STREAM1 ? ch1_hit_s : ch1_hit_c; +assign ch1_rdat = STREAM1 ? ch1_rdat_s : ch1_rdat_c; +assign ch2_hit = STREAM2 ? ch2_hit_s : ch2_hit_c; +assign ch2_rdat = STREAM2 ? ch2_rdat_s : ch2_rdat_c; +assign ch3_hit = STREAM3 ? ch3_hit_s : ch3_hit_c; +assign ch3_rdat = STREAM3 ? ch3_rdat_s : ch3_rdat_c; +assign ch4_hit = STREAM4 ? ch4_hit_s : ch4_hit_c; +assign ch4_rdat = STREAM4 ? ch4_rdat_s : ch4_rdat_c; +assign ch5_hit = STREAM5 ? ch5_hit_s : ch5_hit_c; +assign ch5_rdat = STREAM5 ? ch5_rdat_s : ch5_rdat_c; +assign ch6_hit = STREAM6 ? ch6_hit_s : ch6_hit_c; +assign ch6_rdat = STREAM6 ? ch6_rdat_s : ch6_rdat_c; +assign ch7_hit = STREAM7 ? ch7_hit_s : ch7_hit_c; +assign ch7_rdat = STREAM7 ? ch7_rdat_s : ch7_rdat_c; + +// Register signals onto mem_ui_clk domain +mpmc9_sync #(.W(C0W)) usyn0 +( + .clk(mem_ui_clk), + .cs_i(cs0), + .we_i(we0), + .sel_i(sel0), + .adr_i(adr0), + .dati_i(dati0), + .sr_i(1'b0), + .cr_i(1'b0), + .cs_o(cs0xx), + .we_o(we0xx), + .sel_o(sel0xx), + .adr_o(adr0xx), + .dati_o(dati0xx), + .sr_o(), + .cr_o() +); + +mpmc9_sync #(.W(C1W)) usyn1 +( + .clk(mem_ui_clk), + .cs_i(ics1), + .we_i(we1), + .sel_i(sel1), + .adr_i(adr1), + .dati_i(dati1), + .sr_i(sr1), + .cr_i(cr1), + .cs_o(cs1xx), + .we_o(we1xx), + .sel_o(sel1xx), + .adr_o(adr1xx), + .dati_o(dati1xx), + .sr_o(sr1xx), + .cr_o(cr1xx) +); + +mpmc9_sync #(.W(C2W)) usyn2 +( + .clk(mem_ui_clk), + .cs_i(cs2), + .we_i(we2), + .sel_i(sel2), + .adr_i(adr2), + .dati_i(dati2), + .sr_i(1'b0), + .cr_i(1'b0), + .cs_o(cs2xx), + .we_o(we2xx), + .sel_o(sel2xx), + .adr_o(adr2xx), + .dati_o(dati2xx), + .sr_o(), + .cr_o() +); + +mpmc9_sync #(.W(C3W)) usyn3 +( + .clk(mem_ui_clk), + .cs_i(cs3), + .we_i(we3), + .sel_i(sel3), + .adr_i(adr3), + .dati_i(dati3), + .sr_i(1'b0), + .cr_i(1'b0), + .cs_o(cs3xx), + .we_o(we3xx), + .sel_o(sel3xx), + .adr_o(adr3xx), + .dati_o(dati3xx), + .sr_o(), + .cr_o() +); + +mpmc9_sync #(.W(C4W)) usyn4 +( + .clk(mem_ui_clk), + .cs_i(cs4), + .we_i(we4), + .sel_i(sel4), + .adr_i(adr4), + .dati_i(dati4), + .sr_i(1'b0), + .cr_i(1'b0), + .cs_o(cs4xx), + .we_o(we4xx), + .sel_o(sel4xx), + .adr_o(adr4xx), + .dati_o(dati4xx), + .sr_o(), + .cr_o() +); + +mpmc9_sync #(.W(C5W)) usyn5 +( + .clk(mem_ui_clk), + .cs_i(cs5), + .we_i(1'b0), + .sel_i(sel5), + .adr_i(adr5), + .dati_i(dati5), + .sr_i(1'b0), + .cr_i(1'b0), + .cs_o(cs5xx), + .we_o(), + .sel_o(sel5xx), + .adr_o(adr5xx), + .dati_o(dati5xx), + .sr_o(), + .cr_o() +); + +mpmc9_sync #(.W(C6W)) usyn6 +( + .clk(mem_ui_clk), + .cs_i(cs6), + .we_i(we6), + .sel_i(sel6), + .adr_i(adr6), + .dati_i(dati6), + .sr_i(1'b0), + .cr_i(1'b0), + .cs_o(cs6xx), + .we_o(we6xx), + .sel_o(sel6xx), + .adr_o(adr6xx), + .dati_o(dati6xx), + .sr_o(), + .cr_o() +); + +mpmc9_sync #(.W(C7R)) usyn7 +( + .clk(mem_ui_clk), + .cs_i(cs7), + .we_i(we7), + .sel_i(sel7), + .adr_i(adr7), + .dati_i(dati7), + .sr_i(sr7), + .cr_i(cr7), + .cs_o(cs7xx), + .we_o(we7xx), + .sel_o(sel7xx), + .adr_o(adr7xx), + .dati_o(dati7xx), + .sr_o(sr7xx), + .cr_o(cr7xx) +); + +reg [19:0] rst_ctr; +always @(posedge clk100MHz) +if (rst_i) + rst_ctr <= 24'd0; +else begin + if (!rst_ctr[15]) + rst_ctr <= rst_ctr + 2'd1; + rstn <= rst_ctr[15]; +end + +reg toggle; // CPU1 / CPU0 priority toggle +reg toggle_sr; +reg [19:0] resv_to_cnt; +reg sr1x,sr7x; +reg [127:0] dati128; + +// Detect cache hits on read caches +// For the sprite channel, reading the 64-bits of a strip not beginning at +// a 64-byte aligned paragraph only checks for the 64 bit address adr[5:3]. +// It's assumed that a 4x128-bit strips were read the by the previous access. +// It's also assumed that the strip address won't match because there's more +// than one sprite and sprite accesses are essentially random. +wire ch0_taghit = cs0xx && !we0xx && ch0_hit; +wire ch1_taghit = ics1 && !we1xx && cs1xx && ch1_hit; +wire ch2_taghit = !we2xx && cs2xx && ch2_hit; +wire ch3_taghit = !we3xx && cs3xx && ch3_hit; +wire ch4_taghit = !we4xx && cs4xx && ch4_hit; +wire ch5_taghit = cs5xx && ch5_hit; +wire ch6_taghit = !we6xx && cs6xx && ch6_hit; +wire ch7_taghit = cs7xx && !we7xx && ch7_hit; + +always_comb +begin + sr1x = FALSE; + if (ch1_taghit) + sr1x = sr1xx; +end +always_comb +begin + sr7x = FALSE; + if (ch7_taghit) + sr7x = sr7xx; +end + +// Select the channel +mpmc9_ch_prioritize uchp1 +( + .clk(mem_ui_clk), + .state(state), + .cs0(cs0xx), + .cs1(cs1xx), + .cs2(cs2xx), + .cs3(cs3xx), + .cs4(cs4xx), + .cs5(cs5xx), + .cs6(cs6xx), + .cs7(cs7xx), + .we0(we0xx), + .we1(we1xx), + .we2(we2xx), + .we3(we3xx), + .we4(we4xx), + .we5(1'b0), + .we6(we6xx), + .we7(we7xx), + .ch0_taghit(ch0_taghit), + .ch1_taghit(ch1_taghit), + .ch2_taghit(ch2_taghit), + .ch3_taghit(ch3_taghit), + .ch4_taghit(ch4_taghit), + .ch5_taghit(ch5_taghit), + .ch6_taghit(ch6_taghit), + .ch7_taghit(ch7_taghit), + .ch(nch) +); + + +always_ff @(posedge mem_ui_clk) +if (state==IDLE || (state==PRESET1 && do_wr)) + ch <= nch; + +mpmc9_addr_select +uadrs1 +( + .rst(mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(nch), + .adr0(adr0xx), + .adr1(adr1xx), + .adr2(adr2xx), + .adr3(adr3xx), + .adr4(adr4xx), + .adr5(adr5xx), + .adr6(adr6xx), + .adr7(adr7xx), + .adr(adr) +); + +wire [2:0] app_addr3; + +mpmc9_addr_gen uagen1 +( + .rst(mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .rdy(app_rdy), + .num_strips(num_strips), + .strip_cnt(req_strip_cnt), + .addr_base(adr), + .addr({app_addr3,app_addr}) +); + +mpmc9_waddr_gen uwadgen1 +( + .rst(mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .valid(app_rd_data_valid), + .num_strips(num_strips), + .strip_cnt(resp_strip_cnt), + .addr_base(adr), + .addr(app_waddr) +); + +// Setting the write mask +reg [15:0] wmask0; +reg [15:0] wmask1; +reg [15:0] wmask2; +reg [15:0] wmask3; +reg [15:0] wmask4; +reg [15:0] wmask5; +reg [15:0] wmask6; +reg [15:0] wmask7; + +mpmc9_set_write_mask +#( + .C0W(C0W), + .C1W(C1W), + .C2W(C2W), + .C3W(C3W), + .C4W(C4W), + .C5W(C5W), + .C6W(C6W), + .C7W(C7W) +) +uswm1 +( + .clk(mem_ui_clk), + .state(state), + .we0(we0xx), + .we1(we1xx), + .we2(we2xx), + .we3(we3xx), + .we4(we4xx), + .we5(1'b0), + .we6(we6xx), + .we7(we7xx), + .sel0(sel0xx), + .sel1(sel1xx), + .sel2(sel2xx), + .sel3(sel3xx), + .sel4(sel4xx), + .sel5(sel5xx), + .sel6(sel6xx), + .sel7(sel7xx), + .adr0(adr0xx), + .adr1(adr1xx), + .adr2(adr2xx), + .adr3(adr3xx), + .adr4(adr4xx), + .adr5(adr5xx), + .adr6(adr6xx), + .adr7(adr7xx), + .mask0(wmask0), + .mask1(wmask1), + .mask2(wmask2), + .mask3(wmask3), + .mask4(wmask4), + .mask5(wmask5), + .mask6(wmask6), + .mask7(wmask7) +); + +// Setting the write data +mpmc9_data_select +#( + .C0W(C0W), + .C1W(C1W), + .C2W(C2W), + .C3W(C3W), + .C4W(C4W), + .C5W(C5W), + .C6W(C6W), + .C7W(C7W) +) +uds1 +( + .clk(mem_ui_clk), + .state(state), + .ch(nch), + .dati0(dati0xx), + .dati1(dati1xx), + .dati2(dati2xx), + .dati3(dati3xx), + .dati4(dati4xx), + .dati5('d0), + .dati6(dati6xx), + .dati7(dati7xx), + .dato(dat128) +); + +// Setting the data value. Unlike reads there is only a single strip involved. +// Force unselected byte lanes to $FF +wire [15:0] mem_wdf_mask2; +reg [127:0] dat128x; +genvar g; +generate begin + for (g = 0; g < 16; g = g + 1) + always_comb + if (mem_wdf_mask2[g]) + dat128x[g*8+7:g*8] = 8'hFF; + else + dat128x[g*8+7:g*8] = dat128[g*8+7:g*8]; +end +endgenerate + +always_ff @(posedge mem_ui_clk) +if (mem_ui_rst) + app_wdf_data <= 128'd0; +else begin + if (state==PRESET2) + app_wdf_data <= dat128x; + else if (state==WRITE_TRAMP1) + app_wdf_data <= rmw_data; +end + +generate begin +for (g = 0; g < 16; g = g + 1) begin + always_ff @(posedge mem_ui_clk) + begin + if (state==WRITE_TRAMP) begin + if (app_wdf_mask[g]) + rmw_data[g*8+7:g*8] <= app_wdf_data[g*8+7:g*8]; + else + rmw_data[g*8+7:g*8] <= app_rd_data[g*8+7:g*8]; + end + end +end +end +endgenerate + +always_ff @(posedge mem_ui_clk) +if (state==IDLE) + spriteno_r <= spritenoxx; + +// Setting burst length +mpmc9_set_num_strips +#( + .S0(STRIPS0), + .S1(STRIPS1), + .S2(STRIPS2), + .S3(STRIPS3), + .S4(STRIPS4), + .S5(STRIPS5), + .S6(STRIPS6), + .S7(STRIPS7) +) +usns1 +( + .clk(mem_ui_clk), + .state(state), + .ch(nch), + .we0(we0xx), + .we1(we1xx), + .we2(we2xx), + .we3(we3xx), + .we4(we4xx), + .we5(we5xx), + .we6(we6xx), + .we7(we7xx), + .num_strips(num_strips) +); + +// Setting the data mask. Values are enabled when the data mask is zero. +mpmc9_mask_select umsks1 +( + .rst(mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .wmask0(wmask0), + .wmask1(wmask1), + .wmask2(wmask2), + .wmask3(wmask3), + .wmask4(wmask4), + .wmask5(wmask5), + .wmask6(wmask6), + .wmask7(wmask7), + .mask(app_wdf_mask), + .mask2(mem_wdf_mask2) +); + +// Setting output data. Force output data to zero when not selected to allow +// wire-oring the data. +mpmc9_data_output udo1 +( + .clk0(clk0), .cs0(cs0), .adr0(adr0), .ch0_rdat(ch0_rdat), .dato0(dato0), + .clk1(clk1), .cs1(cs1), .adr1(adr1), .ch1_rdat(ch1_rdat), .dato1(dato1), + .clk2(clk2), .cs2(cs2), .adr2(adr2), .ch2_rdat(ch2_rdat), .dato2(dato2), + .clk3(clk3), .cs3(cs3), .adr3(adr3), .ch3_rdat(ch3_rdat), .dato3(dato3), + .clk4(clk4), .cs4(cs4), .adr4(adr4), .ch4_rdat(ch4_rdat), .dato4(dato4), + .clk5(clk5), .cs5(cs5), .adr5(adr5), .ch5_rdat(ch5_rdat), .dato5(dato5), + .clk6(clk6), .cs6(cs6), .adr6(adr6), .ch6_rdat(ch6_rdat), .dato6(dato6), + .clk7(clk7), .cs7(cs7), .adr7(adr7), .ch7_rdat(ch7_rdat), .dato7(dato7) +); + +mpmc9_ack_gen #(.N(0)) uackg0 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .cs(cs0), + .adr(adr0xx), + .cr(1'b0), + .wr(do_wr), + .to(tocnt[9]), + .taghit(ch0_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .ack(acki0), + .pre_ack(pre_ack0) +); + +mpmc9_ack_gen #(.N(1)) uackg1 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .cs(cs1&ics1), + .adr(adr1xx), + .cr(cr1xx), + .wr(do_wr), + .to(tocnt[9]), + .taghit(ch1_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .ack(acki1), + .pre_ack(pre_ack1) +); + +mpmc9_ack_gen #(.N(2)) uackg2 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .cs(cs2), + .adr(adr2xx), + .cr(1'b0), + .wr(do_wr), + .to(tocnt[9]), + .taghit(ch2_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .ack(acki2), + .pre_ack(pre_ack2) +); + +mpmc9_ack_gen #(.N(3)) uackg3 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .cs(cs3), + .adr(adr3xx), + .cr(1'b0), + .wr(do_wr), + .to(tocnt[9]), + .taghit(ch3_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .ack(acki3), + .pre_ack(pre_ack3) +); + +mpmc9_ack_gen #(.N(4)) uackg4 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .cs(cs4), + .adr(adr4xx), + .cr(1'b0), + .wr(do_wr), + .to(tocnt[9]), + .taghit(ch4_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .ack(acki4), + .pre_ack(pre_ack4) +); + +mpmc9_ack_gen #(.N(5)) uackg5 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .cs(cs5), + .adr(adr5xx), + .cr(1'b0), + .wr(do_wr), + .to(tocnt[9]), + .taghit(ch5_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .ack(acki5), + .pre_ack(pre_ack5) +); + +mpmc9_ack_gen #(.N(6)) uackg6 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .cs(cs6), + .adr(adr6xx), + .cr(1'b0), + .wr(do_wr), + .to(tocnt[9]), + .taghit(ch6_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .ack(acki6), + .pre_ack(pre_ack6) +); + +mpmc9_ack_gen #(.N(7)) uackg7 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .ch(ch), + .cs(ics7), + .adr(adr7xx), + .cr(cr7xx), + .wr(do_wr), + .to(tocnt[9]), + .taghit(ch7_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .ack(acki7), + .pre_ack(pre_ack7) +); + +wire ne_data_valid; +edge_det ued1 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(app_rd_data_valid), .pe(), .ne(ne_data_valid), .ee()); + +mpmc9_state_machine ustmac1 +( + .rst(rst_i|mem_ui_rst), + .clk(mem_ui_clk), + .ch(nch), + .acki0(acki0), + .acki1(acki1), + .acki2(acki2), + .acki3(acki3), + .acki4(acki4), + .acki5(acki5), + .acki6(acki6), + .acki7(acki7), + .ch0_taghit(ch0_taghit), + .ch1_taghit(ch1_taghit), + .ch2_taghit(ch2_taghit), + .ch3_taghit(ch3_taghit), + .ch4_taghit(ch4_taghit), + .ch5_taghit(ch5_taghit), + .ch6_taghit(ch6_taghit), + .ch7_taghit(ch7_taghit), + .wdf_rdy(app_wdf_rdy), + .rdy(app_rdy), + .do_wr(do_wr), + .rd_data_valid(app_rd_data_valid), + .num_strips(num_strips), + .req_strip_cnt(req_strip_cnt), + .resp_strip_cnt(resp_strip_cnt), + .to(tocnt[9]), + .cr1(cr1xx), + .cr7(cr7xx), + .adr1(adr1xx), + .adr7(adr7xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .state(state) +); + + +wire [3:0] prev_state; + +mpmc9_to_cnt utoc1 +( + .clk(mem_ui_clk), + .state(state), + .prev_state(prev_state), + .to_cnt(tocnt) +); + +mpmc9_prev_state upst1 +( + .clk(mem_ui_clk), + .state(state), + .prev_state(prev_state) +); + +mpmc9_app_en_gen ueng1 +( + .clk(mem_ui_clk), + .state(state), + .rdy(app_rdy), + .strip_cnt(req_strip_cnt), + .num_strips(num_strips), + .en(app_en) +); + +mpmc9_app_cmd_gen ucg1 +( + .clk(mem_ui_clk), + .state(state), + .cmd(app_cmd) +); + +mpmc9_app_wdf_wren_gen uwreng1 +( + .clk(mem_ui_clk), + .state(state), + .rdy(app_wdf_rdy), + .wren(app_wdf_wren) +); + +mpmc9_app_wdf_end_gen uwendg1 +( + .clk(mem_ui_clk), + .state(state), + .rdy(app_wdf_rdy), + .wend(app_wdf_end) +); + +mpmc9_req_strip_cnt ursc1 +( + .clk(mem_ui_clk), + .state(state), + .wdf_rdy(app_wdf_rdy), + .rdy(app_rdy), + .num_strips(num_strips), + .strip_cnt(req_strip_cnt) +); + +mpmc9_resp_strip_cnt urespsc1 +( + .clk(mem_ui_clk), + .state(state), + .valid(app_rd_data_valid), + .num_strips(num_strips), + .strip_cnt(resp_strip_cnt) +); + + +mpmc9_do_wr udowr0 +( + .we(we0xx), + .cr(1'b0), + .adr(adr0xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .do_wr(do_wr0) +); + +mpmc9_do_wr udowr1 +( + .we(we1xx), + .cr(cr1xx), + .adr(adr1xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .do_wr(do_wr1) +); + +mpmc9_do_wr udowr2 +( + .we(we2xx), + .cr(1'b0), + .adr(adr2xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .do_wr(do_wr2) +); + +mpmc9_do_wr udowr3 +( + .we(we3xx), + .cr(1'b0), + .adr(adr3xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .do_wr(do_wr3) +); + +mpmc9_do_wr udowr4 +( + .we(we4xx), + .cr(1'b0), + .adr(adr4xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .do_wr(do_wr4) +); + +mpmc9_do_wr udowr5 +( + .we(1'b0), + .cr(1'b0), + .adr(adr5xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .do_wr(do_wr5) +); + +mpmc9_do_wr udowr6 +( + .we(we6xx), + .cr(1'b0), + .adr(adr6xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .do_wr(do_wr6) +); + +mpmc9_do_wr udowr7 +( + .we(we7xx), + .cr(cr7xx), + .adr(adr7xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .do_wr(do_wr7) +); + +mpmc9_do_wr_select udws1 +( + .clk(mem_ui_clk), + .state(state), + .ch(nch), + .wr0(do_wr0), + .wr1(do_wr1), + .wr2(do_wr2), + .wr3(do_wr3), + .wr4(do_wr4), + .wr5(do_wr5), + .wr6(do_wr6), + .wr7(do_wr7), + .wr(do_wr) +); + +// Reservation status bit +mpmc9_resv_bit ursb1 +( + .clk(mem_ui_clk), + .state(state), + .cs(cs1xx), + .we(we1xx), + .ack(acki1), + .cr(cr1xx), + .adr(adr1xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .rb(rb1) +); + +mpmc9_resv_bit ursb7 +( + .clk(mem_ui_clk), + .state(state), + .cs(cs7xx), + .we(we7xx), + .ack(acki7), + .cr(cr7xx), + .adr(adr7xx), + .resv_ch(resv_ch), + .resv_adr(resv_adr), + .rb(rb7) +); + +// Managing address reservations +mpmc9_addr_resv_man uarman1 +( + .rst(mem_ui_rst), + .clk(mem_ui_clk), + .state(state), + .cs1(cs1xx), + .ack1(acki1), + .we1(we1xx), + .adr1(adr1xx), + .sr1(sr1x), + .cr1(cr1xx), + .ch1_taghit(ch1_taghit), + .cs7(cs7xx), + .ack7(acki7), + .we7(we7xx), + .adr7(adr7xx), + .sr7(sr7x), + .cr7(cr7xx), + .ch7_taghit(ch7_taghit), + .resv_ch(resv_ch), + .resv_adr(resv_adr) +); + +endmodule Index: trunk/rtl/mpmc9_ack_gen.sv =================================================================== --- trunk/rtl/mpmc9_ack_gen.sv (nonexistent) +++ trunk/rtl/mpmc9_ack_gen.sv (revision 4) @@ -0,0 +1,98 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_ack_gen(rst, clk, state, ch, cs, adr, cr, wr, to, taghit, + resv_ch, resv_adr, ack, pre_ack); +parameter N = 0; +input rst; +input clk; +input [3:0] state; +input [3:0] ch; +input cs; +input [31:0] adr; +input cr; +input wr; +input to; +input taghit; +input [3:0] resv_ch [0:NAR-1]; +input [31:0] resv_adr [0:NAR-1]; +output reg ack; +output reg pre_ack; + +integer n; +reg [7:0] ack_pipe; + +// Setting ack output +// Ack takes place outside of a state so that reads from different read caches +// may occur at the same time. +always_ff @(posedge clk) +if (rst) + ack_pipe <= 'd0; +else begin + ack_pipe <= {ack_pipe[6:0],ack_pipe[0]}; + + // Reads: the ack doesn't happen until the data's been cached. If there is + // cached data we give an ack right away. + if (taghit) + ack_pipe[0] <= 8'd1; + + if (state==IDLE) begin + if (cr) begin + ack_pipe <= 8'hFF; + for (n = 0; n < NAR; n = n + 1) + if ((resv_ch[n]==N) && (resv_adr[n][31:4]==adr[31:4])) begin + ack_pipe <= 'd0; + end + end + end + + // Write: an ack can be sent back as soon as the write state is reached.. + if ((state==PRESET1 && wr) || to) + if (ch==N) + ack_pipe <= 8'hFF; + + // Clear the ack when the circuit is de-selected. + if (!cs) + ack_pipe <= 'd0; + + ack <= ack_pipe[7]; + pre_ack <= ack_pipe[0]; + +end + +endmodule Index: trunk/rtl/mpmc9_addr_gen.sv =================================================================== --- trunk/rtl/mpmc9_addr_gen.sv (nonexistent) +++ trunk/rtl/mpmc9_addr_gen.sv (revision 4) @@ -0,0 +1,62 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_addr_gen(rst, clk, state, rdy, num_strips, strip_cnt, addr_base, addr); +input rst; +input clk; +input [3:0] state; +input rdy; +input [5:0] num_strips; +input [5:0] strip_cnt; +input [31:0] addr_base; +output reg [31:0] addr; + +always_ff @(posedge clk) +if (rst) + addr <= 32'h1FFFFFFF; +else begin + if (state==PRESET2) + addr <= addr_base; + else if (state==READ_DATA1 && rdy && strip_cnt != num_strips) + addr[31:4] <= addr[31:4] + 2'd1; + // Increment the address if we had to start a new burst. +// else if (state==WRITE_DATA3 && req_strip_cnt!=num_strips) +// app_addr <= app_addr + {req_strip_cnt,4'h0}; // works for only 1 missed burst +end + +endmodule Index: trunk/rtl/mpmc9_addr_resv_man.sv =================================================================== --- trunk/rtl/mpmc9_addr_resv_man.sv (nonexistent) +++ trunk/rtl/mpmc9_addr_resv_man.sv (revision 4) @@ -0,0 +1,182 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_addr_resv_man(rst, clk, state, + cs1, ack1, we1, adr1, sr1, cr1, ch1_taghit, + cs7, ack7, we7, adr7, sr7, cr7, ch7_taghit, + resv_ch, resv_adr); +input rst; +input clk; +input [3:0] state; +input cs1; +input ack1; +input we1; +input [31:0] adr1; +input sr1; +input cr1; +input ch1_taghit; +input cs7; +input ack7; +input we7; +input [31:0] adr7; +input sr7; +input cr7; +input ch7_taghit; +output reg [3:0] resv_ch [0:NAR-1]; +output reg [31:0] resv_adr [0:NAR-1]; + +reg [19:0] resv_to_cnt; +reg toggle, toggle_sr; + +// For address reservation below +reg [7:0] match; +always @(posedge clk) +if (rst) + match <= 8'h00; +else begin + if (match >= NAR) + match <= 8'h00; + else + match <= match + 8'd1; +end + +// Managing address reservations +integer n7; +always_ff @(posedge clk) +if (rst) begin + resv_to_cnt <= 20'd0; + toggle <= FALSE; + toggle_sr <= FALSE; + for (n7 = 0; n7 < NAR; n7 = n7 + 1) + resv_ch[n7] <= 4'hF; +end +else begin + resv_to_cnt <= resv_to_cnt + 20'd1; + + if (sr1 & sr7) begin + if (toggle_sr) begin + reserve_adr(4'h1,adr1); + toggle_sr <= 1'b0; + end + else begin + reserve_adr(4'h7,adr7); + toggle_sr <= 1'b1; + end + end + else begin + if (sr1) + reserve_adr(4'h1,adr1); + if (sr7) + reserve_adr(4'h7,adr7); + end + + if (state==IDLE) begin + if (cs1 & we1 & ~ack1) begin + toggle <= 1'b1; + if (cr1) begin + for (n7 = 0; n7 < NAR; n7 = n7 + 1) + if ((resv_ch[n7]==4'd1) && (resv_adr[n7][31:4]==adr1[31:4])) + resv_ch[n7] <= 4'hF; + end + end + else if (cs7 & we7 & ~ack7) begin + toggle <= 1'b1; + if (cr7) begin + for (n7 = 0; n7 < NAR; n7 = n7 + 1) + if ((resv_ch[n7]==4'd7) && (resv_adr[n7][31:4]==adr7[31:4])) + resv_ch[n7] <= 4'hF; + end + end + else if (!we1 & cs1 & ~ch1_taghit & (cs7 ? toggle : 1'b1)) + toggle <= 1'b0; + else if (!we7 & cs7 & ~ch7_taghit) + toggle <= 1'b1; + end +end + +integer empty_resv; +function resv_held; +input [3:0] ch; +input [31:0] adr; +integer n8; +begin + resv_held = FALSE; + for (n8 = 0; n8 < NAR; n8 = n8 + 1) + if (resv_ch[n8]==ch && resv_adr[n8]==adr) + resv_held = TRUE; +end +endfunction + +// Find an empty reservation bucket +integer n9; +always_comb +begin + empty_resv <= -1; + for (n9 = 0; n9 < NAR; n9 = n9 + 1) + if (resv_ch[n9]==4'hF) + empty_resv <= n9; +end + +// Two reservation buckets are allowed for. There are two (or more) CPU's in the +// system and as long as they are not trying to control the same resource (the +// same semaphore) then they should be able to set a reservation. Ideally there +// could be more reservation buckets available, but it starts to be a lot of +// hardware. +task reserve_adr; +input [3:0] ch; +input [31:0] adr; +begin + // Ignore an attempt to reserve an address that's already reserved. The LWAR + // instruction is usually called in a loop and we don't want it to use up + // all address reservations. + if (!resv_held(ch,adr)) begin + if (empty_resv >= 0) begin + resv_ch[empty_resv] <= ch; + resv_adr[empty_resv] <= adr; + end + // Here there were no free reservation buckets, so toss one of the + // old reservations out. + else begin + resv_ch[match] <= ch; + resv_adr[match] <= adr; + end + end +end +endtask + +endmodule Index: trunk/rtl/mpmc9_addr_select.sv =================================================================== --- trunk/rtl/mpmc9_addr_select.sv (nonexistent) +++ trunk/rtl/mpmc9_addr_select.sv (revision 4) @@ -0,0 +1,78 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_addr_select(rst, clk, state, ch, + adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, + adr); +input rst; +input clk; +input [3:0] state; +input [3:0] ch; +input [31:0] adr0; +input [31:0] adr1; +input [31:0] adr2; +input [31:0] adr3; +input [31:0] adr4; +input [31:0] adr5; +input [31:0] adr6; +input [31:0] adr7; +output reg [31:0] adr; + +// Select the address input +reg [31:0] adrx; +always_ff @(posedge clk) +if (state==IDLE) begin + case(ch) + 3'd0: adrx <= {adr0[AMSB:4],4'h0}; + 3'd1: adrx <= {adr1[AMSB:4],4'h0}; + 3'd2: adrx <= {adr2[AMSB:4],4'h0}; + 3'd3: adrx <= {adr3[AMSB:4],4'h0}; + 3'd4: adrx <= {adr4[AMSB:4],4'h0}; + 3'd5: adrx <= {adr5[AMSB:4],4'h0}; + 3'd6: adrx <= {adr6[AMSB:4],4'h0}; + 3'd7: adrx <= {adr7[AMSB:4],4'h0}; + default: adrx <= 29'h1FFFFFF0; + endcase +end +always_ff @(posedge clk) +if (rst) + adr <= 32'h1FFFFFF0; +else if (state==PRESET1) + adr <= adrx; + +endmodule Index: trunk/rtl/mpmc9_app_cmd_gen.sv =================================================================== --- trunk/rtl/mpmc9_app_cmd_gen.sv (nonexistent) +++ trunk/rtl/mpmc9_app_cmd_gen.sv (revision 4) @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_app_cmd_gen(clk, state, cmd); +input clk; +input [3:0] state; +output reg [2:0] cmd; + +// Strangely, for the DDR3 the default is to have a write command value, +// overridden when a read is needed. The command is processed by the +// WRITE_DATAx states. + +always_ff @(posedge clk) +begin + if (state==IDLE) + cmd <= CMD_WRITE; + else if (state==READ_DATA0) + cmd <= CMD_READ; +end + +endmodule Index: trunk/rtl/mpmc9_app_en_gen.sv =================================================================== --- trunk/rtl/mpmc9_app_en_gen.sv (nonexistent) +++ trunk/rtl/mpmc9_app_en_gen.sv (revision 4) @@ -0,0 +1,62 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_app_en_gen(clk, state, rdy, strip_cnt, num_strips, en); +input clk; +input [3:0] state; +input rdy; +input [5:0] strip_cnt; +input [5:0] num_strips; +output reg en; + +// app_en latches the command and address when app_rdy is active. If app_rdy +// is not true, the command must be retried. +always_ff @(posedge clk) +begin + en <= FALSE; + if (state==WRITE_DATA1) + en <= TRUE; + else if (state==WRITE_DATA2 && !rdy) + en <= TRUE; + else if (state==READ_DATA0) + en <= TRUE; + else if (state==READ_DATA1 && !(rdy && strip_cnt==num_strips)) + en <= TRUE; +end + +endmodule Index: trunk/rtl/mpmc9_app_wdf_end_gen.sv =================================================================== --- trunk/rtl/mpmc9_app_wdf_end_gen.sv (nonexistent) +++ trunk/rtl/mpmc9_app_wdf_end_gen.sv (revision 4) @@ -0,0 +1,54 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_app_wdf_end_gen(clk, state, rdy, wend); +input clk; +input [3:0] state; +input rdy; +output reg wend; + +// app_wdf_wren is used to strobe data into the data fifo when app_wdf_rdy is +// true. +always_ff @(posedge clk) +begin + wend <= FALSE; + if (state==WRITE_DATA0 && rdy) + wend <= TRUE;//req_strip_cnt==num_strips; +end + +endmodule Index: trunk/rtl/mpmc9_app_wdf_wren_gen.sv =================================================================== --- trunk/rtl/mpmc9_app_wdf_wren_gen.sv (nonexistent) +++ trunk/rtl/mpmc9_app_wdf_wren_gen.sv (revision 4) @@ -0,0 +1,54 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_app_wdf_wren_gen(clk, state, rdy, wren); +input clk; +input [3:0] state; +input rdy; +output reg wren; + +// app_wdf_wren is used to strobe data into the data fifo when app_wdf_rdy is +// true. +always_ff @(posedge clk) +begin + wren <= FALSE; + if (state==WRITE_DATA0 && rdy) + wren <= TRUE; +end + +endmodule Index: trunk/rtl/mpmc9_ch_prioritize.sv =================================================================== --- trunk/rtl/mpmc9_ch_prioritize.sv (nonexistent) +++ trunk/rtl/mpmc9_ch_prioritize.sv (revision 4) @@ -0,0 +1,164 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_ch_prioritize(clk, state, + cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7, + we0, we1, we2, we3, we4, we5, we6, we7, + ch0_taghit, ch1_taghit, ch2_taghit, ch3_taghit, + ch4_taghit, ch5_taghit, ch6_taghit, ch7_taghit, + ch); +input clk; +input [3:0] state; +input cs0; +input cs1; +input cs2; +input cs3; +input cs4; +input cs5; +input cs6; +input cs7; +input we0; +input we1; +input we2; +input we3; +input we4; +input we5; +input we6; +input we7; +input ch0_taghit; +input ch1_taghit; +input ch2_taghit; +input ch3_taghit; +input ch4_taghit; +input ch5_taghit; +input ch6_taghit; +input ch7_taghit; +output reg [3:0] ch; + +// This counter used to periodically reverse channel priorities to help ensure +// that a particular channel isn't permanently blocked by other higher priority +// ones. +reg [5:0] elevate_cnt = 'd0; +reg elevate = 1'b0; + +always_ff @(posedge clk) +if (state==PRESET1) begin + elevate_cnt <= elevate_cnt + 6'd1; + elevate <= elevate_cnt == 6'd63; +end + + +// Select the channel +// This prioritizes the channel during the IDLE state. +// During an elevate cycle the channel priorities are reversed. +always_ff @(posedge clk) +begin + if (elevate) begin + if (cs7 & we7) + ch <= 4'd7; + else if (cs6 & we6) + ch <= 4'd6; + else if (cs5 & we5) + ch <= 4'd5; + else if (cs4 & we4) + ch <= 4'd4; + else if (cs3 & we3) + ch <= 4'd3; + else if (cs2 & we2) + ch <= 4'd2; + else if (cs1 & we1) + ch <= 4'd1; + else if (cs0 & we0) + ch <= 4'd0; + else if (cs7 & ~ch7_taghit) + ch <= 4'd7; + else if (cs6 & ~ch6_taghit) + ch <= 4'd6; + else if (cs5 & ~ch5_taghit) + ch <= 4'd5; + else if (cs4 & ~ch4_taghit) + ch <= 4'd4; + else if (cs3 & ~ch3_taghit) + ch <= 4'd3; + else if (cs2 & ~ch2_taghit) + ch <= 4'd2; + else if (cs1 & ~ch1_taghit) + ch <= 4'd1; + else if (cs0 & ~ch0_taghit) + ch <= 4'd0; + else + ch <= 4'hF; + end + // Channel 0 read or write takes precedence + else if (cs0 & we0) + ch <= 4'd0; + else if (cs0 & ~ch0_taghit) + ch <= 4'd0; + else if (cs1 & we1) + ch <= 4'd1; + else if (cs2 & we2) + ch <= 4'd2; + else if (cs3 & we3) + ch <= 4'd3; + else if (cs4 & we4) + ch <= 4'd4; + else if (cs6 & we6) + ch <= 4'd6; + else if (cs7 & we7) + ch <= 4'd7; + // Reads, writes detected above + else if (cs1 & ~ch1_taghit) + ch <= 4'd1; + else if (cs2 & ~ch2_taghit) + ch <= 4'd2; + else if (cs3 & ~ch3_taghit) + ch <= 4'd3; + else if (cs4 & ~ch4_taghit) + ch <= 4'd4; + else if (cs5 & ~ch5_taghit) + ch <= 4'd5; + else if (cs6 & ~ch6_taghit) + ch <= 4'd6; + else if (cs7 & ~ch7_taghit) + ch <= 4'd7; + // Nothing selected + else + ch <= 4'hF; +end + +endmodule Index: trunk/rtl/mpmc9_cmd_gen.sv =================================================================== --- trunk/rtl/mpmc9_cmd_gen.sv (nonexistent) +++ trunk/rtl/mpmc9_cmd_gen.sv (revision 4) @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_cmd_gen(ui_clk, state, cmd); +input ui_clk; +input [3:0] state; +output reg [2:0] cmd; + +// Strangely, for the DDR3 the default is to have a write command value, +// overridden when a read is needed. The command is processed by the +// WRITE_DATAx states. + +always_ff @(posedge ui_clk) +begin + if (state==IDLE) + cmd <= CMD_WRITE; + else if (state==READ_DATA0) + cmd <= CMD_READ; +end + +endmodule Index: trunk/rtl/mpmc9_data_output.sv =================================================================== --- trunk/rtl/mpmc9_data_output.sv (nonexistent) +++ trunk/rtl/mpmc9_data_output.sv (revision 4) @@ -0,0 +1,187 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_data_output( + clk0, cs0, adr0, ch0_rdat, dato0, + clk1, cs1, adr1, ch1_rdat, dato1, + clk2, cs2, adr2, ch2_rdat, dato2, + clk3, cs3, adr3, ch3_rdat, dato3, + clk4, cs4, adr4, ch4_rdat, dato4, + clk5, cs5, adr5, ch5_rdat, dato5, + clk6, cs6, adr6, ch6_rdat, dato6, + clk7, cs7, adr7, ch7_rdat, dato7 +); +parameter C0W = 128; +parameter C1W = 128; +parameter C2W = 32; +parameter C3W = 16; +parameter C4W = 128; +parameter C5W = 64; +parameter C6W = 128; +parameter C7R = 16; + +input clk0; +input clk1; +input clk2; +input clk3; +input clk4; +input clk5; +input clk6; +input clk7; +input cs0; +input cs1; +input cs2; +input cs3; +input cs4; +input cs5; +input cs6; +input cs7; +input [31:0] adr0; +input [31:0] adr1; +input [31:0] adr2; +input [31:0] adr3; +input [31:0] adr4; +input [31:0] adr5; +input [31:0] adr6; +input [31:0] adr7; +input [127:0] ch0_rdat; +input [127:0] ch1_rdat; +input [127:0] ch2_rdat; +input [127:0] ch3_rdat; +input [127:0] ch4_rdat; +input [127:0] ch5_rdat; +input [127:0] ch6_rdat; +input [127:0] ch7_rdat; +output reg [127:0] dato0; +output reg [127:0] dato1; +output reg [127:0] dato2; +output reg [127:0] dato3; +output reg [127:0] dato4; +output reg [127:0] dato5; +output reg [127:0] dato6; +output reg [127:0] dato7; + +reg [127:0] ch0_rdatr; +reg [127:0] ch1_rdatr; +reg [127:0] ch2_rdatr; +reg [127:0] ch3_rdatr; +reg [127:0] ch4_rdatr; +reg [127:0] ch5_rdatr; +reg [127:0] ch6_rdatr; +reg [127:0] ch7_rdatr; + +// Setting output data. Force output data to zero when not selected to allow +// wire-oring the data. +always_ff @(posedge clk0) +`ifdef RED_SCREEN +if (cs0) begin + if (C0W==128) + dato0 <= 128'h7C007C007C007C007C007C007C007C00; + else if (C0W==64) + dato0 <= 64'h7C007C007C007C00; + else if (C0W==32) + dato0 <= 32'h7C007C00; + else if (C0W==16) + dato0 <= 16'h7C00; + else + dato0 <= 8'hE0; +end +else + dato0 <= {C0W{1'b0}}; +`else + tDato(C0W,cs0,adr0[3:0],ch0_rdatr,dato0); +`endif + +// Register data outputs back onto their domain. +always_ff @(posedge clk1) + ch1_rdatr <= ch1_rdat; +always_ff @(posedge clk2) + ch2_rdatr <= ch2_rdat; +always_ff @(posedge clk3) + ch3_rdatr <= ch3_rdat; +always_ff @(posedge clk4) + ch4_rdatr <= ch4_rdat; +always_ff @(posedge clk5) + ch5_rdatr <= ch5_rdat; +always_ff @(posedge clk6) + ch6_rdatr <= ch6_rdat; +always_ff @(posedge clk7) + ch7_rdatr <= ch7_rdat; +always_ff @(posedge clk0) + ch0_rdatr <= ch0_rdat; + +always_ff @(posedge clk1) + tDato(C1W,cs1,adr1[3:0],ch1_rdatr,dato1); +always_ff @(posedge clk2) + tDato(C2W,cs2,adr2[3:0],ch2_rdatr,dato2); +always_ff @(posedge clk3) + tDato(C3W,cs3,adr3[3:0],ch3_rdatr,dato3); +always_ff @(posedge clk4) + tDato(C4W,cs4,adr4[3:0],ch4_rdatr,dato4); +always_ff @(posedge clk5) + tDato(C5W,cs5,adr5[3:0],ch5_rdatr,dato5); +always_ff @(posedge clk6) + tDato(C6W,cs6,adr6[3:0],ch6_rdatr,dato6); +always_ff @(posedge clk7) + tDato(C7R,cs7,adr7[3:0],ch7_rdatr,dato7); + +task tDato; +input [7:0] widi; +input csi; +input [3:0] adri; +input [127:0] dati; +output [127:0] dato; +begin +if (csi) begin + if (widi==8'd128) + dato <= dati; + else if (widi==8'd64) + dato <= dati >> {adri[3],6'h0}; + else if (widi==8'd32) + dato <= dati >> {adri[3:2],5'h0}; + else if (widi==8'd16) + dato <= dati >> {adri[3:1],4'h0}; + else + dato <= dati >> {adri[3:0],3'h0}; +end +else + dato <= 'b0; +end +endtask + +endmodule Index: trunk/rtl/mpmc9_data_select.sv =================================================================== --- trunk/rtl/mpmc9_data_select.sv (nonexistent) +++ trunk/rtl/mpmc9_data_select.sv (revision 4) @@ -0,0 +1,80 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_data_select(clk, state, ch, + dati0, dati1, dati2, dati3, dati4, dati5, dati6, dati7, dato +); +parameter C0W = 128; +parameter C1W = 128; +parameter C2W = 128; +parameter C3W = 128; +parameter C4W = 128; +parameter C5W = 128; +parameter C6W = 128; +parameter C7W = 128; +input clk; +input [3:0] state; +input [3:0] ch; +input [C0W-1:0] dati0; +input [C1W-1:0] dati1; +input [C2W-1:0] dati2; +input [C3W-1:0] dati3; +input [C4W-1:0] dati4; +input [C5W-1:0] dati5; +input [C6W-1:0] dati6; +input [C7W-1:0] dati7; +output reg [127:0] dato; + +// Setting the write data +// Repeat the data across lanes when less than 128-bit. +always_ff @(posedge clk) +if (state==IDLE) begin + case(ch) + 4'd0: dato <= {(128/C0W){dati0}}; + 4'd1: dato <= {(128/C1W){dati1}}; + 4'd2: dato <= {(128/C2W){dati2}}; + 4'd3: dato <= {(128/C3W){dati3}}; + 4'd4: dato <= {(128/C4W){dati4}}; + 4'd5: dato <= {(128/C4W){dati5}}; + 4'd6: dato <= {(128/C6W){dati6}}; + 4'd7: dato <= {(128/C7W){dati7}}; + default: dato <= {2{dati7}}; + endcase +end + +endmodule Index: trunk/rtl/mpmc9_do_wr.sv =================================================================== --- trunk/rtl/mpmc9_do_wr.sv (nonexistent) +++ trunk/rtl/mpmc9_do_wr.sv (revision 4) @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_do_wr(we, cr, adr, resv_ch, resv_adr, do_wr); +input we; +input cr; +input [31:0] adr; +input [3:0] resv_ch [0:NAR-1]; +input [31:0] resv_adr [0:NAR-1]; +output reg do_wr; + +integer n4; + +always_comb +begin + do_wr <= FALSE; + if (we) begin + if (cr) begin + for (n4 = 0; n4 < NAR; n4 = n4 + 1) + if ((resv_ch[n4]==4'd1) && (resv_adr[n4][31:4]==adr[31:4])) + do_wr <= TRUE; + end + else + do_wr <= TRUE; + end +end + +endmodule + + Index: trunk/rtl/mpmc9_do_wr_select.sv =================================================================== --- trunk/rtl/mpmc9_do_wr_select.sv (nonexistent) +++ trunk/rtl/mpmc9_do_wr_select.sv (revision 4) @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_do_wr_select(clk, state, ch, wr0, wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr); +input clk; +input [3:0] state; +input [3:0] ch; +input wr0; +input wr1; +input wr2; +input wr3; +input wr4; +input wr5; +input wr6; +input wr7; +output reg wr; + +always_ff @(posedge clk) +begin + if (state==IDLE) begin + wr <= FALSE; + case(ch) + 4'd0: wr <= wr0; + 4'd1: wr <= wr1; + 4'd2: wr <= wr2; + 4'd3: wr <= wr3; + 4'd4: wr <= wr4; + 4'd5: wr <= wr5; + 4'd6: wr <= wr6; + 4'd7: wr <= wr7; + default: ; + endcase + end +end + +endmodule Index: trunk/rtl/mpmc9_mask_select.sv =================================================================== --- trunk/rtl/mpmc9_mask_select.sv (nonexistent) +++ trunk/rtl/mpmc9_mask_select.sv (revision 4) @@ -0,0 +1,87 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_mask_select(rst, clk, state, ch, + wmask0, wmask1, wmask2, wmask3, wmask4, wmask5, wmask6, wmask7, + mask, mask2 +); +input rst; +input clk; +input [3:0] state; +input [3:0] ch; +input [15:0] wmask0; +input [15:0] wmask1; +input [15:0] wmask2; +input [15:0] wmask3; +input [15:0] wmask4; +input [15:0] wmask5; +input [15:0] wmask6; +input [15:0] wmask7; +output reg [15:0] mask; +output reg [15:0] mask2; + +// Setting the data mask. Values are enabled when the data mask is zero. +always_ff @(posedge clk) +if (rst) + mask2 <= 16'h0000; +else begin + if (state==PRESET1) + case(ch) + 4'd0: mask2 <= wmask0; + 4'd1: mask2 <= wmask1; + 4'd2: mask2 <= wmask2; + 4'd3: mask2 <= wmask3; + 4'd4: mask2 <= wmask4; + 4'd5: mask2 <= wmask5; + 4'd6: mask2 <= wmask6; + 4'd7: mask2 <= wmask7; + default: mask2 <= 16'h0000; + endcase + // For RMW cycle all bytes are writtten. + else if (state==WRITE_TRAMP1) + mask2 <= 16'h0000; +end +always_ff @(posedge clk) +if (rst) + mask <= 16'h0000; +else begin + if (state==PRESET2) + mask <= mask2; +end + +endmodule Index: trunk/rtl/mpmc9_pkg.sv =================================================================== --- trunk/rtl/mpmc9_pkg.sv (nonexistent) +++ trunk/rtl/mpmc9_pkg.sv (revision 4) @@ -0,0 +1,61 @@ +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +package mpmc9_pkg; + +parameter RMW = 0; +parameter NAR = 2; +parameter AMSB = 28; +parameter TRUE = 1'b1; +parameter FALSE = 1'b0; +parameter CMD_READ = 3'b001; +parameter CMD_WRITE = 3'b000; +// State machine states +parameter IDLE = 4'd0; +parameter PRESET1 = 4'd1; +parameter PRESET2 = 4'd2; +parameter WRITE_DATA0 = 4'd3; +parameter WRITE_DATA1 = 4'd4; +parameter WRITE_DATA2 = 4'd5; +parameter WRITE_DATA3 = 4'd7; +parameter READ_DATA0 = 4'd8; +parameter READ_DATA1 = 4'd9; +parameter READ_DATA2 = 4'd10; +parameter WAIT_NACK = 4'd11; +parameter WRITE_TRAMP = 4'd12; // write trampoline +parameter WRITE_TRAMP1 = 4'd13; +parameter PRESET3 = 4'd14; + +endpackage Index: trunk/rtl/mpmc9_prev_state.sv =================================================================== --- trunk/rtl/mpmc9_prev_state.sv (nonexistent) +++ trunk/rtl/mpmc9_prev_state.sv (revision 4) @@ -0,0 +1,52 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_prev_state(clk, state, prev_state); +input clk; +input [3:0] state; +output reg [3:0] prev_state; + +always_ff @(posedge clk) +if (state==IDLE) // We can stay in the idle state as long as we like + prev_state <= IDLE; +else begin + if (state!=prev_state) + prev_state <= state; +end + +endmodule Index: trunk/rtl/mpmc9_req_strip_cnt.sv =================================================================== --- trunk/rtl/mpmc9_req_strip_cnt.sv (nonexistent) +++ trunk/rtl/mpmc9_req_strip_cnt.sv (revision 4) @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +// Manage memory strip counters. + +module mpmc9_req_strip_cnt(clk, state, wdf_rdy, rdy, num_strips, strip_cnt); +input clk; +input [3:0] state; +input wdf_rdy; +input rdy; +input [5:0] num_strips; +output reg [5:0] strip_cnt; + +always_ff @(posedge clk) +if (state==IDLE) + strip_cnt <= 6'd0; +else begin + if (state==WRITE_DATA0 && wdf_rdy) begin + if (strip_cnt != num_strips) + strip_cnt <= strip_cnt + 3'd1; + end + else if (state==READ_DATA1 && rdy) begin + if (strip_cnt != num_strips) + strip_cnt <= strip_cnt + 3'd1; + end +end + +endmodule Index: trunk/rtl/mpmc9_resp_strip_cnt.sv =================================================================== --- trunk/rtl/mpmc9_resp_strip_cnt.sv (nonexistent) +++ trunk/rtl/mpmc9_resp_strip_cnt.sv (revision 4) @@ -0,0 +1,53 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_resp_strip_cnt(clk, state, valid, num_strips, strip_cnt); +input clk; +input [3:0] state; +input valid; +input [5:0] num_strips; +output reg [5:0] strip_cnt; + +always_ff @(posedge clk) +if (state==IDLE) + strip_cnt <= 6'd0; +else if (valid) + if (strip_cnt != num_strips) + strip_cnt <= strip_cnt + 3'd1; + +endmodule Index: trunk/rtl/mpmc9_resv_bit.sv =================================================================== --- trunk/rtl/mpmc9_resv_bit.sv (nonexistent) +++ trunk/rtl/mpmc9_resv_bit.sv (revision 4) @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +// Reservation status bit +module mpmc9_resv_bit(clk, state, cs, we, ack, cr, adr, resv_ch, resv_adr, rb); +input clk; +input [3:0] state; +input cs; +input we; +input ack; +input cr; +input [31:0] adr; +input [3:0] resv_ch [0:NAR-1]; +input [31:0] resv_adr [0:NAR-1]; +output reg rb; + +integer n5; +always_ff @(posedge clk) +if (state==IDLE) begin + if (cs & we & ~ack) begin + if (cr) begin + rb <= FALSE; + for (n5 = 0; n5 < NAR; n5 = n5 + 1) + if ((resv_ch[n5]==4'd1) && (resv_adr[n5][31:4]==adr[31:4])) + rb <= TRUE; + end + end +end + +endmodule Index: trunk/rtl/mpmc9_set_num_strips.sv =================================================================== --- trunk/rtl/mpmc9_set_num_strips.sv (nonexistent) +++ trunk/rtl/mpmc9_set_num_strips.sv (revision 4) @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_set_num_strips(clk, state, ch, + we0, we1, we2, we3, we4, we5, we6, we7, num_strips); +parameter S0 = 6'd63; +parameter S1 = 6'd1; +parameter S2 = 6'd31; +parameter S3 = 6'd63; +parameter S4 = 6'd0; +parameter S5 = 6'd63; +parameter S6 = 6'd63; +parameter S7 = 6'd3; +input clk; +input [3:0] state; +input [3:0] ch; +input we0; +input we1; +input we2; +input we3; +input we4; +input we5; +input we6; +input we7; +output reg [5:0] num_strips; + +// Setting burst length +always_ff @(posedge clk) +if (state==IDLE) begin + num_strips <= 3'd0; + case(ch) + 4'd0: if (!we0) num_strips <= S0; //7 + 4'd1: if (!we1) num_strips <= S1; //1 + 4'd2: if (!we2) num_strips <= S2; + 4'd3: if (!we3) num_strips <= S3; + 4'd4: if (!we4) num_strips <= S4; + 4'd5: if (!we5) num_strips <= S5; //3 + 4'd6: if (!we6) num_strips <= S6; + 4'd7: if (!we7) num_strips <= S7; + default: ; + endcase +end + +endmodule Index: trunk/rtl/mpmc9_set_write_mask.sv =================================================================== --- trunk/rtl/mpmc9_set_write_mask.sv (nonexistent) +++ trunk/rtl/mpmc9_set_write_mask.sv (revision 4) @@ -0,0 +1,130 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_set_write_mask(clk, state, + we0, we1, we2, we3, we4, we5, we6, we7, + sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, + adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, + mask0, mask1, mask2, mask3, mask4, mask5, mask6, mask7 +); +parameter C0W = 128; +parameter C1W = 128; +parameter C2W = 128; +parameter C3W = 128; +parameter C4W = 128; +parameter C5W = 128; +parameter C6W = 128; +parameter C7W = 128; +input clk; +input [3:0] state; +input we0; +input we1; +input we2; +input we3; +input we4; +input we5; +input we6; +input we7; +input [C0W/8-1:0] sel0; +input [C1W/8-1:0] sel1; +input [C2W/8-1:0] sel2; +input [C3W/8-1:0] sel3; +input [C4W/8-1:0] sel4; +input [C5W/8-1:0] sel5; +input [C6W/8-1:0] sel6; +input [C7W/8-1:0] sel7; +input [31:0] adr0; +input [31:0] adr1; +input [31:0] adr2; +input [31:0] adr3; +input [31:0] adr4; +input [31:0] adr5; +input [31:0] adr6; +input [31:0] adr7; +output reg [15:0] mask0; +output reg [15:0] mask1; +output reg [15:0] mask2; +output reg [15:0] mask3; +output reg [15:0] mask4; +output reg [15:0] mask5; +output reg [15:0] mask6; +output reg [15:0] mask7; + +always_ff @(posedge clk) + tMask(C0W,we0,{15'd0,sel0},adr0[3:0],mask0); +always_ff @(posedge clk) + tMask(C1W,we1,{15'd0,sel1},adr1[3:0],mask1); +always_ff @(posedge clk) + tMask(C2W,we2,{15'd0,sel2},adr2[3:0],mask2); +always_ff @(posedge clk) + tMask(C3W,we3,{15'd0,sel3},adr3[3:0],mask3); +always_ff @(posedge clk) + tMask(C4W,we4,{15'd0,sel4},adr4[3:0],mask4); +always_ff @(posedge clk) + tMask(C5W,we5,{15'd0,sel5},adr5[3:0],mask5); +always_ff @(posedge clk) + tMask(C6W,we6,{15'd0,sel6},adr6[3:0],mask6); +always_ff @(posedge clk) + tMask(C7W,we7,{15'd0,sel7},adr7[3:0],mask7); + +task tMask; +input [7:0] widi; +input wei; +input [15:0] seli; +input [3:0] adri; +output [15:0] masko; +begin +if (state==IDLE) + if (wei) begin + if (widi==8'd128) + masko <= ~seli; + else if (widi==8'd64) + masko <= ~({8'd0,seli[7:0]} << {adri[3],3'b0}); + else if (widi==8'd32) + masko <= ~({12'd0,seli[3:0]} << {adri[3:2],2'b0}); + else if (widi==8'd16) + masko <= ~({14'd0,seli[1:0]} << {adri[3:1],1'b0}); + else + masko <= ~({15'd0,seli[0]} << adri[3:0]); + end + else + masko <= 16'h0000; // read all bytes +end +endtask + +endmodule Index: trunk/rtl/mpmc9_state_machine.sv =================================================================== --- trunk/rtl/mpmc9_state_machine.sv (nonexistent) +++ trunk/rtl/mpmc9_state_machine.sv (revision 4) @@ -0,0 +1,257 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_state_machine(rst, clk, ch, + acki0, acki1, acki2, acki3, acki4, acki5, acki6, acki7, + ch0_taghit, ch1_taghit, ch2_taghit, ch3_taghit, ch4_taghit, ch5_taghit, + ch6_taghit, ch7_taghit, wdf_rdy, rdy, do_wr, rd_data_valid, + num_strips, req_strip_cnt, resp_strip_cnt, to, + cr1, cr7, adr1, adr7, + resv_ch, resv_adr, + state +); +input rst; +input clk; +input [3:0] ch; +input acki0; +input acki1; +input acki2; +input acki3; +input acki4; +input acki5; +input acki6; +input acki7; +input ch0_taghit; +input ch1_taghit; +input ch2_taghit; +input ch3_taghit; +input ch4_taghit; +input ch5_taghit; +input ch6_taghit; +input ch7_taghit; +input wdf_rdy; +input rdy; +input do_wr; +input rd_data_valid; +input [5:0] num_strips; +input [5:0] req_strip_cnt; +input [5:0] resp_strip_cnt; +input to; +input cr1; +input cr7; +input [31:0] adr1; +input [31:0] adr7; +input [3:0] resv_ch [0:NAR-1]; +input [31:0] resv_adr [0:NAR-1]; +output reg [3:0] state; + +reg [3:0] next_state; + +// State machine +always_ff @(posedge clk) + state <= next_state; + +integer n3; +always_comb +if (rst) + next_state <= IDLE; +else begin +case(state) +IDLE: + begin + next_state <= IDLE; + // According to the docs there's no need to wait for calib complete. + // Calib complete goes high in sim about 111 us. + // Simulation setting must be set to FAST. + //if (calib_complete) + case(ch) + 3'd0: if (!acki0) next_state <= PRESET1; + 3'd1: + if (!acki1) begin + if (cr1) begin + next_state <= IDLE; + for (n3 = 0; n3 < NAR; n3 = n3 + 1) + if ((resv_ch[n3]==4'd1) && (resv_adr[n3][31:4]==adr1[31:4])) + next_state <= PRESET1; + end + else + next_state <= PRESET1; + end + 3'd2: if (!acki2) next_state <= PRESET1; + 3'd3: if (!acki3) next_state <= PRESET1; + 3'd4: if (!acki4) next_state <= PRESET1; + 3'd5: if (!acki5) next_state <= PRESET1; + 3'd6: if (!acki6) next_state <= PRESET1; + 3'd7: + if (!acki7) begin + if (cr7) begin + next_state <= IDLE; + for (n3 = 0; n3 < NAR; n3 = n3 + 1) + if ((resv_ch[n3]==4'd7) && (resv_adr[n3][31:4]==adr7[31:4])) + next_state <= PRESET1; + end + else + next_state <= PRESET1; + end + default: ; // no channel selected -> stay in IDLE state + endcase + end +// If an ack is received during a preset cycle it is likely a read cycle that +// acked a cycle late. Abort the cycle. +PRESET1: + if (do_wr) + next_state <= PRESET2; + else + case(ch) + 4'd0: if (ch0_taghit) next_state <= IDLE; else next_state <= PRESET2; + 4'd1: if (ch1_taghit) next_state <= IDLE; else next_state <= PRESET2; + 4'd2: if (ch2_taghit) next_state <= IDLE; else next_state <= PRESET2; + 4'd3: if (ch3_taghit) next_state <= IDLE; else next_state <= PRESET2; + 4'd4: if (ch4_taghit) next_state <= IDLE; else next_state <= PRESET2; + 4'd5: if (ch5_taghit) next_state <= IDLE; else next_state <= PRESET2; + 4'd6: if (ch6_taghit) next_state <= IDLE; else next_state <= PRESET2; + 4'd7: if (ch7_taghit) next_state <= IDLE; else next_state <= PRESET2; + default: next_state <= PRESET2; + endcase +// The valid data, data mask and address are placed in app_wdf_data, app_wdf_mask, +// and memm_addr ahead of time. +PRESET2: + if (do_wr) + next_state <= PRESET3; + else + case(ch) + 4'd0: if (ch0_taghit) next_state <= IDLE; else next_state <= PRESET3; + 4'd1: if (ch1_taghit) next_state <= IDLE; else next_state <= PRESET3; + 4'd2: if (ch2_taghit) next_state <= IDLE; else next_state <= PRESET3; + 4'd3: if (ch3_taghit) next_state <= IDLE; else next_state <= PRESET3; + 4'd4: if (ch4_taghit) next_state <= IDLE; else next_state <= PRESET3; + 4'd5: if (ch5_taghit) next_state <= IDLE; else next_state <= PRESET3; + 4'd6: if (ch6_taghit) next_state <= IDLE; else next_state <= PRESET3; + 4'd7: if (ch7_taghit) next_state <= IDLE; else next_state <= PRESET3; + default: next_state <= PRESET3; + endcase +// PRESET3 determines the read or write command +PRESET3: + if (do_wr && !RMW) + next_state <= WRITE_DATA0; + else begin + next_state <= READ_DATA0; + case(ch) + 4'd0: if (ch0_taghit) next_state <= IDLE; else next_state <= READ_DATA0; + 4'd1: if (ch1_taghit) next_state <= IDLE; else next_state <= READ_DATA0; + 4'd2: if (ch2_taghit) next_state <= IDLE; else next_state <= READ_DATA0; + 4'd3: if (ch3_taghit) next_state <= IDLE; else next_state <= READ_DATA0; + 4'd4: if (ch4_taghit) next_state <= IDLE; else next_state <= READ_DATA0; + 4'd5: if (ch5_taghit) next_state <= IDLE; else next_state <= READ_DATA0; + 4'd6: if (ch6_taghit) next_state <= IDLE; else next_state <= READ_DATA0; + 4'd7: if (ch7_taghit) next_state <= IDLE; else next_state <= READ_DATA0; + default: next_state <= READ_DATA0; + endcase + end + +// Write data to the data fifo +// Write occurs when app_wdf_wren is true and app_wdf_rdy is true +WRITE_DATA0: + // Issue a write command if the fifo is full. +// if (!app_wdf_rdy) +// next_state <= WRITE_DATA1; +// else + if (wdf_rdy)// && req_strip_cnt==num_strips) + next_state <= WRITE_DATA1; + else + next_state <= WRITE_DATA0; +WRITE_DATA1: + next_state <= WRITE_DATA2; +WRITE_DATA2: + if (rdy) + next_state <= WRITE_DATA3; + else + next_state <= WRITE_DATA2; +WRITE_DATA3: + next_state <= IDLE; + /* + if (req_strip_cnt==num_strips) + next_state <= IDLE; + else + next_state <= WRITE_DATA0; + */ +// There could be multiple read requests submitted before any response occurs. +// Stay in the SET_CMD_RD until all requested strips have been processed. +READ_DATA0: + next_state <= READ_DATA1; +// Could it take so long to do the request that we start getting responses +// back? +READ_DATA1: + if (rdy && req_strip_cnt==num_strips) + next_state <= READ_DATA2; + else + next_state <= READ_DATA1; +// Wait for incoming responses, but only for so long to prevent a hang. +READ_DATA2: + if (rd_data_valid && resp_strip_cnt==num_strips) + next_state <= WAIT_NACK; + else + next_state <= READ_DATA2; + +WAIT_NACK: + // If we're not seeing a nack and there is a channel selected, then the + // cache tag must not have updated correctly. + // For writes, assume a nack by now. + next_state <= IDLE; + /* + case(ch) + 3'd0: if (ne_acki0) next_state <= IDLE; + 3'd1: if (ne_acki1) next_state <= IDLE; + 3'd2: if (ne_acki2) next_state <= IDLE; + 3'd3: if (ne_acki3) next_state <= IDLE; + 3'd4: if (ne_acki4) next_state <= IDLE; + 3'd5: if (ne_acki5) next_state <= IDLE; + 3'd6: if (ne_acki6) next_state <= IDLE; + 3'd7: if (ne_acki7) next_state <= IDLE; + default: next_state <= IDLE; + endcase + */ +default: next_state <= IDLE; +endcase + +// Is the state machine hung? +if (to) + next_state <= IDLE; +end + +endmodule Index: trunk/rtl/mpmc9_sync.sv =================================================================== --- trunk/rtl/mpmc9_sync.sv (nonexistent) +++ trunk/rtl/mpmc9_sync.sv (revision 4) @@ -0,0 +1,70 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_sync(clk, cs_i, we_i, sel_i, adr_i, dati_i, sr_i, cr_i, + cs_o, we_o, sel_o, adr_o, dati_o, sr_o, cr_o +); +parameter W=128; +input clk; +input cs_i; +input we_i; +input [W/8-1:0] sel_i; +input [31:0] adr_i; +input [W-1:0] dati_i; +input sr_i; +input cr_i; +output reg cs_o; +output reg we_o; +output reg [W/8-1:0] sel_o; +output reg [31:0] adr_o; +output reg [W-1:0] dati_o; +output reg sr_o; +output reg cr_o; + +always_ff @(posedge clk) +begin + cs_o <= cs_i; + we_o <= we_i; + sel_o <= sel_i; + adr_o <= adr_i; + dati_o <= dati_i; + sr_o <= sr_i; + cr_o <= cr_i; +end + +endmodule Index: trunk/rtl/mpmc9_to_cnt.sv =================================================================== --- trunk/rtl/mpmc9_to_cnt.sv (nonexistent) +++ trunk/rtl/mpmc9_to_cnt.sv (revision 4) @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_to_cnt(clk, state, prev_state, to_cnt); +input clk; +input [3:0] state; +input [3:0] prev_state; +output reg [15:0] to_cnt; + +always_ff @(posedge clk) +if (state==IDLE) begin // We can stay in the idle state as long as we like + to_cnt <= 'd0; +end +else begin + if (state==prev_state) begin + to_cnt <= to_cnt+2'd1; + if (to_cnt[9]) + to_cnt <= 'd0; + end +end + +endmodule Index: trunk/rtl/mpmc9_waddr_gen.sv =================================================================== --- trunk/rtl/mpmc9_waddr_gen.sv (nonexistent) +++ trunk/rtl/mpmc9_waddr_gen.sv (revision 4) @@ -0,0 +1,62 @@ +`timescale 1ns / 1ps +// ============================================================================ +// __ +// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +import mpmc9_pkg::*; + +module mpmc9_waddr_gen(rst, clk, state, valid, num_strips, strip_cnt, addr_base, addr); +input rst; +input clk; +input [3:0] state; +input valid; +input [5:0] num_strips; +input [5:0] strip_cnt; +input [31:0] addr_base; +output reg [31:0] addr; + +always_ff @(posedge clk) +if (rst) + addr <= 32'h1FFFFFFF; +else begin + if (state==PRESET2) + addr <= addr_base; + else if (valid && strip_cnt != num_strips) + addr[31:4] <= addr[31:4] + 2'd1; + // Increment the address if we had to start a new burst. +// else if (state==WRITE_DATA3 && req_strip_cnt!=num_strips) +// app_addr <= app_addr + {req_strip_cnt,4'h0}; // works for only 1 missed burst +end + +endmodule Index: trunk/README.md =================================================================== --- trunk/README.md (revision 3) +++ trunk/README.md (revision 4) @@ -1,4 +1,4 @@ -# MPMC8 - Multiport Memory Controller +# MPMC9 - Multiport Memory Controller ## Overview The multi-port memory controller provides eight access ports with either small streaming read caches or a 16kB shared read cache to the ddr3 ram. The multi-port memory controller interfaces between the SoC and a MIG controller. Ports may be customized with parameter settings. Port #5 is setup to handle sprites and is read-only. @@ -33,6 +33,6 @@ ## Parameters STREAMn - cause port number 'n' to use a streaming cache instead of the main cache -STRIPSn - sets the number of memory strips (16 byte accesses) minus 1 for port 'n' to load consecutively (should be 0 (for 1), 1, 3, or 7 (for 8)) +STRIPSn - sets the number of memory strips (16 byte accesses) minus 1 for port 'n' to load consecutively (should be 0 (for 1), 1, 3, 7 (for 8), 63) CnW - sets the data width for the port (Note port #7 C7R must also be set) NAR - sets the number of outstanding address reservation that are present, this should be a small number (eg. 2)

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