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URL https://opencores.org/ocsvn/myblaze/myblaze/trunk

Subversion Repositories myblaze

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  • This comparison shows the changes necessary to convert path
    /myblaze
    from Rev 4 to Rev 5
    Reverse comparison

Rev 4 → Rev 5

/trunk/rtl/core.py
5,9 → 5,9
 
MyBlaze Core, top level entity
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/fetch.py
5,9 → 5,9
 
Fetch Unit
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/gprf.py
5,9 → 5,9
 
General purpose Register File
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/execute.py
5,9 → 5,9
 
Execute Unit
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/lut.py
5,9 → 5,9
 
Lookup tables for sinus and division calculation
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/decoder.py
5,9 → 5,9
 
Instruction Decoder
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/dsram.py
5,9 → 5,9
 
Dual port synchronous ram
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/memory.py
5,9 → 5,9
 
Memory Stage
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/functions.py
5,9 → 5,9
 
Functions
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/uart.py
5,9 → 5,9
 
Simple 3-wire UART
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/defines.py
5,9 → 5,9
 
Constants and Enums
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
/trunk/rtl/bram.py
5,9 → 5,9
 
Block RAM
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:copyright: Copyright (c) 2010 Jian Luo
:author-email: jian.luo.cn(at_)gmail.com
:license: LGPL, see LICENSE for details
:revision: $Id$
"""
 
83,12 → 83,12
width=32,
bank_size=2,
size=16,
to_verilog=False,
to_verilog=1,
filename_pattern='',
):
# XXX: Verilog just don't allow dynamic register slicing
# have to fix ram shape to 4x8bit
if to_verilog:
if to_verilog == 1:
width=32
bank_size=2
bank_count = 2 ** bank_size
123,8 → 123,7
#else:
#print 'READ %x' % int(data_out)
 
#if to_verilog:
if 1:
if to_verilog == 1:
@always_comb
def dumbass_reassemble():
bank_addr.next = address[:bank_size]
/trunk/rtl/debug.py
6,8 → 6,8
Debug functions
:copyright: Copyright (c) 2010 Jian Luo.
:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
:license: BSD, see LICENSE for details.
:author-email: jian.luo.cn(at_)gmail.com.
:license: LGPL, see LICENSE for details.
:revision: $Id$
"""
 
/trunk/rtl/Makefile
1,4 → 1,4
# Makefile by Takar
# Makefile by rockee
 
SRCS=testbench.c
ELFFILE=rom

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