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URL https://opencores.org/ocsvn/mytwoqcache/mytwoqcache/trunk

Subversion Repositories mytwoqcache

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  • This comparison shows the changes necessary to convert path 
    /mytwoqcache/trunk
    from Rev 23 to Rev 24
    ↔ Reverse comparison
  •

Rev 23 → Rev 24

/2QCache.vhd
137,7 → 137,7
signal statetag: tType;
signal stateram: rType;
signal statequeue: fType;
signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag, flag1,
signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag,
interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
signal gal: std_ulogic_vector( 7 downto 0);
 
358,7 → 358,6
accqueue <= '0';
isfull <= '0';
flag <= '0';
flag1 <= '1';
initcount1 <= ( others => '0');
FreeIn <= ( others => '0');
firstf <= ( others => '0');
401,27 → 400,8
stateram <= ramwait;
else
cindex <= FreeOut;
if isfull = '1' then
tagBuff( free).cacheAddr <= FreeOut;
tagBuff( free).cacheValid <= '1';
tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
tagBuff( free).tagValid <= '1';
else
tagRAMOut( free).cacheAddr <= FreeOut;
tagRAMOut( free).cacheValid <= '1';
tagRAMOut( free).tag <= AddressInh( tagRAMOut( free).tag'range);
tagRAMOut( free).tagValid <= '1';
flag1 <= '1';
end if;
isfull <= '0';
getf <= '1';
if IOCodeh = "111" and ldCachedWords = 0 then
stateram <= ramupdate2;
else
readb <= '1';
AddressOut <= AddressInh( AddressOut'range);
stateram <= ramread;
end if;
tagBuff <= tagRAMOut;
stateram <= ramupdate1;
end if;
else
tagBuff <= tagRAMOut;
439,6 → 419,19
en := '1';
if found /= 15 then
stateram <= ramupdate2;
elsif free /= 15 then
tagBuff( free).cacheAddr <= FreeOut;
tagBuff( free).cacheValid <= '1';
tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
tagBuff( free).tagValid <= '1';
getf <= '1';
if IOCodeh = "111" and ldCachedWords = 0 then
stateram <= ramupdate2;
else
readb <= '1';
AddressOut <= AddressInh( AddressOut'range);
stateram <= ramread;
end if;
else
AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
writeb <= '1';
467,10 → 460,6
when ramread =>
readb <= '0';
getf <= '0';
if flag1 = '1' then
tagBuff <= tagRAMOut;
flag1 <= '0';
end if;
stateram <= ramread1;
when ramread1 =>
if readsh = '0' then
480,10 → 469,6
stateram <= ramupdate2;
end if;
when ramupdate2 =>
if flag1 = '1' then
tagBuff <= tagRAMOut;
flag1 <= '0';
end if;
if IOCodeh(2) = '1' then
if IOCodeh(1) = '1' then
If IOCodeh(0) = '1' then
/readme.txt
1,5 → 1,5
Clocks required
hit : 3 + 4 + overhead
load : 3 + 4 + read + overhead
load : 3 + 5 + read + overhead
replace : 3 + 8 + write + read + overhead
overhead from queues (optional) : 5 + write

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