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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:41:47 12/14/2010
-- Design Name:
-- Module Name: Cache - Rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE, work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.global.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/Xilinx/FORTHSP3ADSPC/MYCPU.xst" -ofn "C:/Xilinx/FORTHSP3ADSPC/MYCPU.syr"
Reading design: MYCPU.prj
 
entity Cache is
generic( constant blocksizeld: integer := 11;
constant ldways: integer := 1;
constant ldCachedWords: integer := 2);
port( nReset: in std_ulogic; -- System reset active low
Clock: in std_ulogic; -- System Clock
AddressIn: in std_ulogic_vector(RAMrange'high + 1 downto 0); -- Address of memory fetch
DataIn: in std_ulogic_vector( 31 downto 0); -- Data to write
IOCode: in std_ulogic_vector(2 downto 0); -- operation
-- Bit
-- 2 0 read
-- 1 write
-- 1 0 11 word
-- 10 halfword
-- 01 single byte
-- 00 no operation
DataOut: out std_ulogic_vector( 31 downto 0); -- Data read
done: out std_ulogic;
-- memory interface
AddressOut: out std_ulogic_vector(RAMrange'high downto 0); -- memory address
DataBlockIn: in std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data from memory
reads: out std_ulogic; -- read memory
DataBlockOut: out std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data to memory
Mask: out std_ulogic_vector( 2 ** ldCachedWords * 4 - 1 downto 0); -- enables for each byte active low
writes: out std_ulogic; -- write memory
ack: in std_ulogic -- acknowledge from memory
);
end Cache;
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/global.vhd" in Library work.
Architecture global of Entity global is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_parameters_0.vhd" in Library work.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_s3_dm_iob.vhd" in Library work.
Architecture arc of Entity mig_21_s3_dm_iob is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_s3_dqs_iob.vhd" in Library work.
Architecture arc of Entity mig_21_s3_dqs_iob is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_s3_dq_iob.vhd" in Library work.
Architecture arc of Entity mig_21_s3_dq_iob is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_dqs_delay_0.vhd" in Library work.
Architecture arc_dqs_delay of Entity mig_21_dqs_delay is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_fifo_0_wr_en_0.vhd" in Library work.
Architecture arc of Entity mig_21_fifo_0_wr_en_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_fifo_1_wr_en_0.vhd" in Library work.
Architecture arc of Entity mig_21_fifo_1_wr_en_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_wr_gray_cntr.vhd" in Library work.
Architecture arc of Entity mig_21_wr_gray_cntr is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_rd_gray_cntr.vhd" in Library work.
Architecture arc of Entity mig_21_rd_gray_cntr is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_ram8d_0.vhd" in Library work.
Architecture arc of Entity mig_21_ram8d_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_cal_ctl_0.vhd" in Library work.
Architecture arc_cal_ctl of Entity mig_21_cal_ctl is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_tap_dly.vhd" in Library work.
Architecture arc_tap_dly of Entity mig_21_tap_dly is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_infrastructure_iobs_0.vhd" in Library work.
Architecture arc of Entity mig_21_infrastructure_iobs_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_controller_iobs_0.vhd" in Library work.
Architecture arc of Entity mig_21_controller_iobs_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_path_iobs_0.vhd" in Library work.
Architecture arc of Entity mig_21_data_path_iobs_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_read_0.vhd" in Library work.
Architecture arc of Entity mig_21_data_read_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_read_controller_0.vhd" in Library work.
Architecture arc of Entity mig_21_data_read_controller_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_write_0.vhd" in Library work.
Architecture arc of Entity mig_21_data_write_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_clk_dcm.vhd" in Library work.
Architecture arc of Entity mig_21_clk_dcm is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_cal_top.vhd" in Library work.
Architecture arc of Entity mig_21_cal_top is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_controller_0.vhd" in Library work.
Architecture arc of Entity mig_21_controller_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_path_0.vhd" in Library work.
Architecture arc of Entity mig_21_data_path_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_infrastructure.vhd" in Library work.
Architecture arc of Entity mig_21_infrastructure is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_iobs_0.vhd" in Library work.
Architecture arc of Entity mig_21_iobs_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/ALU.vhd" in Library work.
Architecture rtl of Entity alu is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_top_0.vhd" in Library work.
Architecture arc of Entity mig_21_top_0 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21_infrastructure_top_0.vhd" in Library work.
Architecture arc of Entity mig_21_infrastructure_top is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/fifo_generator_v4_3.vhd" in Library work.
Architecture fifo_generator_v4_3_a of Entity fifo_generator_v4_3 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/theStacks.vhd" in Library work.
Architecture rtl of Entity thestacks is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/ProgramCounter.vhd" in Library work.
Architecture rtl of Entity programcounter is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/dcm1.vhd" in Library work.
Architecture behavioral of Entity dcm1 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/theCore.vhd" in Library work.
Architecture rtl of Entity thecore is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/UART.vhd" in Library work.
Architecture rtl of Entity uart is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/counter.vhd" in Library work.
Architecture rtl of Entity counter is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/IntVectors.vhd" in Library work.
Architecture rtl of Entity intvectors is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/ROMcode.vhd" in Library work.
Architecture rtl of Entity romcode is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mig_21.vhd" in Library work.
Architecture arc_mem_interface_top of Entity mig_21 is up to date.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/Cache.vhd" in Library work.
Entity <cache> compiled.
Entity <cache> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd" in Library work.
WARNING:HDLParsers:3350 - "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd" Line 619. Null range: 7 downto 8
Architecture rtl of Entity mycpu is up to date.
 
architecture Rtl of Cache is
constant ways: integer := 2 ** ldways;
constant ldqueue: integer := 1;
constant ldram: integer := blocksizeld + ldways - 1;
constant ldqueuelength: integer := ldram;
 
type IOType is ( Start, busy);
type tType is ( inittag, startt, startt1, tagtest, tagwait, stateget, stateget1, finish, finished);
type rType is ( raminit, ramstart, ramstart1, ramcheck, ramcheck1, ramcheck2, ramread, ramread1, ramupdate,
ramupdate1, ramupdate2, ramupdate3, ramflush, ramflush1, ramwait, ramwait1, ramclean, ramclean1);
type fType is ( queuestart, queuewait, queuewaitAm1, queuewaitAm2, queuewaitA11, queuewaitA12, queueelim);
subtype myint is natural range 15 downto 0;
type TagRAMType is record
cacheAddr: std_ulogic_vector( ldram - 1 downto 0);
cacheValid: std_ulogic;
Tag: std_ulogic_vector( RAMrange'high downto 2 + ldCachedWords + blocksizeld);
TagValid: std_ulogic;
end record;
type WordType is record
Word: std_ulogic_vector(31 downto 0);
Modified: std_ulogic_vector( 3 downto 0);
end record;
type WordArray is array ( 2 ** ldCachedWords - 1 downto 0) of WordType;
type CacheType is record
Words: WordArray;
FiFoaddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
Am: std_ulogic; -- redifined and renamed
end record;
type FiFoType is record
Word: std_ulogic_vector( blocksizeld - 1 downto 0);
way: std_ulogic_vector( ldways downto 0);
valid: std_ulogic;
end record;
 
type TagRAMarray is array ( ways - 1 downto 0) of TagRAMType;
type TagBuffer is array ( ways - 1 downto 0) of std_ulogic_vector( RAMrange'high - ldCachedWords - blocksizeld - 2 + ldram + 2 downto 0);
type TagFile is array ( 2 ** blocksizeld - 1 downto 0) of std_ulogic_vector( RAMrange'high - ldCachedWords - blocksizeld - 2 + ldram + 2 downto 0);
type TagFiles is array ( ways - 1 downto 0) of TagFile;
 
type RAMFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( 35 downto 0);
type RAMFiles is array ( 2 ** ldCachedWords - 1 downto 0) of RAMFile;
type RAMBuffer is array ( 2 ** ldCachedWords - 1 downto 0) of std_ulogic_vector( 35 downto 0);
type AFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldqueuelength downto 0); -- redimensioned
 
type myarrayf is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldram - 1 downto 0);
type myarrayA is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( blocksizeld + ldways + 1 downto 0);
 
signal RAMs: RAMFiles;
signal Ax: AFile;
signal tagRAM: TagFiles;
signal tagdummy, tagBuff, TagRAMIn, TagRAMOut: TagRAMarray;
signal RecBuff, CacheIn, CacheOut: CacheType;
signal blockIn, blockOut: WordArray;
signal DataInh: std_ulogic_vector( 31 downto 0);
signal A1In, A1Out, AmIn, AmOut: FiFoType;
signal putA1, removeA1, getA1, emptyA1, fullA1: std_ulogic;
signal putAm, removeAm, getAm, emptyAm, fullAm: std_ulogic;
signal A1Inaddr, A1Outaddr, AmInaddr, AmOutaddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
signal emptyf, getf, putf: std_ulogic;
signal cindex, FreeOut, FreeIn: std_ulogic_vector( ldram - 1 downto 0);
signal ramf: myarrayf;
signal counterf: unsigned( ldram downto 0);
signal firstf, lastf: unsigned( ldram - 1 downto 0);
signal newFiFoAddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
signal newAm: std_ulogic; -- redifined and renamed
signal initcount: unsigned( blocksizeld - 1 downto 0);
signal initcount1: unsigned( ldram - 1 downto 0);
signal ramA1: myarrayA;
signal counterA1: unsigned( ldqueuelength downto 0);
signal firstA1, lastA1: unsigned( ldqueuelength - 1 downto 0);
signal ramAm: myarrayA;
signal counterAm: unsigned( ldqueuelength downto 0);
signal firstAm, lastAm: unsigned( ldqueuelength - 1 downto 0);
 
signal AddressInh: std_ulogic_vector( AddressIn'high -1 downto 0);
signal IOCodeh: std_ulogic_vector( IOCode'range);
signal toFlush, AddressInt: std_ulogic_vector( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
signal found, free, elim, del: myint;
signal stateIO: IOType;
signal statetag: tType;
signal stateram: rType;
signal statequeue: fType;
signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted,
interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt: std_ulogic;
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <MYCPU> in library <work> (architecture <rtl>) with generics.
IndexBitWidth = 8
TableBitWidth = 4
 
begin
blockIO: process( nReset, Clock, readb, writeb) is
variable s: std_ulogic;
begin
if nReset /= '1' then
writesh <= '0';
readsh <= '0';
stateIO <= start;
elsif rising_edge(Clock) then
case stateIO is
when start =>
if readb = '1' then
Mask <= ( others => '1');
readsh <= '1';
stateIO <= busy;
elsif writeb = '1' then
s := '0';
for i in blockOut'range loop
DataBlockOut( ( i + 1) * 32 - 1 downto i * 32) <= blockOut( i).word;
Mask( ( i + 1) * 4 - 1 downto i * 4) <= not blockOut( i).Modified;
s := s or blockOut( i).Modified(0) or blockOut( i).Modified(1) or
blockOut( i).Modified(2) or blockOut( i).Modified(3);
end loop;
writesh <= s;
if s = '1' then
stateIO <= busy;
end if;
end if;
when busy =>
if ack = '1' then
stateIO <= start;
 
if readsh = '1' then
for i in blockIn'range loop
blockIn( i).word <= DataBlockIn( ( i + 1) * 32 - 1 downto i * 32);
blockIn( i).Modified <= ( others => '0');
end loop;
end if;
readsh <= '0';
writesh <= '0';
end if;
end case;
end if;
end process blockIO;
writes <= writesh;
reads <= readsh;
tagrams: process ( nReset, Clock) is
variable a, b, d: myint;
variable DataInTag, DataOutTag: TagBuffer;
begin
if rising_edge(Clock) then
if nReset /= '1' then
statetag <= inittag;
writet <= '0';
enableram <= '0';
found <= 15;
free <= 15;
done <= '0'; -- NEW
initcount <= ( others => '0');
AddressInt <= ( others => '0');
IOCodeh <= ( others => '0');
AddressInh <= ( others => '0');
else
case statetag is
when inittag =>
for i in tagRAMIn'range loop
tagRAMIn(i).tagValid <= '0';
tagRAMIn(i).tag <= ( others => '0');
tagRAMIn(i).cacheValid <= '0';
tagRAMIn(i).cacheAddr <= ( others => '0');
end loop;
AddressInt <= std_ulogic_vector(initcount);
initcount <= initcount + 1;
if unsigned( not AddressInt) = 0 then
statetag <= startt;
writet <= '0';
else
writet <= '1';
end if;
when startt =>
if IOCode( 1 downto 0) /= "00" and AddressIn( AddressIn'high) = '0' then
-- request encountered
AddressInh <= AddressIn(AddressInh'range);
IOCodeh <= IOCode;
AddressInt <= AddressIn( AddressInt'range);
DataInh <= DataIn;
statetag <= startt1;
end if;
when startt1 =>
statetag <= tagtest;
when tagtest =>
a := 15;
b := 15;
for i in 0 to TagRAMarray'high loop
if tagRAMOut( i).tagValid = '1' then
if AddressInh(tagRAMout( i).tag'range) = tagRAMout( i).tag then
a := i; -- present
end if;
else
b := i; -- free entry
end if;
end loop;
found <= a;
free <= b;
if stateram = ramstart then
enableram <= '1';
statetag <= tagwait;
end if;
when tagwait =>
writet <= '0';
if interrupt = '1' then
enableram <= '0';
AddressInt <= toFlush;
statetag <= stateget;
elsif queuedone = '1' then
enableram <= '0';
statetag <= finish;
end if;
when stateget =>
statetag <= stateget1;
when stateget1 =>
enableram <= '1';
tagDummy <= tagRAMOut;
for i in tagRAMIn'range loop
if del = i then
tagRAMIn( i).tagvalid <= '0';
tagRAMIn( i).cacheValid <= '0';
tagRAMIn( i).tag <= ( others => '0');
tagRAMIn( i).cacheAddr <= ( others => '0');
writet <= '1';
else
tagRAMIn( i) <= tagRAMOut( i);
end if;
end loop;
statetag <= tagwait;
when finish =>
if doneh = '1' then
tagRAMIn <= tagBuff;
writet <= '1';
AddressInt <= AddressInh( AddressInt'range);
done <= '1';
statetag <= finished;
end if;
when finished => -- NEW
writet <= '0';
done <= '0';
statetag <= startt;
end case;
for i in tagRAM'range loop
DataInTag( i) := TagRAMIn( i).TagValid & TagRAMIn( i).Tag & TagRAMIn( i).cacheValid & TagRAMIn( i).cacheAddr;
if writet = '1' then
tagRAM(i)(to_integer( AddressInt)) <= DataInTag( i);
else
DataOutTag( i) := tagRAM(i)(to_integer( AddressInt));
TagRAMOut( i).cacheAddr <= DataOutTag( i)( ldram - 1 downto 0);
TagRAMOut( i).cacheValid <= DataOutTag( i)( ldram);
TagRAMOut( i).Tag <= DataOutTag( i)( DataOutTag( 0)'high - 1 downto ldram + 1);
TagRAMOut( i).TagValid <= DataOutTag( i)( DataOutTag( 0)'high);
end if;
end loop;
end if;
end if;
end Process tagrams;
dataram: process (nReset, Clock, enableram) is
variable en, acc, hi: std_ulogic;
variable f, g: std_ulogic_vector( CacheIn.FiFoAddr'length downto 0);
variable a, b: RAMBuffer;
variable index, index1: integer;
variable address: std_ulogic_vector( ldram - 1 downto 0);
variable uaddress: unsigned( ldram - 1 downto 0);
variable datum: std_ulogic_vector( FreeIn'range);
variable w: std_ulogic;
begin
if rising_edge(Clock) then
if nReset /= '1' then
enablequeue <= '0';
stateram <= raminit;
writec <= '0';
writeb <= '0';
readb <= '0';
getf <= '0';
doneh <= '0';
elim <= 15;
accinterrupt <= '0';
accqueue <= '0';
initcount1 <= ( others => '0');
FreeIn <= ( others => '0');
firstf <= ( others => '0');
lastf <= ( others => '0');
counterf <= ( others => '0');
else
hi := accinterrupt or interrupt;
acc := accqueue or queuedone;
en := enablequeue and ( hi nor acc);
if ldCachedWords = 0 then
index := 0;
else
index := to_integer( AddressInh( ldCachedWords + 1 downto 2));
end if;
case stateram is
when raminit =>
FreeIn <= std_ulogic_vector( initcount1);
initcount1 <= initcount1 + 1;
if unsigned( not FreeIn) = 0 then
stateram <= ramstart;
putf <= '0';
else
putf <= '1';
end if;
when ramstart =>
putf <= '0';
if enableram = '1' then -- UPDATE
tagBuff <= tagRAMOut;
elim <= 15;
stateram <= ramstart1;
end if;
when ramstart1 =>
putf <= '0';
if enableram = '1' then
if found /= 15 then
cindex <= tagBuff( found).cacheAddr;
writec <= '0';
stateram <= ramupdate;
elsif free /= 15 then
en := '1';
stateram <= ramwait;
else
elim <= 0;
stateram <= ramcheck;
end if;
end if;
when ramcheck =>
writec <= '0';
cindex <= tagBuff( elim).cacheAddr;
stateram <= ramcheck1;
when ramcheck1 =>
stateram <= ramcheck2;
when ramcheck2 =>
if cacheOut.Am = '0' or elim = ways - 1 then
RecBuff <= cacheOut;
en := '1';
stateram <= ramwait;
else
elim <= elim + 1;
stateram <= ramcheck;
end if;
when ramupdate =>
stateram <= ramupdate1;
putf <= '0';
when ramupdate1 =>
cacheIn <= cacheOut;
blockOut <= cacheOut.Words;
RecBuff <= cacheOut;
en := '1';
stateram <= ramwait;
when ramwait =>
doneh <= '0';
writec <= '0';
if hi = '1' then
stateram <= ramwait1;
elsif acc = '1' then
if found /= 15 then
cindex <= tagBuff( found).cacheAddr;
cacheIn <= RecBuff;
blockOut <= RecBuff.Words;
stateram <= ramupdate2;
elsif free /= 15 then
cindex <= FreeOut;
tagBuff( free).cacheAddr <= FreeOut;
tagBuff( free).cacheValid <= '1';
tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
tagBuff( free).tagValid <= '1';
getf <= '1';
if IOCodeh = "111" and ldCachedWords = 0 then
stateram <= ramupdate2;
else
readb <= '1';
AddressOut <= AddressInh( AddressOut'range);
stateram <= ramread;
end if;
else
cindex <= tagBuff( elim).cacheAddr;
cacheIn <= RecBuff;
blockOut <= RecBuff.Words;
AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
writeb <= '1';
stateram <= ramflush;
end if;
end if;
when ramwait1 =>
if del /= 15 and enableram = '1' then
cindex <= tagdummy( del).cacheAddr;
FreeIn <= tagdummy( del).cacheAddr;
putf <= tagdummy( del).cacheValid;
writec <= '0';
stateram <= ramclean;
end if;
when ramread =>
readb <= '0';
getf <= '0';
stateram <= ramread1;
when ramread1 =>
if readsh = '0' then
for i in blockIn'range loop
cacheIn.Words( i) <= blockIn( i);
end loop;
stateram <= ramupdate2;
end if;
when ramupdate2 =>
if IOCodeh(2) = '1' then
if IOCodeh(1) = '1' then
If IOCodeh(0) = '1' then
cacheIn.Words( index).Word <= DataInh;
cacheIn.Words( index).Modified <= "1111";
elsif AddressInh(1) = '1' then
cacheIn.Words( index).Word( 31 downto 16) <= DataInh( 15 downto 0);
cacheIn.Words( index).Modified( 3 downto 2) <= "11";
else
cacheIn.Words( index).Word( 15 downto 0) <= DataInh( 15 downto 0);
cacheIn.Words( index).Modified( 1 downto 0) <= "11";
end if;
else
if AddressInh(1) = '0' then
if AddressInh(0) = '0' then
cacheIn.Words( index).Word( 7 downto 0) <= DataInh( 7 downto 0);
cacheIn.Words( index).Modified(0) <= '1';
else
cacheIn.Words( index).Word( 15 downto 8) <= DataInh( 7 downto 0);
cacheIn.Words( index).Modified(1) <= '1';
end if;
else
if AddressInh(0) = '0' then
cacheIn.Words( index).Word( 23 downto 16) <= DataInh( 7 downto 0);
cacheIn.Words( index).Modified(2) <= '1';
else
cacheIn.Words( index).Word( 31 downto 24) <= DataInh( 7 downto 0);
cacheIn.Words( index).Modified(3) <= '1';
end if;
end if;
end if;
else
DataOut <= cacheIn.Words( index).Word;
end if;
cacheIn.FiFoAddr <= newFiFoAddr;
cacheIn.Am <= newAm;
getf <= '0';
writec <= '1';
doneh <= '1';
stateram <= ramupdate3;
when ramupdate3 =>
hi := '0';
acc := '0';
en := '0';
writec <= '0';
putf <= '0';
doneh <= '0';
stateram <= ramstart;
when ramclean =>
putf <= '0';
stateram <= ramclean1;
when ramclean1 =>
if del /= 15 then
blockOut <= cacheOut.words;
writeb <= tagdummy( del).tagValid;
AddressOut <= tagdummy( del).tag & toFlush & ( ldCachedWords + 1 downto 0 => '0');
stateram <= ramflush;
end if;
when ramflush =>
writeb <= '0';
for i in blockIn'range loop
cacheIn.Words( i).Word <= ( others => '0');
cacheIn.Words( i).Modified <= ( others => '0');
end loop;
stateram <= ramflush1;
when ramflush1 =>
if writesh = '0' then
if del /= 15 and hi = '1' then
doneh <= '1';
en := '1';
hi := '0';
stateram <= ramwait;
else
tagBuff( elim).tag <= AddressInh( tagBuff( elim).tag'range);
tagBuff( elim).tagValid <= '1';
if IOCodeh = "111" and ldCachedWords = 0 then
stateram <= ramupdate2;
else
readb <= '1';
AddressOut <= AddressInh( AddressOut'range);
stateram <= ramread;
end if;
end if;
end if;
end case;
accinterrupt <= hi;
enablequeue <= en;
accqueue <= acc;
f := CacheIn.Am & CacheIn.FiFoAddr;
if writec = '1' then
Ax( to_integer( cindex)) <= f;
else
g := Ax( to_integer( cindex));
CacheOut.FiFoAddr <= g( g'high - 1 downto g'low);
CacheOut.Am <= g( g'high);
end if;
for i in RAMBuffer'range loop
a( i) := CacheIn.Words( i).Modified & CacheIn.Words( i).Word;
if writec = '1' then
RAMs( i)( to_integer( cindex)) <= a( i);
else
b( i) := RAMs( i)( to_integer( cindex));
CacheOut.Words( i).Word <= b( i)( 31 downto 0);
CacheOut.Words( i).Modified <= b( i)( 35 downto 32);
end if;
end loop;
if putf = '1' then
address := std_ulogic_vector( firstf);
datum := FreeIn;
firstf <= firstf + 1;
counterf <= counterf + 1;
w := '1';
else
uaddress := lastf;
if getf = '1' and counterf /= 0 then
counterf <= counterf - 1;
uaddress := uaddress + 1;
end if;
lastf <= uaddress;
address := std_ulogic_vector( uaddress);
w := '0';
end if;
if w = '1' then
ramf( to_integer( address)) <= datum;
else
FreeOut <= ramf( to_integer( address));
end if;
end if;
end if;
end process dataram;
emptyf <= '1' when counterf = 0 else '0';
queues: process( nReset, Clock, enablequeue) is
variable acc, hi: std_ulogic;
variable A1OutBuff, AmOutBuff: std_ulogic_vector( blocksizeld + ldways + 1 downto 0);
variable addressA1: std_ulogic_vector( ldqueuelength - 1 downto 0);
variable diff, uaddressA1: unsigned( ldqueuelength - 1 downto 0);
variable datumA1: std_ulogic_vector( A1OutBuff'range);
variable wA1: std_ulogic;
variable addressAm: std_ulogic_vector( ldqueuelength - 1 downto 0);
variable uaddressAm: unsigned( ldqueuelength - 1 downto 0);
variable datumAm: std_ulogic_vector( AmOutBuff'range);
variable wAm: std_ulogic;
begin
if rising_edge(Clock) then
if nReset /= '1' then
del <= 15;
statequeue <= queuestart;
queuedone <= '0';
interrupt <= '0';
accdone <= '0';
preempted <= '0';
firstA1 <= ( others => '0');
A1Outaddr <= ( others => '0');
lastA1 <= ( others => '0');
counterA1 <= ( others => '0');
firstAm <= ( others => '0');
AmOutaddr <= ( others => '0');
lastAm <= ( others => '0');
counterAm <= ( others => '0');
else
hi := '0';
acc := accdone or doneh;
diff := firstA1 - unsigned( RecBuff.FiFoAddr);
case statequeue is
when queuestart =>
getA1 <= '0';
if enablequeue = '1' then
if found /= 15 then
if RecBuff.Am = '1' or -- in Am
( RecBuff.Am = '0' and diff( diff'high) = '0') then -- in lower half of A1
queuedone <= '1';
newFiFoAddr <= RecBuff.FiFoAddr;
newAm <= RecBuff.Am;
statequeue <= queuewait;
elsif fullAm = '1' then
-- Am full
if AmOut.valid = '1' then
del <= to_integer( AmOut.way);
toFlush <= AmOut.word;
getAm <= '1';
hi := '1';
statequeue <= queuewait;
end if;
else
AmIn.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
AmIn.way <= std_ulogic_vector(to_unsigned( found, ldways + 1));
AmIn.valid <= '1';
putAm <= '1';
A1Inaddr <= RecBuff.FiFoAddr;
removeA1 <= '1';
statequeue <= queuewaitAm1;
end if;
elsif free /= 15 then
if fullA1 = '1' or (emptyf = '1' and emptyA1 = '0') then
-- remove last entry from A1
if A1Out.valid = '1' then
del <= to_integer( A1Out.way);
toFlush <= A1Out.word;
getA1 <= '1';
hi := '1';
statequeue <= queuewait;
end if;
elsif fullAm = '1' and emptyf = '1' then
-- remove last entry from Am
if AmOut.valid = '1' then
del <= to_integer( AmOut.way);
toFlush <= AmOut.word;
getAm <= '1';
hi := '1';
statequeue <= queuewait;
end if;
else
A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
A1In.way <= std_ulogic_vector(to_unsigned( free, ldways + 1));
A1In.valid <= '1';
putA1 <= '1';
statequeue <= queuewaitA11;
end if;
elsif elim /= 15 then
if fullA1 = '1' then
if A1Out.valid = '1' then
if not ( to_integer( A1Out.way) = elim and
A1Out.word = AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords)) then
del <= to_integer( A1Out.way);
toFlush <= A1Out.word;
statequeue <= queueelim;
end if;
getA1 <= '1';
end if;
else
getA1 <= '0'; -- NEW, inserted the only bug!!!!!!!!!!!!!!
A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
A1In.way <= std_ulogic_vector(to_unsigned( elim, ldways + 1));
A1In.valid <= '1';
putA1 <= '1';
statequeue <= queueelim;
end if;
end if;
end if;
when queuewait =>
removeA1 <= '0';
removeAm <= '0';
getAm <= '0';
getA1 <= '0';
queuedone <= '0';
if acc = '1' then
acc := '0';
del <= 15;
statequeue <= queuestart;
end if;
when queuewaitAm1 =>
putAm <= '0';
removeA1 <= '0';
statequeue <= queuewaitAm2;
when queuewaitAm2 =>
newFiFoAddr <= AmOutAddr;
newAm <= '1';
queuedone <= '1';
statequeue <= queuewait;
when queuewaitA11 =>
putA1 <= '0';
statequeue <= queuewaitA12;
when queuewaitA12 =>
newFiFoAddr <= A1OutAddr;
newAm <= '0';
removeA1 <= '0';
removeAm <= '0';
queuedone <= '1';
preempted <= '0';
statequeue <= queuewait;
when queueelim =>
putA1 <= '0';
getA1 <= '0';
if RecBuff.Am = '1' and preempted = '0' then
AmInAddr <= RecBuff.FiFoAddr;
removeAm <= '1';
elsif preempted = '0' then
A1InAddr <= RecBuff.FiFoAddr;
removeA1 <= '1';
end if;
if getA1 = '1' then
hi := '1';
preempted <= '1';
statequeue <= queuewait;
else
statequeue <= queuewaitA12;
end if;
end case;
interrupt <= hi;
accdone <= acc;
if putA1 = '1' or removeA1 = '1' then
if removeA1 = '0' then
addressA1 := std_ulogic_vector( firstA1);
datumA1 := A1In.valid & A1In.way & A1In.Word;
firstA1 <= firstA1 + 1;
counterA1 <= counterA1 + 1;
A1Outaddr <= std_ulogic_vector( firstA1);
else
addressA1 := A1Inaddr( addressA1'range);
datumA1 := ( others => '0');
end if;
wA1 := '1';
else
uaddressA1 := lastA1;
if (getA1 = '1' or A1Out.valid = '0') and counterA1 /= 0 then
counterA1 <= counterA1 - 1;
uaddressA1 := uaddressA1 + 1;
end if;
lastA1 <= uaddressA1;
addressA1 := std_ulogic_vector( uaddressA1);
wA1 := '0';
end if;
if wA1 = '1' then
ramA1( to_integer( addressA1)) <= datumA1;
else
A1OutBuff := ramA1( to_integer( addressA1));
 
A1Out.Word <= A1OutBuff( blocksizeld - 1 downto 0);
A1Out.way <= A1OutBuff( blocksizeld + ldways downto blocksizeld);
A1Out.valid <= A1OutBuff( blocksizeld + ldways + 1);
end if;
if putAm = '1' or removeAm = '1' then
if removeAm = '0' then
addressAm := std_ulogic_vector( firstAm);
datumAm := AmIn.valid & AmIn.way & AmIn.Word;
firstAm <= firstAm + 1;
counterAm <= counterAm + 1;
AmOutaddr <= std_ulogic_vector( firstAm);
else
addressAm := AmInaddr( addressAm'range);
datumAm := ( others => '0');
end if;
wAm := '1';
else
uaddressAm := lastAm;
if (getAm = '1' or AmOut.valid = '0') and counterAm /= 0 then
counterAm <= counterAm - 1;
uaddressAm := uaddressAm + 1;
end if;
lastAm <= uaddressAm;
addressAm := std_ulogic_vector( uaddressAm);
wAm := '0';
end if;
if wAm = '1' then
ramAm( to_integer( addressAm)) <= datumAm;
else
AmOutBuff := ramAm( to_integer( addressAm));
AmOut.Word <= AmOutBuff( blocksizeld - 1 downto 0);
AmOut.way <= AmOutBuff( blocksizeld + ldways downto blocksizeld);
AmOut.valid <= AmOutBuff( blocksizeld + ldways + 1);
end if;
end if;
end if;
end process queues;
 
fullA1 <= counterA1( counterA1'high);
emptyA1 <= '1' when counterA1 = 0 else '0';
 
fullAm <= counterAm( counterAm'high);
emptyAm <= '1' when counterAm = 0 else '0';
 
end Rtl;
Analyzing hierarchy for entity <dcm1> in library <work> (architecture <BEHAVIORAL>) with generics.
basefrequency = 125000000
divisor = 25
multiplicator = 12
 
Analyzing hierarchy for entity <theCore> in library <work> (architecture <Rtl>) with generics.
CacheIndexBitWidth = 8
TableBitWidth = 4
 
Analyzing hierarchy for entity <UART> in library <work> (architecture <Rtl>).
 
Analyzing hierarchy for entity <counter> in library <work> (architecture <Rtl>).
 
Analyzing hierarchy for entity <IntVectors> in library <work> (architecture <Rtl>) with generics.
TableBitWidth = 4
 
Analyzing hierarchy for entity <ROMcode> in library <work> (architecture <Rtl>).
 
Analyzing hierarchy for entity <mig_21> in library <work> (architecture <arc_mem_interface_top>).
 
Analyzing hierarchy for entity <Cache> in library <work> (architecture <Rtl>) with generics.
blocksizeld = 12
ldCachedWords = 1
ldways = 1
 
Analyzing hierarchy for entity <theStacks> in library <work> (architecture <Rtl>) with generics.
CacheIndexBitWidth = 8
 
Analyzing hierarchy for entity <ProgramCounter> in library <work> (architecture <Rtl>) with generics.
TableBitWidth = 4
 
Analyzing hierarchy for entity <mig_21_top_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_infrastructure_top> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <ALU> in library <work> (architecture <Rtl>).
 
Analyzing hierarchy for entity <mig_21_controller_0> in library <work> (architecture <arc>) with generics.
COL_WIDTH = 10
ROW_WIDTH = 13
 
Analyzing hierarchy for entity <mig_21_data_path_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_infrastructure> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_iobs_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_clk_dcm> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_cal_top> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_data_read_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_data_read_controller_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_data_write_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_infrastructure_iobs_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_controller_iobs_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_data_path_iobs_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_cal_ctl> in library <work> (architecture <arc_cal_ctl>).
 
Analyzing hierarchy for entity <mig_21_tap_dly> in library <work> (architecture <arc_tap_dly>).
 
Analyzing hierarchy for entity <mig_21_rd_gray_cntr> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_ram8d_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_dqs_delay> in library <work> (architecture <arc_dqs_delay>).
 
Analyzing hierarchy for entity <mig_21_dqs_delay> in library <work> (architecture <arc_dqs_delay>).
 
Analyzing hierarchy for entity <mig_21_fifo_0_wr_en_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_fifo_1_wr_en_0> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_wr_gray_cntr> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_s3_dm_iob> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_s3_dqs_iob> in library <work> (architecture <arc>).
 
Analyzing hierarchy for entity <mig_21_s3_dq_iob> in library <work> (architecture <arc>).
 
 
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing generic Entity <MYCPU> in library <work> (Architecture <rtl>).
IndexBitWidth = 8
TableBitWidth = 4
WARNING:Xst:753 - "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd" line 381: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'dcm1'.
WARNING:Xst:753 - "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd" line 381: Unconnected output port 'CLK0_OUT' of component 'dcm1'.
WARNING:Xst:753 - "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd" line 415: Unconnected output port 'RTS' of component 'UART'.
WARNING:Xst:753 - "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd" line 477: Unconnected output port 'cntrl0_clk_tb' of component 'mig_21'.
WARNING:Xst:753 - "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd" line 477: Unconnected output port 'cntrl0_sys_rst90_tb' of component 'mig_21'.
WARNING:Xst:753 - "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd" line 477: Unconnected output port 'cntrl0_sys_rst180_tb' of component 'mig_21'.
INFO:Xst:2679 - Register <pattern> in unit <MYCPU> has a constant value of 11111111 during circuit operation. The register is replaced by logic.
Entity <MYCPU> analyzed. Unit <MYCPU> generated.
 
Analyzing generic Entity <dcm1> in library <work> (Architecture <BEHAVIORAL>).
basefrequency = 125000000
divisor = 25
multiplicator = 12
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <dcm1>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <CLKIN_IBUFG_INST> in unit <dcm1>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <CLKIN_IBUFG_INST> in unit <dcm1>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <dcm1>.
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "CLKFX_DIVIDE = 25" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "CLKFX_MULTIPLY = 12" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "CLKIN_PERIOD = 8.0000000000000000" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "CLK_FEEDBACK = 1X" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "DSS_MODE = NONE" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "FACTORY_JF = C080" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "PHASE_SHIFT = 0" for instance <DCM_SP_INST> in unit <dcm1>.
Set user-defined property "STARTUP_WAIT = FALSE" for instance <DCM_SP_INST> in unit <dcm1>.
Entity <dcm1> analyzed. Unit <dcm1> generated.
 
Analyzing generic Entity <theCore> in library <work> (Architecture <Rtl>).
CacheIndexBitWidth = 8
TableBitWidth = 4
Entity <theCore> analyzed. Unit <theCore> generated.
 
Analyzing generic Entity <theStacks> in library <work> (Architecture <Rtl>).
CacheIndexBitWidth = 8
Entity <theStacks> analyzed. Unit <theStacks> generated.
 
Analyzing Entity <ALU> in library <work> (Architecture <Rtl>).
Entity <ALU> analyzed. Unit <ALU> generated.
 
Analyzing generic Entity <ProgramCounter> in library <work> (Architecture <Rtl>).
TableBitWidth = 4
Entity <ProgramCounter> analyzed. Unit <ProgramCounter> generated.
 
Analyzing Entity <UART> in library <work> (Architecture <Rtl>).
WARNING:Xst:2211 - "C:/Xilinx/FORTHSP3ADSPC/UART.vhd" line 140: Instantiating black box module <fifo_generator_v4_3>.
WARNING:Xst:2211 - "C:/Xilinx/FORTHSP3ADSPC/UART.vhd" line 157: Instantiating black box module <fifo_generator_v4_3>.
Entity <UART> analyzed. Unit <UART> generated.
 
Analyzing Entity <counter> in library <work> (Architecture <Rtl>).
Entity <counter> analyzed. Unit <counter> generated.
 
Analyzing generic Entity <IntVectors> in library <work> (Architecture <Rtl>).
TableBitWidth = 4
Entity <IntVectors> analyzed. Unit <IntVectors> generated.
 
Analyzing Entity <ROMcode> in library <work> (Architecture <Rtl>).
Entity <ROMcode> analyzed. Unit <ROMcode> generated.
 
Analyzing Entity <mig_21> in library <work> (Architecture <arc_mem_interface_top>).
Entity <mig_21> analyzed. Unit <mig_21> generated.
 
Analyzing Entity <mig_21_top_0> in library <work> (Architecture <arc>).
Entity <mig_21_top_0> analyzed. Unit <mig_21_top_0> generated.
 
Analyzing generic Entity <mig_21_controller_0> in library <work> (Architecture <arc>).
COL_WIDTH = 10
ROW_WIDTH = 13
Set property "syn_preserve = TRUE" for signal <ba_address_reg1>.
Set property "syn_preserve = TRUE" for signal <ba_address_reg2>.
Set property "syn_preserve = TRUE" for signal <column_address_reg>.
Set property "syn_preserve = TRUE" for signal <row_address_reg>.
Set property "syn_preserve = TRUE" for signal <lmr_dll_rst>.
Set property "syn_preserve = TRUE" for signal <lmr_dll_set>.
Set user-defined property "INIT = 0" for instance <ACK_REG_INST1> in unit <mig_21_controller_0>.
INFO:Xst:1561 - "C:/Xilinx/FORTHSP3ADSPC/mig_21_controller_0.vhd" line 1108: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Xilinx/FORTHSP3ADSPC/mig_21_controller_0.vhd" line 1135: Mux is complete : default of case is discarded
Set user-defined property "INIT = 0" for instance <rst_iob_out> in unit <mig_21_controller_0>.
Set user-defined property "IOB = true" for instance <rst_iob_out> in unit <mig_21_controller_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
INFO:Xst:2679 - Register <ddr_odt2> in unit <mig_21_controller_0> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <mig_21_controller_0> analyzed. Unit <mig_21_controller_0> generated.
 
Analyzing Entity <mig_21_data_path_0> in library <work> (Architecture <arc>).
Entity <mig_21_data_path_0> analyzed. Unit <mig_21_data_path_0> generated.
 
Analyzing Entity <mig_21_data_read_0> in library <work> (Architecture <arc>).
WARNING:Xst:39 - Property "optimize_primitives" not applicable on a signal.
Set property "syn_preserve = TRUE" for signal <fifo0_rd_addr_r>.
WARNING:Xst:39 - Property "optimize_primitives" not applicable on a signal.
Set property "syn_preserve = TRUE" for signal <fifo1_rd_addr_r>.
Entity <mig_21_data_read_0> analyzed. Unit <mig_21_data_read_0> generated.
 
Analyzing Entity <mig_21_rd_gray_cntr> in library <work> (Architecture <arc>).
INFO:Xst:1561 - "C:/Xilinx/FORTHSP3ADSPC/mig_21_rd_gray_cntr.vhd" line 110: Mux is complete : default of case is discarded
Set user-defined property "INIT = 0" for instance <bit0> in unit <mig_21_rd_gray_cntr>.
Set user-defined property "INIT = 0" for instance <bit1> in unit <mig_21_rd_gray_cntr>.
Set user-defined property "INIT = 0" for instance <bit2> in unit <mig_21_rd_gray_cntr>.
Set user-defined property "INIT = 0" for instance <bit3> in unit <mig_21_rd_gray_cntr>.
Entity <mig_21_rd_gray_cntr> analyzed. Unit <mig_21_rd_gray_cntr> generated.
 
Analyzing Entity <mig_21_ram8d_0> in library <work> (Architecture <arc>).
Set user-defined property "INIT = 0000" for instance <fifo_bit0> in unit <mig_21_ram8d_0>.
Set user-defined property "INIT = 0000" for instance <fifo_bit1> in unit <mig_21_ram8d_0>.
Set user-defined property "INIT = 0000" for instance <fifo_bit2> in unit <mig_21_ram8d_0>.
Set user-defined property "INIT = 0000" for instance <fifo_bit3> in unit <mig_21_ram8d_0>.
Set user-defined property "INIT = 0000" for instance <fifo_bit4> in unit <mig_21_ram8d_0>.
Set user-defined property "INIT = 0000" for instance <fifo_bit5> in unit <mig_21_ram8d_0>.
Set user-defined property "INIT = 0000" for instance <fifo_bit6> in unit <mig_21_ram8d_0>.
Set user-defined property "INIT = 0000" for instance <fifo_bit7> in unit <mig_21_ram8d_0>.
Entity <mig_21_ram8d_0> analyzed. Unit <mig_21_ram8d_0> generated.
 
Analyzing Entity <mig_21_data_read_controller_0> in library <work> (Architecture <arc>).
Set property "buffer_type = none" for signal <dqs_delayed_col0>.
Set property "buffer_type = none" for signal <dqs_delayed_col1>.
Set user-defined property "syn_preserve = TRUE" for instance <gen_delay[0].dqs_delay_col0> in unit <mig_21_data_read_controller_0>.
Set user-defined property "syn_preserve = TRUE" for instance <gen_delay[0].dqs_delay_col1> in unit <mig_21_data_read_controller_0>.
Set user-defined property "syn_preserve = TRUE" for instance <gen_delay[1].dqs_delay_col0> in unit <mig_21_data_read_controller_0>.
Set user-defined property "syn_preserve = TRUE" for instance <gen_delay[1].dqs_delay_col1> in unit <mig_21_data_read_controller_0>.
Set user-defined property "syn_preserve = TRUE" for instance <gen_delay[2].dqs_delay_col0> in unit <mig_21_data_read_controller_0>.
Set user-defined property "syn_preserve = TRUE" for instance <gen_delay[2].dqs_delay_col1> in unit <mig_21_data_read_controller_0>.
Set user-defined property "syn_preserve = TRUE" for instance <gen_delay[3].dqs_delay_col0> in unit <mig_21_data_read_controller_0>.
Set user-defined property "syn_preserve = TRUE" for instance <gen_delay[3].dqs_delay_col1> in unit <mig_21_data_read_controller_0>.
Entity <mig_21_data_read_controller_0> analyzed. Unit <mig_21_data_read_controller_0> generated.
 
Analyzing Entity <mig_21_dqs_delay.1> in library <work> (Architecture <arc_dqs_delay>).
Set user-defined property "INIT = F3C0" for instance <one> in unit <mig_21_dqs_delay.1>.
Set property "syn_noprune = TRUE" for instance <one> in unit <mig_21_dqs_delay.1>.
Set user-defined property "INIT = EE22" for instance <two> in unit <mig_21_dqs_delay.1>.
Set property "syn_noprune = TRUE" for instance <two> in unit <mig_21_dqs_delay.1>.
Set user-defined property "INIT = E2E2" for instance <three> in unit <mig_21_dqs_delay.1>.
Set property "syn_noprune = TRUE" for instance <three> in unit <mig_21_dqs_delay.1>.
Set user-defined property "INIT = FF00" for instance <four> in unit <mig_21_dqs_delay.1>.
Set property "syn_noprune = TRUE" for instance <four> in unit <mig_21_dqs_delay.1>.
Set user-defined property "INIT = F3C0" for instance <five> in unit <mig_21_dqs_delay.1>.
Set property "syn_noprune = TRUE" for instance <five> in unit <mig_21_dqs_delay.1>.
Set user-defined property "INIT = E2E2" for instance <six> in unit <mig_21_dqs_delay.1>.
Set property "syn_noprune = TRUE" for instance <six> in unit <mig_21_dqs_delay.1>.
Entity <mig_21_dqs_delay.1> analyzed. Unit <mig_21_dqs_delay.1> generated.
 
Analyzing Entity <mig_21_dqs_delay.2> in library <work> (Architecture <arc_dqs_delay>).
Set user-defined property "INIT = F3C0" for instance <one> in unit <mig_21_dqs_delay.2>.
Set property "syn_noprune = TRUE" for instance <one> in unit <mig_21_dqs_delay.2>.
Set user-defined property "INIT = EE22" for instance <two> in unit <mig_21_dqs_delay.2>.
Set property "syn_noprune = TRUE" for instance <two> in unit <mig_21_dqs_delay.2>.
Set user-defined property "INIT = E2E2" for instance <three> in unit <mig_21_dqs_delay.2>.
Set property "syn_noprune = TRUE" for instance <three> in unit <mig_21_dqs_delay.2>.
Set user-defined property "INIT = FF00" for instance <four> in unit <mig_21_dqs_delay.2>.
Set property "syn_noprune = TRUE" for instance <four> in unit <mig_21_dqs_delay.2>.
Set user-defined property "INIT = F3C0" for instance <five> in unit <mig_21_dqs_delay.2>.
Set property "syn_noprune = TRUE" for instance <five> in unit <mig_21_dqs_delay.2>.
Set user-defined property "INIT = E2E2" for instance <six> in unit <mig_21_dqs_delay.2>.
Set property "syn_noprune = TRUE" for instance <six> in unit <mig_21_dqs_delay.2>.
Entity <mig_21_dqs_delay.2> analyzed. Unit <mig_21_dqs_delay.2> generated.
 
Analyzing Entity <mig_21_fifo_0_wr_en_0> in library <work> (Architecture <arc>).
Set user-defined property "KEEP_HIERARCHY = YES" for unit <mig_21_fifo_0_wr_en_0>.
Set user-defined property "INIT = 0" for instance <delay_ff> in unit <mig_21_fifo_0_wr_en_0>.
Entity <mig_21_fifo_0_wr_en_0> analyzed. Unit <mig_21_fifo_0_wr_en_0> generated.
 
Analyzing Entity <mig_21_fifo_1_wr_en_0> in library <work> (Architecture <arc>).
Set user-defined property "KEEP_HIERARCHY = YES" for unit <mig_21_fifo_1_wr_en_0>.
Set user-defined property "INIT = 0" for instance <delay_ff_1> in unit <mig_21_fifo_1_wr_en_0>.
Entity <mig_21_fifo_1_wr_en_0> analyzed. Unit <mig_21_fifo_1_wr_en_0> generated.
 
Analyzing Entity <mig_21_wr_gray_cntr> in library <work> (Architecture <arc>).
Set user-defined property "KEEP_HIERARCHY = YES" for unit <mig_21_wr_gray_cntr>.
INFO:Xst:1561 - "C:/Xilinx/FORTHSP3ADSPC/mig_21_wr_gray_cntr.vhd" line 104: Mux is complete : default of case is discarded
Set user-defined property "INIT = 0" for instance <bit0> in unit <mig_21_wr_gray_cntr>.
Set user-defined property "INIT = 0" for instance <bit1> in unit <mig_21_wr_gray_cntr>.
Set user-defined property "INIT = 0" for instance <bit2> in unit <mig_21_wr_gray_cntr>.
Set user-defined property "INIT = 0" for instance <bit3> in unit <mig_21_wr_gray_cntr>.
Entity <mig_21_wr_gray_cntr> analyzed. Unit <mig_21_wr_gray_cntr> generated.
 
Analyzing Entity <mig_21_data_write_0> in library <work> (Architecture <arc>).
Set property "syn_preserve = TRUE" for signal <write_data0>.
Set property "syn_preserve = TRUE" for signal <write_data1>.
Set property "syn_preserve = TRUE" for signal <write_data2>.
Set property "syn_preserve = TRUE" for signal <write_data3>.
Set property "syn_preserve = TRUE" for signal <write_data4>.
Set property "syn_preserve = TRUE" for signal <write_data_m0>.
Set property "syn_preserve = TRUE" for signal <write_data_m1>.
Set property "syn_preserve = TRUE" for signal <write_data_m2>.
Set property "syn_preserve = TRUE" for signal <write_data_m3>.
Set property "syn_preserve = TRUE" for signal <write_data_m4>.
Set property "syn_preserve = TRUE" for signal <write_data90>.
Set property "syn_preserve = TRUE" for signal <write_data90_1>.
Set property "syn_preserve = TRUE" for signal <write_data90_2>.
Set property "syn_preserve = TRUE" for signal <write_data270>.
Set property "syn_preserve = TRUE" for signal <write_data270_1>.
Set property "syn_preserve = TRUE" for signal <write_data270_2>.
Entity <mig_21_data_write_0> analyzed. Unit <mig_21_data_write_0> generated.
 
Analyzing Entity <mig_21_infrastructure> in library <work> (Architecture <arc>).
Entity <mig_21_infrastructure> analyzed. Unit <mig_21_infrastructure> generated.
 
Analyzing Entity <mig_21_iobs_0> in library <work> (Architecture <arc>).
Entity <mig_21_iobs_0> analyzed. Unit <mig_21_iobs_0> generated.
 
Analyzing Entity <mig_21_infrastructure_iobs_0> in library <work> (Architecture <arc>).
Set user-defined property "INIT = 0" for instance <gen_clk[0].U_inst> in unit <mig_21_infrastructure_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_clk[1].U_inst> in unit <mig_21_infrastructure_iobs_0>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_clk_obufds[0].r_inst> in unit <mig_21_infrastructure_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_clk_obufds[0].r_inst> in unit <mig_21_infrastructure_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_clk_obufds[0].r_inst> in unit <mig_21_infrastructure_iobs_0>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_clk_obufds[1].r_inst> in unit <mig_21_infrastructure_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_clk_obufds[1].r_inst> in unit <mig_21_infrastructure_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_clk_obufds[1].r_inst> in unit <mig_21_infrastructure_iobs_0>.
Entity <mig_21_infrastructure_iobs_0> analyzed. Unit <mig_21_infrastructure_iobs_0> generated.
 
Analyzing Entity <mig_21_controller_iobs_0> in library <work> (Architecture <arc>).
Set user-defined property "INIT = 0" for instance <iob_web> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <iob_web> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "INIT = 0" for instance <iob_rasb> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <iob_rasb> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "INIT = 0" for instance <iob_casb> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <iob_casb> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <r16> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <r16> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <r16> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <r16> in unit <mig_21_controller_iobs_0>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <r17> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <r17> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <r17> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <r17> in unit <mig_21_controller_iobs_0>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <r18> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <r18> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <r18> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <r18> in unit <mig_21_controller_iobs_0>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <r19> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <r19> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <r19> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <r19> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <iob_cke1> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <iob_cke> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <iob_cke> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <r20> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <r20> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <r20> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <r20> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <iob_odt> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <iob_odt> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <ODT_iob_obuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <ODT_iob_obuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <ODT_iob_obuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <ODT_iob_obuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[12].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[12].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[12].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[12].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[12].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[12].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[11].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[11].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[11].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[11].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[11].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[11].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[10].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[10].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[10].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[10].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[10].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[10].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[9].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[9].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[9].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[9].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[9].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[9].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[8].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[8].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[8].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[8].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[8].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[8].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[7].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[7].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[7].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[7].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[7].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[7].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[6].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[6].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[6].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[6].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[6].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[6].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[5].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[5].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[5].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[5].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[5].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[5].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[4].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[4].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[4].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[4].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[4].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[4].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[3].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[3].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[3].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[3].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[3].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[3].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[2].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[2].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[2].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[2].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[2].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[2].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[1].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[1].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[1].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[1].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[1].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[1].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_addr[0].iob_addr> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_addr[0].iob_addr> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_addr[0].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_addr[0].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_addr[0].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_addr[0].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_ba[1].iob_ba> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_ba[1].iob_ba> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_ba[1].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_ba[1].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_ba[1].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_ba[1].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "INIT = 0" for instance <gen_ba[0].iob_ba> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOB = true" for instance <gen_ba[0].iob_ba> in unit <mig_21_controller_iobs_0>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_ba[0].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <gen_ba[0].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <gen_ba[0].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <gen_ba[0].r> in unit <mig_21_controller_iobs_0>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <rst_iob_inbuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <rst_iob_inbuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <rst_iob_inbuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <rst_iob_inbuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <rst_iob_inbuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <rst_iob_outbuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "DRIVE = 12" for instance <rst_iob_outbuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <rst_iob_outbuf> in unit <mig_21_controller_iobs_0>.
Set user-defined property "SLEW = SLOW" for instance <rst_iob_outbuf> in unit <mig_21_controller_iobs_0>.
Entity <mig_21_controller_iobs_0> analyzed. Unit <mig_21_controller_iobs_0> generated.
 
Analyzing Entity <mig_21_data_path_iobs_0> in library <work> (Architecture <arc>).
Entity <mig_21_data_path_iobs_0> analyzed. Unit <mig_21_data_path_iobs_0> generated.
 
Analyzing Entity <mig_21_s3_dm_iob> in library <work> (Architecture <arc>).
Set user-defined property "INIT = 0" for instance <DDR_DM0_OUT> in unit <mig_21_s3_dm_iob>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <DM1_OBUF> in unit <mig_21_s3_dm_iob>.
Set user-defined property "DRIVE = 12" for instance <DM1_OBUF> in unit <mig_21_s3_dm_iob>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <DM1_OBUF> in unit <mig_21_s3_dm_iob>.
Set user-defined property "SLEW = SLOW" for instance <DM1_OBUF> in unit <mig_21_s3_dm_iob>.
Entity <mig_21_s3_dm_iob> analyzed. Unit <mig_21_s3_dm_iob> generated.
 
Analyzing Entity <mig_21_s3_dqs_iob> in library <work> (Architecture <arc>).
Set user-defined property "INIT = 0" for instance <U1> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "IOB = true" for instance <U1> in unit <mig_21_s3_dqs_iob>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "INIT = 0" for instance <U2> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <U3> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <U3> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "SLEW = SLOW" for instance <U3> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <U4> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "DIFF_TERM = FALSE" for instance <U4> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "DQS_BIAS = FALSE" for instance <U4> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <U4> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <U4> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <U4> in unit <mig_21_s3_dqs_iob>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <U4> in unit <mig_21_s3_dqs_iob>.
Entity <mig_21_s3_dqs_iob> analyzed. Unit <mig_21_s3_dqs_iob> generated.
 
Analyzing Entity <mig_21_s3_dq_iob> in library <work> (Architecture <arc>).
Set user-defined property "INIT = 0" for instance <DDR_OUT> in unit <mig_21_s3_dq_iob>.
Set user-defined property "INIT = 0" for instance <DQ_T> in unit <mig_21_s3_dq_iob>.
Set user-defined property "IOB = true" for instance <DQ_T> in unit <mig_21_s3_dq_iob>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <DQ_OBUFT> in unit <mig_21_s3_dq_iob>.
Set user-defined property "DRIVE = 12" for instance <DQ_OBUFT> in unit <mig_21_s3_dq_iob>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <DQ_OBUFT> in unit <mig_21_s3_dq_iob>.
Set user-defined property "SLEW = SLOW" for instance <DQ_OBUFT> in unit <mig_21_s3_dq_iob>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <DQ_IBUF> in unit <mig_21_s3_dq_iob>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <DQ_IBUF> in unit <mig_21_s3_dq_iob>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <DQ_IBUF> in unit <mig_21_s3_dq_iob>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <DQ_IBUF> in unit <mig_21_s3_dq_iob>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <DQ_IBUF> in unit <mig_21_s3_dq_iob>.
Entity <mig_21_s3_dq_iob> analyzed. Unit <mig_21_s3_dq_iob> generated.
 
Analyzing Entity <mig_21_infrastructure_top> in library <work> (Architecture <arc>).
Entity <mig_21_infrastructure_top> analyzed. Unit <mig_21_infrastructure_top> generated.
 
Analyzing Entity <mig_21_clk_dcm> in library <work> (Architecture <arc>).
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "CLKFX_DIVIDE = 1" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "CLKFX_MULTIPLY = 4" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "CLK_FEEDBACK = 1X" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "DSS_MODE = NONE" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "FACTORY_JF = C080" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "PHASE_SHIFT = 0" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "SIM_MODE = SAFE" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "STARTUP_WAIT = FALSE" for instance <DCM_INST1> in unit <mig_21_clk_dcm>.
Set user-defined property "CLK_SEL_TYPE = SYNC" for instance <BUFG_CLK0> in unit <mig_21_clk_dcm>.
Set user-defined property "CLK_SEL_TYPE = SYNC" for instance <BUFG_CLK90> in unit <mig_21_clk_dcm>.
Entity <mig_21_clk_dcm> analyzed. Unit <mig_21_clk_dcm> generated.
 
Analyzing Entity <mig_21_cal_top> in library <work> (Architecture <arc>).
Entity <mig_21_cal_top> analyzed. Unit <mig_21_cal_top> generated.
 
Analyzing Entity <mig_21_cal_ctl> in library <work> (Architecture <arc_cal_ctl>).
Set user-defined property "KEEP_HIERARCHY = YES" for unit <mig_21_cal_ctl>.
Set property "syn_keep = TRUE" for signal <cnt>.
Set property "syn_keep = TRUE" for signal <trans_onedtct>.
Set property "syn_keep = TRUE" for signal <trans_twodtct>.
Set property "syn_keep = TRUE" for signal <phase_cnt>.
Set property "syn_keep = TRUE" for signal <tap_dly_reg>.
Set property "syn_keep = TRUE" for signal <enb_trans_two_dtct>.
Set property "syn_keep = TRUE" for signal <tapfordqs_val>.
INFO:Xst:1432 - Contents of array <tap_dly_reg> may be accessed with a negative index, causing simulation mismatch.
INFO:Xst:1433 - Contents of array <tap_dly_reg> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
Entity <mig_21_cal_ctl> analyzed. Unit <mig_21_cal_ctl> generated.
 
Analyzing Entity <mig_21_tap_dly> in library <work> (Architecture <arc_tap_dly>).
Set user-defined property "KEEP_HIERARCHY = YES" for unit <mig_21_tap_dly>.
Set property "syn_preserve = TRUE" for signal <tap>.
Set property "syn_preserve = TRUE" for signal <flop1>.
Set user-defined property "INIT = E2E2" for instance <l0> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l1> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l2> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l3> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l4> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l5> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l6> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l7> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l8> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l9> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l10> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l11> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l12> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l13> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l14> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l15> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l16> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l17> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l18> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l19> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l20> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l21> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l22> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l23> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l24> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l25> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l26> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l27> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l28> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l29> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l30> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = E2E2" for instance <l31> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[0].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[1].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[2].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[3].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[4].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[5].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[6].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[7].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[8].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[9].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[10].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[11].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[12].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[13].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[14].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[15].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[16].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[17].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[18].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[19].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[20].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[21].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[22].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[23].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[24].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[25].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[26].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[27].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[28].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[29].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[30].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap1[31].r> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[0].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[1].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[2].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[3].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[4].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[5].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[6].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[7].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[8].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[9].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[10].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[11].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[12].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[13].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[14].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[15].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[16].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[17].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[18].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[19].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[20].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[21].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[22].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[23].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[24].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[25].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[26].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[27].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[28].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[29].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <gen_tap2[30].u> in unit <mig_21_tap_dly>.
Set user-defined property "INIT = 0" for instance <u31> in unit <mig_21_tap_dly>.
Entity <mig_21_tap_dly> analyzed. Unit <mig_21_tap_dly> generated.
 
Analyzing generic Entity <cache> in library <work> (Architecture <Rtl>).
blocksizeld = 12
ldCachedWords = 1
ldways = 1
INFO:Xst:2679 - Register <blockIn<1>.Modified> in unit <cache> has a constant value of 0000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <blockIn<0>.Modified> in unit <cache> has a constant value of 0000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <AmIn.valid> in unit <cache> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <A1In.valid> in unit <cache> has a constant value of 1 during circuit operation. The register is replaced by logic.
Entity <cache> analyzed. Unit <cache> generated.
 
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <ddr_odt_cntrl> in unit <mig_21_controller_0> has a constant value of 0 during circuit operation. The register is replaced by logic.
 
Synthesizing Unit <counter>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/counter.vhd".
Found 4-bit register for signal <Tint>.
Found 27-bit 4-to-1 multiplexer for signal <DataOut>.
Found 24-bit register for signal <counters<0>.count>.
Found 24-bit register for signal <counters<0>.reload>.
Found 3-bit register for signal <counters<0>.source>.
Found 1-bit register for signal <counters<0>.tc>.
Found 24-bit register for signal <counters<1>.count>.
Found 24-bit register for signal <counters<1>.reload>.
Found 3-bit register for signal <counters<1>.source>.
Found 1-bit register for signal <counters<1>.tc>.
Found 24-bit register for signal <counters<2>.count>.
Found 24-bit register for signal <counters<2>.reload>.
Found 3-bit register for signal <counters<2>.source>.
Found 1-bit register for signal <counters<2>.tc>.
Found 24-bit register for signal <counters<3>.count>.
Found 24-bit register for signal <counters<3>.reload>.
Found 3-bit register for signal <counters<3>.source>.
Found 1-bit register for signal <counters<3>.tc>.
Found 108-bit register for signal <Data>.
Found 4-bit register for signal <oldsource>.
Found 24-bit subtractor for signal <sub0000$sub0000> created at line 110.
Found 24-bit subtractor for signal <sub0001$sub0000> created at line 110.
Found 24-bit subtractor for signal <sub0002$sub0000> created at line 110.
Found 24-bit subtractor for signal <sub0003$sub0000> created at line 110.
Summary:
inferred 324 D-type flip-flop(s).
inferred 4 Adder/Subtractor(s).
inferred 27 Multiplexer(s).
Unit <counter> synthesized.
 
 
Synthesizing Unit <IntVectors>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/IntVectors.vhd".
Found 4-bit register for signal <Vector>.
Found 16-bit subtractor for signal <$sub0000> created at line 96.
Found 16-bit register for signal <blocking>.
Found 16-bit register for signal <buffered>.
Found 16-bit register for signal <Interrupts>.
Found 16-bit register for signal <masks>.
Found 16-bit subtractor for signal <newBlocking0$sub0000> created at line 130.
Found 16-bit subtractor for signal <newpending$addsub0000> created at line 104.
Found 16-bit register for signal <oldSignal>.
Found 16-bit register for signal <pending>.
Found 4-bit register for signal <pipe>.
Found 1-bit register for signal <Quitted>.
Found 1-bit register for signal <Valid>.
Summary:
inferred 106 D-type flip-flop(s).
inferred 3 Adder/Subtractor(s).
Unit <IntVectors> synthesized.
 
 
Synthesizing Unit <ROMcode>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/ROMcode.vhd".
Found 512x32-bit ROM for signal <bdata_2$rom0000> created at line 4674.
Found 512x32-bit ROM for signal <bdata_3$rom0000> created at line 4674.
Found 512x32-bit ROM for signal <bdata_4$rom0000> created at line 4674.
Found 512x32-bit ROM for signal <bdata_5$rom0000> created at line 4674.
Found 512x32-bit ROM for signal <bdata_6$rom0000> created at line 4674.
Found 512x32-bit ROM for signal <bdata_7$rom0000> created at line 4674.
Found 512x32-bit ROM for signal <bdata_8$rom0000> created at line 4674.
Found 512x32-bit ROM for signal <bdata_0$rom0000> created at line 4674.
Found 512x32-bit ROM for signal <bdata_1$rom0000> created at line 4674.
Found 288-bit register for signal <bdata>.
Found 4-bit register for signal <old>.
INFO:Xst:738 - HDL ADVISOR - 288 flip-flops were inferred for signal <bdata>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
Summary:
inferred 9 ROM(s).
inferred 292 D-type flip-flop(s).
Unit <ROMcode> synthesized.
 
 
Synthesizing Unit <cache>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/Cache.vhd".
WARNING:Xst:646 - Signal <emptyAm> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <blockIn<1>.Modified> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <blockIn<0>.Modified> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 4096x26-bit single-port RAM <Mram_tagRAM<1>> for signal <tagRAM<1>>.
Found 4096x13-bit single-port RAM <Mram_Ax> for signal <Ax>.
Found 4096x15-bit single-port RAM <Mram_ramAm> for signal <ramAm>.
Found 4096x36-bit single-port RAM <Mram_RAMs<1>> for signal <RAMs<1>>.
Found 4096x36-bit single-port RAM <Mram_RAMs<0>> for signal <RAMs<0>>.
Found 4096x15-bit single-port RAM <Mram_ramA1> for signal <ramA1>.
Found 4096x12-bit single-port RAM <Mram_ramf> for signal <ramf>.
Found 4096x26-bit single-port RAM <Mram_tagRAM<0>> for signal <tagRAM<0>>.
Found finite state machine <FSM_0> for signal <stateram>.
-----------------------------------------------------------------------
| States | 18 |
| Transitions | 41 |
| Inputs | 13 |
| Outputs | 19 |
| Clock | Clock (rising_edge) |
| Reset | nReset (negative) |
| Reset type | synchronous |
| Reset State | raminit |
| Power Up State | raminit |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <statetag>.
-----------------------------------------------------------------------
| States | 9 |
| Transitions | 16 |
| Inputs | 7 |
| Outputs | 11 |
| Clock | Clock (rising_edge) |
| Reset | nReset (negative) |
| Reset type | synchronous |
| Reset State | inittag |
| Power Up State | inittag |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_2> for signal <statequeue>.
-----------------------------------------------------------------------
| States | 7 |
| Transitions | 29 |
| Inputs | 17 |
| Outputs | 9 |
| Clock | Clock (rising_edge) |
| Reset | nReset (negative) |
| Reset type | synchronous |
| Reset State | queuestart |
| Power Up State | queuestart |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 32-bit register for signal <DataOut>.
Found 1-bit register for signal <done>.
Found 8-bit register for signal <Mask>.
Found 27-bit register for signal <AddressOut>.
Found 64-bit register for signal <DataBlockOut>.
Found 2-bit register for signal <A1In.way>.
Found 12-bit register for signal <A1In.Word>.
Found 12-bit register for signal <A1Inaddr>.
Found 1-bit register for signal <A1Out.valid>.
Found 2-bit register for signal <A1Out.way>.
Found 12-bit register for signal <A1Out.Word>.
Found 12-bit register for signal <A1Outaddr>.
Found 1-bit register for signal <accdone>.
Found 1-bit register for signal <accinterrupt>.
Found 1-bit register for signal <accqueue>.
Found 27-bit register for signal <AddressInh>.
Found 12-bit register for signal <AddressInt>.
Found 2-bit register for signal <AmIn.way>.
Found 12-bit register for signal <AmIn.Word>.
Found 12-bit register for signal <AmInaddr>.
Found 1-bit register for signal <AmOut.valid>.
Found 2-bit register for signal <AmOut.way>.
Found 12-bit register for signal <AmOut.Word>.
Found 12-bit register for signal <AmOutaddr>.
Found 32-bit register for signal <blockIn<0>.Word>.
Found 32-bit register for signal <blockIn<1>.Word>.
Found 4-bit register for signal <blockOut<0>.Modified>.
Found 32-bit register for signal <blockOut<0>.Word>.
Found 4-bit register for signal <blockOut<1>.Modified>.
Found 32-bit register for signal <blockOut<1>.Word>.
Found 1-bit register for signal <CacheIn.Am>.
Found 12-bit register for signal <CacheIn.FiFoaddr>.
Found 4-bit register for signal <CacheIn.Words<0>.Modified>.
Found 32-bit register for signal <CacheIn.Words<0>.Word>.
Found 4-bit register for signal <CacheIn.Words<1>.Modified>.
Found 32-bit register for signal <CacheIn.Words<1>.Word>.
Found 1-bit register for signal <CacheOut.Am>.
Found 12-bit register for signal <CacheOut.FiFoaddr>.
Found 4-bit register for signal <CacheOut.Words<0>.Modified>.
Found 32-bit register for signal <CacheOut.Words<0>.Word>.
Found 4-bit register for signal <CacheOut.Words<1>.Modified>.
Found 32-bit register for signal <CacheOut.Words<1>.Word>.
Found 12-bit register for signal <cindex>.
Found 13-bit updown counter for signal <counterA1>.
Found 13-bit updown counter for signal <counterAm>.
Found 13-bit updown counter for signal <counterf>.
Found 32-bit register for signal <DataInh>.
Found 12-bit register for signal <datum>.
Found 15-bit register for signal <datumA1>.
Found 15-bit register for signal <datumAm>.
Found 4-bit register for signal <del>.
Found 12-bit subtractor for signal <diff$sub0000> created at line 651.
Found 1-bit register for signal <doneh>.
Found 4-bit register for signal <elim>.
Found 4-bit adder for signal <elim$addsub0000> created at line 407.
Found 1-bit register for signal <enablequeue>.
Found 1-bit register for signal <enableram>.
Found 12-bit up counter for signal <firstA1>.
Found 12-bit up counter for signal <firstAm>.
Found 12-bit up counter for signal <firstf>.
Found 4-bit register for signal <found>.
Found 12-bit comparator equal for signal <found$cmp_eq0000> created at line 249.
Found 12-bit comparator equal for signal <found$cmp_eq0001> created at line 249.
Found 4-bit register for signal <free>.
Found 12-bit register for signal <FreeIn>.
Found 12-bit register for signal <FreeOut>.
Found 1-bit register for signal <getA1>.
Found 1-bit register for signal <getAm>.
Found 1-bit register for signal <getf>.
Found 12-bit up counter for signal <initcount>.
Found 12-bit up counter for signal <initcount1>.
Found 1-bit register for signal <interrupt>.
Found 3-bit register for signal <IOCodeh>.
Found 12-bit register for signal <lastA1>.
Found 12-bit register for signal <lastAm>.
Found 12-bit register for signal <lastf>.
Found 1-bit register for signal <newAm>.
Found 12-bit register for signal <newFiFoAddr>.
Found 1-bit register for signal <preempted>.
Found 1-bit register for signal <putA1>.
Found 1-bit register for signal <putAm>.
Found 1-bit register for signal <putf>.
Found 1-bit register for signal <queuedone>.
Found 1-bit register for signal <readb>.
Found 1-bit register for signal <readsh>.
Found 1-bit register for signal <RecBuff.Am>.
Found 12-bit register for signal <RecBuff.FiFoaddr>.
Found 4-bit register for signal <RecBuff.Words<0>.Modified>.
Found 32-bit register for signal <RecBuff.Words<0>.Word>.
Found 4-bit register for signal <RecBuff.Words<1>.Modified>.
Found 32-bit register for signal <RecBuff.Words<1>.Word>.
Found 1-bit register for signal <removeA1>.
Found 1-bit register for signal <removeAm>.
Found 1-bit register for signal <stateIO<0>>.
Found 4-bit comparator equal for signal <statequeue$cmp_eq0000> created at line 712.
Found 12-bit comparator equal for signal <statequeue$cmp_eq0001> created at line 712.
Found 12-bit register for signal <tagBuff<0>.cacheAddr>.
Found 1-bit register for signal <tagBuff<0>.cacheValid>.
Found 12-bit register for signal <tagBuff<0>.Tag>.
Found 1-bit register for signal <tagBuff<0>.TagValid>.
Found 12-bit register for signal <tagBuff<1>.cacheAddr>.
Found 1-bit register for signal <tagBuff<1>.cacheValid>.
Found 12-bit register for signal <tagBuff<1>.Tag>.
Found 1-bit register for signal <tagBuff<1>.TagValid>.
Found 12-bit register for signal <tagdummy<0>.cacheAddr>.
Found 1-bit register for signal <tagdummy<0>.cacheValid>.
Found 12-bit register for signal <tagdummy<0>.Tag>.
Found 1-bit register for signal <tagdummy<0>.TagValid>.
Found 12-bit register for signal <tagdummy<1>.cacheAddr>.
Found 1-bit register for signal <tagdummy<1>.cacheValid>.
Found 12-bit register for signal <tagdummy<1>.Tag>.
Found 1-bit register for signal <tagdummy<1>.TagValid>.
Found 12-bit register for signal <TagRAMIn<0>.cacheAddr>.
Found 1-bit register for signal <TagRAMIn<0>.cacheValid>.
Found 12-bit register for signal <TagRAMIn<0>.Tag>.
Found 1-bit register for signal <TagRAMIn<0>.TagValid>.
Found 12-bit register for signal <TagRAMIn<1>.cacheAddr>.
Found 1-bit register for signal <TagRAMIn<1>.cacheValid>.
Found 12-bit register for signal <TagRAMIn<1>.Tag>.
Found 1-bit register for signal <TagRAMIn<1>.TagValid>.
Found 12-bit register for signal <TagRAMOut<0>.cacheAddr>.
Found 1-bit register for signal <TagRAMOut<0>.cacheValid>.
Found 12-bit register for signal <TagRAMOut<0>.Tag>.
Found 1-bit register for signal <TagRAMOut<0>.TagValid>.
Found 12-bit register for signal <TagRAMOut<1>.cacheAddr>.
Found 1-bit register for signal <TagRAMOut<1>.cacheValid>.
Found 12-bit register for signal <TagRAMOut<1>.Tag>.
Found 1-bit register for signal <TagRAMOut<1>.TagValid>.
Found 12-bit register for signal <toFlush>.
Found 12-bit adder for signal <uaddress$addsub0000> created at line 594.
Found 12-bit adder for signal <uaddressA1$addsub0000> created at line 803.
Found 12-bit adder for signal <uaddressAm$addsub0000> created at line 836.
Found 1-bit register for signal <writeb>.
Found 1-bit register for signal <writec>.
Found 1-bit register for signal <writesh>.
Found 1-bit register for signal <writet>.
Summary:
inferred 3 Finite State Machine(s).
inferred 8 RAM(s).
inferred 8 Counter(s).
inferred 1090 D-type flip-flop(s).
inferred 5 Adder/Subtractor(s).
inferred 4 Comparator(s).
Unit <cache> synthesized.
 
 
Synthesizing Unit <ProgramCounter>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/ProgramCounter.vhd".
Register <SavedOpcode> equivalent to <Opcode> has been removed
Found 1-bit register for signal <Token>.
Found 1-bit register for signal <abortload>.
Found 8-bit register for signal <Opcode>.
Found 40-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 84.
Found 1-bit register for signal <delayed>.
Found 1-bit register for signal <execute>.
Found 1-bit register for signal <halt>.
Found 32-bit register for signal <Im>.
Found 1-bit register for signal <indirect>.
Found 1-bit register for signal <load>.
Found 4-bit adder for signal <load1>.
Found 4-bit adder for signal <load3>.
Found 4-bit adder for signal <load5>.
Found 1-bit register for signal <newdelayed>.
Found 28-bit adder for signal <newPC$add0000> created at line 224.
Found 25-bit adder for signal <nextnextPC$add0000> created at line 100.
Found 8-bit register for signal <nextOpcode>.
Found 28-bit register for signal <nextPC>.
Found 28-bit register for signal <PC>.
Found 26-bit register for signal <predictedAddress>.
Found 26-bit adder for signal <predictedAddress$share0000>.
Found 1-bit register for signal <present>.
Found 1-bit register for signal <Quitted>.
Found 1-bit register for signal <running>.
Found 40-bit register for signal <saved>.
Found 4-bit register for signal <service>.
Found 32-bit register for signal <thefirst>.
Found 32-bit 4-to-1 multiplexer for signal <thefirst$mux0002>.
Found 32-bit register for signal <thesecond>.
Found 32-bit register for signal <thethird>.
Found 3-bit register for signal <valid>.
Summary:
inferred 202 D-type flip-flop(s).
inferred 6 Adder/Subtractor(s).
inferred 72 Multiplexer(s).
Unit <ProgramCounter> synthesized.
 
 
Synthesizing Unit <ALU>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/ALU.vhd".
Found 32-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 183.
Found 1-bit 8-to-1 multiplexer for signal <res$mux0000> created at line 89.
Found 32-bit 4-to-1 multiplexer for signal <result<2>>.
Found 32-bit xor2 for signal <result_3$xor0000> created at line 178.
Found 33-bit adder carry in for signal <temp$add0000> created at line 62.
Found 34-bit shifter logical left for signal <temp0$shift0000> created at line 140.
Found 34-bit shifter logical right for signal <temp0$shift0001> created at line 144.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 65 Multiplexer(s).
inferred 2 Combinational logic shifter(s).
Unit <ALU> synthesized.
 
 
Synthesizing Unit <mig_21_infrastructure>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_infrastructure.vhd".
Found 5-bit register for signal <delay_sel_val1>.
Found 1-bit register for signal <rst_calib1_r1>.
Found 1-bit register for signal <rst_calib1_r2>.
Summary:
inferred 7 D-type flip-flop(s).
Unit <mig_21_infrastructure> synthesized.
 
 
Synthesizing Unit <mig_21_data_write_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_write_0.vhd".
WARNING:Xst:646 - Signal <write_en_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 1-bit register for signal <write_en_val>.
Found 64-bit register for signal <write_data1>.
Found 64-bit register for signal <write_data2>.
Found 32-bit register for signal <write_data270>.
Found 32-bit register for signal <write_data270_1>.
Found 32-bit register for signal <write_data270_2>.
Found 64-bit register for signal <write_data3>.
Found 64-bit register for signal <write_data4>.
Found 32-bit register for signal <write_data90>.
Found 32-bit register for signal <write_data90_1>.
Found 32-bit register for signal <write_data90_2>.
Found 8-bit register for signal <write_data_m1>.
Found 8-bit register for signal <write_data_m2>.
Found 4-bit register for signal <write_data_m270>.
Found 4-bit register for signal <write_data_m270_1>.
Found 4-bit register for signal <write_data_m270_2>.
Found 8-bit register for signal <write_data_m3>.
Found 8-bit register for signal <write_data_m4>.
Found 4-bit register for signal <write_data_m90>.
Found 4-bit register for signal <write_data_m90_1>.
Found 4-bit register for signal <write_data_m90_2>.
Found 1-bit register for signal <write_en_P1>.
Summary:
inferred 506 D-type flip-flop(s).
Unit <mig_21_data_write_0> synthesized.
 
 
Synthesizing Unit <mig_21_cal_ctl>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_cal_ctl_0.vhd".
WARNING:Xst:646 - Signal <cnt_val<31:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 5-bit register for signal <tapfordqs>.
Found 1-bit 32-to-1 multiplexer for signal <$varindex0000> created at line 217.
Found 6-bit up counter for signal <cnt>.
Found 6-bit up counter for signal <cnt1>.
Found 1-bit register for signal <enb_trans_two_dtct>.
Found 5-bit comparator less for signal <enb_trans_two_dtct$cmp_lt0000> created at line 142.
Found 5-bit up counter for signal <phase_cnt>.
Found 1-bit register for signal <reset_r>.
Found 32-bit register for signal <tap_dly_reg>.
Found 5-bit register for signal <tapfordqs_val>.
Found 5-bit comparator greater for signal <tapfordqs_val$cmp_gt0000> created at line 239.
Found 5-bit comparator greater for signal <tapfordqs_val$cmp_gt0001> created at line 241.
Found 1-bit register for signal <trans_onedtct>.
Found 1-bit register for signal <trans_twodtct>.
Summary:
inferred 3 Counter(s).
inferred 46 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 1 Multiplexer(s).
Unit <mig_21_cal_ctl> synthesized.
 
 
Synthesizing Unit <dcm1>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/dcm1.vhd".
Unit <dcm1> synthesized.
 
 
Synthesizing Unit <UART>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/UART.vhd".
WARNING:Xst:646 - Signal <sAlmostFull> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found finite state machine <FSM_3> for signal <ReceiveState>.
-----------------------------------------------------------------------
| States | 6 |
| Transitions | 16 |
| Inputs | 5 |
| Outputs | 7 |
| Clock | Clk (rising_edge) |
| Reset | ReceiveState$or0000 (positive) |
| Reset type | asynchronous |
| Reset State | idle |
| Power Up State | idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_4> for signal <TransmitState>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 15 |
| Inputs | 8 |
| Outputs | 6 |
| Clock | Clk (rising_edge) |
| Reset | ReceiveState$or0000 (positive) |
| Reset type | asynchronous |
| Reset State | idle |
| Power Up State | idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 1-bit register for signal <TxD>.
Found 24-bit 8-to-1 multiplexer for signal <DataOut>.
Found 25-bit subtractor for signal <$sub0000> created at line 238.
Found 1-bit xor8 for signal <a$xor0000> created at line 302.
Found 1-bit register for signal <baudrateset>.
Found 24-bit register for signal <Count0>.
Found 25-bit register for signal <CountR>.
Found 25-bit register for signal <CountT>.
Found 1-bit register for signal <Detect>.
Found 24-bit register for signal <Divisor>.
Found 9-bit register for signal <escapech>.
Found 1-bit register for signal <escaped>.
Found 1-bit register for signal <halfbitR>.
Found 1-bit register for signal <halfbitT>.
Found 2-bit register for signal <Parity>.
Found 9-bit register for signal <Received>.
Found 1-bit xor10 for signal <Received_8$xor0000> created at line 480.
Found 1-bit register for signal <reset>.
Found 1-bit register for signal <rput>.
Found 1-bit register for signal <Sample>.
Found 1-bit register for signal <sget>.
Found 1-bit register for signal <shotR>.
Found 1-bit register for signal <shotT>.
Found 2-bit register for signal <Stopbits>.
Found 25-bit subtractor for signal <sub0001$sub0000> created at line 382.
Found 24-bit subtractor for signal <sub0002$sub0000> created at line 388.
Found 10-bit register for signal <ToTransmit>.
Found 1-bit register for signal <unlock>.
Found 1-bit register for signal <WordLength>.
Found 1-bit register for signal <xoff>.
Found 9-bit register for signal <xoffch>.
Found 1-bit register for signal <xoffsent>.
Found 1-bit register for signal <xon>.
Found 9-bit register for signal <xonch>.
Found 1-bit register for signal <xonsent>.
Summary:
inferred 2 Finite State Machine(s).
inferred 140 D-type flip-flop(s).
inferred 3 Adder/Subtractor(s).
inferred 24 Multiplexer(s).
inferred 2 Xor(s).
Unit <UART> synthesized.
 
 
Synthesizing Unit <theStacks>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/theStacks.vhd".
WARNING:Xst:1780 - Signal <oldsaverunning> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SourceStep<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 512x32-bit dual-port RAM <Mram_Cache> for signal <Cache>.
Found 512x32-bit dual-port RAM <Mram_Cache_ren> for signal <Cache>.
Found 512x32-bit dual-port RAM <Mram_Cache_ren_1> for signal <Cache>.
Found 1-bit register for signal <TOSValid>.
Found 26-bit adder for signal <$add0000> created at line 577.
Found 26-bit adder for signal <$add0001> created at line 573.
Found 8-bit subtractor for signal <$sub0000> created at line 580.
Found 26-bit subtractor for signal <$sub0002> created at line 578.
Found 32-bit 4-to-1 multiplexer for signal <Actual<0><1>>.
Found 32-bit 4-to-1 multiplexer for signal <Actual<1><1>>.
Found 2-bit register for signal <afast>.
Found 3-bit register for signal <aIOCode>.
Found 5-bit register for signal <AluFunc>.
Found 5-bit register for signal <AluFuncPop>.
Found 1-bit register for signal <aSelect<0>>.
Found 1-bit 4-to-1 multiplexer for signal <aSelect_0$mux0000>.
Found 26-bit register for signal <aStackLength>.
Found 26-bit register for signal <aStackPtr>.
Found 8-bit register for signal <aTail>.
Found 28-bit register for signal <aTarget>.
Found 8-bit register for signal <aTop>.
Found 32-bit register for signal <BufferedInput>.
Found 26-bit adder for signal <BufferedInput$add0000> created at line 718.
Found 32-bit register for signal <BufferedOutput>.
Found 32-bit 4-to-1 multiplexer for signal <BufferedOutput$mux0000>.
Found 3-bit register for signal <ByteSelect>.
Found 9-bit register for signal <Cachedminor>.
Found 9-bit subtractor for signal <Cachedminor$sub0001> created at line 604.
Found 1-bit register for signal <Carry>.
Found 3-bit register for signal <early>.
Found 2-bit register for signal <fast>.
Found 1-bit register for signal <fetch>.
Found 32-bit register for signal <ImmediatePop>.
Found 32-bit register for signal <ImmediateStep>.
Found 9-bit register for signal <IndexI>.
Found 9-bit register for signal <indexL>.
Found 9-bit register for signal <IndexR>.
Found 8-bit subtractor for signal <indexs$sub0000> created at line 190.
Found 9-bit register for signal <minuend>.
Found 64-bit register for signal <modified>.
Found 32-bit 4-to-1 multiplexer for signal <modified_0$mux0002>.
Found 32-bit 8-to-1 multiplexer for signal <modified_0$mux0003> created at line 284.
Found 9-bit adder for signal <newCached$add0000> created at line 495.
Found 9-bit subtractor for signal <newCached$addsub0000> created at line 428.
Found 9-bit comparator equal for signal <newearly_0$cmp_eq0000> created at line 250.
Found 9-bit comparator equal for signal <newearly_1$cmp_eq0000> created at line 259.
Found 9-bit comparator equal for signal <newearly_2$cmp_eq0000> created at line 268.
Found 8-bit adder for signal <newIndexR$add0000> created at line 696.
Found 8-bit adder for signal <newTail$addsub0000> created at line 575.
Found 26-bit adder for signal <newTarget0_27_2$add0000> created at line 682.
Found 8-bit subtractor for signal <newTop$addsub0000> created at line 468.
Found 2-bit subtractor for signal <newToPop$addsub0000> created at line 438.
Found 9-bit comparator greater for signal <newToPop$cmp_gt0000> created at line 427.
Found 9-bit register for signal <oldf>.
Found 9-bit register for signal <olds>.
Found 1-bit register for signal <oldstall1>.
Found 96-bit register for signal <overload>.
Found 64-bit register for signal <Phantom<0>>.
Found 64-bit register for signal <Phantom<1>>.
Found 64-bit 4-to-1 multiplexer for signal <Pre>.
Found 1-bit register for signal <preStore>.
Found 2-bit register for signal <prevalid>.
Found 32-bit register for signal <Random>.
Found 1-bit register for signal <ReadPop>.
Found 1-bit register for signal <ReadStep>.
Found 27-bit subtractor for signal <relative>.
Found 1-bit register for signal <saverunning>.
Found 2-bit register for signal <SelectAluPop>.
Found 2-bit register for signal <SelectData>.
Found 1-bit register for signal <SelectedOp<0>>.
Found 1-bit register for signal <SelectedPop<0>>.
Found 1-bit register for signal <SelectedStep<0>>.
Found 4-bit register for signal <SourcePop>.
Found 4-bit register for signal <SourceStep>.
Found 8-bit register for signal <Stack<0>.Append>.
Found 9-bit register for signal <Stack<0>.Cached>.
Found 2-bit register for signal <Stack<0>.ReloadState>.
Found 26-bit register for signal <Stack<0>.StackLength>.
Found 26-bit register for signal <Stack<0>.StackPtr>.
Found 8-bit register for signal <Stack<0>.Tail>.
Found 8-bit register for signal <Stack<0>.Top>.
Found 8-bit register for signal <Stack<1>.Append>.
Found 9-bit register for signal <Stack<1>.Cached>.
Found 2-bit register for signal <Stack<1>.ReloadState>.
Found 26-bit register for signal <Stack<1>.StackLength>.
Found 26-bit register for signal <Stack<1>.StackPtr>.
Found 8-bit register for signal <Stack<1>.Tail>.
Found 8-bit register for signal <Stack<1>.Top>.
Found 3-bit register for signal <StackFuncPop>.
Found 3-bit register for signal <StackFuncStep>.
Found 1-bit register for signal <stall1>.
Found 1-bit register for signal <stall2>.
Found 1-bit register for signal <store>.
Found 26-bit subtractor for signal <sub0001$sub0000> created at line 571.
Found 26-bit register for signal <targetStep>.
Found 32-bit register for signal <TheFirst>.
Found 32-bit register for signal <TheSecond>.
Found 3-bit register for signal <theStackFunc>.
Found 2-bit register for signal <vfast>.
Found 32-bit 8-to-1 multiplexer for signal <visible<1>>.
Found 32-bit 8-to-1 multiplexer for signal <w_0$mux0002> created at line 284.
Found 1-bit xor2 for signal <w_0$xor0000> created at line 284.
Found 1-bit xor2 for signal <w_0$xor0001> created at line 293.
Found 1-bit register for signal <WritePop>.
Found 1-bit register for signal <WriteStep>.
Found 9-bit comparator equal for signal <x_1$cmp_eq0000> created at line 227.
Found 9-bit comparator equal for signal <x_1$cmp_eq0001> created at line 228.
Found 32-bit 4-to-1 multiplexer for signal <x_1$mux0002> created at line 227.
Found 1-bit xor2 for signal <y_1$xor0000> created at line 240.
Summary:
inferred 3 RAM(s).
inferred 936 D-type flip-flop(s).
inferred 16 Adder/Subtractor(s).
inferred 6 Comparator(s).
inferred 321 Multiplexer(s).
Unit <theStacks> synthesized.
 
 
Synthesizing Unit <mig_21_controller_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_controller_0.vhd".
WARNING:Xst:646 - Signal <rst_dqs_div_r1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <odt_deassert> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <lmr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <init_done_dis> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dqs_reset3_clk0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dqs_enable3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Register <wrburst_end_1> equivalent to <rdburst_end_1> has been removed
Register <wrburst_end_2> equivalent to <rdburst_end_2> has been removed
Found finite state machine <FSM_5> for signal <current_state>.
-----------------------------------------------------------------------
| States | 12 |
| Transitions | 40 |
| Inputs | 15 |
| Outputs | 8 |
| Clock | clk (falling_edge) |
| Reset | rst180_r (positive) |
| Reset type | synchronous |
| Reset State | idle |
| Power Up State | idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_6> for signal <init_current_state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 28 |
| Inputs | 15 |
| Outputs | 6 |
| Clock | clk (falling_edge) |
| Reset | init_current_state$or0000 (positive) |
| Reset type | synchronous |
| Reset State | init_idle |
| Power Up State | init_idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Using one-hot encoding for signal <burst_length>.
Found 1-bit register for signal <ar_done>.
Found 1-bit register for signal <rst_calib>.
Found 1-bit register for signal <write_enable>.
Found 1-bit register for signal <accept_cmd_in>.
Found 23-bit register for signal <address_reg>.
Found 1-bit register for signal <ar_done_reg>.
Found 1-bit register for signal <auto_ref>.
Found 1-bit register for signal <auto_ref1>.
Found 1-bit register for signal <auto_ref_detect1>.
Found 1-bit register for signal <auto_ref_issued>.
Found 1-bit register for signal <auto_ref_wait>.
Found 1-bit register for signal <auto_ref_wait1>.
Found 1-bit register for signal <auto_ref_wait2>.
Found 11-bit up counter for signal <autoref_count>.
Found 1-bit register for signal <autoref_value>.
Found 2-bit register for signal <ba_address_reg1>.
Found 2-bit register for signal <ba_address_reg2>.
Found 3-bit register for signal <burst_length>.
Found 3-bit down counter for signal <cas_count>.
Found 3-bit subtractor for signal <cas_count$sub0000> created at line 631.
Found 13-bit register for signal <column_address_reg>.
Found 6-bit down counter for signal <count6>.
Found 13-bit register for signal <ddr_address1>.
Found 2-bit register for signal <ddr_ba1>.
Found 1-bit register for signal <ddr_casb2>.
Found 1-bit register for signal <ddr_rasb2>.
Found 1-bit register for signal <ddr_web2>.
Found 8-bit down counter for signal <dll_rst_count>.
Found 3-bit down counter for signal <dqs_div_cascount>.
Found 3-bit register for signal <dqs_div_rdburstcount>.
Found 3-bit subtractor for signal <dqs_div_rdburstcount$addsub0000> created at line 1320.
Found 1-bit register for signal <dqs_enable1>.
Found 1-bit register for signal <dqs_enable2>.
Found 1-bit register for signal <dqs_enable_int>.
Found 1-bit register for signal <dqs_reset1_clk0>.
Found 1-bit register for signal <dqs_reset2_clk0>.
Found 1-bit register for signal <dqs_reset_int>.
Found 1-bit register for signal <go_to_active>.
Found 4-bit up counter for signal <init_count>.
Found 1-bit register for signal <init_done>.
Found 1-bit register for signal <init_mem>.
Found 1-bit register for signal <init_memory>.
Found 7-bit down counter for signal <init_pre_count>.
Found 3-bit down counter for signal <rcdr_count>.
Found 3-bit down counter for signal <rcdw_count>.
Found 1-bit register for signal <rdburst_end_1>.
Found 1-bit register for signal <rdburst_end_2>.
Found 1-bit register for signal <read_cmd1>.
Found 1-bit register for signal <read_cmd2>.
Found 1-bit register for signal <read_cmd3>.
Found 8-bit down counter for signal <rfc_count>.
Found 1-bit register for signal <rfc_count_reg>.
Found 13-bit register for signal <row_address_reg>.
Found 3-bit subtractor for signal <rp_cnt_value$addsub0000> created at line 432.
Found 3-bit register for signal <rp_count>.
Found 1-bit register for signal <rpcnt0>.
Found 1-bit register for signal <rst0_r>.
Found 1-bit register for signal <rst180_r>.
Found 1-bit register for signal <rst_dqs_div_r>.
Found 3-bit down counter for signal <wr_count>.
Found 1-bit register for signal <wrburst_end_3>.
Found 3-bit down counter for signal <wrburst_end_cnt>.
Found 1-bit register for signal <write_cmd1>.
Summary:
inferred 2 Finite State Machine(s).
inferred 12 Counter(s).
inferred 115 D-type flip-flop(s).
inferred 3 Adder/Subtractor(s).
Unit <mig_21_controller_0> synthesized.
 
 
Synthesizing Unit <mig_21_rd_gray_cntr>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_rd_gray_cntr.vhd".
Found 16x4-bit ROM for signal <d_in>.
Found 1-bit register for signal <reset90_r>.
Summary:
inferred 1 ROM(s).
inferred 1 D-type flip-flop(s).
Unit <mig_21_rd_gray_cntr> synthesized.
 
 
Synthesizing Unit <mig_21_ram8d_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_ram8d_0.vhd".
Unit <mig_21_ram8d_0> synthesized.
 
 
Synthesizing Unit <mig_21_dqs_delay_1>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_dqs_delay_0.vhd".
Unit <mig_21_dqs_delay_1> synthesized.
 
 
Synthesizing Unit <mig_21_dqs_delay_2>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_dqs_delay_0.vhd".
Unit <mig_21_dqs_delay_2> synthesized.
 
 
Synthesizing Unit <mig_21_fifo_0_wr_en_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_fifo_0_wr_en_0.vhd".
Unit <mig_21_fifo_0_wr_en_0> synthesized.
 
 
Synthesizing Unit <mig_21_fifo_1_wr_en_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_fifo_1_wr_en_0.vhd".
Unit <mig_21_fifo_1_wr_en_0> synthesized.
 
 
Synthesizing Unit <mig_21_wr_gray_cntr>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_wr_gray_cntr.vhd".
Found 16x4-bit ROM for signal <d_in>.
Summary:
inferred 1 ROM(s).
Unit <mig_21_wr_gray_cntr> synthesized.
 
 
Synthesizing Unit <mig_21_infrastructure_iobs_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_infrastructure_iobs_0.vhd".
Unit <mig_21_infrastructure_iobs_0> synthesized.
 
 
Synthesizing Unit <mig_21_controller_iobs_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_controller_iobs_0.vhd".
Unit <mig_21_controller_iobs_0> synthesized.
 
 
Synthesizing Unit <mig_21_s3_dm_iob>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_s3_dm_iob.vhd".
Unit <mig_21_s3_dm_iob> synthesized.
 
 
Synthesizing Unit <mig_21_s3_dqs_iob>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_s3_dqs_iob.vhd".
Unit <mig_21_s3_dqs_iob> synthesized.
 
 
Synthesizing Unit <mig_21_s3_dq_iob>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_s3_dq_iob.vhd".
Unit <mig_21_s3_dq_iob> synthesized.
 
 
Synthesizing Unit <mig_21_clk_dcm>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_clk_dcm.vhd".
Unit <mig_21_clk_dcm> synthesized.
 
 
Synthesizing Unit <mig_21_tap_dly>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_tap_dly.vhd".
Found 1-bit xor2 for signal <flop2_xnor_0$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_1$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_10$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_11$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_12$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_13$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_14$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_15$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_16$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_17$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_18$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_19$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_2$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_20$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_21$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_22$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_23$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_24$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_25$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_26$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_27$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_28$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_29$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_3$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_30$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_4$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_5$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_6$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_7$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_8$xor0000>.
Found 1-bit xor2 for signal <flop2_xnor_9$xor0000>.
Found 1-bit register for signal <reset_r>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <mig_21_tap_dly> synthesized.
 
 
Synthesizing Unit <theCore>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/theCore.vhd".
Found 128x3-bit ROM for signal <Func$mux0000> created at line 223.
Found 1-bit register for signal <illegal>.
Found 5-bit register for signal <AFunc>.
Found 3-bit register for signal <Func>.
Found 32-bit register for signal <Immediate>.
Found 2-bit register for signal <SelectAlu>.
Found 1-bit register for signal <SelectedStack<0>>.
Found 4-bit register for signal <SelectSource>.
Found 2-bit register for signal <toPop>.
Summary:
inferred 1 ROM(s).
inferred 46 D-type flip-flop(s).
Unit <theCore> synthesized.
 
 
Synthesizing Unit <mig_21_data_read_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_read_0.vhd".
Found 16-bit register for signal <fifo0_rd_addr_r>.
Found 16-bit register for signal <fifo1_rd_addr_r>.
Found 32-bit register for signal <fifo_0_data_out_r>.
Found 32-bit register for signal <fifo_1_data_out_r>.
Found 64-bit register for signal <first_sdr_data>.
Found 1-bit register for signal <read_valid_data_1_r>.
Found 1-bit register for signal <read_valid_data_1_r1>.
Found 1-bit register for signal <reset90_r>.
Summary:
inferred 163 D-type flip-flop(s).
Unit <mig_21_data_read_0> synthesized.
 
 
Synthesizing Unit <mig_21_data_read_controller_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_read_controller_0.vhd".
Found 1-bit register for signal <u_data_val>.
Found 4-bit comparator equal for signal <fifo_0_empty$cmp_eq0000> created at line 244.
Found 4-bit register for signal <fifo_0_wr_addr_2d>.
Found 4-bit register for signal <fifo_0_wr_addr_3d>.
Found 4-bit register for signal <fifo_0_wr_addr_d>.
Found 4-bit comparator equal for signal <fifo_1_empty$cmp_eq0000> created at line 246.
Found 4-bit register for signal <fifo_1_wr_addr_2d>.
Found 4-bit register for signal <fifo_1_wr_addr_3d>.
Found 4-bit register for signal <fifo_1_wr_addr_d>.
Found 1-bit register for signal <read_valid_data_r>.
Found 1-bit register for signal <read_valid_data_r1>.
Found 1-bit register for signal <reset90_r>.
Found 1-bit register for signal <reset_r>.
Summary:
inferred 29 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <mig_21_data_read_controller_0> synthesized.
 
 
Synthesizing Unit <mig_21_data_path_iobs_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_path_iobs_0.vhd".
Unit <mig_21_data_path_iobs_0> synthesized.
 
 
Synthesizing Unit <mig_21_cal_top>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_cal_top.vhd".
Unit <mig_21_cal_top> synthesized.
 
 
Synthesizing Unit <mig_21_infrastructure_top>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_infrastructure_top_0.vhd".
WARNING:Xst:647 - Input <sys_clkb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Register <wait_200us_int> equivalent to <wait_200us> has been removed
Found 1-bit register for signal <wait_200us>.
Found 16-bit up counter for signal <counter200>.
Found 17-bit comparator less for signal <counter200$cmp_lt0000> created at line 174.
Found 1-bit register for signal <sys_rst>.
Found 1-bit register for signal <sys_rst180>.
Found 1-bit register for signal <sys_rst180_1>.
Found 1-bit register for signal <sys_rst180_o>.
Found 1-bit register for signal <sys_rst90>.
Found 1-bit register for signal <sys_rst90_1>.
Found 1-bit register for signal <sys_rst90_o>.
Found 1-bit register for signal <sys_rst_1>.
Found 1-bit register for signal <sys_rst_o>.
Found 1-bit register for signal <wait_200us_i>.
Found 1-bit register for signal <wait_clk270>.
Found 1-bit register for signal <wait_clk90>.
Summary:
inferred 1 Counter(s).
inferred 13 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <mig_21_infrastructure_top> synthesized.
 
 
Synthesizing Unit <mig_21_data_path_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_data_path_0.vhd".
Unit <mig_21_data_path_0> synthesized.
 
 
Synthesizing Unit <mig_21_iobs_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_iobs_0.vhd".
Unit <mig_21_iobs_0> synthesized.
 
 
Synthesizing Unit <mig_21_top_0>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21_top_0.vhd".
Unit <mig_21_top_0> synthesized.
 
 
Synthesizing Unit <mig_21>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mig_21.vhd".
WARNING:Xst:1780 - Signal <dbg_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dbg_trans_twodtct> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dbg_trans_onedtct> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dbg_rst_calib> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dbg_phase_cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dbg_enb_trans_two_dtct> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dbg_delay_sel> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <dbg_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dbg_cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <control> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <mig_21> synthesized.
 
 
Synthesizing Unit <MYCPU>.
Related source file is "C:/Xilinx/FORTHSP3ADSPC/mycpu.vhd".
WARNING:Xst:646 - Signal <stack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <AddressOutd<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found finite state machine <FSM_7> for signal <DDRstate>.
-----------------------------------------------------------------------
| States | 11 |
| Transitions | 21 |
| Inputs | 8 |
| Outputs | 13 |
| Clock | Clock (rising_edge) |
| Reset | MasterReset (negative) |
| Reset type | asynchronous |
| Reset State | start |
| Power Up State | start |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 1-bit register for signal <acc>.
Found 1-bit register for signal <ackd>.
Found 1-bit register for signal <burst_done>.
Found 64-bit register for signal <captured>.
Found 1-bit register for signal <CEROM>.
Found 5-bit register for signal <chain>.
Found 64-bit register for signal <DataBlockInd>.
Found 32-bit register for signal <DBin>.
Found 1-bit register for signal <highlow>.
Found 8-bit register for signal <mymask>.
Found 1-bit register for signal <nReady>.
Found 1-bit register for signal <olddata_valid_out>.
Found 1-bit register for signal <oldROMtoStack>.
Found 4-bit register for signal <onehot>.
Found 1-bit register for signal <PPQ>.
Found 1-bit register for signal <sh>.
Found 3-bit register for signal <user_command_register>.
Found 8-bit register for signal <user_data_mask>.
Found 25-bit register for signal <user_input_address>.
Found 64-bit register for signal <user_input_data>.
Summary:
inferred 1 Finite State Machine(s).
inferred 284 D-type flip-flop(s).
Unit <MYCPU> synthesized.
 
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# RAMs : 11
4096x12-bit single-port RAM : 1
4096x13-bit single-port RAM : 1
4096x15-bit single-port RAM : 2
4096x26-bit single-port RAM : 2
4096x36-bit single-port RAM : 2
512x32-bit dual-port RAM : 3
# ROMs : 20
128x3-bit ROM : 1
16x4-bit ROM : 10
512x32-bit ROM : 9
# Adders/Subtractors : 41
12-bit adder : 3
12-bit subtractor : 1
16-bit subtractor : 3
2-bit subtractor : 1
24-bit subtractor : 5
25-bit adder : 1
25-bit subtractor : 2
26-bit adder : 5
26-bit subtractor : 2
27-bit subtractor : 1
28-bit adder : 1
3-bit subtractor : 3
33-bit adder carry in : 1
4-bit adder : 4
8-bit adder : 2
8-bit subtractor : 3
9-bit adder : 1
9-bit subtractor : 2
# Counters : 24
11-bit up counter : 1
12-bit up counter : 5
13-bit updown counter : 3
16-bit up counter : 1
3-bit down counter : 6
4-bit up counter : 1
5-bit up counter : 1
6-bit down counter : 1
6-bit up counter : 2
7-bit down counter : 1
8-bit down counter : 2
# Registers : 847
1-bit register : 629
10-bit register : 1
12-bit register : 33
13-bit register : 3
15-bit register : 2
16-bit register : 6
2-bit register : 15
23-bit register : 1
24-bit register : 10
25-bit register : 2
26-bit register : 4
27-bit register : 6
28-bit register : 3
3-bit register : 17
32-bit register : 50
4-bit register : 29
40-bit register : 1
5-bit register : 7
64-bit register : 8
8-bit register : 10
9-bit register : 10
# Comparators : 16
12-bit comparator equal : 3
17-bit comparator less : 1
4-bit comparator equal : 3
5-bit comparator greater : 2
5-bit comparator less : 1
9-bit comparator equal : 5
9-bit comparator greater : 1
# Multiplexers : 18
1-bit 32-to-1 multiplexer : 1
1-bit 4-to-1 multiplexer : 1
1-bit 8-to-1 multiplexer : 1
24-bit 8-to-1 multiplexer : 1
27-bit 4-to-1 multiplexer : 1
32-bit 4-to-1 multiplexer : 9
32-bit 8-to-1 multiplexer : 3
40-bit 4-to-1 multiplexer : 1
# Logic shifters : 2
34-bit shifter logical left : 1
34-bit shifter logical right : 1
# Xors : 37
1-bit xor10 : 1
1-bit xor2 : 34
1-bit xor8 : 1
32-bit xor2 : 1
 
=========================================================================
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
Analyzing FSM <FSM_7> for best encoding.
Optimizing FSM <DDRstate/FSM> on signal <DDRstate[1:11]> with one-hot encoding.
-------------------------
State | Encoding
-------------------------
start | 00000000001
idle | 00000000010
refresh | 00000000100
clear | 00000100000
delay | 00000001000
delay1 | 00001000000
delay2 | 00010000000
ack | 00000010000
readcmd | 10000000000
writecmd | 00100000000
sweep | 01000000000
-------------------------
Analyzing FSM <FSM_6> for best encoding.
Optimizing FSM <myRAM/top_00/controller0/init_current_state/FSM> on signal <init_current_state[1:2]> with user encoding.
--------------------------------
State | Encoding
--------------------------------
init_idle | 00
init_precharge | 01
init_auto_refresh | 10
init_load_mode_reg | 11
--------------------------------
Analyzing FSM <FSM_5> for best encoding.
Optimizing FSM <myRAM/top_00/controller0/current_state/FSM> on signal <current_state[1:4]> with gray encoding.
-------------------------------------
State | Encoding
-------------------------------------
idle | 0000
precharge | 1111
auto_refresh | 0001
active | 0011
first_write | 0110
write_wait | 0101
burst_write | 1100
precharge_after_write | 0100
precharge_after_write_2 | 1101
read_wait | 1110
burst_read | 0111
active_wait | 0010
-------------------------------------
Analyzing FSM <FSM_4> for best encoding.
Optimizing FSM <oneUART/TransmitState/FSM> on signal <TransmitState[1:2]> with sequential encoding.
-------------------------
State | Encoding
-------------------------
idle | 00
sending | 01
stopping | 11
sendingdone | 10
-------------------------
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <oneUART/ReceiveState/FSM> on signal <ReceiveState[1:6]> with one-hot encoding.
------------------------------
State | Encoding
------------------------------
idle | 000001
receivedata | 000010
receiveparity | 010000
receivestopbit | 001000
receivedstopbits | 000100
move | 100000
------------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <dcache/statequeue/FSM> on signal <statequeue[1:3]> with user encoding.
--------------------------
State | Encoding
--------------------------
queuestart | 000
queuewait | 001
queuewaitam1 | 010
queuewaitam2 | 011
queuewaita11 | 100
queuewaita12 | 101
queueelim | 110
--------------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <dcache/statetag/FSM> on signal <statetag[1:9]> with one-hot encoding.
------------------------
State | Encoding
------------------------
inittag | 000000001
startt | 000000010
startt1 | 000000100
tagtest | 000001000
tagwait | 000010000
stateget | 000100000
stateget1 | 010000000
finish | 001000000
finished | 100000000
------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <dcache/stateram/FSM> on signal <stateram[1:18]> with one-hot encoding.
----------------------------------
State | Encoding
----------------------------------
raminit | 000000000000000001
ramstart | 000000000000000010
ramstart1 | 000000000000000100
ramcheck | 000000000000100000
ramcheck1 | 000000000001000000
ramcheck2 | 000000000010000000
ramread | 000000100000000000
ramread1 | 000100000000000000
ramupdate | 000000000000001000
ramupdate1 | 000000000100000000
ramupdate2 | 000000010000000000
ramupdate3 | 001000000000000000
ramflush | 000001000000000000
ramflush1 | 100000000000000000
ramwait | 000000000000010000
ramwait1 | 000000001000000000
ramclean | 000010000000000000
ramclean1 | 010000000000000000
----------------------------------
Reading core <fifo_generator_v4_3.ngc>.
Loading core <fifo_generator_v4_3> for timing and area information for instance <sfifo>.
Loading core <fifo_generator_v4_3> for timing and area information for instance <rfifo>.
INFO:Xst:2261 - The FF/Latch <indexL_0> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_0>
INFO:Xst:2261 - The FF/Latch <indexL_1> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_1>
INFO:Xst:2261 - The FF/Latch <indexL_2> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_2>
INFO:Xst:2261 - The FF/Latch <indexL_3> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_3>
INFO:Xst:2261 - The FF/Latch <indexL_4> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_4>
INFO:Xst:2261 - The FF/Latch <ByteSelect_0> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTarget_0>
INFO:Xst:2261 - The FF/Latch <indexL_5> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_5>
INFO:Xst:2261 - The FF/Latch <indexL_6> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_6>
INFO:Xst:2261 - The FF/Latch <indexL_7> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_7>
INFO:Xst:2261 - The FF/Latch <oldf_8> in Unit <myStacks> is equivalent to the following FF/Latch, which will be removed : <olds_8>
INFO:Xst:2261 - The FF/Latch <tapfordqs_val_0> in Unit <cal_ctl0> is equivalent to the following FF/Latch, which will be removed : <tapfordqs_val_4>
WARNING:Xst:638 - in unit myRAM/infrastructure_top0/cal_top0/cal_ctl0 Conflict on KEEP property on signal tapfordqs_val<0> and tapfordqs_val<4> tapfordqs_val<4> signal will be lost.
INFO:Xst:2261 - The FF/Latch <tapfordqs_0> in Unit <cal_ctl0> is equivalent to the following FF/Latch, which will be removed : <tapfordqs_4>
INFO:Xst:2261 - The FF/Latch <free_1> in Unit <dcache> is equivalent to the following 2 FFs/Latches, which will be removed : <free_2> <free_3>
WARNING:Xst:1710 - FF/Latch <fast_1> (without init value) has a constant value of 0 in block <myStacks>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <column_address_reg_10> (without init value) has a constant value of 0 in block <controller0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <column_address_reg_11> (without init value) has a constant value of 0 in block <controller0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <column_address_reg_12> (without init value) has a constant value of 0 in block <controller0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <burst_length_2> (without init value) has a constant value of 0 in block <controller0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <SourceStep_3> of sequential type is unconnected in block <myStacks>.
WARNING:Xst:2677 - Node <burst_length_0> of sequential type is unconnected in block <controller0>.
WARNING:Xst:2677 - Node <AddressOut_0> of sequential type is unconnected in block <dcache>.
WARNING:Xst:2677 - Node <AddressOut_1> of sequential type is unconnected in block <dcache>.
WARNING:Xst:2677 - Node <column_address_reg_10> of sequential type is unconnected in block <controller0>.
WARNING:Xst:2677 - Node <column_address_reg_11> of sequential type is unconnected in block <controller0>.
WARNING:Xst:2677 - Node <column_address_reg_12> of sequential type is unconnected in block <controller0>.
WARNING:Xst:2404 - FFs/Latches <column_address_reg<12:10>> (without init value) have a constant value of 0 in block <mig_21_controller_0>.
WARNING:Xst:2404 - FFs/Latches <fast<1:1>> (without init value) have a constant value of 0 in block <theStacks>.
 
Synthesizing (advanced) Unit <ROMcode>.
INFO:Xst:3044 - The ROM <Mrom_bdata_3_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_3>.
INFO:Xst:3044 - The ROM <Mrom_bdata_2_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_2>.
INFO:Xst:3044 - The ROM <Mrom_bdata_4_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_4>.
INFO:Xst:3044 - The ROM <Mrom_bdata_5_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_5>.
INFO:Xst:3044 - The ROM <Mrom_bdata_6_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_6>.
INFO:Xst:3044 - The ROM <Mrom_bdata_8_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_8>.
INFO:Xst:3044 - The ROM <Mrom_bdata_7_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_7>.
INFO:Xst:3044 - The ROM <Mrom_bdata_0_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_0>.
INFO:Xst:3044 - The ROM <Mrom_bdata_1_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <bdata_1>.
INFO:Xst:3225 - The RAM <Mrom_bdata_3_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<3>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Mrom_bdata_2_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<2>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Mrom_bdata_4_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<4>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Mrom_bdata_5_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<5>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Mrom_bdata_6_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<6>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Mrom_bdata_8_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<8>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Mrom_bdata_7_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<7>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Mrom_bdata_0_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<0>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Mrom_bdata_1_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <Address> | |
| diA | connected to internal node | |
| doA | connected to signal <bdata<1>> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <ROMcode> synthesized (advanced).
 
Synthesizing (advanced) Unit <cache>.
INFO:Xst:3226 - The RAM <Mram_Ax> will be implemented as a BLOCK RAM, absorbing the following register(s): <g_varindex0000>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 13-bit | |
| mode | no-change | |
| clkA | connected to signal <Clock> | rise |
| enA | connected to signal <nReset> | high |
| weA | connected to signal <writec> | high |
| addrA | connected to signal <cindex> | |
| diA | connected to signal <CacheIn_FiFoaddr> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_tagRAM<1>> will be implemented as a BLOCK RAM, absorbing the following register(s): <_varindex0000>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 26-bit | |
| mode | no-change | |
| clkA | connected to signal <Clock> | rise |
| enA | connected to signal <nReset> | high |
| weA | connected to signal <writet> | high |
| addrA | connected to signal <AddressInt> | |
| diA | connected to signal <TagRAMIn<1>_cacheAddr> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_RAMs<1>> will be implemented as a BLOCK RAM, absorbing the following register(s): <_varindex0002>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 36-bit | |
| mode | no-change | |
| clkA | connected to signal <Clock> | rise |
| enA | connected to signal <nReset> | high |
| weA | connected to signal <writec> | high |
| addrA | connected to signal <cindex> | |
| diA | connected to signal <CacheIn_Words<1>_Word> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_RAMs<0>> will be implemented as a BLOCK RAM, absorbing the following register(s): <_varindex0003>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 36-bit | |
| mode | no-change | |
| clkA | connected to signal <Clock> | rise |
| enA | connected to signal <nReset> | high |
| weA | connected to signal <writec> | high |
| addrA | connected to signal <cindex> | |
| diA | connected to signal <CacheIn_Words<0>_Word> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_tagRAM<0>> will be implemented as a BLOCK RAM, absorbing the following register(s): <_varindex0001>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 26-bit | |
| mode | no-change | |
| clkA | connected to signal <Clock> | rise |
| enA | connected to signal <nReset> | high |
| weA | connected to signal <writet> | high |
| addrA | connected to signal <AddressInt> | |
| diA | connected to signal <TagRAMIn<0>_cacheAddr> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_ramAm> will be implemented as a BLOCK RAM, absorbing the following register(s): <AmOutBuff_varindex0000>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 15-bit | |
| mode | no-change | |
| clkA | connected to signal <Clock> | rise |
| enA | connected to signal <nReset> | high |
| weA | connected to signal <counterAm_or0000> | high |
| addrA | connected to internal node | |
| diA | connected to internal node | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_ramf> will be implemented as a BLOCK RAM, absorbing the following register(s): <FreeOut>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 12-bit | |
| mode | no-change | |
| clkA | connected to signal <Clock> | rise |
| enA | connected to signal <nReset> | high |
| weA | connected to signal <putf> | high |
| addrA | connected to internal node | |
| diA | connected to internal node | |
| doA | connected to signal <FreeOut> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_ramA1> will be implemented as a BLOCK RAM, absorbing the following register(s): <A1OutBuff_varindex0000>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 15-bit | |
| mode | no-change | |
| clkA | connected to signal <Clock> | rise |
| enA | connected to signal <nReset> | high |
| weA | connected to signal <counterA1_or0000> | high |
| addrA | connected to internal node | |
| diA | connected to internal node | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <cache> synthesized (advanced).
 
Synthesizing (advanced) Unit <theStacks>.
INFO:Xst:3226 - The RAM <Mram_Cache> will be implemented as a BLOCK RAM, absorbing the following register(s): <Random>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | read-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to signal <store_0> | high |
| addrA | connected to signal <IndexI> | |
| diA | connected to signal <tostore_0_mux0002> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkB | connected to signal <Clock> | rise |
| enB | connected to signal <newearly_2_mux0001> | low |
| addrB | connected to internal node | |
| doB | connected to signal <Random> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_Cache_ren> will be implemented as a BLOCK RAM, absorbing the following register(s): <TheSecond>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | read-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to signal <store_1> | high |
| addrA | connected to signal <IndexI> | |
| diA | connected to signal <tostore_0_mux0002> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkB | connected to signal <Clock> | rise |
| enB | connected to signal <TheSecond_not0001> | high |
| addrB | connected to internal node | |
| doB | connected to signal <TheSecond> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram_Cache_ren_1> will be implemented as a BLOCK RAM, absorbing the following register(s): <TheFirst>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 512-word x 32-bit | |
| mode | read-first | |
| clkA | connected to signal <Clock> | rise |
| weA | connected to signal <store_2> | high |
| addrA | connected to signal <IndexI> | |
| diA | connected to signal <tostore_0_mux0002> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 512-word x 32-bit | |
| mode | write-first | |
| clkB | connected to signal <Clock> | rise |
| enB | connected to signal <TheFirst_not0001> | high |
| addrB | connected to internal node | |
| doB | connected to signal <TheFirst> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <theStacks> synthesized (advanced).
WARNING:Xst:2677 - Node <burst_length_0> of sequential type is unconnected in block <mig_21_controller_0>.
WARNING:Xst:2677 - Node <SourceStep_3> of sequential type is unconnected in block <theStacks>.
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# FSMs : 8
# RAMs : 20
4096x12-bit single-port block RAM : 1
4096x13-bit single-port block RAM : 1
4096x15-bit single-port block RAM : 2
4096x26-bit single-port block RAM : 2
4096x36-bit single-port block RAM : 2
512x32-bit dual-port block RAM : 3
512x32-bit single-port block RAM : 9
# ROMs : 11
128x3-bit ROM : 1
16x4-bit ROM : 10
# Adders/Subtractors : 41
12-bit adder : 3
12-bit subtractor : 1
16-bit subtractor : 3
2-bit subtractor : 1
24-bit subtractor : 5
25-bit adder : 1
25-bit subtractor : 2
26-bit adder : 5
26-bit subtractor : 2
27-bit subtractor : 1
28-bit adder : 1
3-bit subtractor : 3
33-bit adder carry in : 1
4-bit adder : 4
8-bit adder : 2
8-bit subtractor : 3
9-bit adder : 1
9-bit subtractor : 2
# Counters : 24
11-bit up counter : 1
12-bit up counter : 5
13-bit updown counter : 3
16-bit up counter : 1
3-bit down counter : 6
4-bit up counter : 1
5-bit up counter : 1
6-bit down counter : 1
6-bit up counter : 2
7-bit down counter : 1
8-bit down counter : 2
# Registers : 4019
Flip-Flops : 4019
# Comparators : 16
12-bit comparator equal : 3
17-bit comparator less : 1
4-bit comparator equal : 3
5-bit comparator greater : 2
5-bit comparator less : 1
9-bit comparator equal : 5
9-bit comparator greater : 1
# Multiplexers : 18
1-bit 32-to-1 multiplexer : 1
1-bit 4-to-1 multiplexer : 1
1-bit 8-to-1 multiplexer : 1
24-bit 8-to-1 multiplexer : 1
27-bit 4-to-1 multiplexer : 1
32-bit 4-to-1 multiplexer : 9
32-bit 8-to-1 multiplexer : 3
40-bit 4-to-1 multiplexer : 1
# Logic shifters : 2
34-bit shifter logical left : 1
34-bit shifter logical right : 1
# Xors : 37
1-bit xor10 : 1
1-bit xor2 : 34
1-bit xor8 : 1
32-bit xor2 : 1
 
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <burst_length_2> (without init value) has a constant value of 0 in block <mig_21_controller_0>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <free_1> in Unit <cache> is equivalent to the following 2 FFs/Latches, which will be removed : <free_2> <free_3>
INFO:Xst:2261 - The FF/Latch <tapfordqs_val_0> in Unit <mig_21_cal_ctl> is equivalent to the following FF/Latch, which will be removed : <tapfordqs_val_4>
WARNING:Xst:638 - in unit mig_21_cal_ctl Conflict on KEEP property on signal tapfordqs_val<0> and tapfordqs_val<4> tapfordqs_val<4> signal will be lost.
INFO:Xst:2261 - The FF/Latch <tapfordqs_0> in Unit <mig_21_cal_ctl> is equivalent to the following FF/Latch, which will be removed : <tapfordqs_4>
INFO:Xst:2261 - The FF/Latch <ByteSelect_0> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTarget_0>
INFO:Xst:2261 - The FF/Latch <indexL_0> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_0>
INFO:Xst:2261 - The FF/Latch <indexL_1> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_1>
INFO:Xst:2261 - The FF/Latch <indexL_2> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_2>
INFO:Xst:2261 - The FF/Latch <indexL_3> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_3>
INFO:Xst:2261 - The FF/Latch <indexL_4> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_4>
INFO:Xst:2261 - The FF/Latch <oldf_8> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <olds_8>
INFO:Xst:2261 - The FF/Latch <indexL_5> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_5>
INFO:Xst:2261 - The FF/Latch <indexL_6> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_6>
INFO:Xst:2261 - The FF/Latch <indexL_7> in Unit <theStacks> is equivalent to the following FF/Latch, which will be removed : <aTail_7>
INFO:Xst:2261 - The FF/Latch <reset90_r> in Unit <mig_21_data_read_0> is equivalent to the following 2 FFs/Latches, which will be removed : <fifo1_rd_addr_inst/reset90_r> <fifo0_rd_addr_inst/reset90_r>
INFO:Xst:2261 - The FF/Latch <found_1> in Unit <cache> is equivalent to the following 2 FFs/Latches, which will be removed : <found_2> <found_3>
WARNING:Xst:1710 - FF/Latch <user_command_register_0> (without init value) has a constant value of 0 in block <MYCPU>. This FF/Latch will be trimmed during the optimization process.
 
Optimizing unit <MYCPU> ...
 
Optimizing unit <counter> ...
 
Optimizing unit <IntVectors> ...
 
Optimizing unit <ROMcode> ...
 
Optimizing unit <cache> ...
 
Optimizing unit <ALU> ...
 
Optimizing unit <mig_21_infrastructure> ...
 
Optimizing unit <mig_21_data_write_0> ...
 
Optimizing unit <mig_21_cal_ctl> ...
 
Optimizing unit <mig_21_controller_0> ...
WARNING:Xst:1710 - FF/Latch <dqs_div_rdburstcount_2> (without init value) has a constant value of 0 in block <mig_21_controller_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dqs_div_rdburstcount_2> (without init value) has a constant value of 0 in block <mig_21_controller_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dqs_div_rdburstcount_2> (without init value) has a constant value of 0 in block <mig_21_controller_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dqs_div_rdburstcount_2> (without init value) has a constant value of 0 in block <mig_21_controller_0>. This FF/Latch will be trimmed during the optimization process.
 
Optimizing unit <mig_21_ram8d_0> ...
 
Optimizing unit <mig_21_dqs_delay_2> ...
 
Optimizing unit <mig_21_fifo_0_wr_en_0> ...
 
Optimizing unit <mig_21_fifo_1_wr_en_0> ...
 
Optimizing unit <mig_21_wr_gray_cntr> ...
 
Optimizing unit <mig_21_controller_iobs_0> ...
 
Optimizing unit <mig_21_tap_dly> ...
 
Optimizing unit <ProgramCounter> ...
 
Optimizing unit <UART> ...
 
Optimizing unit <theStacks> ...
 
Optimizing unit <mig_21_data_read_0> ...
 
Optimizing unit <mig_21_data_read_controller_0> ...
 
Optimizing unit <mig_21_data_path_iobs_0> ...
 
Optimizing unit <theCore> ...
 
Optimizing unit <mig_21_infrastructure_top> ...
WARNING:Xst:2677 - Node <dcache/AddressOut_1> of sequential type is unconnected in block <MYCPU>.
WARNING:Xst:2677 - Node <dcache/AddressOut_0> of sequential type is unconnected in block <MYCPU>.
 
Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <myRAM/top_00/data_path0/data_read0/reset90_r> in Unit <MYCPU> is equivalent to the following FF/Latch, which will be removed : <myRAM/top_00/data_path0/data_read_controller0/reset90_r>
INFO:Xst:2261 - The FF/Latch <myRAM/top_00/controller0/rst0_r> in Unit <MYCPU> is equivalent to the following FF/Latch, which will be removed : <myRAM/top_00/data_path0/data_read_controller0/reset_r>
INFO:Xst:2261 - The FF/Latch <myRAM/top_00/data_path0/data_read0/read_valid_data_1_r> in Unit <MYCPU> is equivalent to the following FF/Latch, which will be removed : <myRAM/top_00/data_path0/data_read_controller0/read_valid_data_r>
INFO:Xst:2261 - The FF/Latch <myRAM/top_00/data_path0/data_read0/read_valid_data_1_r1> in Unit <MYCPU> is equivalent to the following FF/Latch, which will be removed : <myRAM/top_00/data_path0/data_read_controller0/read_valid_data_r1>
Found area constraint ratio of 100 (+ 5) on block MYCPU, actual ratio is 30.
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i>
FlipFlop myCore/myStacks/SelectedOp_0 has been replicated 2 time(s)
FlipFlop myCore/myStacks/SelectedPop_0 has been replicated 1 time(s)
FlipFlop myCore/myStacks/afast_1 has been replicated 1 time(s)
FlipFlop myCore/myStacks/fast has been replicated 1 time(s)
FlipFlop myCore/myStacks/stall1 has been replicated 1 time(s)
FlipFlop myRAM/infrastructure_top0/sys_rst has been replicated 4 time(s)
 
Final Macro Processing ...
 
Processing Unit <MYCPU> :
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m90_2_3>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m90_2_2>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m90_2_1>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m90_2_0>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_31>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_30>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_29>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_28>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_27>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_26>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_25>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_24>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_23>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_22>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_21>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_20>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_19>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_18>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_17>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_16>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_15>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_14>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_13>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_12>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_11>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_10>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_9>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_8>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_7>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_6>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_5>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_4>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_3>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_2>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_1>.
Found 7-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data90_2_0>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_31>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_30>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_29>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_28>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_27>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_26>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_25>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_24>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_23>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_22>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_21>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_20>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_19>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_18>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_17>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_16>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_15>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_14>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_13>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_12>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_11>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_10>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_9>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_8>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_7>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_6>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_5>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_4>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_3>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_2>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_1>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data270_2_0>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m270_2_3>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m270_2_2>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m270_2_1>.
Found 3-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m270_2_0>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m4_7>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m4_6>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m4_5>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data_m4_4>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_63>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_62>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_61>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_60>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_59>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_58>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_57>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_56>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_55>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_54>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_53>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_52>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_51>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_50>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_49>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_48>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_47>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_46>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_45>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_44>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_43>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_42>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_41>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_40>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_39>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_38>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_37>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_36>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_35>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_34>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_33>.
Found 4-bit shift register for signal <myRAM/top_00/data_path0/data_write0/write_data4_32>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_9>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_8>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_7>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_6>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_5>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_4>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_3>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_2>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_1>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/column_address_reg_0>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_12>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_11>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_10>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_9>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_8>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_7>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_6>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_5>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_4>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_3>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_2>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_1>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/row_address_reg_0>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/ba_address_reg2_1>.
Found 2-bit shift register for signal <myRAM/top_00/controller0/ba_address_reg2_0>.
Found 4-bit shift register for signal <myCore/myProgramCounter/service_3>.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <onehot_3> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <MYCPU> processed.
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers : 3693
Flip-Flops : 3693
# Shift Registers : 134
2-bit shift register : 25
3-bit shift register : 36
4-bit shift register : 37
7-bit shift register : 36
 
=========================================================================
 
=========================================================================
* Partition Report *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
* Final Report *
=========================================================================
 
Clock Information:
------------------
------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-------+
SysClock | mydcm/DCM_SP_INST:CLKFX+myRAM/infrastructure_top0/clk_dcm0/DCM_INST1:CLK90| 602 |
SysClock | mydcm/DCM_SP_INST:CLKFX+myRAM/infrastructure_top0/clk_dcm0/DCM_INST1:CLK0 | 3622 |
myRAM/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/clk_out(myRAM/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one:O)| NONE(*)(myRAM/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0)| 13 |
myRAM/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/clk_out(myRAM/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one:O)| NONE(*)(myRAM/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1)| 13 |
myRAM/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/clk_out(myRAM/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one:O)| NONE(*)(myRAM/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0)| 13 |
myRAM/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/clk_out(myRAM/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one:O)| NONE(*)(myRAM/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1)| 13 |
myRAM/top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/clk_out(myRAM/top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/one:O)| NONE(*)(myRAM/top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit0)| 13 |
myRAM/top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/clk_out(myRAM/top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/one:O)| NONE(*)(myRAM/top_00/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit1)| 13 |
myRAM/top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/clk_out(myRAM/top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/one:O)| NONE(*)(myRAM/top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit0)| 13 |
myRAM/top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/clk_out(myRAM/top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/one:O)| NONE(*)(myRAM/top_00/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit1)| 13 |
------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-------+
(*) These 8 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
 
Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
---------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------+
myRAM/infrastructure_top0/sys_rst_3(myRAM/infrastructure_top0/sys_rst_3:Q) | NONE(PPQ) | 444 |
myRAM/infrastructure_top0/sys_rst_4(myRAM/infrastructure_top0/sys_rst_4:Q) | NONE(myCore/SelectAlu_0) | 443 |
myRAM/infrastructure_top0/sys_rst_5(myRAM/infrastructure_top0/sys_rst_5:Q) | NONE(myCore/myProgramCounter/Im_0) | 443 |
myRAM/infrastructure_top0/sys_rst(myRAM/infrastructure_top0/sys_rst:Q) | NONE(CEROM) | 163 |
oneUART/resetfifo(oneUART/resetfifo1:O) | NONE(oneUART/Count0_0) | 93 |
myRAM/top_00/controller0/rst0_r(myRAM/top_00/controller0/rst0_r:Q) | NONE(myRAM/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0)| 40 |
oneUART/rfifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(oneUART/rfifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(oneUART/rfifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_afull_i) | 34 |
oneUART/sfifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(oneUART/sfifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(oneUART/sfifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_afull_i) | 34 |
oneUART/rfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(oneUART/rfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(oneUART/rfifo/BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1) | 25 |
oneUART/sfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(oneUART/sfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(oneUART/sfifo/BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1) | 25 |
oneUART/rfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<0>(oneUART/rfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0:Q)| NONE(oneUART/rfifo/BU2/U0/grf.rf/mem/dout_i_0) | 9 |
oneUART/sfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<0>(oneUART/sfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0:Q)| NONE(oneUART/sfifo/BU2/U0/grf.rf/mem/dout_i_0) | 9 |
oneUART/rfifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(oneUART/rfifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O) | NONE(oneUART/rfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0) | 2 |
oneUART/sfifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(oneUART/sfifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O) | NONE(oneUART/sfifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0) | 2 |
oneUART/rfifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(oneUART/rfifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O) | NONE(oneUART/rfifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1) | 1 |
oneUART/sfifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(oneUART/sfifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O) | NONE(oneUART/sfifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1) | 1 |
---------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -4
 
Minimum period: 6.620ns (Maximum Frequency: 151.057MHz)
Minimum input arrival time before clock: 38.589ns
Maximum output required time after clock: 5.558ns
Maximum combinational path delay: 5.789ns
 
=========================================================================
WARNING:Xst:616 - Invalid property "syn_preserve TRUE": Did not attach to myRAM/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0.
WARNING:Xst:616 - Invalid property "syn_preserve TRUE": Did not attach to myRAM/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1.
WARNING:Xst:616 - Invalid property "syn_preserve TRUE": Did not attach to myRAM/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0.
WARNING:Xst:616 - Invalid property "syn_preserve TRUE": Did not attach to myRAM/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1.
WARNING:Xst:616 - Invalid property "syn_preserve TRUE": Did not attach to myRAM/top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0.
WARNING:Xst:616 - Invalid property "syn_preserve TRUE": Did not attach to myRAM/top_00/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1.
WARNING:Xst:616 - Invalid property "syn_preserve TRUE": Did not attach to myRAM/top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0.
WARNING:Xst:616 - Invalid property "syn_preserve TRUE": Did not attach to myRAM/top_00/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1.
 
Process "Synthesize - XST" completed successfully
 
Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc MYCPU.ucf -p xc3sd1800a-fg676-4 MYCPU.ngc MYCPU.ngd
 
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc MYCPU.ucf -p xc3sd1800a-fg676-4
MYCPU.ngc MYCPU.ngd
 
Reading NGO file "C:/Xilinx/FORTHSP3ADSPC/MYCPU.ngc" ...
Loading design module "C:\Xilinx\FORTHSP3ADSPC/fifo_generator_v4_3.ngc"...
Gathering constraint information from source properties...
Done.
 
Annotating constraints to design from ucf file "MYCPU.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
 
 
 
Done...
 
Checking expanded design ...
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
 
Writing NGD file "MYCPU.ngd" ...
Total REAL time to NGDBUILD completion: 12 sec
Total CPU time to NGDBUILD completion: 12 sec
 
Writing NGDBUILD log file "MYCPU.bld"...
 
NGDBUILD done.
 
Process "Translate" completed successfully
 
Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc3sd1800a-fg676-4 -timing -logic_opt off -ol high -t 1 -register_duplication off -cm area -ir off -pr off -power off -o MYCPU_map.ncd MYCPU.ngd MYCPU.pcf
Using target part "3sd1800afg676-4".
Mapping design into LUTs...
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "myRAM/infrastructure_top0/clk_dcm0/BUFG_CLK0" (output
signal=myRAM/clk_0) has a mix of clock and non-clock loads. The non-clock
loads are:
Pin I0 of myRAM/infrastructure_top0/cal_top0/tap_dly0/l0
Running directed packing...
WARNING:Pack:266 - The function generator
dcache/CacheIn_Words<1>_Word_24_or00011 failed to merge with F5 multiplexer
dcache/accqueue_mux00011_f5. There is a conflict for the FXMUX. The design
will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator
myCore/myStacks/BufferedInput_mux0001<0>21 failed to merge with F5
multiplexer myCore/myStacks/BufferedInput_mux0001<31>15_SW1. There is a
conflict for the FXMUX. The design will exhibit suboptimal timing.
Running delay-based LUT packing...
Updating timing models...
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
Running timing-driven placement...
Total REAL time at the beginning of Placer: 24 secs
Total CPU time at the beginning of Placer: 24 secs
 
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:ff6ba948) REAL time: 27 secs
 
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:ff6ba948) REAL time: 27 secs
 
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:ff6ba948) REAL time: 27 secs
 
Phase 4.2 Initial Clock and IO Placement
 
Phase 4.2 Initial Clock and IO Placement (Checksum:762984d7) REAL time: 33 secs
 
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:762984d7) REAL time: 33 secs
 
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:762984d7) REAL time: 33 secs
 
Phase 7.8 Global Placement
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Phase 7.8 Global Placement (Checksum:4caadda1) REAL time: 1 mins 13 secs
 
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:4caadda1) REAL time: 1 mins 13 secs
 
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:59d55149) REAL time: 2 mins 17 secs
 
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:59d55149) REAL time: 2 mins 18 secs
 
Total REAL time to Placer completion: 2 mins 18 secs
Total CPU time to Placer completion: 2 mins 18 secs
Running post-placement packing...
 
Design Summary:
Number of errors: 0
Number of warnings: 19
Logic Utilization:
Number of Slice Flip Flops: 3,925 out of 33,280 11%
Number of 4 input LUTs: 8,447 out of 33,280 25%
Logic Distribution:
Number of occupied Slices: 5,917 out of 16,640 35%
Number of Slices containing only related logic: 5,917 out of 5,917 100%
Number of Slices containing unrelated logic: 0 out of 5,917 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 8,678 out of 33,280 26%
Number used as logic: 8,185
Number used as a route-thru: 231
Number used for Dual Port RAMs: 128
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 134
 
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
 
Number of bonded IOBs: 97 out of 519 18%
IOB Flip Flops: 20
IOB Master Pads: 6
IOB Slave Pads: 6
Number of ODDR2s used: 48
Number of DDR_ALIGNMENT = NONE 48
Number of DDR_ALIGNMENT = C0 0
Number of DDR_ALIGNMENT = C1 0
Number of BUFGMUXs: 4 out of 24 16%
Number of DCMs: 2 out of 8 25%
Number of RAMB16BWERs: 61 out of 84 72%
 
Number of RPM macros: 1
Average Fanout of Non-Clock Nets: 3.59
 
Peak Memory Usage: 570 MB
Total REAL time to MAP completion: 2 mins 25 secs
Total CPU time to MAP completion: 2 mins 24 secs
 
Mapping completed.
See MAP report file "MYCPU_map.mrp" for details.
 
Process "Map" completed successfully
 
Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -pl std -rl std -xe n -t 1 MYCPU_map.ncd MYCPU.ncd MYCPU.pcf
 
 
 
Constraints file: MYCPU.pcf.
Loading device for application Rf_Device from file '3sd1800a.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"MYCPU" is an NCD, version 3.2, device xc3sd1800a, package fg676, speed -4
WARNING:Par:281 -
Use of the PAR Extra Effort Levels (-xe n or c) is only available for the Placer and Router when the PAR Effort Level
set to maximum (-ol high) or when the Placer or Router Effort Level is set to maximum (-pl high or -rl high). It is
strongly recommended that the Placer Effort Level be set to "h"igh when using PAR Extra Effort Levels
 
 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
 
 
Device speed data version: "PRODUCTION 1.34 2013-10-13".
 
 
 
Design Summary Report:
 
Number of External IOBs 97 out of 519 18%
 
Number of External Input IOBs 17
 
Number of External Input IBUFs 17
Number of LOCed External Input IBUFs 17 out of 17 100%
 
 
Number of External Output IOBs 40
 
Number of External Output DIFFMs 2
Number of LOCed External Output DIFFMs 2 out of 2 100%
 
Number of External Output DIFFSs 2
Number of LOCed External Output DIFFSs 2 out of 2 100%
 
Number of External Output IOBs 36
Number of LOCed External Output IOBs 36 out of 36 100%
 
 
Number of External Bidir IOBs 40
 
Number of External Bidir DIFFMs 4
Number of LOCed External Bidir DIFFMs 4 out of 4 100%
 
Number of External Bidir DIFFSs 4
Number of LOCed External Bidir DIFFSs 4 out of 4 100%
 
Number of External Bidir IOBs 32
Number of LOCed External Bidir IOBs 32 out of 32 100%
 
 
Number of BUFGMUXs 4 out of 24 16%
Number of DCMs 2 out of 8 25%
Number of RAMB16BWERs 61 out of 84 72%
Number of Slices 5917 out of 16640 35%
Number of SLICEMs 216 out of 8320 2%
 
Number of LOCed Slices 125 out of 5917 2%
Number of LOCed SLICEMs 83 out of 216 38%
 
 
 
Overall effort level (-ol): Not applicable because -pl and -rl switches are used
Router effort level (-rl): Standard
 
INFO:Timing:2802 - Read 103 constraints. If you are experiencing memory or runtime issues it may help to consolidate
some of these constraints. For more details please do a search for "timing:2802" at http://www.xilinx.com/support.
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
Starting initial Timing Analysis. REAL time: 16 secs
Finished initial Timing Analysis. REAL time: 16 secs
 
Starting Router
 
 
Phase 1 : 42764 unrouted; REAL time: 37 secs
 
Phase 2 : 37934 unrouted; REAL time: 39 secs
 
Phase 3 : 10166 unrouted; REAL time: 46 secs
 
Phase 4 : 10380 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 55 secs
 
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 10 secs
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN
bel_d_dcm_dll_lowf_minperiod_clkin
Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MINIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN
Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN
bel_d_dcm_dll_lowf_maxperiod_clkin
Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS"
Type = MAXIMUM_PERIOD
Pin = "DCM_DCM/CLKIN"
Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN"
NumConnDefs = 0
NumModeDefs = 3
RadioButton[1] = DLL_FREQUENCY_MODE:LOW
RadioButton[2] = DFS_FREQUENCY_MODE:LOW
RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF
InvertedFlag = false
SyncFlag = false
SensePosFlag = false
ExtraTag = "DCM_DFS_CLK_OUTPUTS"
 
Updating file: MYCPU.ncd with current fully routed design.
 
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 18 secs
 
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 18 secs
 
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 22 secs
WARNING:Route:455 - CLK Net:myRAM/clk_0 may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/data_read0/dqs_delayed_col0_n<3> may have excessive skew because
6 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/dqs_delayed_col0<3> may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/dqs_delayed_col1<3> may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/data_read0/dqs_delayed_col1_n<3> may have excessive skew because
5 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/data_read0/dqs_delayed_col0_n<2> may have excessive skew because
6 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/dqs_delayed_col0<2> may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/dqs_delayed_col1<2> may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/data_read0/dqs_delayed_col1_n<2> may have excessive skew because
5 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/dqs_delayed_col1<1> may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/data_read0/dqs_delayed_col1_n<1> may have excessive skew because
5 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/data_read0/dqs_delayed_col0_n<0> may have excessive skew because
6 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/dqs_delayed_col0<0> may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/data_read0/dqs_delayed_col0_n<1> may have excessive skew because
6 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/dqs_delayed_col0<1> may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/dqs_delayed_col1<0> may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:myRAM/top_00/data_path0/data_read0/dqs_delayed_col1_n<0> may have excessive skew because
5 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
 
Total REAL time to Router completion: 1 mins 22 secs
Total CPU time to Router completion: 1 mins 21 secs
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| myRAM/clk_0 | BUFGMUX_X2Y1| No | 291 | 0.249 | 1.709 |
+---------------------+--------------+------+------+------------+-------------+
| Clock90 | BUFGMUX_X1Y0| No | 419 | 0.307 | 1.765 |
+---------------------+--------------+------+------+------------+-------------+
| Clock | BUFGMUX_X2Y11| No | 2918 | 0.305 | 1.765 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/dqs_delayed_col1 | | | | | |
| <0> | Local| | 7 | 0.008 | 0.474 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/data_read0/dqs_d | | | | | |
| elayed_col0_n<0> | Local| | 6 | 0.069 | 1.033 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/dqs_delayed_col1 | | | | | |
| <1> | Local| | 7 | 0.050 | 0.495 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/data_read0/dqs_d | | | | | |
| elayed_col0_n<1> | Local| | 6 | 0.566 | 1.479 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/dqs_delayed_col1 | | | | | |
| <2> | Local| | 7 | 0.034 | 0.487 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/data_read0/dqs_d | | | | | |
| elayed_col0_n<2> | Local| | 6 | 0.291 | 1.217 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/dqs_delayed_col1 | | | | | |
| <3> | Local| | 7 | 0.020 | 0.504 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/data_read0/dqs_d | | | | | |
| elayed_col0_n<3> | Local| | 6 | 0.825 | 1.523 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/dqs_delayed_col0 | | | | | |
| <0> | Local| | 6 | 0.017 | 0.473 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/dqs_delayed_col0 | | | | | |
| <1> | Local| | 6 | 0.038 | 0.483 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/dqs_delayed_col0 | | | | | |
| <2> | Local| | 6 | 0.018 | 0.468 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/dqs_delayed_col0 | | | | | |
| <3> | Local| | 6 | 0.014 | 0.476 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/data_read0/dqs_d | | | | | |
| elayed_col1_n<0> | Local| | 5 | 0.840 | 1.468 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/data_read0/dqs_d | | | | | |
| elayed_col1_n<1> | Local| | 5 | 0.553 | 1.490 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/data_read0/dqs_d | | | | | |
| elayed_col1_n<2> | Local| | 5 | 0.805 | 1.485 |
+---------------------+--------------+------+------+------------+-------------+
|myRAM/top_00/data_pa | | | | | |
|th0/data_read0/dqs_d | | | | | |
| elayed_col1_n<3> | Local| | 5 | 0.871 | 1.462 |
+---------------------+--------------+------+------+------------+-------------+
 
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
 
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
 
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
 
Number of Timing Constraints that were not applied: 5
 
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
 
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
NET "myRAM/infrastructure_top0/cal_top0/t | MAXDELAY | 0.002ns| 0.398ns| 0| 0
ap_dly0/tap<7>" MAXDELAY = 0.4 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/infrastructure_top0/cal_top0/t | MAXDELAY | 0.002ns| 0.398ns| 0| 0
ap_dly0/tap<23>" MAXDELAY = 0.4 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/infrastructure_top0/cal_top0/t | MAXDELAY | 0.002ns| 0.398ns| 0| 0
ap_dly0/tap<15>" MAXDELAY = 0.4 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/dqs_div_rst" MAXDELAY = | MAXDELAY | 0.003ns| 0.465ns| 0| 0
0.468 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.004ns| 0.186ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.004ns| 0.186ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.004ns| 0.186ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.004ns| 0.186ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.004ns| 0.186ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.004ns| 0.186ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.004ns| 0.186ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.004ns| 0.186ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data_read_co | MAXDELAY | 0.014ns| 0.186ns| 0| 0
ntroller0/rst_dqs_div_delayed/delay4" | | | | |
MAXDELAY = 0.2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.025ns| 0.165ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.025ns| 0.165ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.025ns| 0.165ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.025ns| 0.165ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.025ns| 0.165ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.025ns| 0.165ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.025ns| 0.165ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.025ns| 0.165ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.035ns| 0.155ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.035ns| 0.155ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.035ns| 0.155ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data_read_co | MAXDELAY | 0.035ns| 0.165ns| 0| 0
ntroller0/rst_dqs_div_delayed/delay3" | | | | |
MAXDELAY = 0.2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.035ns| 0.155ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.035ns| 0.155ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.035ns| 0.155ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.035ns| 0.155ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.035ns| 0.155ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.069ns| 0.121ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.069ns| 0.121ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.069ns| 0.121ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.069ns| 0.121ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.069ns| 0.121ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.069ns| 0.121ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.069ns| 0.121ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.069ns| 0.121ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.085ns| 0.105ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.085ns| 0.105ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.085ns| 0.105ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.085ns| 0.105ns| 0| 0
_read_controller0/gen_delay[1].dqs_delay_ | | | | |
col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.085ns| 0.105ns| 0| 0
_read_controller0/gen_delay[3].dqs_delay_ | | | | |
col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.085ns| 0.105ns| 0| 0
_read_controller0/gen_delay[0].dqs_delay_ | | | | |
col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.085ns| 0.105ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data | MAXDELAY | 0.085ns| 0.105ns| 0| 0
_read_controller0/gen_delay[2].dqs_delay_ | | | | |
col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data_read_co | MAXDELAY | 0.095ns| 0.105ns| 0| 0
ntroller0/rst_dqs_div_delayed/delay2" | | | | |
MAXDELAY = 0.2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/dqs_int_delay_in<1>" MA | MAXDELAY | 0.098ns| 1.563ns| 0| 0
XDELAY = 1.661 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data_read_co | MAXDELAY | 0.126ns| 0.074ns| 0| 0
ntroller0/rst_dqs_div_delayed/delay5" | | | | |
MAXDELAY = 0.2 ns | | | | |
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "mydcm/CLKFX_BUF" | SETUP | 0.143ns| 16.523ns| 0| 0
derived from NET "mydcm/CLKIN_IBUFG" PE | HOLD | 0.848ns| | 0| 0
RIOD = 8 ns HIGH 40% | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data_read_co | MAXDELAY | 0.156ns| 0.044ns| 0| 0
ntroller0/rst_dqs_div_delayed/delay1" | | | | |
MAXDELAY = 0.2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/dqs_int_delay_in<2>" MA | MAXDELAY | 0.215ns| 1.446ns| 0| 0
XDELAY = 1.661 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_WADDR_CLK = MAXDELAY FROM TIMEGRP "dqs | SETUP | 0.376ns| 4.624ns| 0| 0
_clk" TO TIMEGRP "fifo_waddr_clk" 5 | HOLD | 0.833ns| | 0| 0
ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "myRAM/infrastruc | SETUP | 0.399ns| 15.070ns| 0| 0
ture_top0/clk_dcm0/clk0dcm" derived from | HOLD | 0.760ns| | 0| 0
PERIOD analysis for net "mydcm/CLKFX_BUF | | | | |
" derived from NET "mydcm/CLKIN_IBUFG" PE | | | | |
RIOD = 8 ns HIGH 40% | | | | |
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "myRAM/infrastruc | SETUP | 0.577ns| 14.357ns| 0| 0
ture_top0/clk_dcm0/clk90dcm" derived from | HOLD | 0.813ns| | 0| 0
PERIOD analysis for net "mydcm/CLKFX_BU | | | | |
F" derived from NET "mydcm/CLKIN_IBUFG" P | | | | |
ERIOD = 8 ns HIGH 40% | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/data_read_co | MAXDELAY | 0.721ns| 2.286ns| 0| 0
ntroller0/rst_dqs_div" MAXDELAY = | | | | |
3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_WE_CLK = MAXDELAY FROM TIMEGRP "dqs_cl | SETUP | 0.791ns| 4.209ns| 0| 0
k" TO TIMEGRP "fifo_we_clk" 5 ns | HOLD | 0.881ns| | 0| 0
DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/dqs_int_delay_in<0>" MA | MAXDELAY | 0.867ns| 0.794ns| 0| 0
XDELAY = 1.661 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/dqs_int_delay_in<3>" MA | MAXDELAY | 0.900ns| 0.761ns| 0| 0
XDELAY = 1.661 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_en | MAXDELAY | 1.085ns| 1.922ns| 0| 0
<0>" MAXDELAY = 3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_en | MAXDELAY | 1.385ns| 1.622ns| 0| 0
<1>" MAXDELAY = 3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_en | MAXDELAY | 1.496ns| 1.511ns| 0| 0
<3>" MAXDELAY = 3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_en | MAXDELAY | 1.702ns| 1.305ns| 0| 0
<3>" MAXDELAY = 3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_en | MAXDELAY | 1.712ns| 1.295ns| 0| 0
<1>" MAXDELAY = 3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_en | MAXDELAY | 1.825ns| 1.182ns| 0| 0
<2>" MAXDELAY = 3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_en | MAXDELAY | 1.973ns| 1.034ns| 0| 0
<2>" MAXDELAY = 3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "mydcm/CLKIN_IBUFG" PERIOD = 8 ns HIG | MINHIGHPULSE| 2.000ns| 6.000ns| 0| 0
H 40% | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_en | MAXDELAY | 2.040ns| 0.967ns| 0| 0
<0>" MAXDELAY = 3.007 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 3.553ns| 2.837ns| 0| 0
dr<0>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 3.910ns| 2.480ns| 0| 0
dr<0>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.003ns| 2.387ns| 0| 0
dr<2>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.069ns| 2.321ns| 0| 0
dr<2>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.104ns| 2.286ns| 0| 0
dr<1>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.236ns| 2.154ns| 0| 0
dr<14>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.379ns| 2.011ns| 0| 0
dr<13>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.436ns| 1.954ns| 0| 0
dr<3>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.460ns| 1.930ns| 0| 0
dr<14>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.463ns| 1.927ns| 0| 0
dr<7>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.465ns| 1.925ns| 0| 0
dr<12>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.477ns| 1.913ns| 0| 0
dr<3>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.493ns| 1.897ns| 0| 0
dr<13>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.542ns| 1.848ns| 0| 0
dr<9>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.557ns| 1.833ns| 0| 0
dr<12>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.669ns| 1.721ns| 0| 0
dr<5>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.675ns| 1.715ns| 0| 0
dr<5>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.710ns| 1.680ns| 0| 0
dr<1>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.713ns| 1.677ns| 0| 0
dr<6>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.739ns| 1.651ns| 0| 0
dr<4>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.763ns| 1.627ns| 0| 0
dr<15>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.791ns| 1.599ns| 0| 0
dr<4>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.841ns| 1.549ns| 0| 0
dr<10>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.852ns| 1.538ns| 0| 0
dr<11>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.921ns| 1.469ns| 0| 0
dr<8>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 4.941ns| 1.449ns| 0| 0
dr<10>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 4.948ns| 1.442ns| 0| 0
dr<6>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 5.003ns| 1.387ns| 0| 0
dr<8>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 5.023ns| 1.367ns| 0| 0
dr<11>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 5.053ns| 1.337ns| 0| 0
dr<15>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_0_wr_ad | MAXDELAY | 5.064ns| 1.326ns| 0| 0
dr<9>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "myRAM/top_00/data_path0/fifo_1_wr_ad | MAXDELAY | 5.118ns| 1.272ns| 0| 0
dr<7>" MAXDELAY = 6.39 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK = MAXDELAY FROM TIMEGRP "clk0" TO | SETUP | 6.073ns| 11.927ns| 0| 0
TIMEGRP "dqs_clk" 18 ns DATAPATHONLY | HOLD | 4.459ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_SYS_CLK = PERIOD TIMEGRP "SYS_CLK" 15 | MINLOWPULSE | 9.000ns| 6.000ns| 0| 0
ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_myRAM_infrastructure_top0_clk_dcm0_clk | MINLOWPULSE | 11.796ns| 3.204ns| 0| 0
90dcm = PERIOD TIMEGRP "myRAM_inf | | | | |
rastructure_top0_clk_dcm0_clk90dcm" TS_SY | | | | |
S_CLK PHASE 3.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_myRAM_infrastructure_top0_clk_dcm0_clk | MINPERIOD | 12.986ns| 2.014ns| 0| 0
0dcm = PERIOD TIMEGRP "myRAM_infr | | | | |
astructure_top0_clk_dcm0_clk0dcm" TS_SYS_ | | | | |
CLK HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK90 = MAXDELAY FROM TIMEGRP "dqs_clk | SETUP | 13.628ns| 4.372ns| 0| 0
" TO TIMEGRP "clk90" 18 ns DATAPA | HOLD | 1.812ns| | 0| 0
THONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_DQS_CLK = MAXDELAY FROM TIMEGRP "dqs_c | N/A | N/A| N/A| N/A| N/A
lk" TO TIMEGRP "fifo_clk" 5 ns DA | | | | |
TAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
 
 
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for mydcm/CLKIN_IBUFG
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|mydcm/CLKIN_IBUFG | 8.000ns| 6.000ns| 7.931ns| 0| 0| 0| 978599|
| mydcm/CLKFX_BUF | 16.667ns| 16.523ns| 15.070ns| 0| 0| 975077| 3522|
| myRAM/infrastructure_top0/clk| 16.667ns| 15.070ns| N/A| 0| 0| 2373| 0|
| _dcm0/clk0dcm | | | | | | | |
| myRAM/infrastructure_top0/clk| 16.667ns| 14.357ns| N/A| 0| 0| 1149| 0|
| _dcm0/clk90dcm | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
Derived Constraints for TS_SYS_CLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK | 15.000ns| 6.000ns| 3.204ns| 0| 0| 0| 0|
| TS_myRAM_infrastructure_top0_c| 15.000ns| 2.014ns| N/A| 0| 0| 0| 0|
| lk_dcm0_clk0dcm | | | | | | | |
| TS_myRAM_infrastructure_top0_c| 15.000ns| 3.204ns| N/A| 0| 0| 0| 0|
| lk_dcm0_clk90dcm | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 1 mins 29 secs
Total CPU time to PAR completion: 1 mins 26 secs
 
Peak Memory Usage: 560 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 18
Number of info messages: 1
 
Writing design to file MYCPU.ncd
 
 
 
PAR done!
 
Process "Place & Route" completed successfully
 
Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 3 -a -s 4 -n 3 -xml MYCPU.twx MYCPU.ncd -o MYCPU.twr MYCPU.pcf -ucf MYCPU.ucf
Loading device for application Rf_Device from file '3sd1800a.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
"MYCPU" is an NCD, version 3.2, device xc3sd1800a, package fg676, speed -4
 
Analysis completed Fri Apr 06 09:48:50 2018
--------------------------------------------------------------------------------
 
Generating Report ...
 
Number of warnings: 0
Total time: 18 secs
 
Process "Generate Post-Place & Route Static Timing" completed successfully
 
Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f MYCPU.ut MYCPU.ncd
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/dqs_delayed_col1<0> is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/data_read0/dqs_delayed_col0_n<0> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/dqs_delayed_col1<1> is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/data_read0/dqs_delayed_col0_n<1> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/dqs_delayed_col1<2> is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/data_read0/dqs_delayed_col0_n<2> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/dqs_delayed_col1<3> is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/data_read0/dqs_delayed_col0_n<3> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/dqs_delayed_col0<0> is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/dqs_delayed_col0<1> is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/dqs_delayed_col0<2> is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/dqs_delayed_col0<3> is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/data_read0/dqs_delayed_col1_n<0> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/data_read0/dqs_delayed_col1_n<1> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/data_read0/dqs_delayed_col1_n<2> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
myRAM/top_00/data_path0/data_read0/dqs_delayed_col1_n<3> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
with the CLKFX and CLKFX180 outputs of the DCM comp mydcm/DCM_SP_INST,
consult the device Interactive Data Sheet.
 
Process "Generate Programming File" completed successfully

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