URL
https://opencores.org/ocsvn/natalius_8bit_risc/natalius_8bit_risc/trunk
Subversion Repositories natalius_8bit_risc
Compare Revisions
- This comparison shows the changes necessary to convert path
/natalius_8bit_risc
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/trunk/impl_prj/_xmsgs/pn_parser.xmsgs
0,0 → 1,36
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/ALU.v\" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/LIFO.v\" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/control_unit.v\" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/data_path.v\" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/instruction_memory.v\" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/natalius_processor.v\" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/regfile.v\" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/shiftbyte.v\" into library work</arg> |
</msg> |
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</messages> |
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/trunk/impl_prj/impl_prj.gise
0,0 → 1,28
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<!-- --> |
|
<!-- For tool use only. Do not edit. --> |
|
<!-- --> |
|
<!-- ProjectNavigator created generated project file. --> |
|
<!-- For use in tracking generated file and other information --> |
|
<!-- allowing preservation of process status. --> |
|
<!-- --> |
|
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> |
|
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version> |
|
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="impl_prj.xise"/> |
|
<files xmlns="http://www.xilinx.com/XMLSchema"/> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"/> |
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</generated_project> |
/trunk/impl_prj/impl_prj.xise
0,0 → 1,372
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="../mem_video.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../memram.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../pines.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../pong_top_level.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../vga_control.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../processor_core/ALU.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../processor_core/control_unit.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../processor_core/data_path.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../processor_core/instruction_memory.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../processor_core/LIFO.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../processor_core/natalius_processor.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../processor_core/regfile.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../processor_core/shiftbyte.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
</files> |
|
<properties> |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/> |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc3s1600e" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Module|pong_top_level" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="../pong_top_level.v" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pong_top_level" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="pong_top_level" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pong_top_level_map.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="pong_top_level_timesim.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pong_top_level_synthesis.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pong_top_level_translate.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="impl_prj" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-06-04T20:47:53" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A10F4C0F3C0C4053B4B3A1D0365B4F85" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings/> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
</autoManagedFiles> |
|
</project> |
/trunk/impl_prj/iseconfig/impl_prj.projectmgr
0,0 → 1,87
<?xml version='1.0' encoding='utf-8'?> |
<!--This is an ISE project configuration file.--> |
<!--It holds project specific layout data for the projectmgr plugin.--> |
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> |
<Project version="2" owner="projectmgr" name="impl_prj" > |
<!--This is an ISE project configuration file.--> |
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > |
<ClosedNodes> |
<ClosedNodesVersion>2</ClosedNodesVersion> |
<ClosedNode>/pong_top_level C:|natalius|pong_top_level.v/processor - natalius_processor</ClosedNode> |
</ClosedNodes> |
<SelectedItems> |
<SelectedItem>processor - natalius_processor (C:/natalius/processor_core/natalius_processor.v)</SelectedItem> |
</SelectedItems> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000019e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000019e0000000100000000000000000000000100000000</ViewHeaderState> |
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> |
<CurrentItem>processor - natalius_processor (C:/natalius/processor_core/natalius_processor.v)</CurrentItem> |
</ItemView> |
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > |
<ClosedNodes> |
<ClosedNodesVersion>1</ClosedNodesVersion> |
<ClosedNode>Design Utilities</ClosedNode> |
</ClosedNodes> |
<SelectedItems/> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" /> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem/> |
</ItemView> |
<ItemView guiview="File" > |
<ClosedNodes> |
<ClosedNodesVersion>1</ClosedNodesVersion> |
</ClosedNodes> |
<SelectedItems/> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000</ViewHeaderState> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem></CurrentItem> |
</ItemView> |
<ItemView guiview="Library" > |
<ClosedNodes> |
<ClosedNodesVersion>1</ClosedNodesVersion> |
<ClosedNode>work</ClosedNode> |
</ClosedNodes> |
<SelectedItems/> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>work</CurrentItem> |
</ItemView> |
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > |
<ClosedNodes> |
<ClosedNodesVersion>1</ClosedNodesVersion> |
<ClosedNode>Configure Target Device</ClosedNode> |
<ClosedNode>Design Utilities</ClosedNode> |
<ClosedNode>Implement Design</ClosedNode> |
<ClosedNode>Synthesize - XST</ClosedNode> |
<ClosedNode>User Constraints</ClosedNode> |
</ClosedNodes> |
<SelectedItems> |
<SelectedItem></SelectedItem> |
</SelectedItems> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001af000000010000000100000000000000000000000064ffffffff000000810000000000000001000001af0000000100000000</ViewHeaderState> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem></CurrentItem> |
</ItemView> |
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_MEM" guiview="Process" > |
<ClosedNodes> |
<ClosedNodesVersion>1</ClosedNodesVersion> |
</ClosedNodes> |
<SelectedItems/> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" /> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem/> |
</ItemView> |
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView> |
<CurrentView>Implementation</CurrentView> |
</Project> |
/trunk/impl_prj/iseconfig/pong_top_level.xreport
0,0 → 1,217
<?xml version='1.0' encoding='UTF-8'?> |
<report-views version="2.0" > |
<header> |
<DateModified>2012-06-05T08:46:23</DateModified> |
<ModuleName>pong_top_level</ModuleName> |
<SummaryTimeStamp>Unknown</SummaryTimeStamp> |
<SavedFilePath>C:/natalius/impl_prj/iseconfig/pong_top_level.xreport</SavedFilePath> |
<ImplementationReportsDirectory>C:/natalius/impl_prj\</ImplementationReportsDirectory> |
<DateInitialized>2012-06-04T20:48:18</DateInitialized> |
<EnableMessageFiltering>false</EnableMessageFiltering> |
</header> |
<body> |
<viewgroup label="Design Overview" > |
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="pong_top_level_summary.html" label="Summary" > |
<toc-item title="Design Overview" target="Design Overview" /> |
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> |
<toc-item title="Performance Summary" target="Performance Summary" /> |
<toc-item title="Failing Constraints" target="Failing Constraints" /> |
<toc-item title="Detailed Reports" target="Detailed Reports" /> |
</view> |
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="pong_top_level_envsettings.html" label="System Settings" /> |
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="pong_top_level_map.xrpt" label="IOB Properties" /> |
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="pong_top_level_map.xrpt" label="Control Set Information" /> |
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="pong_top_level_map.xrpt" label="Module Level Utilization" /> |
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="pong_top_level.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> |
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="pong_top_level_par.xrpt" label="Pinout Report" /> |
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="pong_top_level_par.xrpt" label="Clock Report" /> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="pong_top_level.twx" label="Static Timing" /> |
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="pong_top_level_html/fit/report.htm" label="CPLD Fitter Report" /> |
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="pong_top_level_html/tim/report.htm" label="CPLD Timing Report" /> |
</viewgroup> |
<viewgroup label="XPS Errors and Warnings" > |
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> |
<view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" /> |
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> |
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> |
</viewgroup> |
<viewgroup label="XPS Reports" > |
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> |
<view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" /> |
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> |
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> |
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="pong_top_level.log" label="System Log File" /> |
</viewgroup> |
<viewgroup label="Errors and Warnings" > |
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> |
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> |
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> |
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> |
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> |
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> |
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> |
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> |
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> |
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> |
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> |
</viewgroup> |
<viewgroup label="Detailed Reports" > |
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="pong_top_level.syr" label="Synthesis Report" > |
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> |
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> |
<toc-item title="HDL Compilation" target=" HDL Compilation " /> |
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> |
<toc-item title="HDL Analysis" target=" HDL Analysis " /> |
<toc-item title="HDL Parsing" target=" HDL Parsing " /> |
<toc-item title="HDL Elaboration" target=" HDL Elaboration " /> |
<toc-item title="HDL Synthesis" target=" HDL Synthesis " /> |
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> |
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> |
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> |
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> |
<toc-item title="Partition Report" target=" Partition Report " /> |
<toc-item title="Final Report" target=" Final Report " /> |
<toc-item title="Design Summary" target=" Design Summary " /> |
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> |
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> |
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> |
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> |
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> |
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> |
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> |
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> |
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> |
</view> |
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="pong_top_level.srr" label="Synplify Report" /> |
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="pong_top_level.prec_log" label="Precision Report" /> |
<view inputState="Synthesized" program="ngdbuild" type="Report" file="pong_top_level.bld" label="Translation Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Command Line" target="Command Line:" /> |
<toc-item title="Partition Status" target="Partition Implementation Status" /> |
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> |
</view> |
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="pong_top_level_map.mrp" label="Map Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> |
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> |
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> |
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> |
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> |
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> |
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> |
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> |
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> |
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> |
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> |
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> |
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="pong_top_level.par" label="Place and Route Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Device Utilization" target="Device Utilization Summary:" /> |
<toc-item title="Router Information" target="Starting Router" /> |
<toc-item title="Partition Status" target="Partition Implementation Status" /> |
<toc-item title="Clock Report" target="Generating Clock Report" /> |
<toc-item title="Timing Results" target="Timing Score:" /> |
<toc-item title="Final Summary" target="Peak Memory Usage:" /> |
</view> |
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="pong_top_level.twr" label="Post-PAR Static Timing Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Timing Report Description" target="Device,package,speed:" /> |
<toc-item title="Informational Messages" target="INFO:" /> |
<toc-item title="Warning Messages" target="WARNING:" /> |
<toc-item title="Timing Constraints" target="Timing constraint:" /> |
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
<toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
<toc-item title="Timing Summary" target="Timing summary:" /> |
<toc-item title="Trace Settings" target="Trace Settings:" /> |
</view> |
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="pong_top_level.rpt" label="CPLD Fitter Report (Text)" > |
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> |
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> |
<toc-item title="Pin Resources" target="** Pin Resources **" /> |
<toc-item title="Global Resources" target="** Global Control Resources **" /> |
</view> |
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="pong_top_level.tim" label="CPLD Timing Report (Text)" > |
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> |
<toc-item title="Performance Summary" target="Performance Summary:" /> |
</view> |
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="pong_top_level.pwr" label="Power Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Power summary" target="Power summary" /> |
<toc-item title="Thermal summary" target="Thermal summary" /> |
</view> |
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="pong_top_level.bgn" label="Bitgen Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> |
<toc-item title="Final Summary" target="DRC detected" /> |
</view> |
</viewgroup> |
<viewgroup label="Secondary Reports" > |
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> |
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/pong_top_level_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/pong_top_level_translate.nlf" label="Post-Translate Simulation Model Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="pong_top_level_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> |
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="pong_top_level_map.map" label="Map Log File" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
<toc-item title="Design Information" target="Design Information" /> |
<toc-item title="Design Summary" target="Design Summary" /> |
</view> |
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> |
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level_preroute.twr" label="Post-Map Static Timing Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Timing Report Description" target="Device,package,speed:" /> |
<toc-item title="Informational Messages" target="INFO:" /> |
<toc-item title="Warning Messages" target="WARNING:" /> |
<toc-item title="Timing Constraints" target="Timing constraint:" /> |
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
<toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
<toc-item title="Timing Summary" target="Timing summary:" /> |
<toc-item title="Trace Settings" target="Trace Settings:" /> |
</view> |
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/pong_top_level_map.nlf" label="Post-Map Simulation Model Report" /> |
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level_map.psr" label="Physical Synthesis Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="pong_top_level_pad.txt" label="Pad Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="pong_top_level.unroutes" label="Unroutes Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
</view> |
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level_preroute.tsi" label="Post-Map Constraints Interaction Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level.grf" label="Guide Results Report" /> |
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level.dly" label="Asynchronous Delay Report" /> |
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level.clk_rgn" label="Clock Region Report" /> |
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level.tsi" label="Post-Place and Route Constraints Interaction Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
</view> |
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="pong_top_level_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> |
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/pong_top_level_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> |
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="pong_top_level_sta.nlf" label="Primetime Netlist Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="pong_top_level.ibs" label="IBIS Model" > |
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> |
<toc-item title="Component" target="Component " /> |
</view> |
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level.lck" label="Back-annotate Pin Report" > |
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> |
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> |
</view> |
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="pong_top_level.lpc" label="Locked Pin Constraints" > |
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> |
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> |
</view> |
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/pong_top_level_timesim.nlf" label="Post-Fit Simulation Model Report" /> |
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> |
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> |
</viewgroup> |
</body> |
</report-views> |
/trunk/impl_prj/pong_top_level.bit
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+Xilinx Design Summary
+
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Date Generated: 06/05/2012 - 08:46:23
+
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pong_top_level Project Status | |||
Project File: | +impl_prj.xise | +Parser Errors: | +No Errors | +
Module Name: | +pong_top_level | +Implementation State: | +New | +
Target Device: | +xc3s1600e-4fg320 | +
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++ |
Product Version: | ISE 12.4 | +
|
++ |
Design Goal: | +Balanced | +
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++ | +
Design Strategy: | +Xilinx Default (unlocked) | +
|
++ |
Environment: | ++ |
|
++ |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | +Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |