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/README.md
1,12 → 1,12
# Introduction |
## Introduction |
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Welcome to the NEO430 Processor project! |
Welcome to the __NEO430 Processor__ project! |
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You need a small but still powerful, customizable and microcontroller-like |
processor system for your next FPGA design? Then the NEO430 is the perfect |
choice for you! |
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This processor is based on the Texas Instruments MSP430 ISA and provides 100% |
This processor is based on the Texas Instruments MSP430(TM) ISA and provides 100% |
compatibility with the original instruction set. The NEO430 is not an MSP430 |
clone – it is more a complete new implementation from the bottom up. The |
processor features a very small outline, already implementing standard |
32,7 → 32,7
setup from this project, upload it to your FPGA board of choice and start |
exploring the capabilities of the NEO430 processor. Application program |
generation (and even installation) works by executing a single "make" command. |
Jump to the "Let’s Get It Starte" chapter, which provides a lot of guides and |
Jump to the "Let’s Get It Started" chapter, which provides a lot of guides and |
tutorials to make your first NEO430 setup run: |
https://github.com/stnolting/neo430/blob/master/doc/NEO430.pdf |
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50,24 → 50,25
- Application compilation scripts for Windows and Linux/Cygwin |
- Completely described in behavioral, platform-independent VHDL |
- Fully synchronous design, no latches, no gated clocks |
- Operates at high frequencies (150 MHz) - no clock-domain crossing required for integration |
- Very small outline and high operating frequency compared to other implementations ;) |
- Internal DMEN (RAM, for data) and IMEM (RAM or ROM, for code), configurable sizes |
- One external interrupt line |
- Customizable processor hardware configuration |
- Optional custom function unit (CFU) to add your custom memory-mapped functions |
- Optional multiplier/divider unit (MULDIV) |
- Optional high-precision timer (TIMER) |
- Optional USART interface; UART and SPI (USART) |
- Optional USART interface; UART and SPI in parallel (USART) |
- Optional general purpose parallel IO port (GPIO), 16 inputs, 16 outputs, with pin-change interrupt |
- Optional 32-bit Wishbone bus interface adapter (WB32) |
- Optional 32-bit Wishbone bus interface adapter (WB32) - including bridges to Avalon(TM) bus and AXI-Lite(TM) |
- Optional watchdog timer (WDT) |
- Optional internal bootloader (2kB ROM) |
- Optional cyclic redundancy check unit (CRC16/32) |
- Optional custom functions unit (CFU) for user-defined processor extensions |
- Optional 3 channel 8-bit PWM controller |
- Optional internal bootloader (2kB ROM) with serial user console and automatic boot from external EEPROM |
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## Differences to TI's original MSP430 processors |
## Differences to TI's Original MSP430(TM) Processors |
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- Completely different processor modules with different functionality |
- No hardware multiplier support (but emulated in software) |
- Maximum of 32kB instruction memory and 28kB data memory |
- Specific memory map – included NEO430 linker script and compilation script required |
- Custom binary executable format |
79,6 → 80,22
- Internal bootloader with text interface (via UART serial port) |
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## Implementation Results |
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Mapping results generated for HW version 0x0170. The full (default) configuration includes |
all optional processor modules. |
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| __Xilinx Virtex-6__ | LUTs | FFs | BRAMs | DSPs | f_max | |
|-------------------------------------|:----:|-----|-------|------|---------| |
| Full (default) configuration: | TBA | TBA | 4 | 0 | TBA MHz | |
| Minimal configuration (CPU + GPIO): | TBA | TBA | 3 | 0 | TBA MHz | |
|
| __Intel/Altera Cyclone IV__ | LUTs | FFs | Memory bits | DSPs | f_max | |
|-------------------------------------|:----:|-----|-------------|------|---------| |
| Full (default) configuration: | 1588 | 868 | 65792 | 0 | 115 MHz | |
| Minimal configuration (CPU + GPIO): | 614 | 232 | 49408 | 0 | 120 MHz | |
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## Let's Get It Started! |
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* At first, make sure to get the most recent version of this project from GitHub: |
113,5 → 130,17
stnolting@gmail.com |
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## Proprietary Notice |
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"MSP430" is a trademark of Texas Instruments Corporation. |
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"Virtex", "ISE" and "Vivado" are trademarks of Xilinx Inc. |
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"Cyclone", "Quartus" and "Avalon bus" are trademarks of Intel Corporation. |
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"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc. |
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<img src="https://github.com/stnolting/neo430/blob/master/doc/figures/oshw_logo.png" width="100px"/> |