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/NEORV32.legacy.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/NEORV32.legacy.pdf
NEORV32.legacy.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: figures/neorv32_processor.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: src_adoc/cpu.adoc =================================================================== --- src_adoc/cpu.adoc (revision 57) +++ src_adoc/cpu.adoc (revision 58) @@ -6,11 +6,11 @@ **Key Features** * 32-bit pipelined/multi-cycle in-order `rv32` RISC-V CPU -* Optional RISC-V extensions: `rv32[i/e][m][a][c][b][Zfinx]` + `[u][Zicsr][Zifencei]` +* Optional RISC-V extensions: `rv32[i/e][m][a][c][b][u]` + `[Zfinx][Zicsr][Zifencei]` * Compatible to the RISC-V user specifications and a subset of the RISC-V privileged architecture specifications – passes the official RISC-V Architecture Tests (v2+) * Official RISC-V open-source architecture ID -* Safe execution hardware (see section 2.7. Execution Safety); among other things, the CPU supports all traps from the RISC-V specifications -(including bus access exceptions) and traps on all unimplemented/illegal/malformed instructions +* Standard RISC-V interrupts (_external_, _timer_, _software_) plus 16 _fast_ interrupts and 1 non-maskable interrupt +* Supports most of the traps from the RISC-V specifications (including bus access exceptions) and traps on all unimplemented/illegal/malformed instructions * Optional physical memory configuration (PMP), compatible to the RISC-V specifications * Optional hardware performance monitors (HPM) for application benchmarking * Separated interfaces for instruction fetch and data access (merged into single bus via a bus switch for @@ -206,11 +206,14 @@ interface provides big- and little-endian configurations. See section <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information. [IMPORTANT] -The `misa` CSR is read-only. It reflects the synthesized CPU extensions. Hence, all implemented +The `misa` CSR is read-only. It shows the synthesized CPU extensions. Hence, all implemented CPU extensions are always active and cannot be enabled/disabled dynamically during runtime. Any write access to it (in machine mode) is ignored and will not cause any exception or side-effects. [IMPORTANT] +The `mip` CSR is read-only. Pending IRQs can be cleared using the `mie` CSR. + +[IMPORTANT] The physical memory protection (see section <<_machine_physical_memory_protection>>) only supports the modes _OFF_ and _NAPOT_ yet and a minimal granularity of 8 bytes per region. @@ -281,6 +284,8 @@ | `d_bus_priv_o` | 2 | out | current CPU privilege level 4+^| **System Time** | `time_i` | 64 | in | system time input (from MTIME) +4+^| **Non-Maskable Interrupt** +| `nm_irq_i` | 1 | in | non-maskable interrupt 4+^| **Interrupts (RISC-V-compatible)** | `msw_irq_i` | 1 | in | RISC-V machine software interrupt | `mext_irq_i` | 1 | in | RISC-V machine external interrupt @@ -719,11 +724,19 @@ **Custom Fast Interrupt Request Lines** -As a custom extension, the NEORV32 CPU features 16 fast interrupt request lines via the `firq_i` CPU top +As a custom extension, the NEORV32 CPU features 16 fast interrupt request lines via the `firq_i` CPU (/Processor) top entity signals. These interrupts have custom configuration and status flags in the `mie` and `mip` CSRs and also -provide custom trap codes. +provide custom trap codes in `mcause`. +**Non-Maskable Interrupt** + +The NEORV32 CPU features a single non-maskable interrupt source via the `nm_irq_i` CPU (/Processor) top +entity signal that can be used to signal critical system conditions. This interrupt source _cannot_ be disabled at all (even not in interrupt service routines). +Hence, it does _not_ provide configuration/status flags in the `mie` and `mip` CSRs. The RISC-V-compatible +`mcause` value `0x80000000` is used to indicate the non-maskable interrupt. + + <<< // #################################################################################################################### :sectnums!: @@ -734,36 +747,36 @@ [options="header",grid="rows"] |======================= | Prio. | `mcause` | [RISC-V] | ID [C] | Cause | `mepc` | `mtval` -| 1 | `0x8000000B` | 1.11 | _TRAP_CODE_MEI_ | machine external interrupt | _I-PC_ | _0_ +| 1 | `0x80000000` | 1.0 | _TRAP_CODE_NMI_ | non-maskable interrupt | _I-PC_ | _0_ | 2 | `0x8000000B` | 1.11 | _TRAP_CODE_MEI_ | machine external interrupt | _I-PC_ | _0_ -| 2 | `0x80000003` | 1.3 | _TRAP_CODE_MSI_ | machine software interrupt | _I-PC_ | _0_ -| 3 | `0x80000007` | 1.7 | _TRAP_CODE_MTI_ | machine timer interrupt (from mtime) | _I-PC_ | _0_ -| 4 | `0x80000010` | 1.16 | _TRAP_CODE_FIRQ_0_ | fast interrupt request channel | _I-PC_ | _0_ -| 5 | `0x80000011` | 1.17 | _TRAP_CODE_FIRQ_1_ | fast interrupt request channel | _I-PC_ | _0_ -| 6 | `0x80000012` | 1.18 | _TRAP_CODE_FIRQ_2_ | fast interrupt request channel | _I-PC_ | _0_ -| 7 | `0x80000013` | 1.19 | _TRAP_CODE_FIRQ_3_ | fast interrupt request channel | _I-PC_ | _0_ -| 8 | `0x80000014` | 1.20 | _TRAP_CODE_FIRQ_4_ | fast interrupt request channel | _I-PC_ | _0_ -| 9 | `0x80000015` | 1.21 | _TRAP_CODE_FIRQ_5_ | fast interrupt request channel | _I-PC_ | _0_ -| 10 | `0x80000016` | 1.22 | _TRAP_CODE_FIRQ_6_ | fast interrupt request channel | _I-PC_ | _0_ -| 11 | `0x80000017` | 1.23 | _TRAP_CODE_FIRQ_7_ | fast interrupt request channel | _I-PC_ | _0_ -| 12 | `0x80000018` | 1.24 | _TRAP_CODE_FIRQ_8_ | fast interrupt request channel | _I-PC_ | _0_ -| 13 | `0x80000019` | 1.25 | _TRAP_CODE_FIRQ_9_ | fast interrupt request channel | _I-PC_ | _0_ -| 14 | `0x8000001a` | 1.26 | _TRAP_CODE_FIRQ_10_ | fast interrupt request channel | _I-PC_ | _0_ -| 15 | `0x8000001b` | 1.27 | _TRAP_CODE_FIRQ_11_ | fast interrupt request channel | _I-PC_ | _0_ -| 16 | `0x8000001c` | 1.28 | _TRAP_CODE_FIRQ_12_ | fast interrupt request channel | _I-PC_ | _0_ -| 17 | `0x8000001d` | 1.29 | _TRAP_CODE_FIRQ_13_ | fast interrupt request channel | _I-PC_ | _0_ -| 18 | `0x8000001e` | 1.30 | _TRAP_CODE_FIRQ_14_ | fast interrupt request channel | _I-PC_ | _0_ -| 19 | `0x8000001f` | 1.31 | _TRAP_CODE_FIRQ_15_ | fast interrupt request channel | _I-PC_ | _0_ -| 20 | `0x00000001` | 0.1 | _TRAP_CODE_I_ACCESS_ | instruction access fault | _B-ADR_ | _PC_ -| 21 | `0x00000002` | 0.2 | _TRAP_CODE_I_ILLEGAL_ | illegal instruction | _PC_ | _Inst_ -| 22 | `0x00000000` | 0.0 | _TRAP_CODE_I_MISALIGNED_ | instruction address misaligned | _B-ADR_ | _PC_ -| 23 | `0x0000000B` | 0.11 | _TRAP_CODE_MENV_CALL_ | environment call from M-mode (ECALL in machine-mode) | _PC_ | _PC_ -| 24 | `0x00000008` | 0.8 | _TRAP_CODE_UENV_CALL_ | environment call from U-mode(ECALL in user-mode) | _PC_ | _PC_ -| 25 | `0x00000003` | 0.3 | _TRAP_CODE_BREAKPOINT_ | breakpoint (EBREAK) | _PC_ | _PC_ -| 26 | `0x00000006` | 0.6 | _TRAP_CODE_S_MISALIGNED_ | store address misaligned | _B-ADR_ | _B-ADR_ -| 27 | `0x00000004` | 0.4 | _TRAP_CODE_L_MISALIGNED_ | load address misaligned | _B-ADR_ | _B-ADR_ -| 28 | `0x00000007` | 0.7 | _TRAP_CODE_S_ACCESS_ | store access fault | _B-ADR_ | _B-ADR_ -| 29 | `0x00000005` | 0.5 | _TRAP_CODE_L_ACCESS_ | lad access fault | _B-ADR_ | _B-ADR_ +| 3 | `0x80000003` | 1.3 | _TRAP_CODE_MSI_ | machine software interrupt | _I-PC_ | _0_ +| 4 | `0x80000007` | 1.7 | _TRAP_CODE_MTI_ | machine timer interrupt (from mtime) | _I-PC_ | _0_ +| 5 | `0x80000010` | 1.16 | _TRAP_CODE_FIRQ_0_ | fast interrupt request channel | _I-PC_ | _0_ +| 6 | `0x80000011` | 1.17 | _TRAP_CODE_FIRQ_1_ | fast interrupt request channel | _I-PC_ | _0_ +| 7 | `0x80000012` | 1.18 | _TRAP_CODE_FIRQ_2_ | fast interrupt request channel | _I-PC_ | _0_ +| 8 | `0x80000013` | 1.19 | _TRAP_CODE_FIRQ_3_ | fast interrupt request channel | _I-PC_ | _0_ +| 9 | `0x80000014` | 1.20 | _TRAP_CODE_FIRQ_4_ | fast interrupt request channel | _I-PC_ | _0_ +| 10 | `0x80000015` | 1.21 | _TRAP_CODE_FIRQ_5_ | fast interrupt request channel | _I-PC_ | _0_ +| 11 | `0x80000016` | 1.22 | _TRAP_CODE_FIRQ_6_ | fast interrupt request channel | _I-PC_ | _0_ +| 12 | `0x80000017` | 1.23 | _TRAP_CODE_FIRQ_7_ | fast interrupt request channel | _I-PC_ | _0_ +| 13 | `0x80000018` | 1.24 | _TRAP_CODE_FIRQ_8_ | fast interrupt request channel | _I-PC_ | _0_ +| 14 | `0x80000019` | 1.25 | _TRAP_CODE_FIRQ_9_ | fast interrupt request channel | _I-PC_ | _0_ +| 15 | `0x8000001a` | 1.26 | _TRAP_CODE_FIRQ_10_ | fast interrupt request channel | _I-PC_ | _0_ +| 16 | `0x8000001b` | 1.27 | _TRAP_CODE_FIRQ_11_ | fast interrupt request channel | _I-PC_ | _0_ +| 17 | `0x8000001c` | 1.28 | _TRAP_CODE_FIRQ_12_ | fast interrupt request channel | _I-PC_ | _0_ +| 18 | `0x8000001d` | 1.29 | _TRAP_CODE_FIRQ_13_ | fast interrupt request channel | _I-PC_ | _0_ +| 19 | `0x8000001e` | 1.30 | _TRAP_CODE_FIRQ_14_ | fast interrupt request channel | _I-PC_ | _0_ +| 20 | `0x8000001f` | 1.31 | _TRAP_CODE_FIRQ_15_ | fast interrupt request channel | _I-PC_ | _0_ +| 21 | `0x00000001` | 0.1 | _TRAP_CODE_I_ACCESS_ | instruction access fault | _B-ADR_ | _PC_ +| 22 | `0x00000002` | 0.2 | _TRAP_CODE_I_ILLEGAL_ | illegal instruction | _PC_ | _Inst_ +| 23 | `0x00000000` | 0.0 | _TRAP_CODE_I_MISALIGNED_ | instruction address misaligned | _B-ADR_ | _PC_ +| 24 | `0x0000000B` | 0.11 | _TRAP_CODE_MENV_CALL_ | environment call from M-mode (ECALL in machine-mode) | _PC_ | _PC_ +| 25 | `0x00000008` | 0.8 | _TRAP_CODE_UENV_CALL_ | environment call from U-mode(ECALL in user-mode) | _PC_ | _PC_ +| 26 | `0x00000003` | 0.3 | _TRAP_CODE_BREAKPOINT_ | breakpoint (EBREAK) | _PC_ | _PC_ +| 27 | `0x00000006` | 0.6 | _TRAP_CODE_S_MISALIGNED_ | store address misaligned | _B-ADR_ | _B-ADR_ +| 28 | `0x00000004` | 0.4 | _TRAP_CODE_L_MISALIGNED_ | load address misaligned | _B-ADR_ | _B-ADR_ +| 29 | `0x00000007` | 0.7 | _TRAP_CODE_S_ACCESS_ | store access fault | _B-ADR_ | _B-ADR_ +| 30 | `0x00000005` | 0.5 | _TRAP_CODE_L_ACCESS_ | lad access fault | _B-ADR_ | _B-ADR_ |======================= **Notes**
/src_adoc/cpu_csr.adoc
55,7 → 55,7
* `S` - have a constrained compatibility; for example not all specified bits are available
 
.NEORV32 Control and Status Registers (CSRs)
[cols="<1,<2,<2,^1,<3,^1"]
[cols="<4,<6,<11,^3,<11,^3"]
[options="header"]
|=======================
| Address | Name [ASM] | Name [C] | R/W | Function | Note
69,13 → 69,13
| 0x304 | `mie` | _CSR_MIE_ | r/w | Machine interrupt enable register | `C`
| 0x305 | `mtvec` | _CSR_MTVEC_ | r/w | Machine trap-handler base address (for ALL traps) |
| 0x306 | `mcounteren` | _CSR_MCOUNTEREN_ | r/w | Machine counter-enable register | `S`
| 0x310 | `mstatush` | _CSR_MSTATUSH_ | r/- | Machine status register – high word | `SR`
| 0x310 | `mstatush` | _CSR_MSTATUSH_ | r/- | Machine status register – high word | `RS`
6+^| **<<_machine_trap_handling>>**
| 0x340 | `mscratch` | _CSR_MSCRATCH_ | r/w | Machine scratch register |
| 0x341 | `mepc` | _CSR_MEPC_ | r/w | Machine exception program counter |
| 0x342 | `mcause` | _CSR_MCAUSE_ | r/w | Machine trap cause | `C`
| 0x343 | `mtval` | _CSR_MTVAL_ | r/w | Machine bad address or instruction |
| 0x344 | `mip` | _CSR_MIP_ | r/w | Machine interrupt pending register | `C`
| 0x344 | `mip` | _CSR_MIP_ | r/- | Machine interrupt pending register | `CR`
6+^| **<<_machine_physical_memory_protection>>**
| 0x3a0 .. 0x3af | `pmpcfg0` .. `pmpcfg15` | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `S`
| 0x3b0 .. 0x3ef | `pmpaddr0` .. `pmpaddr63`| _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
379,9 → 379,10
[frame="topbot",grid="none"]
|======
| 0x344 | **Machine interrupt Pending** | `mip`
3+| Reset value: _UNDEFINED_
3+| The `mip` CSR is compatible to the RISC-V specifications and provides custom extensions. It shows pending interrupts. Any pending interrupt can
be cleared by writing zero to the according bit(s). The following CSR bits are implemented (all remaining bits are always zero and are read-only).
3+| Reset value: _0x00000000_
3+| The `mip` CSR is _partly_ compatible to the RISC-V specifications and also provides custom extensions. It shows currently pending interrupts. Since this register is
read-only, pending interrupt can only be cleared by disabling and re-enabling the according `mie` CSr bit. Writing to this CSR will
raise an illegal instruction exception. The following CSR bits are implemented (all remaining bits are always zero and are read-only).
|======
 
.Machine interrupt pending register
389,10 → 390,10
[options="header",grid="rows"]
|=======================
| Bit | Name [C] | R/W | Function
| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/w | fast interrupt channel 15..0 pending
| 11 | _CSR_MIP_MEIP_ | r/w | machine _external_ interrupt pending
| 7 | _CSR_MIP_MTIP_ | r/w | machine _timer_ interrupt pending
| 3 | _CSR_MIP_MSIP_ | r/w | machine _software_ interrupt pending
| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/- | fast interrupt channel 15..0 pending
| 11 | _CSR_MIP_MEIP_ | r/- | machine _external_ interrupt pending
| 7 | _CSR_MIP_MTIP_ | r/- | machine _timer_ interrupt pending
| 3 | _CSR_MIP_MSIP_ | r/- | machine _software_ interrupt pending
|=======================
 
 
407,7 → 408,7
 
[TIP]
If trying to access an PMP-related CSR beyond _PMP_NUM_REGIONS_ **no illegal instruction
exception** is triggered. The according CSRs are read-only and always return zero.
exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
 
[IMPORTANT]
The RISC-V-compatible NEORV32 physical memory protection only implements the _NAPOT_
568,11 → 569,11
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
according `[m]hpmcounter*[h]` and `mhpmevent*` CSRs.
 
The total size of the HPMs can be configured before syntheis via the _HPM_CNT_WIDTH_ generic (1..64-bit).
The total size of the HPMs can be configured before synthesis via the _HPM_CNT_WIDTH_ generic (1..64-bit).
 
[TIP]
If trying to access an HPM-related CSR beyond _HPM_NUM_CNTS_ **no illegal instruction exception is
triggered**. The according CSRs are read-only and always return zero.
triggered**. The according CSRs are read-only (writes are ignored) and always return zero.
 
[NOTE]
The total LSB-aligned HPM counter size (low word CSR + high word CSR) is defined via the
774,4 → 775,6
| 5 | _CPU_MZEXT_ZFINX_ | r/- | `Zfinx` extensions available (enabled via _CPU_EXTENSION_RISCV_Zfinx_ generic)
| 6 | _CPU_MZEXT_ZXSCNT_ | r/- | custom extension: "Small CPU counters": `cycle[h]` & `instret[h]` CSRs have less than 64-bit when set (when _CPU_CNT_WIDTH_ generic is less than 64).
| 7 | _CPU_MZEXT_ZXNOCNT_ | r/- | custom extension: "NO CPU counters": `cycle[h]` & `instret[h]` CSRs are not available at all when set (when _CPU_CNT_WIDTH_ generic is 0).
| 8 | _CSR_MZEXT_PMP_ | r/- | PMP (physical memory protection) extension available (_PMP_NUM_REGIONS_ generic > 0) when set (r/-)
| 9 | _CSR_MZEXT_HPM_ | r/- | HPM (hardware performance monitors) extension available (_HPM_NUM_CNTS_ generic > 0) when set (r/-)
|=======================
/src_adoc/neorv32.adoc
2,7 → 2,7
:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.5.4.8
:revnumber: v1.5.5.0
:doctype: book
:sectnums:
:icons: image
/src_adoc/overview.adoc
209,33 → 209,34
[cols="<2,<8"]
[grid="topbot"]
|=======================
| Hardware version: | `1.5.2.4`
| Hardware version: | `1.5.4.9`
| Top entity: | `rtl/core/neorv32_top.vhd`
|=======================
 
.Hardware utilization by the processor modules
.Hardware utilization by the processor modules (mandatory core modules in **bold**)
[cols="<2,<8,>1,>1,>2,>1"]
[options="header",grid="rows"]
|=======================
| Module | Description | LEs | FFs | MEM bits | DSPs
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32768 | 0
| BUSSWITCH | Bus mux for CPU instr. and data interfaces | 65 | 8 | 0 | 0
| iCACHE | Instruction cache (4 blocks, 256 bytes per block) | 234 | 156 | 8192 | 0
| CFS | Custom functions subsystem | - | - | - | -
| DMEM | Processor-internal data memory (8kB) | 6 | 2 | 65536 | 0
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0
| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0
| MTIME | Machine system timer | 274 | 166 | 0 | 0
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0
| PWM | Pulse_width modulation controller | 71 | 69 | 0 | 0
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0
| SYSINFO | System configuration information memory | 10 | 10 | 0 | 0
| TRNG | True random number generator | 132 | 105 | 0 | 0
| TWI | Two-wire interface | 77 | 44 | 0 | 0
| UART0/1 | Universal asynchronous receiver/transmitter | 176 | 132 | 0 | 0
| WDT | Watchdog timer | 60 | 45 | 0 | 0
| WISHBONE | External memory interface | 129 | 104 | 0 | 0
| Module | Description | LEs | FFs | MEM bits | DSPs
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32768 | 0
| **BUSKEEPER** | Processor-internal bus monitor | 11 | 6 | 0 | 0
| **BUSSWITCH** | Bus mux for CPU instr. and data interface | 49 | 8 | 0 | 0
| CFS | Custom functions subsystem | - | - | - | -
| DMEM | Processor-internal data memory (8kB) | 18 | 2 | 65536 | 0
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0
| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 220 | 154 | 8192 | 0
| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0
| MTIME | Machine system timer | 289 | 200 | 0 | 0
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0
| PWM | Pulse_width modulation controller | 71 | 69 | 0 | 0
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0
| **SYSINFO** | System configuration information memory | 10 | 10 | 0 | 0
| TRNG | True random number generator | 132 | 105 | 0 | 0
| TWI | Two-wire interface | 77 | 44 | 0 | 0
| UART0/1 | Universal asynchronous receiver/transmitter o/1 | 176 | 132 | 0 | 0
| WDT | Watchdog timer | 60 | 45 | 0 | 0
| WISHBONE | External memory interface | 129 | 104 | 0 | 0
|=======================
 
 
/src_adoc/soc.adoc
94,6 → 94,7
4+^| **System time input from external MTIME unit**
| `mtime_i` | 32 | in | machine timer time (to `time[h]` CSRs) from external _MTIME_ unit if the processor-internal <<_machine_system_timer_mtime,**MTIME**>> unit is NOT used
4+^| **Interrupts**
| `nm_irq_i` | 1 | in | non-maskable interrupt
| `soc_firq_i` | 6 | in | platform fast interrupt channels (custom)
| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V)
| `msw_irq_i` | 1 | in | machine software interrupt (RISC-V)
314,7 → 315,8
|======
| **PMP_NUM_REGIONS** | _natural_ | 0
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
protection logic will be implemented at all.
protection logic will be implemented at all. Setting _PMP_NUM_REGIONS_ > 0 will set the _CSR_MZEXT_PMP_ flag
in the `mzext` CSR.
|======
 
 
337,7 → 339,8
|======
| **HPM_NUM_CNTS** | _natural_ | 0
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero no
hardware performance monitor logic will be implemented at all.
hardware performance monitor logic will be implemented at all. Setting _HPM_NUM_CNTS_ > 0 will set the _CSR_MZEXT_HPM_ flag
in the `mzext` CSR.
|======
 
 
612,6 → 615,11
:sectnums:
=== Processor Interrupts
 
[TIP]
The interrupt request signals have specific `mip` CSR bits (see <<_machine_trap_setup>>), specifc
`mie` CSR bits (see <<_machine_trap_handling>>) and specifc `mcause` CSR trap codes and trap
priorities (see <<_traps_exceptions_and_interrupts>>).
 
**RISC-V Standard Interrupts**
 
The processor setup features the standard RISC-V interrupt lines for "machine timer interrupt", "machine
625,11 → 633,6
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
(`FIRQ0` – `FIRQ15`).
 
[TIP]
The fast interrupt request signals have custom `mip` CSR bits (see <<_machine_trap_setup>>), custom
`mie` CSR bits (see <<_machine_trap_handling>>) and custom `mcause` CSR trap codes and trap
priories (see <<_traps_exceptions_and_interrupts>>).
 
The fast interrupt request signals are divided into two groups. The FIRQs with higher priority (FIRQ0 –
FIRQ9) are dedicated for processor-internal usage. The FIRQs with lower priority (FIRQ10 – FIRQ15) are
available for custom usage via the processor's top entity signal `soc_firq_i`.
654,7 → 657,12
| 10:15 | `soc_firq_i(5:0)` | Custom platform use; available via processor's top signal
|=======================
 
**Non-Maskable Interrupt**
 
The NEORV32 features a single non-maskable interrupt source via the `nm_irq_i` top
entity signal that can be used to signal critical system conditions. This interrupt source _cannot_ be disabled. Hence, it does _not_ provide
configuration/status flags in the `mie` and `mip` CSRs. The RISC-V-compatible `mcause` value `0x80000000` is used to indicate the non-maskable interrupt.
 
<<<
// ####################################################################################################################
:sectnums:
670,6 → 678,10
.NEORV32 processor - address space (default configuration)
image::../figures/address_space.png[900]
 
[TIP]
These four memory regions are handled by the linker when compiling a NEORV32 executable.
See section <<_executable_image_format>> for more information.
 
**Address Space Layout**
 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
/src_adoc/soc_pwm.adoc
46,7 → 46,7
 
[TIP]
A more sophisticated frequency generation option is provided by by the numerically-controlled oscillator
module (see section <<_numerically_controller-oscillator_nco>>).
module (see section <<_numerically_controller_oscillator_nco>>).
 
<<<
.PWM register map
/src_adoc/software.adoc
207,6 → 207,7
example: `$ make MARCH=-march=rv32ic clean_all exe`
 
 
 
<<<
// ####################################################################################################################
:sectnums:
213,13 → 214,34
=== Executable Image Format
 
When all the application sources have been compiled and linked, a final executable file has to be generated.
For this purpose, the makefile uses the NEORV32-specific linker script `sw/common/neorv32.ld` to link
all the sections into only four final sections: `.text`, `.rodata`, `.data` and `.bss`. These four section contain
everything required for the application to run:
For this purpose, the makefile uses the NEORV32-specific linker script `sw/common/neorv32.ld`. This linker script defines three memory sections:
`rom`, `ram` and `iodev`. These sections have specific access attributes: Read access (`r`), write access (`w`) and executable (`x`).
 
.Linker memory sections
[cols="<2,^1,<7"]
[options="header",grid="rows"]
|=======================
| Memory section | Attributes | Description
| `rom` | `rx` | Instruction memory (IMEM) **OR** bootloader ROM
| `ram` | `rwx` | Data memory (DMEM)
| `iodev` | `rw` | Memory-mapped IO/peripheral devices
|=======================
 
The `iodev` section is reserved for processor-internal memory-mapped IO and peripheral devices. The linker does not use this section at all
and just passes the start and end adresses of this section to the start-up code `crt0.S` (see next section).
 
[NOTE]
The `rom` region is used to place the instructions of "normal" applications. If the bootloader is being compiled, the makefile defines the `make_bootloader`
symbol, which changes the _ORIGIN_ (base address) and _LENGTH_ (size) attributes of the `rom` region according to the BOOTROM definitions.
 
The linker maps all the regions from the compiled object files into only four final sections: `.text`, `.rodata`, `.data` and `.bss`
using the specified memory section. These four regions contain everything required for the application to run:
 
.Executable regions
[cols="<1,<9"]
[grid="none"]
[options="header",grid="rows"]
|=======================
| Region | Description
| `.text` | Executable instructions generated from the start-up code and all application sources.
| `.rodata` | Constants (like strings) from the application; also the initial data for initialized variables.
| `.data` | This section is required for the address generation of fixed (= global) variables only.
255,7 → 277,22
provides a simple protection against data transmission or storage errors.
 
 
=== Start-Up Code (crt0)
 
The CPU (and also the processor) requires a minimal start-up and initialization code o bring the CPU (and the SoC) into a stable and initialized state before the
acutal application can be executed. This start-up code is located in `sw/common/crt0.S` and is automatically linked with _every_ application program.
The `crt0.S` is directly executed right after a reset and performs the following operations:
 
* Initialize integer registers `x1 - x31` (or `x1 - x15` when using the `E` CPU extension) to a defined value.
* Initialize all CPU core CSRs and also install a default "dummy" trap handler for _all_ traps.
* Initialize the global pointer `gp` and the stack pointer `sp` according to the `.data` segment layout provided by the linker script.
* Clear IO area: Write zero to all memory-mapped registers within the IO region (`iodev` section). If certain devices have not been implemented, a bus access fault exception will occur. This exception is captured by the dummy trap handler.
* Clear the `.bss` section defined by the linker script.
* Copy read-only data from the `.text` section to the `.data` section to set initialized variables.
* Call the application's `main` function (with no arguments: `argc` = `argv` = 0).
* If the `main` function returns, the processor goes to an endless sleep mode (using a simple loop or via the `wfi` instruction if available).
 
 
<<<
// ####################################################################################################################
:sectnums:
466,37 → 503,13
:sectnums:
=== NEORV32 Runtime Environment
 
The NEORV32 provides a minimal runtime environment (RTE) that mainly takes care of two things:
The NEORV32 provides a minimal runtime environment (RTE) that takes care of a stable
and _safe_ execution environment by handling _all_ traps (including interrupts).
 
* clean application start
* stable and _safe_ execution environment (e.g. handling of exceptions/interrupts)
 
[NOTE]
Performance or latency-optimized applications or embedded operating systems should use a custom
trap management.
Using the RTE is **optional**. The RTE provides a simple and comfortable way of delegating traps while making sure that all traps (even though they are not
explicitly used by the application) are handled correctly. Performance-optimized applications or embedded operating systems should not use the RTE for delegating traps.
 
 
:sectnums:
==== CRT0 Start-Up Code
 
The initial part of the runtime environment is the `sw/common/crt0.S` application start-up code. This piece
of code is automatically linked with every application program and represents the starting point for every
application - regardless if you are using the actual RTE in your application or not. The start-up code is directly executed after a reset.
Ir performs the following operations to bring the CPU (and the SoC) into a stable and initialized state:
 
* Initialize integer registers `x1` – `x15`/`x31`.
* Initialize all CPU core CSRs.
* Initialize the global pointer `gp` and the stack pointer `sp` according to the `.data` segment layout provided by the linker script.
* Clear IO area: Write zero to all memory-mapped registers within the IO region. If certain devices have not been implemented, a bus access fault exception will occur. This exception is captured by a simple dummy handler in the start-up code.
* Clear the `.bss` section defined by the linker script.
* Copy read-only data from the `.text` section to the `.data` section to set initialized variables.
* Call the application's `main` function (with no arguments).
* If the `main` function returns, the processor goes to an endless sleep mode (using a simple loop or via the `wfi` instruction if available).
 
 
:sectnums:
==== Using the NEORV32 Runtime Environment (RTE) in Your Application
 
When execution enters the application's `main` function, the actual runtime environment is responsible for catching all implemented exceptions
and interrupts. To activate the NEORV32 RTE execute the following function:
 
/NEORV32.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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