OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl/core
    from Rev 23 to Rev 24
    ↔ Reverse comparison
  •

Rev 23 → Rev 24

/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 836) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 849) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
44,7 → 44,7
00000033 => x"00158593",
00000034 => x"ff5ff06f",
00000035 => x"00001597",
00000036 => x"c8458593",
00000036 => x"cb858593",
00000037 => x"80000617",
00000038 => x"f6c60613",
00000039 => x"80000697",
87,25 → 87,25
00000076 => x"b0050513",
00000077 => x"00112623",
00000078 => x"00812423",
00000079 => x"500000ef",
00000080 => x"7e4000ef",
00000079 => x"514000ef",
00000080 => x"7f8000ef",
00000081 => x"02050c63",
00000082 => x"3a4000ef",
00000083 => x"00001537",
00000084 => x"a3850513",
00000085 => x"584000ef",
00000084 => x"a4c50513",
00000085 => x"598000ef",
00000086 => x"00000513",
00000087 => x"7d8000ef",
00000087 => x"7ec000ef",
00000088 => x"00000413",
00000089 => x"0ff47513",
00000090 => x"7cc000ef",
00000090 => x"7e0000ef",
00000091 => x"0c800513",
00000092 => x"774000ef",
00000092 => x"788000ef",
00000093 => x"00140413",
00000094 => x"fedff06f",
00000095 => x"00001537",
00000096 => x"a1450513",
00000097 => x"554000ef",
00000096 => x"a2850513",
00000097 => x"568000ef",
00000098 => x"00c12083",
00000099 => x"00812403",
00000100 => x"00000513",
163,7 → 163,7
00000152 => x"30200073",
00000153 => x"00001737",
00000154 => x"00279793",
00000155 => x"a5470713",
00000155 => x"a6870713",
00000156 => x"00e787b3",
00000157 => x"0007a783",
00000158 => x"00078067",
174,7 → 174,7
00000163 => x"f8f764e3",
00000164 => x"00001737",
00000165 => x"00279793",
00000166 => x"a8470713",
00000166 => x"a9870713",
00000167 => x"00e787b3",
00000168 => x"0007a783",
00000169 => x"00078067",
218,10 → 218,10
00000207 => x"00000000",
00000208 => x"00001537",
00000209 => x"ff010113",
00000210 => x"ac850513",
00000210 => x"adc50513",
00000211 => x"00112623",
00000212 => x"00812423",
00000213 => x"3dc000ef",
00000213 => x"3f0000ef",
00000214 => x"34202473",
00000215 => x"00b00793",
00000216 => x"0487f263",
233,7 → 233,7
00000222 => x"00001537",
00000223 => x"00040593",
00000224 => x"c5050513",
00000225 => x"3ac000ef",
00000225 => x"3c0000ef",
00000226 => x"0400006f",
00000227 => x"00001737",
00000228 => x"00279793",
248,8 → 248,8
00000237 => x"0007a783",
00000238 => x"00078067",
00000239 => x"00001537",
00000240 => x"ad050513",
00000241 => x"36c000ef",
00000240 => x"ae450513",
00000241 => x"380000ef",
00000242 => x"341025f3",
00000243 => x"00059783",
00000244 => x"00044a63",
263,51 → 263,51
00000252 => x"00001537",
00000253 => x"c6050513",
00000254 => x"01010113",
00000255 => x"3340006f",
00000255 => x"3480006f",
00000256 => x"00001537",
00000257 => x"af050513",
00000257 => x"b0450513",
00000258 => x"fbdff06f",
00000259 => x"00001537",
00000260 => x"b0c50513",
00000260 => x"b2050513",
00000261 => x"fb1ff06f",
00000262 => x"00001537",
00000263 => x"b2050513",
00000263 => x"b3450513",
00000264 => x"fa5ff06f",
00000265 => x"00001537",
00000266 => x"b2c50513",
00000266 => x"b4050513",
00000267 => x"f99ff06f",
00000268 => x"00001537",
00000269 => x"b4450513",
00000269 => x"b5850513",
00000270 => x"f8dff06f",
00000271 => x"00001537",
00000272 => x"b5850513",
00000272 => x"b6c50513",
00000273 => x"f81ff06f",
00000274 => x"00001537",
00000275 => x"b7450513",
00000275 => x"b8850513",
00000276 => x"f75ff06f",
00000277 => x"00001537",
00000278 => x"b8850513",
00000278 => x"b9c50513",
00000279 => x"f69ff06f",
00000280 => x"00001537",
00000281 => x"b9c50513",
00000281 => x"bb050513",
00000282 => x"f5dff06f",
00000283 => x"00001537",
00000284 => x"bb850513",
00000284 => x"bcc50513",
00000285 => x"f51ff06f",
00000286 => x"00001537",
00000287 => x"bd050513",
00000287 => x"be450513",
00000288 => x"f45ff06f",
00000289 => x"00001537",
00000290 => x"bec50513",
00000290 => x"c0050513",
00000291 => x"f39ff06f",
00000292 => x"00001537",
00000293 => x"c0450513",
00000293 => x"c1450513",
00000294 => x"f2dff06f",
00000295 => x"00001537",
00000296 => x"c1c50513",
00000296 => x"c2850513",
00000297 => x"f21ff06f",
00000298 => x"00001537",
00000299 => x"c3450513",
00000299 => x"c3c50513",
00000300 => x"f15ff06f",
00000301 => x"ffe58593",
00000302 => x"f2dff06f",
327,475 → 327,475
00000316 => x"00112623",
00000317 => x"00812423",
00000318 => x"00912223",
00000319 => x"1a000793",
00000320 => x"30579073",
00000321 => x"00000413",
00000322 => x"01000493",
00000323 => x"00040513",
00000324 => x"00140413",
00000325 => x"0ff47413",
00000326 => x"fa5ff0ef",
00000327 => x"fe9418e3",
00000328 => x"00c12083",
00000329 => x"00812403",
00000330 => x"00412483",
00000331 => x"01010113",
00000332 => x"00008067",
00000333 => x"fd010113",
00000334 => x"02812423",
00000335 => x"02912223",
00000336 => x"03212023",
00000337 => x"01312e23",
00000338 => x"01412c23",
00000339 => x"02112623",
00000340 => x"01512a23",
00000341 => x"00001a37",
00000342 => x"00050493",
00000343 => x"00058413",
00000344 => x"00058523",
00000345 => x"00000993",
00000346 => x"00410913",
00000347 => x"cf0a0a13",
00000348 => x"00a00593",
00000349 => x"00048513",
00000350 => x"438000ef",
00000351 => x"00aa0533",
00000352 => x"00054783",
00000353 => x"01390ab3",
00000319 => x"301027f3",
00000320 => x"00079863",
00000321 => x"00001537",
00000322 => x"cf050513",
00000323 => x"238000ef",
00000324 => x"1a000793",
00000325 => x"30579073",
00000326 => x"00000413",
00000327 => x"01000493",
00000328 => x"00040513",
00000329 => x"00140413",
00000330 => x"0ff47413",
00000331 => x"f91ff0ef",
00000332 => x"fe9418e3",
00000333 => x"00c12083",
00000334 => x"00812403",
00000335 => x"00412483",
00000336 => x"01010113",
00000337 => x"00008067",
00000338 => x"fd010113",
00000339 => x"02812423",
00000340 => x"02912223",
00000341 => x"03212023",
00000342 => x"01312e23",
00000343 => x"01412c23",
00000344 => x"02112623",
00000345 => x"01512a23",
00000346 => x"00001a37",
00000347 => x"00050493",
00000348 => x"00058413",
00000349 => x"00058523",
00000350 => x"00000993",
00000351 => x"00410913",
00000352 => x"d24a0a13",
00000353 => x"00a00593",
00000354 => x"00048513",
00000355 => x"00fa8023",
00000356 => x"00a00593",
00000357 => x"3d4000ef",
00000358 => x"00198993",
00000359 => x"00a00793",
00000360 => x"00050493",
00000361 => x"fcf996e3",
00000362 => x"00090693",
00000363 => x"00900713",
00000364 => x"03000613",
00000365 => x"0096c583",
00000366 => x"00070793",
00000367 => x"fff70713",
00000368 => x"01071713",
00000369 => x"01075713",
00000370 => x"00c59a63",
00000371 => x"000684a3",
00000372 => x"fff68693",
00000373 => x"fe0710e3",
00000374 => x"00000793",
00000375 => x"00f907b3",
00000376 => x"00000593",
00000377 => x"0007c703",
00000378 => x"00070c63",
00000379 => x"00158693",
00000380 => x"00b405b3",
00000381 => x"00e58023",
00000382 => x"01069593",
00000383 => x"0105d593",
00000384 => x"fff78713",
00000385 => x"02f91863",
00000386 => x"00b40433",
00000387 => x"00040023",
00000388 => x"02c12083",
00000389 => x"02812403",
00000390 => x"02412483",
00000391 => x"02012903",
00000392 => x"01c12983",
00000393 => x"01812a03",
00000394 => x"01412a83",
00000395 => x"03010113",
00000396 => x"00008067",
00000397 => x"00070793",
00000398 => x"fadff06f",
00000399 => x"fa002023",
00000400 => x"fe002683",
00000401 => x"00151513",
00000402 => x"00000713",
00000403 => x"04a6f263",
00000404 => x"000016b7",
00000405 => x"00000793",
00000406 => x"ffe68693",
00000407 => x"04e6e463",
00000408 => x"00167613",
00000409 => x"0015f593",
00000410 => x"01879793",
00000411 => x"01e61613",
00000412 => x"00c7e7b3",
00000413 => x"01d59593",
00000414 => x"00b7e7b3",
00000415 => x"00e7e7b3",
00000416 => x"10000737",
00000417 => x"00e7e7b3",
00000418 => x"faf02023",
00000419 => x"00008067",
00000420 => x"00170793",
00000421 => x"01079713",
00000422 => x"40a686b3",
00000423 => x"01075713",
00000424 => x"fadff06f",
00000425 => x"ffe78513",
00000426 => x"0fd57513",
00000427 => x"00051a63",
00000428 => x"00375713",
00000429 => x"00178793",
00000430 => x"0ff7f793",
00000431 => x"fa1ff06f",
00000432 => x"00175713",
00000433 => x"ff1ff06f",
00000434 => x"fa002783",
00000435 => x"fe07cee3",
00000436 => x"faa02223",
00000437 => x"00008067",
00000438 => x"ff010113",
00000439 => x"00812423",
00000440 => x"01212023",
00000441 => x"00112623",
00000442 => x"00912223",
00000443 => x"00050413",
00000444 => x"00a00913",
00000445 => x"00044483",
00000446 => x"00140413",
00000447 => x"00049e63",
00000448 => x"00c12083",
00000449 => x"00812403",
00000450 => x"00412483",
00000451 => x"00012903",
00000452 => x"01010113",
00000453 => x"00008067",
00000454 => x"01249663",
00000455 => x"00d00513",
00000456 => x"fa9ff0ef",
00000457 => x"00048513",
00000458 => x"fa1ff0ef",
00000459 => x"fc9ff06f",
00000460 => x"fa010113",
00000461 => x"02912a23",
00000462 => x"04f12a23",
00000463 => x"000014b7",
00000464 => x"04410793",
00000465 => x"02812c23",
00000466 => x"03212823",
00000467 => x"03412423",
00000468 => x"03512223",
00000469 => x"03612023",
00000470 => x"01712e23",
00000471 => x"02112e23",
00000472 => x"03312623",
00000473 => x"01812c23",
00000474 => x"00050413",
00000475 => x"04b12223",
00000476 => x"04c12423",
00000477 => x"04d12623",
00000478 => x"04e12823",
00000479 => x"05012c23",
00000480 => x"05112e23",
00000481 => x"00f12023",
00000482 => x"02500a13",
00000483 => x"00a00a93",
00000484 => x"07300913",
00000485 => x"07500b13",
00000486 => x"07800b93",
00000487 => x"cfc48493",
00000488 => x"00044c03",
00000489 => x"020c0463",
00000490 => x"134c1263",
00000491 => x"00144783",
00000492 => x"00240993",
00000493 => x"09278c63",
00000494 => x"04f96263",
00000495 => x"06300713",
00000496 => x"0ae78463",
00000497 => x"06900713",
00000498 => x"0ae78c63",
00000499 => x"03c12083",
00000500 => x"03812403",
00000501 => x"03412483",
00000502 => x"03012903",
00000503 => x"02c12983",
00000504 => x"02812a03",
00000505 => x"02412a83",
00000506 => x"02012b03",
00000507 => x"01c12b83",
00000508 => x"01812c03",
00000509 => x"06010113",
00000510 => x"00008067",
00000511 => x"0b678c63",
00000512 => x"fd7796e3",
00000513 => x"00012783",
00000514 => x"00410693",
00000515 => x"00068513",
00000516 => x"0007a583",
00000517 => x"00478713",
00000518 => x"00e12023",
00000519 => x"02000613",
00000520 => x"00000713",
00000521 => x"00e5d7b3",
00000522 => x"00f7f793",
00000523 => x"00f487b3",
00000524 => x"0007c783",
00000525 => x"00470713",
00000526 => x"fff68693",
00000527 => x"00f68423",
00000528 => x"fec712e3",
00000529 => x"00010623",
00000530 => x"0140006f",
00000531 => x"00012783",
00000532 => x"0007a503",
00000533 => x"00478713",
00000534 => x"00e12023",
00000535 => x"e7dff0ef",
00000536 => x"00098413",
00000537 => x"f3dff06f",
00000538 => x"00012783",
00000539 => x"0007c503",
00000540 => x"00478713",
00000541 => x"00e12023",
00000542 => x"e51ff0ef",
00000543 => x"fe5ff06f",
00000544 => x"00012783",
00000545 => x"0007a403",
00000546 => x"00478713",
00000547 => x"00e12023",
00000548 => x"00045863",
00000549 => x"02d00513",
00000550 => x"40800433",
00000551 => x"e2dff0ef",
00000552 => x"00410593",
00000553 => x"00040513",
00000554 => x"c8dff0ef",
00000555 => x"00410513",
00000556 => x"fadff06f",
00000557 => x"00012783",
00000558 => x"00410593",
00000559 => x"00478713",
00000560 => x"0007a503",
00000561 => x"00e12023",
00000562 => x"fe1ff06f",
00000563 => x"015c1663",
00000564 => x"00d00513",
00000565 => x"df5ff0ef",
00000566 => x"00140993",
00000567 => x"000c0513",
00000568 => x"f99ff06f",
00000569 => x"00050593",
00000570 => x"fe002503",
00000571 => x"ff010113",
00000572 => x"00112623",
00000573 => x"00f55513",
00000574 => x"044000ef",
00000575 => x"00051863",
00000576 => x"00c12083",
00000577 => x"01010113",
00000578 => x"00008067",
00000579 => x"00000013",
00000580 => x"00000013",
00000581 => x"00000013",
00000582 => x"00000013",
00000583 => x"fff50513",
00000584 => x"fddff06f",
00000585 => x"fe802503",
00000586 => x"01055513",
00000587 => x"00157513",
00000588 => x"00008067",
00000589 => x"f8a02223",
00000590 => x"00008067",
00000591 => x"00050613",
00000592 => x"00000513",
00000593 => x"0015f693",
00000594 => x"00068463",
00000595 => x"00c50533",
00000596 => x"0015d593",
00000597 => x"00161613",
00000598 => x"fe0596e3",
00000599 => x"00008067",
00000600 => x"06054063",
00000601 => x"0605c663",
00000602 => x"00058613",
00000603 => x"00050593",
00000604 => x"fff00513",
00000605 => x"02060c63",
00000606 => x"00100693",
00000607 => x"00b67a63",
00000608 => x"00c05863",
00000609 => x"00161613",
00000610 => x"00169693",
00000611 => x"feb66ae3",
00000612 => x"00000513",
00000613 => x"00c5e663",
00000614 => x"40c585b3",
00000615 => x"00d56533",
00000616 => x"0016d693",
00000617 => x"00165613",
00000618 => x"fe0696e3",
00000619 => x"00008067",
00000620 => x"00008293",
00000621 => x"fb5ff0ef",
00000622 => x"00058513",
00000623 => x"00028067",
00000624 => x"40a00533",
00000625 => x"00b04863",
00000626 => x"40b005b3",
00000627 => x"f9dff06f",
00000628 => x"40b005b3",
00000629 => x"00008293",
00000630 => x"f91ff0ef",
00000631 => x"40a00533",
00000632 => x"00028067",
00000633 => x"00008293",
00000634 => x"0005ca63",
00000635 => x"00054c63",
00000636 => x"f79ff0ef",
00000637 => x"00058513",
00000638 => x"00028067",
00000639 => x"40b005b3",
00000640 => x"fe0558e3",
00000641 => x"40a00533",
00000642 => x"f61ff0ef",
00000643 => x"40b00533",
00000644 => x"00028067",
00000645 => x"6f727245",
00000646 => x"4e202172",
00000647 => x"5047206f",
00000648 => x"75204f49",
00000649 => x"2074696e",
00000650 => x"746e7973",
00000651 => x"69736568",
00000652 => x"2164657a",
00000653 => x"0000000a",
00000654 => x"6e696c42",
00000655 => x"676e696b",
00000656 => x"44454c20",
00000657 => x"6d656420",
00000658 => x"7270206f",
00000659 => x"6172676f",
00000660 => x"00000a6d",
00000661 => x"000002a8",
00000662 => x"000002b4",
00000663 => x"000002c0",
00000664 => x"000002cc",
00000665 => x"000002d8",
00000666 => x"000002e0",
00000667 => x"000002e8",
00000668 => x"000002f0",
00000669 => x"00000214",
00000670 => x"00000214",
00000671 => x"00000214",
00000672 => x"000002f8",
00000673 => x"00000300",
00000355 => x"438000ef",
00000356 => x"00aa0533",
00000357 => x"00054783",
00000358 => x"01390ab3",
00000359 => x"00048513",
00000360 => x"00fa8023",
00000361 => x"00a00593",
00000362 => x"3d4000ef",
00000363 => x"00198993",
00000364 => x"00a00793",
00000365 => x"00050493",
00000366 => x"fcf996e3",
00000367 => x"00090693",
00000368 => x"00900713",
00000369 => x"03000613",
00000370 => x"0096c583",
00000371 => x"00070793",
00000372 => x"fff70713",
00000373 => x"01071713",
00000374 => x"01075713",
00000375 => x"00c59a63",
00000376 => x"000684a3",
00000377 => x"fff68693",
00000378 => x"fe0710e3",
00000379 => x"00000793",
00000380 => x"00f907b3",
00000381 => x"00000593",
00000382 => x"0007c703",
00000383 => x"00070c63",
00000384 => x"00158693",
00000385 => x"00b405b3",
00000386 => x"00e58023",
00000387 => x"01069593",
00000388 => x"0105d593",
00000389 => x"fff78713",
00000390 => x"02f91863",
00000391 => x"00b40433",
00000392 => x"00040023",
00000393 => x"02c12083",
00000394 => x"02812403",
00000395 => x"02412483",
00000396 => x"02012903",
00000397 => x"01c12983",
00000398 => x"01812a03",
00000399 => x"01412a83",
00000400 => x"03010113",
00000401 => x"00008067",
00000402 => x"00070793",
00000403 => x"fadff06f",
00000404 => x"fa002023",
00000405 => x"fe002683",
00000406 => x"00151513",
00000407 => x"00000713",
00000408 => x"04a6f263",
00000409 => x"000016b7",
00000410 => x"00000793",
00000411 => x"ffe68693",
00000412 => x"04e6e463",
00000413 => x"00167613",
00000414 => x"0015f593",
00000415 => x"01879793",
00000416 => x"01e61613",
00000417 => x"00c7e7b3",
00000418 => x"01d59593",
00000419 => x"00b7e7b3",
00000420 => x"00e7e7b3",
00000421 => x"10000737",
00000422 => x"00e7e7b3",
00000423 => x"faf02023",
00000424 => x"00008067",
00000425 => x"00170793",
00000426 => x"01079713",
00000427 => x"40a686b3",
00000428 => x"01075713",
00000429 => x"fadff06f",
00000430 => x"ffe78513",
00000431 => x"0fd57513",
00000432 => x"00051a63",
00000433 => x"00375713",
00000434 => x"00178793",
00000435 => x"0ff7f793",
00000436 => x"fa1ff06f",
00000437 => x"00175713",
00000438 => x"ff1ff06f",
00000439 => x"fa002783",
00000440 => x"fe07cee3",
00000441 => x"faa02223",
00000442 => x"00008067",
00000443 => x"ff010113",
00000444 => x"00812423",
00000445 => x"01212023",
00000446 => x"00112623",
00000447 => x"00912223",
00000448 => x"00050413",
00000449 => x"00a00913",
00000450 => x"00044483",
00000451 => x"00140413",
00000452 => x"00049e63",
00000453 => x"00c12083",
00000454 => x"00812403",
00000455 => x"00412483",
00000456 => x"00012903",
00000457 => x"01010113",
00000458 => x"00008067",
00000459 => x"01249663",
00000460 => x"00d00513",
00000461 => x"fa9ff0ef",
00000462 => x"00048513",
00000463 => x"fa1ff0ef",
00000464 => x"fc9ff06f",
00000465 => x"fa010113",
00000466 => x"02912a23",
00000467 => x"04f12a23",
00000468 => x"000014b7",
00000469 => x"04410793",
00000470 => x"02812c23",
00000471 => x"03212823",
00000472 => x"03412423",
00000473 => x"03512223",
00000474 => x"03612023",
00000475 => x"01712e23",
00000476 => x"02112e23",
00000477 => x"03312623",
00000478 => x"01812c23",
00000479 => x"00050413",
00000480 => x"04b12223",
00000481 => x"04c12423",
00000482 => x"04d12623",
00000483 => x"04e12823",
00000484 => x"05012c23",
00000485 => x"05112e23",
00000486 => x"00f12023",
00000487 => x"02500a13",
00000488 => x"00a00a93",
00000489 => x"07300913",
00000490 => x"07500b13",
00000491 => x"07800b93",
00000492 => x"d3048493",
00000493 => x"00044c03",
00000494 => x"020c0463",
00000495 => x"134c1263",
00000496 => x"00144783",
00000497 => x"00240993",
00000498 => x"09278c63",
00000499 => x"04f96263",
00000500 => x"06300713",
00000501 => x"0ae78463",
00000502 => x"06900713",
00000503 => x"0ae78c63",
00000504 => x"03c12083",
00000505 => x"03812403",
00000506 => x"03412483",
00000507 => x"03012903",
00000508 => x"02c12983",
00000509 => x"02812a03",
00000510 => x"02412a83",
00000511 => x"02012b03",
00000512 => x"01c12b83",
00000513 => x"01812c03",
00000514 => x"06010113",
00000515 => x"00008067",
00000516 => x"0b678c63",
00000517 => x"fd7796e3",
00000518 => x"00012783",
00000519 => x"00410693",
00000520 => x"00068513",
00000521 => x"0007a583",
00000522 => x"00478713",
00000523 => x"00e12023",
00000524 => x"02000613",
00000525 => x"00000713",
00000526 => x"00e5d7b3",
00000527 => x"00f7f793",
00000528 => x"00f487b3",
00000529 => x"0007c783",
00000530 => x"00470713",
00000531 => x"fff68693",
00000532 => x"00f68423",
00000533 => x"fec712e3",
00000534 => x"00010623",
00000535 => x"0140006f",
00000536 => x"00012783",
00000537 => x"0007a503",
00000538 => x"00478713",
00000539 => x"00e12023",
00000540 => x"e7dff0ef",
00000541 => x"00098413",
00000542 => x"f3dff06f",
00000543 => x"00012783",
00000544 => x"0007c503",
00000545 => x"00478713",
00000546 => x"00e12023",
00000547 => x"e51ff0ef",
00000548 => x"fe5ff06f",
00000549 => x"00012783",
00000550 => x"0007a403",
00000551 => x"00478713",
00000552 => x"00e12023",
00000553 => x"00045863",
00000554 => x"02d00513",
00000555 => x"40800433",
00000556 => x"e2dff0ef",
00000557 => x"00410593",
00000558 => x"00040513",
00000559 => x"c8dff0ef",
00000560 => x"00410513",
00000561 => x"fadff06f",
00000562 => x"00012783",
00000563 => x"00410593",
00000564 => x"00478713",
00000565 => x"0007a503",
00000566 => x"00e12023",
00000567 => x"fe1ff06f",
00000568 => x"015c1663",
00000569 => x"00d00513",
00000570 => x"df5ff0ef",
00000571 => x"00140993",
00000572 => x"000c0513",
00000573 => x"f99ff06f",
00000574 => x"00050593",
00000575 => x"fe002503",
00000576 => x"ff010113",
00000577 => x"00112623",
00000578 => x"00f55513",
00000579 => x"044000ef",
00000580 => x"00051863",
00000581 => x"00c12083",
00000582 => x"01010113",
00000583 => x"00008067",
00000584 => x"00000013",
00000585 => x"00000013",
00000586 => x"00000013",
00000587 => x"00000013",
00000588 => x"fff50513",
00000589 => x"fddff06f",
00000590 => x"fe802503",
00000591 => x"01055513",
00000592 => x"00157513",
00000593 => x"00008067",
00000594 => x"f8a02223",
00000595 => x"00008067",
00000596 => x"00050613",
00000597 => x"00000513",
00000598 => x"0015f693",
00000599 => x"00068463",
00000600 => x"00c50533",
00000601 => x"0015d593",
00000602 => x"00161613",
00000603 => x"fe0596e3",
00000604 => x"00008067",
00000605 => x"06054063",
00000606 => x"0605c663",
00000607 => x"00058613",
00000608 => x"00050593",
00000609 => x"fff00513",
00000610 => x"02060c63",
00000611 => x"00100693",
00000612 => x"00b67a63",
00000613 => x"00c05863",
00000614 => x"00161613",
00000615 => x"00169693",
00000616 => x"feb66ae3",
00000617 => x"00000513",
00000618 => x"00c5e663",
00000619 => x"40c585b3",
00000620 => x"00d56533",
00000621 => x"0016d693",
00000622 => x"00165613",
00000623 => x"fe0696e3",
00000624 => x"00008067",
00000625 => x"00008293",
00000626 => x"fb5ff0ef",
00000627 => x"00058513",
00000628 => x"00028067",
00000629 => x"40a00533",
00000630 => x"00b04863",
00000631 => x"40b005b3",
00000632 => x"f9dff06f",
00000633 => x"40b005b3",
00000634 => x"00008293",
00000635 => x"f91ff0ef",
00000636 => x"40a00533",
00000637 => x"00028067",
00000638 => x"00008293",
00000639 => x"0005ca63",
00000640 => x"00054c63",
00000641 => x"f79ff0ef",
00000642 => x"00058513",
00000643 => x"00028067",
00000644 => x"40b005b3",
00000645 => x"fe0558e3",
00000646 => x"40a00533",
00000647 => x"f61ff0ef",
00000648 => x"40b00533",
00000649 => x"00028067",
00000650 => x"6f727245",
00000651 => x"4e202172",
00000652 => x"5047206f",
00000653 => x"75204f49",
00000654 => x"2074696e",
00000655 => x"746e7973",
00000656 => x"69736568",
00000657 => x"2164657a",
00000658 => x"0000000a",
00000659 => x"6e696c42",
00000660 => x"676e696b",
00000661 => x"44454c20",
00000662 => x"6d656420",
00000663 => x"7270206f",
00000664 => x"6172676f",
00000665 => x"00000a6d",
00000666 => x"000002a8",
00000667 => x"000002b4",
00000668 => x"000002c0",
00000669 => x"000002cc",
00000670 => x"000002d8",
00000671 => x"000002e0",
00000672 => x"000002e8",
00000673 => x"000002f0",
00000674 => x"00000214",
00000675 => x"00000214",
00000676 => x"00000214",
00000677 => x"00000308",
00000678 => x"00000214",
00000677 => x"000002f8",
00000678 => x"00000300",
00000679 => x"00000214",
00000680 => x"00000214",
00000681 => x"00000310",
00000682 => x"00000214",
00000681 => x"00000214",
00000682 => x"00000308",
00000683 => x"00000214",
00000684 => x"00000214",
00000685 => x"00000214",
00000686 => x"00000318",
00000687 => x"00000320",
00000688 => x"00000328",
00000689 => x"00000330",
00000690 => x"4554523c",
00000691 => x"0000203e",
00000692 => x"74736e49",
00000693 => x"74637572",
00000694 => x"206e6f69",
00000695 => x"72646461",
00000696 => x"20737365",
00000697 => x"6173696d",
00000698 => x"6e67696c",
00000699 => x"00006465",
00000700 => x"74736e49",
00000701 => x"74637572",
00000702 => x"206e6f69",
00000703 => x"65636361",
00000704 => x"66207373",
00000705 => x"746c7561",
00000706 => x"00000000",
00000707 => x"656c6c49",
00000708 => x"206c6167",
00000709 => x"74736e69",
00000710 => x"74637572",
00000711 => x"006e6f69",
00000712 => x"61657242",
00000713 => x"696f706b",
00000714 => x"0000746e",
00000715 => x"64616f4c",
00000716 => x"64646120",
00000717 => x"73736572",
00000718 => x"73696d20",
00000719 => x"67696c61",
00000720 => x"0064656e",
00000721 => x"64616f4c",
00000722 => x"63636120",
00000723 => x"20737365",
00000724 => x"6c756166",
00000725 => x"00000074",
00000726 => x"726f7453",
00000727 => x"64612065",
00000728 => x"73657264",
00000729 => x"696d2073",
00000730 => x"696c6173",
00000731 => x"64656e67",
00000732 => x"00000000",
00000733 => x"726f7453",
00000734 => x"63612065",
00000735 => x"73736563",
00000736 => x"75616620",
00000737 => x"0000746c",
00000738 => x"69766e45",
00000739 => x"6d6e6f72",
00000740 => x"20746e65",
00000741 => x"6c6c6163",
00000742 => x"00000000",
00000743 => x"6863614d",
00000744 => x"20656e69",
00000745 => x"74666f73",
00000746 => x"65726177",
00000747 => x"746e6920",
00000748 => x"75727265",
00000749 => x"00007470",
00000750 => x"6863614d",
00000751 => x"20656e69",
00000752 => x"656d6974",
00000753 => x"6e692072",
00000754 => x"72726574",
00000755 => x"00747075",
00000756 => x"6863614d",
00000757 => x"20656e69",
00000758 => x"65747865",
00000759 => x"6c616e72",
00000760 => x"746e6920",
00000761 => x"75727265",
00000762 => x"00007470",
00000763 => x"74736146",
00000764 => x"746e6920",
00000765 => x"75727265",
00000766 => x"30207470",
00000767 => x"44572820",
00000768 => x"00002954",
00000769 => x"74736146",
00000770 => x"746e6920",
00000771 => x"75727265",
00000772 => x"31207470",
00000773 => x"50472820",
00000774 => x"00294f49",
00000775 => x"74736146",
00000776 => x"746e6920",
00000777 => x"75727265",
00000778 => x"32207470",
00000779 => x"41552820",
00000780 => x"00295452",
00000781 => x"74736146",
00000782 => x"746e6920",
00000783 => x"75727265",
00000784 => x"33207470",
00000785 => x"50532820",
00000786 => x"57542f49",
00000787 => x"00002949",
00000686 => x"00000310",
00000687 => x"00000214",
00000688 => x"00000214",
00000689 => x"00000214",
00000690 => x"00000214",
00000691 => x"00000318",
00000692 => x"00000320",
00000693 => x"00000328",
00000694 => x"00000330",
00000695 => x"4554523c",
00000696 => x"0000203e",
00000697 => x"74736e49",
00000698 => x"74637572",
00000699 => x"206e6f69",
00000700 => x"72646461",
00000701 => x"20737365",
00000702 => x"6173696d",
00000703 => x"6e67696c",
00000704 => x"00006465",
00000705 => x"74736e49",
00000706 => x"74637572",
00000707 => x"206e6f69",
00000708 => x"65636361",
00000709 => x"66207373",
00000710 => x"746c7561",
00000711 => x"00000000",
00000712 => x"656c6c49",
00000713 => x"206c6167",
00000714 => x"74736e69",
00000715 => x"74637572",
00000716 => x"006e6f69",
00000717 => x"61657242",
00000718 => x"696f706b",
00000719 => x"0000746e",
00000720 => x"64616f4c",
00000721 => x"64646120",
00000722 => x"73736572",
00000723 => x"73696d20",
00000724 => x"67696c61",
00000725 => x"0064656e",
00000726 => x"64616f4c",
00000727 => x"63636120",
00000728 => x"20737365",
00000729 => x"6c756166",
00000730 => x"00000074",
00000731 => x"726f7453",
00000732 => x"64612065",
00000733 => x"73657264",
00000734 => x"696d2073",
00000735 => x"696c6173",
00000736 => x"64656e67",
00000737 => x"00000000",
00000738 => x"726f7453",
00000739 => x"63612065",
00000740 => x"73736563",
00000741 => x"75616620",
00000742 => x"0000746c",
00000743 => x"69766e45",
00000744 => x"6d6e6f72",
00000745 => x"20746e65",
00000746 => x"6c6c6163",
00000747 => x"00000000",
00000748 => x"6863614d",
00000749 => x"20656e69",
00000750 => x"74666f73",
00000751 => x"65726177",
00000752 => x"746e6920",
00000753 => x"75727265",
00000754 => x"00007470",
00000755 => x"6863614d",
00000756 => x"20656e69",
00000757 => x"656d6974",
00000758 => x"6e692072",
00000759 => x"72726574",
00000760 => x"00747075",
00000761 => x"6863614d",
00000762 => x"20656e69",
00000763 => x"65747865",
00000764 => x"6c616e72",
00000765 => x"746e6920",
00000766 => x"75727265",
00000767 => x"00007470",
00000768 => x"74736146",
00000769 => x"746e6920",
00000770 => x"75727265",
00000771 => x"30207470",
00000772 => x"00000000",
00000773 => x"74736146",
00000774 => x"746e6920",
00000775 => x"75727265",
00000776 => x"31207470",
00000777 => x"00000000",
00000778 => x"74736146",
00000779 => x"746e6920",
00000780 => x"75727265",
00000781 => x"32207470",
00000782 => x"00000000",
00000783 => x"74736146",
00000784 => x"746e6920",
00000785 => x"75727265",
00000786 => x"33207470",
00000787 => x"00000000",
00000788 => x"6e6b6e55",
00000789 => x"206e776f",
00000790 => x"25783028",
836,14 → 836,27
00000825 => x"00000378",
00000826 => x"00000378",
00000827 => x"00000454",
00000828 => x"33323130",
00000829 => x"37363534",
00000830 => x"00003938",
00000831 => x"33323130",
00000832 => x"37363534",
00000833 => x"62613938",
00000834 => x"66656463",
00000835 => x"00000000",
00000828 => x"4554523c",
00000829 => x"4157203e",
00000830 => x"4e494e52",
00000831 => x"43202147",
00000832 => x"43205550",
00000833 => x"73205253",
00000834 => x"65747379",
00000835 => x"6f6e206d",
00000836 => x"76612074",
00000837 => x"616c6961",
00000838 => x"21656c62",
00000839 => x"522f3c20",
00000840 => x"003e4554",
00000841 => x"33323130",
00000842 => x"37363534",
00000843 => x"00003938",
00000844 => x"33323130",
00000845 => x"37363534",
00000846 => x"62613938",
00000847 => x"66656463",
00000848 => x"00000000",
others => x"00000000"
);
 
/neorv32_cpu.vhd
135,6 → 135,7
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
 
-- co-processor interface --
signal cp_opa, cp_opb : std_ulogic_vector(data_width_c-1 downto 0);
signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
signal cp0_valid, cp1_valid : std_ulogic;
signal cp0_start, cp1_start : std_ulogic;
268,6 → 269,8
add_o => alu_add, -- OPA + OPB
res_o => alu_res, -- ALU result
-- co-processor interface --
cp_opa_o => cp_opa, -- co-processor operand a
cp_opb_o => cp_opb, -- co-processor operand b
cp0_start_o => cp0_start, -- trigger co-processor 0
cp0_data_i => cp0_data, -- co-processor 0 result
cp0_valid_i => cp0_valid, -- co-processor 0 result valid
294,8 → 297,8
ctrl_i => ctrl, -- main control bus
-- data input --
start_i => cp0_start, -- trigger operation
rs1_i => rs1, -- rf source 1
rs2_i => rs2, -- rf source 2
rs1_i => cp_opa, -- rf source 1
rs2_i => cp_opb, -- rf source 2
-- result and status --
res_o => cp0_data, -- operation result
valid_o => cp0_valid -- data output valid
/neorv32_cpu_alu.vhd
62,6 → 62,8
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
-- co-processor interface --
cp_opa_o : out std_ulogic_vector(data_width_c-1 downto 0); -- co-processor operand a
cp_opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- co-processor operand b
cp0_start_o : out std_ulogic; -- trigger co-processor 0
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
81,6 → 83,7
-- results --
signal add_res : std_ulogic_vector(data_width_c-1 downto 0);
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
 
-- comparator --
signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
108,14 → 111,9
busy : std_ulogic;
start : std_ulogic;
halt : std_ulogic;
rb_ff0 : std_ulogic;
rb_ff1 : std_ulogic;
end record;
signal cp_ctrl : cp_ctrl_t;
 
-- bit manipulation --
signal bitm_res : std_ulogic_vector(31 downto 0);
 
begin
 
-- Operand Mux ----------------------------------------------------------------------------
166,19 → 164,6
add_o <= add_res; -- direct output
 
 
-- Bit Manipulation Unit ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
 
-- ------------------ --
-- UNDER CONSTRUCTION --
-- ------------------ --
 
--bitm_minmax <= rs1_i when ((cmp_less xor ???) = '1') else rs2_i; -- min[u] / max[u]
 
-- result of bit manipulation operation --
bitm_res <= opa and (not opb); -- ANDN
 
 
-- Iterative Shifter Unit -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shifter_unit: process(rstn_i, clk_i)
233,24 → 218,17
if (rstn_i = '0') then
cp_ctrl.cmd_ff <= '0';
cp_ctrl.busy <= '0';
cp_ctrl.rb_ff0 <= '0';
cp_ctrl.rb_ff1 <= '0';
elsif rising_edge(clk_i) then
if (CPU_EXTENSION_RISCV_M = true) then
cp_ctrl.cmd_ff <= ctrl_i(ctrl_cp_use_c);
cp_ctrl.rb_ff0 <= '0';
cp_ctrl.rb_ff1 <= cp_ctrl.rb_ff0;
if (cp_ctrl.start = '1') then
cp_ctrl.busy <= '1';
elsif ((cp0_valid_i or cp1_valid_i) = '1') then -- cp computation done?
cp_ctrl.busy <= '0';
cp_ctrl.rb_ff0 <= '1';
cp_ctrl.busy <= '0';
end if;
else -- no co-processor(s) implemented
cp_ctrl.cmd_ff <= '0';
cp_ctrl.busy <= '0';
cp_ctrl.rb_ff0 <= '0';
cp_ctrl.rb_ff1 <= '0';
end if;
end if;
end process cp_arbiter;
263,16 → 241,23
-- co-processor operation running? --
cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
 
-- co-processor operands --
cp_opa_o <= opa;
cp_opb_o <= opb;
 
-- co-processor result --
cp_res <= cp0_data_i or cp1_data_i; -- only the selcted cp may output data != 0
 
 
-- ALU Function Select --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter, bitm_res)
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter)
begin
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
when alu_cmd_bitm_c => alu_res <= bitm_res;
when alu_cmd_xor_c => alu_res <= opa xor opb;
when alu_cmd_or_c => alu_res <= opa or opb;
when alu_cmd_and_c => alu_res <= opa and opb;
when alu_cmd_bclr_c => alu_res <= opa and (not opb);
when alu_cmd_sub_c => alu_res <= sub_res;
when alu_cmd_add_c => alu_res <= add_res;
when alu_cmd_shift_c => alu_res <= shifter.sreg;
285,7 → 270,7
-- ALU Result -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
wait_o <= shifter.halt or cp_ctrl.halt; -- wait until iterative units have completed
res_o <= (cp0_data_i or cp1_data_i) when (cp_ctrl.rb_ff1 = '1') else alu_res; -- FIXME
res_o <= cp_res when (ctrl_i(ctrl_cp_use_c) = '1') else alu_res; -- FIXME?
 
 
end neorv32_cpu_cpu_rtl;
/neorv32_cpu_control.vhd
729,7 → 729,7
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_auipc_c(5)) then -- AUIPC
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
else -- LUI
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA ( = 0)
end if;
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation
784,7 → 784,7
 
when opcode_syscsr_c => -- system/csr access
-- ------------------------------------------------------------
csr.re_nxt <= csr_acc_valid; -- read CSR if valid access
csr.re_nxt <= csr_acc_valid; -- always read CSR if valid access
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
when funct12_ecall_c => -- ECALL
818,14 → 818,13
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- default
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '0'; -- default
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- default
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- default ALU operation = OR
-- ctrl_nxt(ctrl_alu_bmop2_c downto ctrl_alu_bmop0_c) <= alu_bm_andn_c; -- bit manipulation operation = ANDN
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- default ALU operation = OR
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
-- register operations --
when funct3_csrrw_c => -- CSRRW
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- OPB = rs2
ctrl_nxt(ctrl_rf_clear_rs2_c) <= '1'; -- rs2 = 0
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = rs1
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
csr.we_nxt <= csr_acc_valid; -- always write CSR if valid access
when funct3_csrrs_c => -- CSRRS
836,7 → 835,7
when funct3_csrrc_c => -- CSRRC
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bitm_c; -- actual ALU operation = bit manipulation (ANDN)
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bclr_c; -- actual ALU operation = bit clear
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1 is not zero_reg and if valid access
-- immediate operations --
when funct3_csrrwi_c => -- CSRRWI
853,7 → 852,7
when funct3_csrrci_c => -- CSRRCI
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bitm_c; -- actual ALU operation = bit manipulation (ANDN)
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bclr_c; -- actual ALU operation = bit clear
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if UIMM5 is not zero (bits from rs1 filed) and if valid access
when others => -- undefined
NULL;
/neorv32_cpu_regfile.vhd
154,10 → 154,10
end process rf_access;
 
 
-- Check if reading from r0 ---------------------------------------------------------------
-- Check if reading from x0 ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
rs1_o <= (others => '0') when ((rs1_clear or ctrl_i(ctrl_rf_clear_rs1_c)) = '1') else rs1_read;
rs2_o <= (others => '0') when ((rs2_clear or ctrl_i(ctrl_rf_clear_rs2_c)) = '1') else rs2_read;
rs2_o <= (others => '0') when (rs2_clear = '1') else rs2_read;
 
 
end neorv32_cpu_regfile_rtl;
/neorv32_package.vhd
178,42 → 178,41
constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
constant ctrl_rf_clear_rs1_c : natural := 18; -- force rs1=r0
constant ctrl_rf_clear_rs2_c : natural := 19; -- force rs2=r0
-- alu --
constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (1-=CSR)
constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM)
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (1-=rs1)
constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
constant ctrl_alu_shift_ar_c : natural := 30; -- is arithmetic shift
constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0
constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1
constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2
constant ctrl_alu_opa_mux_lsb_c : natural := 22; -- operand A select lsb (00=rs1, 01=PC)
constant ctrl_alu_opa_mux_msb_c : natural := 23; -- operand A select msb (1-=CSR)
constant ctrl_alu_opb_mux_lsb_c : natural := 24; -- operand B select lsb (00=rs2, 01=IMM)
constant ctrl_alu_opb_mux_msb_c : natural := 25; -- operand B select msb (1-=rs1)
constant ctrl_alu_opc_mux_c : natural := 26; -- operand C select (0=IMM, 1=rs2)
constant ctrl_alu_unsigned_c : natural := 27; -- is unsigned ALU operation
constant ctrl_alu_shift_dir_c : natural := 28; -- shift direction (0=left, 1=right)
constant ctrl_alu_shift_ar_c : natural := 29; -- is arithmetic shift
-- bus interface --
constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
constant ctrl_bus_rd_c : natural := 33; -- read data request
constant ctrl_bus_wr_c : natural := 34; -- write data request
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
constant ctrl_bus_ierr_ack_c : natural := 40; -- acknowledge instruction fetch bus exception
constant ctrl_bus_derr_ack_c : natural := 41; -- acknowledge data access bus exception
constant ctrl_bus_fence_c : natural := 42; -- executed fence operation
constant ctrl_bus_fencei_c : natural := 43; -- executed fencei operation
constant ctrl_bus_size_lsb_c : natural := 30; -- transfer size lsb (00=byte, 01=half-word)
constant ctrl_bus_size_msb_c : natural := 31; -- transfer size msb (10=word, 11=?)
constant ctrl_bus_rd_c : natural := 32; -- read data request
constant ctrl_bus_wr_c : natural := 33; -- write data request
constant ctrl_bus_if_c : natural := 34; -- instruction fetch request
constant ctrl_bus_mar_we_c : natural := 35; -- memory address register write enable
constant ctrl_bus_mdo_we_c : natural := 36; -- memory data out register write enable
constant ctrl_bus_mdi_we_c : natural := 37; -- memory data in register write enable
constant ctrl_bus_unsigned_c : natural := 38; -- is unsigned load
constant ctrl_bus_ierr_ack_c : natural := 39; -- acknowledge instruction fetch bus exception
constant ctrl_bus_derr_ack_c : natural := 40; -- acknowledge data access bus exception
constant ctrl_bus_fence_c : natural := 41; -- executed fence operation
constant ctrl_bus_fencei_c : natural := 42; -- executed fencei operation
-- co-processor --
constant ctrl_cp_use_c : natural := 44; -- is cp operation
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select lsb
constant ctrl_cp_id_msb_c : natural := 46; -- cp select msb
constant ctrl_cp_cmd0_c : natural := 47; -- cp command bit 0
constant ctrl_cp_cmd1_c : natural := 48; -- cp command bit 1
constant ctrl_cp_cmd2_c : natural := 49; -- cp command bit 2
constant ctrl_cp_use_c : natural := 43; -- is cp operation
constant ctrl_cp_id_lsb_c : natural := 44; -- cp select lsb
constant ctrl_cp_id_msb_c : natural := 45; -- cp select msb
constant ctrl_cp_cmd0_c : natural := 46; -- cp command bit 0
constant ctrl_cp_cmd1_c : natural := 47; -- cp command bit 1
constant ctrl_cp_cmd2_c : natural := 48; -- cp command bit 2
-- control bus size --
constant ctrl_width_c : natural := 50; -- control bus size
constant ctrl_width_c : natural := 49; -- control bus size
 
-- ALU Comparator Bus ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
332,7 → 331,7
constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= A xor B
constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A or B
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
constant alu_cmd_bitm_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= bit manipulation
constant alu_cmd_bclr_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
 
-- Trap ID Codes --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
646,6 → 645,8
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
-- co-processor interface --
cp_opa_o : out std_ulogic_vector(data_width_c-1 downto 0); -- co-processor operand a
cp_opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- co-processor operand b
cp0_start_o : out std_ulogic; -- trigger co-processor 0
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
cp0_valid_i : in std_ulogic; -- co-processor 0 result valid

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