URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/rtl/core
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/neorv32_bootloader_image.vhd
83,7 → 83,7
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95,537 → 95,537
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00000223 => x"00500793", |
00000224 => x"0287e063", |
00000225 => x"03040513", |
00000226 => x"0ff57513", |
00000227 => x"0b1000ef", |
00000228 => x"221000ef", |
00000229 => x"00100513", |
00000230 => x"1f5000ef", |
00000231 => x"0000006f", |
00000232 => x"ffff1537", |
00000233 => x"e7850513", |
00000234 => x"0b5000ef", |
00000235 => x"fe5ff06f", |
00000236 => x"fe010113", |
00000237 => x"01212823", |
00000238 => x"00050913", |
00000239 => x"ffff1537", |
00000240 => x"00912a23", |
00000241 => x"e8050513", |
00000242 => x"ffff14b7", |
00000243 => x"00812c23", |
00000244 => x"01312623", |
00000245 => x"00112e23", |
00000246 => x"01c00413", |
00000247 => x"081000ef", |
00000248 => x"fe448493", |
00000249 => x"ffc00993", |
00000250 => x"008957b3", |
00000251 => x"00f7f793", |
00000252 => x"00f487b3", |
00000253 => x"0007c503", |
00000254 => x"ffc40413", |
00000255 => x"041000ef", |
00000256 => x"ff3414e3", |
00000257 => x"01c12083", |
00000258 => x"01812403", |
00000259 => x"01412483", |
00000260 => x"01012903", |
00000261 => x"00c12983", |
00000262 => x"02010113", |
00000263 => x"00008067", |
00000264 => x"fb010113", |
00000265 => x"04112623", |
00000266 => x"04512423", |
00000267 => x"04612223", |
00000268 => x"04712023", |
00000269 => x"02812e23", |
00000270 => x"02a12c23", |
00000271 => x"02b12a23", |
00000272 => x"02c12823", |
00000273 => x"02d12623", |
00000274 => x"02e12423", |
00000275 => x"02f12223", |
00000276 => x"03012023", |
00000277 => x"01112e23", |
00000278 => x"01c12c23", |
00000279 => x"01d12a23", |
00000280 => x"01e12823", |
00000281 => x"01f12623", |
00000282 => x"34201473", |
00000283 => x"800007b7", |
00000284 => x"00778793", |
00000285 => x"02f40a63", |
00000286 => x"ffff1537", |
00000287 => x"e8450513", |
00000288 => x"7dc000ef", |
00000289 => x"00040513", |
00000290 => x"f29ff0ef", |
00000291 => x"ffff1537", |
00000292 => x"e9450513", |
00000293 => x"7c8000ef", |
00000294 => x"34101573", |
00000295 => x"f15ff0ef", |
00000296 => x"00500513", |
00000297 => x"ebdff0ef", |
00000298 => x"00000513", |
00000299 => x"0c1000ef", |
00000300 => x"6bc000ef", |
00000301 => x"fc1017f3", |
00000302 => x"0027d793", |
00000303 => x"00a78533", |
00000304 => x"00f537b3", |
00000305 => x"00b785b3", |
00000306 => x"6d0000ef", |
00000307 => x"03c12403", |
00000308 => x"04c12083", |
00000309 => x"04812283", |
00000310 => x"04412303", |
00000311 => x"04012383", |
00000312 => x"03812503", |
00000313 => x"03412583", |
00000314 => x"03012603", |
00000315 => x"02c12683", |
00000316 => x"02812703", |
00000317 => x"02412783", |
00000318 => x"02012803", |
00000319 => x"01c12883", |
00000320 => x"01812e03", |
00000321 => x"01412e83", |
00000322 => x"01012f03", |
00000323 => x"00c12f83", |
00000324 => x"05010113", |
00000325 => x"30200073", |
00000326 => x"fe010113", |
00000327 => x"00112e23", |
00000328 => x"00812c23", |
00000329 => x"00912a23", |
00000330 => x"01212823", |
00000331 => x"01312623", |
00000332 => x"01412423", |
00000333 => x"01512223", |
00000334 => x"f1301973", |
00000335 => x"00000a93", |
00000336 => x"00900993", |
00000337 => x"00300a13", |
00000338 => x"00400493", |
00000339 => x"41500433", |
00000340 => x"00341413", |
00000341 => x"01840413", |
00000342 => x"00895433", |
00000343 => x"0ff47413", |
00000344 => x"00000513", |
00000345 => x"0489ec63", |
00000346 => x"00050863", |
00000347 => x"03050513", |
00000348 => x"0ff57513", |
00000349 => x"6c8000ef", |
00000350 => x"03040513", |
00000351 => x"0ff57513", |
00000352 => x"6bc000ef", |
00000353 => x"014a8663", |
00000354 => x"02e00513", |
00000355 => x"6b0000ef", |
00000356 => x"001a8a93", |
00000357 => x"fa9a9ce3", |
00000358 => x"01c12083", |
00000359 => x"01812403", |
00000360 => x"01412483", |
00000361 => x"01012903", |
00000362 => x"00c12983", |
00000363 => x"00812a03", |
00000364 => x"00412a83", |
00000365 => x"02010113", |
00000366 => x"00008067", |
00000367 => x"ff640413", |
00000368 => x"00150513", |
00000369 => x"0ff47413", |
00000370 => x"0ff57513", |
00000371 => x"f99ff06f", |
00000372 => x"ff010113", |
00000373 => x"00000513", |
00000374 => x"00112623", |
00000375 => x"00812423", |
00000376 => x"734000ef", |
00000377 => x"00500513", |
00000378 => x"770000ef", |
00000379 => x"00000513", |
00000380 => x"768000ef", |
00000381 => x"00050413", |
00000382 => x"00000513", |
00000383 => x"738000ef", |
00000384 => x"00c12083", |
00000385 => x"0ff47513", |
00000386 => x"00812403", |
00000387 => x"01010113", |
00000388 => x"00008067", |
00000389 => x"ff010113", |
00000390 => x"00000513", |
00000391 => x"00112623", |
00000392 => x"00812423", |
00000393 => x"6f0000ef", |
00000394 => x"09e00513", |
00000395 => x"72c000ef", |
00000396 => x"00000513", |
00000397 => x"724000ef", |
00000398 => x"00050413", |
00000399 => x"00000513", |
00000400 => x"6f4000ef", |
00000401 => x"00c12083", |
00000402 => x"0ff47513", |
00000403 => x"00812403", |
00000404 => x"01010113", |
00000405 => x"00008067", |
00000406 => x"ff010113", |
00000407 => x"00000513", |
00000408 => x"00112623", |
00000409 => x"6b0000ef", |
00000410 => x"00600513", |
00000411 => x"6ec000ef", |
00000412 => x"00c12083", |
00000413 => x"00000513", |
00000414 => x"01010113", |
00000415 => x"6b80006f", |
00000416 => x"ff010113", |
00000417 => x"00812423", |
00000418 => x"00050413", |
00000419 => x"01055513", |
00000420 => x"0ff57513", |
00000421 => x"00112623", |
00000422 => x"6c0000ef", |
00000423 => x"00845513", |
00000424 => x"0ff57513", |
00000425 => x"6b4000ef", |
00000426 => x"0ff47513", |
00000427 => x"00812403", |
00000428 => x"00c12083", |
00000429 => x"01010113", |
00000430 => x"6a00006f", |
00000431 => x"ff010113", |
00000432 => x"00812423", |
00000433 => x"00050413", |
00000434 => x"00000513", |
00000435 => x"00112623", |
00000436 => x"644000ef", |
00000437 => x"00300513", |
00000438 => x"680000ef", |
00000439 => x"00040513", |
00000440 => x"fa1ff0ef", |
00000441 => x"00000513", |
00000442 => x"670000ef", |
00000443 => x"00050413", |
00000444 => x"00000513", |
00000445 => x"640000ef", |
00000446 => x"00c12083", |
00000447 => x"0ff47513", |
00000448 => x"00812403", |
00000449 => x"01010113", |
00000450 => x"00008067", |
00000451 => x"fd010113", |
00000452 => x"02812423", |
00000453 => x"02912223", |
00000454 => x"03212023", |
00000455 => x"01312e23", |
00000456 => x"02112623", |
00000457 => x"00050493", |
00000458 => x"00300413", |
00000459 => x"00358913", |
00000460 => x"fff00993", |
00000461 => x"02049e63", |
00000462 => x"514000ef", |
00000463 => x"00c10793", |
00000464 => x"008787b3", |
00000465 => x"00a78023", |
00000466 => x"fff40413", |
00000467 => x"ff3414e3", |
00000468 => x"02c12083", |
00000469 => x"02812403", |
00000470 => x"00c12503", |
00000471 => x"02412483", |
00000472 => x"02012903", |
00000473 => x"01c12983", |
00000474 => x"03010113", |
00000475 => x"00008067", |
00000476 => x"40890533", |
00000477 => x"f49ff0ef", |
00000478 => x"fc5ff06f", |
00000479 => x"fd010113", |
00000480 => x"02112623", |
00000481 => x"02812423", |
00000482 => x"02912223", |
00000483 => x"03212023", |
00000484 => x"01312e23", |
00000485 => x"01412c23", |
00000486 => x"01512a23", |
00000487 => x"01612823", |
00000488 => x"01712623", |
00000489 => x"fc001473", |
00000490 => x"00847413", |
00000491 => x"00040663", |
00000492 => x"00400513", |
00000493 => x"badff0ef", |
00000494 => x"00050493", |
00000495 => x"02051863", |
00000496 => x"ffff1537", |
00000497 => x"e9c50513", |
00000498 => x"494000ef", |
00000499 => x"000405b7", |
00000500 => x"00048513", |
00000501 => x"f39ff0ef", |
00000502 => x"4788d7b7", |
00000503 => x"afe78793", |
00000504 => x"02f50463", |
00000505 => x"00000513", |
00000506 => x"fcdff06f", |
00000507 => x"ffff1537", |
00000508 => x"ebc50513", |
00000509 => x"468000ef", |
00000510 => x"e1dff0ef", |
00000511 => x"fc0518e3", |
00000512 => x"00300513", |
00000513 => x"fb1ff06f", |
00000514 => x"00040a37", |
00000515 => x"004a0593", |
00000516 => x"00048513", |
00000517 => x"ef9ff0ef", |
00000518 => x"00050913", |
00000519 => x"008a0593", |
00000520 => x"00048513", |
00000521 => x"ee9ff0ef", |
00000522 => x"00050a93", |
00000523 => x"fc6017f3", |
00000524 => x"00100513", |
00000525 => x"f927e0e3", |
00000526 => x"fc401bf3", |
00000527 => x"00000993", |
00000528 => x"ffc97b13", |
00000529 => x"00ca0a13", |
00000530 => x"014985b3", |
00000531 => x"053b1663", |
00000532 => x"01540433", |
00000533 => x"00200513", |
00000534 => x"f4041ee3", |
00000535 => x"ffff1537", |
00000536 => x"ec850513", |
00000537 => x"3f8000ef", |
00000538 => x"34091073", |
00000539 => x"02c12083", |
00000540 => x"02812403", |
00000541 => x"02412483", |
00000542 => x"02012903", |
00000543 => x"01c12983", |
00000544 => x"01812a03", |
00000545 => x"01412a83", |
00000546 => x"01012b03", |
00000547 => x"00c12b83", |
00000548 => x"03010113", |
00000549 => x"00008067", |
00000550 => x"00048513", |
00000551 => x"e71ff0ef", |
00000552 => x"017987b3", |
00000553 => x"00a40433", |
00000554 => x"00a7a023", |
00000555 => x"00498993", |
00000556 => x"f99ff06f", |
00000557 => x"ff010113", |
00000558 => x"00112623", |
00000559 => x"00812423", |
00000560 => x"00912223", |
00000561 => x"00058413", |
00000562 => x"00050493", |
00000563 => x"d8dff0ef", |
00000564 => x"00000513", |
00000565 => x"440000ef", |
00000566 => x"00200513", |
00000567 => x"47c000ef", |
00000568 => x"00048513", |
00000569 => x"d9dff0ef", |
00000570 => x"00040513", |
00000571 => x"46c000ef", |
00000572 => x"00000513", |
00000573 => x"440000ef", |
00000574 => x"cd9ff0ef", |
00000575 => x"00157513", |
00000576 => x"fe051ce3", |
00000577 => x"00c12083", |
00000578 => x"00812403", |
00000579 => x"00412483", |
00000580 => x"01010113", |
00000581 => x"00008067", |
00000582 => x"fe010113", |
00000583 => x"00812c23", |
00000584 => x"00912a23", |
00000585 => x"01212823", |
00000586 => x"00112e23", |
00000587 => x"00b12623", |
00000588 => x"00300413", |
00000589 => x"00350493", |
00000590 => x"fff00913", |
00000591 => x"00c10793", |
00000592 => x"008787b3", |
00000593 => x"0007c583", |
00000594 => x"40848533", |
00000595 => x"fff40413", |
00000596 => x"f65ff0ef", |
00000597 => x"ff2414e3", |
00000598 => x"01c12083", |
00000599 => x"01812403", |
00000600 => x"01412483", |
00000601 => x"01012903", |
00000602 => x"02010113", |
00000603 => x"00008067", |
00000604 => x"ff010113", |
00000605 => x"00112623", |
00000606 => x"00812423", |
00000607 => x"00050413", |
00000608 => x"cd9ff0ef", |
00000609 => x"00000513", |
00000610 => x"38c000ef", |
00000611 => x"0d800513", |
00000612 => x"3c8000ef", |
00000613 => x"0ff47513", |
00000614 => x"3c0000ef", |
00000613 => x"00040513", |
00000614 => x"ce9ff0ef", |
00000615 => x"00000513", |
00000616 => x"394000ef", |
00000617 => x"ce5ff0ef", |
00000617 => x"c2dff0ef", |
00000618 => x"00157513", |
00000619 => x"fe051ce3", |
00000620 => x"00c12083", |
643,7 → 643,7
00000632 => x"34001473", |
00000633 => x"02041863", |
00000634 => x"ffff1537", |
00000635 => x"eb050513", |
00000635 => x"e4450513", |
00000636 => x"01812403", |
00000637 => x"01c12083", |
00000638 => x"01412483", |
657,12 → 657,12
00000646 => x"ecc50513", |
00000647 => x"240000ef", |
00000648 => x"00040513", |
00000649 => x"96dff0ef", |
00000649 => x"98dff0ef", |
00000650 => x"ffff1537", |
00000651 => x"ed850513", |
00000652 => x"22c000ef", |
00000653 => x"00040537", |
00000654 => x"959ff0ef", |
00000654 => x"979ff0ef", |
00000655 => x"ffff1537", |
00000656 => x"ef450513", |
00000657 => x"218000ef", |
671,10 → 671,10
00000660 => x"1ec000ef", |
00000661 => x"07900793", |
00000662 => x"0af49e63", |
00000663 => x"c71ff0ef", |
00000663 => x"bb9ff0ef", |
00000664 => x"00051663", |
00000665 => x"00300513", |
00000666 => x"8d9ff0ef", |
00000666 => x"8f9ff0ef", |
00000667 => x"ffff1537", |
00000668 => x"f0050513", |
00000669 => x"01045493", |
688,11 → 688,11
00000677 => x"4788d5b7", |
00000678 => x"afe58593", |
00000679 => x"00040537", |
00000680 => x"e5dff0ef", |
00000680 => x"e79ff0ef", |
00000681 => x"00040537", |
00000682 => x"00040593", |
00000683 => x"00450513", |
00000684 => x"e4dff0ef", |
00000684 => x"e69ff0ef", |
00000685 => x"fc401a73", |
00000686 => x"000409b7", |
00000687 => x"ffc47413", |
704,18 → 704,18
00000693 => x"02849663", |
00000694 => x"00898513", |
00000695 => x"412005b3", |
00000696 => x"e1dff0ef", |
00000696 => x"e39ff0ef", |
00000697 => x"ffff1537", |
00000698 => x"eac50513", |
00000698 => x"ec850513", |
00000699 => x"f05ff06f", |
00000700 => x"00090513", |
00000701 => x"e61ff0ef", |
00000701 => x"e7dff0ef", |
00000702 => x"01490933", |
00000703 => x"f91ff06f", |
00000704 => x"0007a583", |
00000705 => x"00448493", |
00000706 => x"00b90933", |
00000707 => x"df1ff0ef", |
00000707 => x"e0dff0ef", |
00000708 => x"fbdff06f", |
00000709 => x"01c12083", |
00000710 => x"01812403", |
921,40 → 921,40
00000910 => x"45203a65", |
00000911 => x"75636578", |
00000912 => x"00006574", |
00000913 => x"746f6f42", |
00000914 => x"2e676e69", |
00000915 => x"0a0a2e2e", |
00000916 => x"00000000", |
00000917 => x"52450a07", |
00000918 => x"00005f52", |
00000919 => x"6e6b6e75", |
00000920 => x"006e776f", |
00000921 => x"00007830", |
00000922 => x"58450a0a", |
00000923 => x"54504543", |
00000924 => x"3a4e4f49", |
00000925 => x"00000020", |
00000926 => x"30204020", |
00000927 => x"00000078", |
00000928 => x"69617741", |
00000929 => x"676e6974", |
00000930 => x"6f656e20", |
00000931 => x"32337672", |
00000932 => x"6578655f", |
00000933 => x"6e69622e", |
00000934 => x"202e2e2e", |
00000935 => x"00000000", |
00000936 => x"64616f4c", |
00000937 => x"2e676e69", |
00000938 => x"00202e2e", |
00000939 => x"00004b4f", |
00000940 => x"65206f4e", |
00000941 => x"75636578", |
00000942 => x"6c626174", |
00000943 => x"76612065", |
00000944 => x"616c6961", |
00000945 => x"2e656c62", |
00000946 => x"00000000", |
00000913 => x"65206f4e", |
00000914 => x"75636578", |
00000915 => x"6c626174", |
00000916 => x"76612065", |
00000917 => x"616c6961", |
00000918 => x"2e656c62", |
00000919 => x"00000000", |
00000920 => x"746f6f42", |
00000921 => x"2e676e69", |
00000922 => x"0a0a2e2e", |
00000923 => x"00000000", |
00000924 => x"52450a07", |
00000925 => x"00005f52", |
00000926 => x"6e6b6e75", |
00000927 => x"006e776f", |
00000928 => x"00007830", |
00000929 => x"58450a0a", |
00000930 => x"54504543", |
00000931 => x"3a4e4f49", |
00000932 => x"00000020", |
00000933 => x"30204020", |
00000934 => x"00000078", |
00000935 => x"69617741", |
00000936 => x"676e6974", |
00000937 => x"6f656e20", |
00000938 => x"32337672", |
00000939 => x"6578655f", |
00000940 => x"6e69622e", |
00000941 => x"202e2e2e", |
00000942 => x"00000000", |
00000943 => x"64616f4c", |
00000944 => x"2e676e69", |
00000945 => x"00202e2e", |
00000946 => x"00004b4f", |
00000947 => x"74697257", |
00000948 => x"78302065", |
00000949 => x"00000000", |
982,7 → 982,7
00000971 => x"4c420a0a", |
00000972 => x"203a5644", |
00000973 => x"206e754a", |
00000974 => x"32203532", |
00000974 => x"32203732", |
00000975 => x"0a303230", |
00000976 => x"3a565748", |
00000977 => x"00002020", |
/neorv32_cpu_control.vhd
149,8 → 149,7
|
-- irq controller -- |
signal exc_buf : std_ulogic_vector(exception_width_c-1 downto 0); |
signal exc_ack : std_ulogic_vector(exception_width_c-1 downto 0); |
signal exc_ack_nxt : std_ulogic_vector(exception_width_c-1 downto 0); |
signal exc_ack : std_ulogic; |
signal exc_src : std_ulogic_vector(exception_width_c-1 downto 0); |
signal exc_fire : std_ulogic; |
signal irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0); |
324,11 → 323,10
-- Arbiter State Machine Comb ----------------------------------------------- |
-- ----------------------------------------------------------------------------- |
arbiter_comb: process(state, ctrl, i_reg, alu_wait_i, bus_wait_i, exc_cpu_start, ma_load_i, be_load_i, ma_store_i, be_store_i, |
i_reg, ci_reg, i_buf, instr_i, is_ci, iavail, pc_backup_reg, ci_valid, ci_instr32) |
ci_reg, i_buf, instr_i, is_ci, iavail, pc_backup_reg, ci_valid, ci_instr32) |
variable alu_immediate_v : std_ulogic; |
variable alu_operation_v : std_ulogic_vector(2 downto 0); |
variable rs1_is_r0_v : std_ulogic; |
variable rd_is_r0_v : std_ulogic; |
begin |
-- arbiter defaults -- |
state_nxt <= state; |
398,13 → 396,7
rs1_is_r0_v := '1'; |
end if; |
|
-- is rd = r0? -- |
rd_is_r0_v := '0'; |
if (i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") then |
rd_is_r0_v := '1'; |
end if; |
|
|
-- state machine: instruction fetch and execution -- |
case state is |
|
573,7 → 565,7
|
when opcode_syscsr_c => -- system/csr access |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_csr_re_c) <= '1'; -- ALWAYS READ CSR!!! (OLD: not rd_is_r0_v; -- valid CSR read if rd is not r0) |
ctrl_nxt(ctrl_csr_re_c) <= '1'; -- ALWAYS READ CSR!!! (OLD: valid CSR read if rd is not r0) |
if (i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system |
case i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is |
when x"000" => env_call <= '1'; state_nxt <= IFETCH_0; -- ECALL |
690,7 → 682,7
|
-- Illegal Instruction Check -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
illegal_instruction_check: process(i_reg, state, ctrl_nxt) |
illegal_instruction_check: process(i_reg, state, ctrl_nxt, ci_valid, ci_illegal) |
begin |
if (state = EXECUTE) then |
-- defaults -- |
902,7 → 894,7
if (rstn_i = '0') then |
exc_buf <= (others => '0'); |
irq_buf <= (others => '0'); |
exc_ack <= (others => '0'); |
exc_ack <= '0'; |
irq_ack <= (others => '0'); |
exc_src <= (others => '0'); |
exc_cpu_start <= '0'; |
911,29 → 903,21
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
-- exception buffer: misaligned load/store/instruction address |
exc_buf(exception_lalign_c) <= (exc_buf(exception_lalign_c) or ma_load_i) and (not exc_ack(exception_lalign_c)); |
exc_buf(exception_salign_c) <= (exc_buf(exception_salign_c) or ma_store_i) and (not exc_ack(exception_salign_c)); |
exc_buf(exception_ialign_c) <= (exc_buf(exception_ialign_c) or ma_instr_i) and (not exc_ack(exception_ialign_c)); |
exc_buf(exception_lalign_c) <= (exc_buf(exception_lalign_c) or ma_load_i) and (not exc_ack); |
exc_buf(exception_salign_c) <= (exc_buf(exception_salign_c) or ma_store_i) and (not exc_ack); |
exc_buf(exception_ialign_c) <= (exc_buf(exception_ialign_c) or ma_instr_i) and (not exc_ack); |
-- exception buffer: load/store/instruction bus access error |
exc_buf(exception_laccess_c) <= (exc_buf(exception_laccess_c) or be_load_i) and (not exc_ack(exception_laccess_c)); |
exc_buf(exception_saccess_c) <= (exc_buf(exception_saccess_c) or be_store_i) and (not exc_ack(exception_saccess_c)); |
exc_buf(exception_iaccess_c) <= (exc_buf(exception_iaccess_c) or be_instr_i) and (not exc_ack(exception_iaccess_c)); |
exc_buf(exception_laccess_c) <= (exc_buf(exception_laccess_c) or be_load_i) and (not exc_ack); |
exc_buf(exception_saccess_c) <= (exc_buf(exception_saccess_c) or be_store_i) and (not exc_ack); |
exc_buf(exception_iaccess_c) <= (exc_buf(exception_iaccess_c) or be_instr_i) and (not exc_ack); |
-- exception buffer: illegal instruction / env call / break point |
exc_buf(exception_iillegal_c) <= (exc_buf(exception_iillegal_c) or illegal_instr_exc) and (not exc_ack(exception_iillegal_c)); |
exc_buf(exception_m_envcall_c) <= (exc_buf(exception_m_envcall_c) or env_call) and (not exc_ack(exception_m_envcall_c)); |
exc_buf(exception_break_c) <= (exc_buf(exception_break_c) or break_point) and (not exc_ack(exception_break_c)); |
exc_buf(exception_iillegal_c) <= (exc_buf(exception_iillegal_c) or illegal_instr_exc) and (not exc_ack); |
exc_buf(exception_m_envcall_c) <= (exc_buf(exception_m_envcall_c) or env_call) and (not exc_ack); |
exc_buf(exception_break_c) <= (exc_buf(exception_break_c) or break_point) and (not exc_ack); |
-- interrupt buffer: machine software/external/timer interrupt |
irq_buf(interrupt_msw_irq_c) <= mie_msie and (irq_buf(interrupt_msw_irq_c) or mip_msip) and (not irq_ack(interrupt_msw_irq_c)); |
if (IO_CLIC_USE = true) then |
irq_buf(interrupt_mext_irq_c) <= mie_meie and (irq_buf(interrupt_mext_irq_c) or clic_irq_i) and (not irq_ack(interrupt_mext_irq_c)); |
else |
irq_buf(interrupt_mext_irq_c) <= '0'; |
end if; |
if (IO_MTIME_USE = true) then |
irq_buf(interrupt_mtime_irq_c) <= mie_mtie and (irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not irq_ack(interrupt_mtime_irq_c)); |
else |
irq_buf(interrupt_mtime_irq_c) <= '0'; |
end if; |
irq_buf(interrupt_msw_irq_c) <= mie_msie and (irq_buf(interrupt_msw_irq_c) or mip_msip) and (not irq_ack(interrupt_msw_irq_c)); |
irq_buf(interrupt_mext_irq_c) <= mie_meie and (irq_buf(interrupt_mext_irq_c) or clic_irq_i) and (not irq_ack(interrupt_mext_irq_c)); |
irq_buf(interrupt_mtime_irq_c) <= mie_mtie and (irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not irq_ack(interrupt_mtime_irq_c)); |
|
-- exception control -- |
if (exc_cpu_start = '0') then -- |
943,13 → 927,13
mtinst <= i_reg; -- MTINST NOT FOULLY IMPLEMENTED YET! FIXME |
mtinst(1) <= not is_ci; -- bit is set for uncompressed instruction |
exc_src <= exc_buf; -- capture source for hardware |
exc_ack <= exc_ack_nxt; -- capture and clear with exception ACK mask |
exc_ack <= '1'; -- clear execption |
irq_ack <= irq_ack_nxt; -- capture and clear with interrupt ACK mask |
exc_cpu_start <= '1'; |
end if; |
else -- waiting for exception handler to get started |
if (exc_cpu_ack = '1') then -- handler started? |
exc_ack <= (others => '0'); |
exc_ack <= '0'; |
irq_ack <= (others => '0'); |
exc_cpu_start <= '0'; |
end if; |
957,7 → 941,7
else -- (CPU_EXTENSION_RISCV_Zicsr = false) |
exc_buf <= (others => '0'); |
irq_buf <= (others => '0'); |
exc_ack <= (others => '0'); |
exc_ack <= '0'; |
irq_ack <= (others => '0'); |
exc_src <= (others => '0'); |
exc_cpu_start <= '0'; |
979,7 → 963,6
begin |
-- defaults -- |
exc_cause_nxt <= (others => '0'); |
exc_ack_nxt <= (others => '0'); |
irq_ack_nxt <= (others => '0'); |
|
-- interrupt: 1.11 machine external interrupt -- |
1001,29 → 984,23
irq_ack_nxt(interrupt_msw_irq_c) <= '1'; |
|
|
-- the following traps are caused by synchronous exceptions |
-- here we do not need an acknowledge mask since only one exception can trigger at the same time |
|
-- trap/fault: 0.0 instruction address misaligned -- |
elsif (exc_buf(exception_ialign_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "0000"; |
exc_ack_nxt(exception_ialign_c) <= '1'; |
exc_ack_nxt(exception_iaccess_c) <= '1'; |
exc_ack_nxt(exception_iillegal_c) <= '1'; |
|
-- trap/fault: 0.1 instruction access fault -- |
elsif (exc_buf(exception_iaccess_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "0001"; |
exc_ack_nxt(exception_ialign_c) <= '1'; |
exc_ack_nxt(exception_iaccess_c) <= '1'; |
exc_ack_nxt(exception_iillegal_c) <= '1'; |
|
-- trap/fault: 0.2 illegal instruction -- |
elsif (exc_buf(exception_iillegal_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "0010"; |
exc_ack_nxt(exception_ialign_c) <= '1'; |
exc_ack_nxt(exception_iaccess_c) <= '1'; |
exc_ack_nxt(exception_iillegal_c) <= '1'; |
|
|
-- trap/fault: 0.11 environment call from M-mode -- |
1030,13 → 1007,11
elsif (exc_buf(exception_m_envcall_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "1011"; |
exc_ack_nxt(exception_m_envcall_c) <= '1'; |
|
-- trap/fault: 0.3 breakpoint -- |
elsif (exc_buf(exception_break_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "0011"; |
exc_ack_nxt(exception_break_c) <= '1'; |
|
|
-- trap/fault: 0.6 store address misaligned - |
1043,42 → 1018,26
elsif (exc_buf(exception_salign_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "0110"; |
exc_ack_nxt(exception_salign_c) <= '1'; |
exc_ack_nxt(exception_lalign_c) <= '1'; |
exc_ack_nxt(exception_saccess_c) <= '1'; |
exc_ack_nxt(exception_laccess_c) <= '1'; |
|
-- trap/fault: 0.4 load address misaligned -- |
elsif (exc_buf(exception_lalign_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "0100"; |
exc_ack_nxt(exception_salign_c) <= '1'; |
exc_ack_nxt(exception_lalign_c) <= '1'; |
exc_ack_nxt(exception_saccess_c) <= '1'; |
exc_ack_nxt(exception_laccess_c) <= '1'; |
|
-- trap/fault: 0.7 store access fault -- |
elsif (exc_buf(exception_saccess_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "0111"; |
exc_ack_nxt(exception_salign_c) <= '1'; |
exc_ack_nxt(exception_lalign_c) <= '1'; |
exc_ack_nxt(exception_saccess_c) <= '1'; |
exc_ack_nxt(exception_laccess_c) <= '1'; |
|
-- trap/fault: 0.5 load access fault -- |
elsif (exc_buf(exception_laccess_c) = '1') then |
exc_cause_nxt(exc_cause_nxt'left) <= '0'; |
exc_cause_nxt(3 downto 0) <= "0101"; |
exc_ack_nxt(exception_salign_c) <= '1'; |
exc_ack_nxt(exception_lalign_c) <= '1'; |
exc_ack_nxt(exception_saccess_c) <= '1'; |
exc_ack_nxt(exception_laccess_c) <= '1'; |
|
-- undefined / not implemented -- |
else |
exc_cause_nxt <= (others => '0'); -- default |
exc_ack_nxt <= (others => '0'); -- default |
exc_cause_nxt <= (others => '0'); |
irq_ack_nxt <= (others => '0'); |
end if; |
end process exc_priority; |
|
1100,35 → 1059,38
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
mip_msip <= '0'; |
|
-- register that can be modified by user -- |
if (ctrl(ctrl_csr_we_c) = '1') then -- manual update |
case i_reg(31 downto 20) is |
-- machine trap setup -- |
when x"300" => -- R/W: mstatus - machine status register |
|
-- machine trap setup -- |
if (i_reg(31 downto 24) = x"30") then |
if (i_reg(23 downto 20) = x"0") then -- R/W: mstatus - machine status register |
mstatus_mie <= csr_wdata_i(03); |
mstatus_mpie <= csr_wdata_i(07); |
when x"304" => -- R/W: mie - machine interrupt-enable register |
end if; |
if (i_reg(23 downto 20) = x"4") then -- R/W: mie - machine interrupt-enable register |
mie_msie <= csr_wdata_i(03); -- SW IRQ enable |
if (IO_MTIME_USE = true) then |
mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable |
end if; |
if (IO_CLIC_USE = true) then |
mie_meie <= csr_wdata_i(11); -- EXT IRQ enable |
end if; |
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable |
mie_meie <= csr_wdata_i(11); -- EXT IRQ enable |
end if; |
if (i_reg(23 downto 20) = x"5") then -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
mtvec <= csr_wdata_i; |
-- machine trap handling -- |
when x"340" => -- R/W: mscratch - machine scratch register |
end if; |
end if; |
|
-- machine trap handling -- |
if (i_reg(31 downto 24) = x"34") then |
if (i_reg(23 downto 20) = x"0") then -- R/W: mscratch - machine scratch register |
mscratch <= csr_wdata_i; |
when x"344" => -- R/W: mip - machine interrupt pending |
end if; |
if (i_reg(23 downto 20) = x"1") then-- R/W: mepc - machine exception program counter |
mepc <= csr_wdata_i; |
end if; |
if (i_reg(23 downto 20) = x"4") then -- R/W: mip - machine interrupt pending |
mip_msip <= csr_wdata_i(03); -- manual SW IRQ trigger |
-- machine trap handling -- |
when x"341" => -- R/W: mepc - machine exception program counter |
mepc <= csr_wdata_i; |
-- undefined/unavailable -- |
when others => |
NULL; |
end case; |
end if; |
end if; |
|
else -- automatic update by hardware |
-- machine exception PC & exception value register -- |
/neorv32_cpu_cp_muldiv.vhd
111,18 → 111,18
when IDLE => |
opx <= rs1_i; |
opy <= rs2_i; |
cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c); |
if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then |
cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c); |
state <= DECODE; |
end if; |
|
when DECODE => |
cnt <= "11111"; |
if (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) then -- result sign compensation for div? |
div_res_corr <= opx(opx'left) xor opy(opy'left); |
else |
div_res_corr <= '0'; |
end if; |
cnt <= "11111"; |
if (operation = '1') then -- division |
state <= INIT_OPX; |
else -- multiplication |
185,7 → 185,7
end process multiplier_core; |
|
-- MUL: do another addition -- |
mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opy_is_signed, opx) |
mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx) |
begin |
if (mul_product(0) = '1') then |
if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB |
/neorv32_devnull.vhd
61,11 → 61,8
architecture neorv32_devnull_rtl of neorv32_devnull is |
|
-- configuration -- |
constant sim_output_en_c : boolean := true; -- output lowest byte as char to simulator |
constant sim_output_en_c : boolean := true; -- output lowest byte as char to simulator when enabled |
|
-- text.io -- |
file file_devnull_out : text open write_mode is "neorv32.devnull.out"; |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(devnull_size_c); -- low address boundary bit |
83,27 → 80,26
-- Read/Write Access ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
rw_access: process(clk_i) |
file file_devnull_out : text open write_mode is "neorv32.devnull.out"; |
variable i : integer; |
variable la, lb : line; -- we need to variables here since "writeline" seems to flush the source variable |
begin |
if rising_edge(clk_i) then |
ack_o <= acc_en and (wren_i or rden_i); |
if ((acc_en and wren_i and ben_i(0)) = '1') then |
if ((acc_en and wren_i and ben_i(0)) = '1') and (sim_output_en_c = true) then |
-- print lowest byte as ASCII to console -- |
if (sim_output_en_c = true) then |
i := to_integer(unsigned(data_i(7 downto 0))); |
if (i >= 128) then -- out of range? |
i := 0; |
end if; |
if (i /= 10) and (i /= 13) then -- skip linebreaks |
write(la, character'val(i)); |
write(lb, character'val(i)); |
end if; |
if (i = 10) then -- line break: write to screen and file |
writeline(output, la); |
writeline(file_devnull_out, lb); |
end if; |
i := to_integer(unsigned(data_i(7 downto 0))); |
if (i >= 128) then -- out of range? |
i := 0; |
end if; |
if (i /= 10) and (i /= 13) then -- skip line breaks - they are issued via "writeline" |
write(la, character'val(i)); |
write(lb, character'val(i)); |
end if; |
if (i = 10) then -- line break: write to screen and file |
writeline(output, la); |
writeline(file_devnull_out, lb); |
end if; |
end if; |
end if; |
end process rw_access; |
/neorv32_mtime.vhd
50,6 → 50,7
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
74,7 → 75,6
signal wren : std_ulogic; -- module access enable |
|
-- accessible regs -- |
signal mtime_we : std_ulogic; |
signal mtimecmp : std_ulogic_vector(63 downto 0); |
signal mtime_lo : std_ulogic_vector(32 downto 0); |
signal mtime_lo_msb_ff : std_ulogic; |
97,6 → 97,26
wren <= acc_en and wren_i; |
|
|
-- System Time Update --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
system_time: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (rstn_i = '0') then |
mtime_lo <= (others => '0'); |
mtime_hi <= (others => '0'); |
else |
-- mtime low -- |
mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1); |
-- mtime high -- |
if ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry? |
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1); |
end if; |
end if; |
end if; |
end process system_time; |
|
|
-- Write Access --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
wr_access: process(clk_i) |
120,36 → 140,6
end if; |
end loop; -- byte enable |
end if; |
|
-- any access to mtime at all? -- |
mtime_we <= '0'; |
if (wren = '1') and ((addr = mtime_time_lo_addr_c) or (addr = mtime_time_hi_addr_c)) then |
mtime_we <= '1'; |
end if; |
|
-- mtime low -- |
mtime_lo_msb_ff <= mtime_lo(mtime_lo'left); |
if (wren = '1') and (addr = mtime_time_lo_addr_c) then |
mtime_lo(mtime_lo'left) <= '0'; -- clear overflow bit on every access |
for i in 0 to 3 loop |
if (ben_i(i) = '1') then |
mtime_lo(00+7+i*8 downto 00+0+i*8) <= data_i(7+i*8 downto 0+i*8); |
end if; |
end loop; -- byte enable |
else -- incrment |
mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1); |
end if; |
|
-- mtime high -- |
if (wren = '1') and (addr = mtime_time_hi_addr_c) then |
for i in 0 to 3 loop |
if (ben_i(i) = '1') then |
mtime_hi(00+7+i*8 downto 00+0+i*8) <= data_i(7+i*8 downto 0+i*8); |
end if; |
end loop; -- byte enable |
elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry? |
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1); |
end if; |
end if; |
end process wr_access; |
|
195,14 → 185,19
irq_ctrl: process(clk_i) |
begin |
if rising_edge(clk_i) then |
irq_flag_ff <= irq_flag; |
if (irq_flag = '0') or (mtime_we = '1') then -- idle or mtime manual write |
irq_flag <= '0'; |
if (cmp_match_ff = '1') then |
irq_flag <= '1'; |
if (rstn_i = '0') then |
irq_flag_ff <= '0'; |
irq_flag <= '0'; |
else |
irq_flag_ff <= irq_flag; |
if (irq_flag = '0') then -- idle |
irq_flag <= '0'; |
if (cmp_match_ff = '1') then |
irq_flag <= '1'; |
end if; |
elsif (wren = '1') and (addr = mtime_cmp_hi_addr_c) then -- ACK |
irq_flag <= '0'; |
end if; |
elsif (wren = '1') and (addr = mtime_cmp_hi_addr_c) then -- ACK |
irq_flag <= '0'; |
end if; |
end if; |
end process irq_ctrl; |
/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - FIXED! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"00000204"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"00000206"; -- no touchy! |
|
-- Internal Functions --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
49,9 → 49,9
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural; |
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector; |
function bool_to_ulogic_f(cond : boolean) return std_ulogic; |
function or_all_f(a : std_ulogic_vector) return std_ulogic; |
function and_all_f(a : std_ulogic_vector) return std_ulogic; |
function xor_all_f(a : std_ulogic_vector) return std_ulogic; |
function or_all_f( a : std_ulogic_vector) return std_ulogic; |
function and_all_f( a : std_ulogic_vector) return std_ulogic; |
function xor_all_f( a : std_ulogic_vector) return std_ulogic; |
function xnor_all_f(a : std_ulogic_vector) return std_ulogic; |
|
-- Processor-internal Address Space Layout ------------------------------------------------ |
172,7 → 172,7
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?) |
constant ctrl_bus_rd_c : natural := 33; -- read data request |
constant ctrl_bus_wr_c : natural := 34; -- write data request |
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (output PC, otherwise output MAR) |
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR) |
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable |
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable |
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable |
405,6 → 405,64
); |
end component; |
|
-- Component: CPU Top Entity -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic; -- bus transfer error |
-- external interrupts -- |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
); |
end component; |
|
-- Component: CPU Control ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu_control |
602,64 → 660,6
); |
end component; |
|
-- Component: CPU Top Entity -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic; -- bus transfer error |
-- external interrupts -- |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
); |
end component; |
|
-- Component: Processor-internal instruction memory (IMEM) -------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_imem |
719,6 → 719,7
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
949,8 → 950,8
); |
end component; |
|
-- Component: Dummy Device with SIM Output (DEVNULL) ------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
---- Component: Dummy Device with SIM Output (DEVNULL) ------------------------------------- |
---- ------------------------------------------------------------------------------------------- |
component neorv32_devnull |
port ( |
-- host access -- |
/neorv32_top.vhd
587,7 → 587,9
clic_xirq(6) <= ext_irq_i(0); |
clic_xirq(7) <= ext_irq_i(1); -- lowest priority |
|
ext_ack_o <= clic_xirq(7 downto 6); -- external interrupt request acknowledge |
-- external interrupt request acknowledge -- |
ext_ack_o(0) <= clic_xack(6); |
ext_ack_o(1) <= clic_xack(7); |
|
neorv32_clic_inst_false: |
if (IO_CLIC_USE = false) generate |
641,6 → 643,7
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset, low-active, async |
addr_i => cpu_addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
848,7 → 851,7
ack_o => devnull_ack -- transfer acknowledge |
); |
end generate; |
|
|
neorv32_devnull_inst_false: |
if (IO_DEVNULL_USE = false) generate |
devnull_rdata <= (others => '0'); |