URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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- This comparison shows the changes necessary to convert path
/neorv32/trunk/rtl/core
- from Rev 69 to Rev 70
- ↔ Reverse comparison
Rev 69 → Rev 70
/mem/neorv32_dmem.cyclone2.vhd
File deleted
/mem/neorv32_imem.cyclone2.vhd
File deleted
/mem/README.md
7,7 → 7,7
For the first implementation the `*.default.vhd` files should be selected. The HDL style for describing |
memories used by these files has proven **platform-independence** across several FPGA architectures and toolchains. |
|
If synthesis fails to infer actual block RAM resources from these default files, try the legacy `*.cyclone2.vhd` files, which |
If synthesis fails to infer actual block RAM resources from these default files, try the legacy `*.legacy.vhd` files, which |
provide a different HDL style. These files are intended for legacy support of older Intel/Altera Quartus versions (13.0 and older). However, |
these files do **not** use platform-specific macros or primitives - so they might also work for other FPGAs and toolchains. |
|
/mem/neorv32_dmem.legacy.vhd
0,0 → 1,130
-- ################################################################################################# |
-- # << NEORV32 - Processor-internal data memory (DMEM) >> # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
architecture neorv32_dmem_rtl of neorv32_dmem is |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := 31; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(DMEM_SIZE); -- low address boundary bit |
|
-- local signals -- |
signal acc_en : std_ulogic; |
signal rdata : std_ulogic_vector(31 downto 0); |
signal rden : std_ulogic; |
signal addr : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0); |
signal addr_ff : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0); |
|
-- -------------------------------------------------------------------------------------------------------------- -- |
-- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- |
-- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- |
-- -------------------------------------------------------------------------------------------------------------- -- |
|
-- RAM - not initialized at all -- |
signal mem_ram_b0 : mem8_t(0 to DMEM_SIZE/4-1); |
signal mem_ram_b1 : mem8_t(0 to DMEM_SIZE/4-1); |
signal mem_ram_b2 : mem8_t(0 to DMEM_SIZE/4-1); |
signal mem_ram_b3 : mem8_t(0 to DMEM_SIZE/4-1); |
|
-- read data -- |
signal mem_ram_b0_rd, mem_ram_b1_rd, mem_ram_b2_rd, mem_ram_b3_rd : std_ulogic_vector(7 downto 0); |
|
begin |
|
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using legacy HDL style DMEM." severity note; |
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) & " bytes)." severity note; |
|
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; |
addr <= addr_i(index_size_f(DMEM_SIZE/4)+1 downto 2); -- word aligned |
|
|
-- Memory Access -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
mem_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
addr_ff <= addr; |
if (acc_en = '1') then -- reduce switching activity when not accessed |
if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0 |
mem_ram_b0(to_integer(unsigned(addr))) <= data_i(07 downto 00); |
end if; |
if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1 |
mem_ram_b1(to_integer(unsigned(addr))) <= data_i(15 downto 08); |
end if; |
if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2 |
mem_ram_b2(to_integer(unsigned(addr))) <= data_i(23 downto 16); |
end if; |
if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3 |
mem_ram_b3(to_integer(unsigned(addr))) <= data_i(31 downto 24); |
end if; |
end if; |
end if; |
end process mem_access; |
|
-- sync(!) read - alternative HDL style -- |
mem_ram_b0_rd <= mem_ram_b0(to_integer(unsigned(addr_ff))); |
mem_ram_b1_rd <= mem_ram_b1(to_integer(unsigned(addr_ff))); |
mem_ram_b2_rd <= mem_ram_b2(to_integer(unsigned(addr_ff))); |
mem_ram_b3_rd <= mem_ram_b3(to_integer(unsigned(addr_ff))); |
|
|
-- Bus Feedback --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
bus_feedback: process(clk_i) |
begin |
if rising_edge(clk_i) then |
rden <= acc_en and rden_i; |
ack_o <= acc_en and (rden_i or wren_i); |
end if; |
end process bus_feedback; |
|
-- pack -- |
rdata <= mem_ram_b3_rd & mem_ram_b2_rd & mem_ram_b1_rd & mem_ram_b0_rd; |
|
-- output gate -- |
data_o <= rdata when (rden = '1') else (others => '0'); |
|
|
end neorv32_dmem_rtl; |
/mem/neorv32_imem.legacy.vhd
0,0 → 1,176
-- ################################################################################################# |
-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> # |
-- # ********************************************************************************************* # |
-- # This memory optionally includes the in-place executable image of the application. See the # |
-- # processor's documentary to get more information. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator |
|
architecture neorv32_imem_rtl of neorv32_imem is |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := 31; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(IMEM_SIZE); -- low address boundary bit |
|
-- local signals -- |
signal acc_en : std_ulogic; |
signal rdata : std_ulogic_vector(31 downto 0); |
signal rden : std_ulogic; |
signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0); |
signal addr_ff : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0); |
|
-- --------------------------- -- |
-- IMEM as pre-initialized ROM -- |
-- --------------------------- -- |
|
-- application (image) size in bytes -- |
constant imem_app_size_c : natural := (application_init_image'length)*4; |
|
-- ROM - initialized with executable code -- |
constant mem_rom : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4); |
|
-- read data -- |
signal mem_rom_rd : std_ulogic_vector(31 downto 0); |
|
-- -------------------------------------------------------------------------------------------------------------- -- |
-- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- |
-- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- |
-- -------------------------------------------------------------------------------------------------------------- -- |
|
-- RAM - not initialized at all -- |
signal mem_ram_b0 : mem8_t(0 to IMEM_SIZE/4-1); |
signal mem_ram_b1 : mem8_t(0 to IMEM_SIZE/4-1); |
signal mem_ram_b2 : mem8_t(0 to IMEM_SIZE/4-1); |
signal mem_ram_b3 : mem8_t(0 to IMEM_SIZE/4-1); |
|
-- read data -- |
signal mem_b0_rd, mem_b1_rd, mem_b2_rd, mem_b3_rd : std_ulogic_vector(7 downto 0); |
|
begin |
|
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using legacy HDL style IMEM." severity note; |
assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) & |
" bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note; |
-- |
assert not (IMEM_AS_IROM = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as blank RAM (" & natural'image(IMEM_SIZE) & |
" bytes)." severity note; |
-- |
assert not ((IMEM_AS_IROM = true) and (imem_app_size_c > IMEM_SIZE)) report "NEORV32 PROCESSOR CONFIG ERROR: Application (image = " & natural'image(imem_app_size_c) & |
" bytes) does not fit into processor-internal IMEM (ROM = " & natural'image(IMEM_SIZE) & " bytes)!" severity error; |
|
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; |
addr <= addr_i(index_size_f(IMEM_SIZE/4)+1 downto 2); -- word aligned |
|
|
-- Implement IMEM as pre-initialized ROM -------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
imem_rom: |
if (IMEM_AS_IROM = true) generate |
mem_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (acc_en = '1') then -- reduce switching activity when not accessed |
mem_rom_rd <= mem_rom(to_integer(unsigned(addr))); |
end if; |
end if; |
end process mem_access; |
-- read data -- |
rdata <= mem_rom_rd; |
end generate; |
|
|
-- Implement IMEM as not-initialized RAM -------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
imem_ram: |
if (IMEM_AS_IROM = false) generate |
mem_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
addr_ff <= addr; |
if (acc_en = '1') then -- reduce switching activity when not accessed |
if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0 |
mem_ram_b0(to_integer(unsigned(addr))) <= data_i(07 downto 00); |
end if; |
if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1 |
mem_ram_b1(to_integer(unsigned(addr))) <= data_i(15 downto 08); |
end if; |
if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2 |
mem_ram_b2(to_integer(unsigned(addr))) <= data_i(23 downto 16); |
end if; |
if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3 |
mem_ram_b3(to_integer(unsigned(addr))) <= data_i(31 downto 24); |
end if; |
end if; |
end if; |
end process mem_access; |
-- sync(!) read - alternative HDL style -- |
mem_b0_rd <= mem_ram_b0(to_integer(unsigned(addr_ff))); |
mem_b1_rd <= mem_ram_b1(to_integer(unsigned(addr_ff))); |
mem_b2_rd <= mem_ram_b2(to_integer(unsigned(addr_ff))); |
mem_b3_rd <= mem_ram_b3(to_integer(unsigned(addr_ff))); |
-- pack -- |
rdata <= mem_b3_rd & mem_b2_rd & mem_b1_rd & mem_b0_rd; |
end generate; |
|
|
-- Bus Feedback --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
bus_feedback: process(clk_i) |
begin |
if rising_edge(clk_i) then |
rden <= acc_en and rden_i; |
if (IMEM_AS_IROM = true) then |
ack_o <= acc_en and rden_i; |
else |
ack_o <= acc_en and (rden_i or wren_i); |
end if; |
end if; |
end process bus_feedback; |
|
-- output gate -- |
data_o <= rdata when (rden = '1') else (others => '0'); |
|
|
end neorv32_imem_rtl; |
/neorv32_application_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin> |
-- Size: 3468 bytes |
-- Size: 3448 bytes |
|
library ieee; |
use ieee.std_logic_1164.all; |
67,7 → 67,7
00000053 => x"00158593", |
00000054 => x"ff5ff06f", |
00000055 => x"00001597", |
00000056 => x"cb058593", |
00000056 => x"c9c58593", |
00000057 => x"80000617", |
00000058 => x"f1c60613", |
00000059 => x"80000697", |
114,15 → 114,15
00000100 => x"b0050513", |
00000101 => x"00112623", |
00000102 => x"088000ef", |
00000103 => x"780000ef", |
00000103 => x"768000ef", |
00000104 => x"00050c63", |
00000105 => x"730000ef", |
00000105 => x"714000ef", |
00000106 => x"00001537", |
00000107 => x"ac850513", |
00000107 => x"ab050513", |
00000108 => x"134000ef", |
00000109 => x"020000ef", |
00000110 => x"00001537", |
00000111 => x"aa450513", |
00000111 => x"a8c50513", |
00000112 => x"124000ef", |
00000113 => x"00c12083", |
00000114 => x"00100513", |
133,12 → 133,12
00000119 => x"00000593", |
00000120 => x"00112623", |
00000121 => x"00812423", |
00000122 => x"744000ef", |
00000122 => x"72c000ef", |
00000123 => x"00000513", |
00000124 => x"00150413", |
00000125 => x"00000593", |
00000126 => x"0ff57513", |
00000127 => x"730000ef", |
00000127 => x"718000ef", |
00000128 => x"0c800513", |
00000129 => x"164000ef", |
00000130 => x"00040513", |
157,7 → 157,7
00000143 => x"00151593", |
00000144 => x"00078513", |
00000145 => x"00060493", |
00000146 => x"7b0000ef", |
00000146 => x"798000ef", |
00000147 => x"01051513", |
00000148 => x"000017b7", |
00000149 => x"01055513", |
238,11 → 238,11
00000224 => x"02912223", |
00000225 => x"03212023", |
00000226 => x"01312e23", |
00000227 => x"66c000ef", |
00000227 => x"654000ef", |
00000228 => x"00c12603", |
00000229 => x"00000693", |
00000230 => x"00000593", |
00000231 => x"5c4000ef", |
00000231 => x"5ac000ef", |
00000232 => x"00050413", |
00000233 => x"00058993", |
00000234 => x"f95ff0ef", |
276,608 → 276,603
00000262 => x"00000013", |
00000263 => x"ff1ff06f", |
00000264 => x"fc5ff06f", |
00000265 => x"00000000", |
00000266 => x"00000000", |
00000267 => x"00000000", |
00000268 => x"fc010113", |
00000269 => x"02112e23", |
00000270 => x"02512c23", |
00000271 => x"02612a23", |
00000272 => x"02712823", |
00000273 => x"02a12623", |
00000274 => x"02b12423", |
00000275 => x"02c12223", |
00000276 => x"02d12023", |
00000277 => x"00e12e23", |
00000278 => x"00f12c23", |
00000279 => x"01012a23", |
00000280 => x"01112823", |
00000281 => x"01c12623", |
00000282 => x"01d12423", |
00000283 => x"01e12223", |
00000284 => x"01f12023", |
00000285 => x"34102773", |
00000286 => x"34071073", |
00000287 => x"342027f3", |
00000288 => x"0807c863", |
00000289 => x"00071683", |
00000290 => x"00300593", |
00000291 => x"0036f693", |
00000292 => x"00270613", |
00000293 => x"00b69463", |
00000294 => x"00470613", |
00000295 => x"34161073", |
00000296 => x"00b00713", |
00000297 => x"04f77a63", |
00000298 => x"6ac00793", |
00000299 => x"000780e7", |
00000300 => x"03c12083", |
00000301 => x"03812283", |
00000302 => x"03412303", |
00000303 => x"03012383", |
00000304 => x"02c12503", |
00000305 => x"02812583", |
00000306 => x"02412603", |
00000307 => x"02012683", |
00000308 => x"01c12703", |
00000309 => x"01812783", |
00000310 => x"01412803", |
00000311 => x"01012883", |
00000312 => x"00c12e03", |
00000313 => x"00812e83", |
00000314 => x"00412f03", |
00000315 => x"00012f83", |
00000316 => x"04010113", |
00000317 => x"30200073", |
00000318 => x"00001737", |
00000319 => x"00279793", |
00000320 => x"ae470713", |
00000321 => x"00e787b3", |
00000322 => x"0007a783", |
00000323 => x"00078067", |
00000324 => x"80000737", |
00000325 => x"ffd74713", |
00000326 => x"00e787b3", |
00000327 => x"01c00713", |
00000328 => x"f8f764e3", |
00000329 => x"00001737", |
00000330 => x"00279793", |
00000331 => x"b1470713", |
00000332 => x"00e787b3", |
00000333 => x"0007a783", |
00000334 => x"00078067", |
00000265 => x"fc010113", |
00000266 => x"02112e23", |
00000267 => x"02512c23", |
00000268 => x"02612a23", |
00000269 => x"02712823", |
00000270 => x"02a12623", |
00000271 => x"02b12423", |
00000272 => x"02c12223", |
00000273 => x"02d12023", |
00000274 => x"00e12e23", |
00000275 => x"00f12c23", |
00000276 => x"01012a23", |
00000277 => x"01112823", |
00000278 => x"01c12623", |
00000279 => x"01d12423", |
00000280 => x"01e12223", |
00000281 => x"01f12023", |
00000282 => x"34102773", |
00000283 => x"34071073", |
00000284 => x"342027f3", |
00000285 => x"0407c463", |
00000286 => x"00071683", |
00000287 => x"00300593", |
00000288 => x"0036f693", |
00000289 => x"00270613", |
00000290 => x"00b69463", |
00000291 => x"00470613", |
00000292 => x"34161073", |
00000293 => x"00b00713", |
00000294 => x"00f77663", |
00000295 => x"69000793", |
00000296 => x"0500006f", |
00000297 => x"00001737", |
00000298 => x"00279793", |
00000299 => x"acc70713", |
00000300 => x"00e787b3", |
00000301 => x"0007a783", |
00000302 => x"00078067", |
00000303 => x"80000737", |
00000304 => x"ffd74713", |
00000305 => x"00e787b3", |
00000306 => x"01c00713", |
00000307 => x"fcf768e3", |
00000308 => x"00001737", |
00000309 => x"00279793", |
00000310 => x"afc70713", |
00000311 => x"00e787b3", |
00000312 => x"0007a783", |
00000313 => x"00078067", |
00000314 => x"800007b7", |
00000315 => x"0007a783", |
00000316 => x"000780e7", |
00000317 => x"03c12083", |
00000318 => x"03812283", |
00000319 => x"03412303", |
00000320 => x"03012383", |
00000321 => x"02c12503", |
00000322 => x"02812583", |
00000323 => x"02412603", |
00000324 => x"02012683", |
00000325 => x"01c12703", |
00000326 => x"01812783", |
00000327 => x"01412803", |
00000328 => x"01012883", |
00000329 => x"00c12e03", |
00000330 => x"00812e83", |
00000331 => x"00412f03", |
00000332 => x"00012f83", |
00000333 => x"04010113", |
00000334 => x"30200073", |
00000335 => x"800007b7", |
00000336 => x"0007a783", |
00000337 => x"f69ff06f", |
00000338 => x"800007b7", |
00000339 => x"0047a783", |
00000340 => x"f5dff06f", |
00000341 => x"800007b7", |
00000342 => x"0087a783", |
00000343 => x"f51ff06f", |
00000344 => x"800007b7", |
00000345 => x"00c7a783", |
00000346 => x"f45ff06f", |
00000347 => x"8101a783", |
00000348 => x"f3dff06f", |
00000349 => x"8141a783", |
00000350 => x"f35ff06f", |
00000351 => x"8181a783", |
00000352 => x"f2dff06f", |
00000353 => x"81c1a783", |
00000354 => x"f25ff06f", |
00000355 => x"8201a783", |
00000356 => x"f1dff06f", |
00000357 => x"8241a783", |
00000358 => x"f15ff06f", |
00000359 => x"8281a783", |
00000360 => x"f0dff06f", |
00000361 => x"82c1a783", |
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00000660 => x"f91ff0ef", |
00000661 => x"40a00533", |
00000662 => x"00028067", |
00000663 => x"00008293", |
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00000665 => x"00054c63", |
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00000667 => x"00058513", |
00000668 => x"00028067", |
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00000673 => x"00058513", |
00000669 => x"40b005b3", |
00000670 => x"fe0558e3", |
00000671 => x"40a00533", |
00000672 => x"f61ff0ef", |
00000673 => x"40b00533", |
00000674 => x"00028067", |
00000675 => x"40b005b3", |
00000676 => x"fe0558e3", |
00000677 => x"40a00533", |
00000678 => x"f61ff0ef", |
00000679 => x"40b00533", |
00000680 => x"00028067", |
00000681 => x"6f727245", |
00000682 => x"4e202172", |
00000683 => x"5047206f", |
00000684 => x"75204f49", |
00000685 => x"2074696e", |
00000686 => x"746e7973", |
00000687 => x"69736568", |
00000688 => x"2164657a", |
00000689 => x"0000000a", |
00000690 => x"6e696c42", |
00000691 => x"676e696b", |
00000692 => x"44454c20", |
00000693 => x"6d656420", |
00000694 => x"7270206f", |
00000695 => x"6172676f", |
00000696 => x"00000a6d", |
00000697 => x"0000053c", |
00000698 => x"00000548", |
00000699 => x"00000554", |
00000700 => x"00000560", |
00000701 => x"0000056c", |
00000702 => x"00000574", |
00000703 => x"0000057c", |
00000704 => x"00000584", |
00000705 => x"0000058c", |
00000706 => x"000004a8", |
00000707 => x"000004a8", |
00000708 => x"00000594", |
00000709 => x"0000059c", |
00000710 => x"000004a8", |
00000711 => x"000004a8", |
00000712 => x"000004a8", |
00000713 => x"000005a4", |
00000714 => x"000004a8", |
00000715 => x"000004a8", |
00000716 => x"000004a8", |
00000717 => x"000005ac", |
00000718 => x"000004a8", |
00000719 => x"000004a8", |
00000720 => x"000004a8", |
00000721 => x"000004a8", |
00000722 => x"000005b4", |
00000723 => x"000005bc", |
00000724 => x"000005c4", |
00000725 => x"000005cc", |
00000726 => x"000005d4", |
00000727 => x"000005dc", |
00000728 => x"000005e4", |
00000729 => x"000005ec", |
00000730 => x"000005f4", |
00000731 => x"000005fc", |
00000732 => x"00000604", |
00000733 => x"0000060c", |
00000734 => x"00000614", |
00000735 => x"0000061c", |
00000736 => x"00000624", |
00000737 => x"0000062c", |
00000738 => x"00007830", |
00000739 => x"4554523c", |
00000740 => x"0000203e", |
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00000742 => x"74637572", |
00000743 => x"206e6f69", |
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00000745 => x"20737365", |
00000746 => x"6173696d", |
00000747 => x"6e67696c", |
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00000751 => x"206e6f69", |
00000752 => x"65636361", |
00000753 => x"66207373", |
00000754 => x"746c7561", |
00000755 => x"00000000", |
00000756 => x"656c6c49", |
00000757 => x"206c6167", |
00000758 => x"74736e69", |
00000759 => x"74637572", |
00000760 => x"006e6f69", |
00000761 => x"61657242", |
00000762 => x"696f706b", |
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00000675 => x"6f727245", |
00000676 => x"4e202172", |
00000677 => x"5047206f", |
00000678 => x"75204f49", |
00000679 => x"2074696e", |
00000680 => x"746e7973", |
00000681 => x"69736568", |
00000682 => x"2164657a", |
00000683 => x"0000000a", |
00000684 => x"6e696c42", |
00000685 => x"676e696b", |
00000686 => x"44454c20", |
00000687 => x"6d656420", |
00000688 => x"7270206f", |
00000689 => x"6172676f", |
00000690 => x"00000a6d", |
00000691 => x"000004e8", |
00000692 => x"0000053c", |
00000693 => x"00000548", |
00000694 => x"00000550", |
00000695 => x"00000558", |
00000696 => x"00000560", |
00000697 => x"00000568", |
00000698 => x"00000570", |
00000699 => x"00000578", |
00000700 => x"0000049c", |
00000701 => x"0000049c", |
00000702 => x"00000580", |
00000703 => x"00000588", |
00000704 => x"0000049c", |
00000705 => x"0000049c", |
00000706 => x"0000049c", |
00000707 => x"00000590", |
00000708 => x"0000049c", |
00000709 => x"0000049c", |
00000710 => x"0000049c", |
00000711 => x"00000598", |
00000712 => x"0000049c", |
00000713 => x"0000049c", |
00000714 => x"0000049c", |
00000715 => x"0000049c", |
00000716 => x"000005a0", |
00000717 => x"000005a8", |
00000718 => x"000005b0", |
00000719 => x"000005b8", |
00000720 => x"000005c0", |
00000721 => x"000005c8", |
00000722 => x"000005d0", |
00000723 => x"000005d8", |
00000724 => x"000005e0", |
00000725 => x"000005e8", |
00000726 => x"000005f0", |
00000727 => x"000005f8", |
00000728 => x"00000600", |
00000729 => x"00000608", |
00000730 => x"00000610", |
00000731 => x"00000618", |
00000732 => x"00007830", |
00000733 => x"4554523c", |
00000734 => x"0000203e", |
00000735 => x"74736e49", |
00000736 => x"74637572", |
00000737 => x"206e6f69", |
00000738 => x"72646461", |
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00000740 => x"6173696d", |
00000741 => x"6e67696c", |
00000742 => x"00006465", |
00000743 => x"74736e49", |
00000744 => x"74637572", |
00000745 => x"206e6f69", |
00000746 => x"65636361", |
00000747 => x"66207373", |
00000748 => x"746c7561", |
00000749 => x"00000000", |
00000750 => x"656c6c49", |
00000751 => x"206c6167", |
00000752 => x"74736e69", |
00000753 => x"74637572", |
00000754 => x"006e6f69", |
00000755 => x"61657242", |
00000756 => x"696f706b", |
00000757 => x"0000746e", |
00000758 => x"64616f4c", |
00000759 => x"64646120", |
00000760 => x"73736572", |
00000761 => x"73696d20", |
00000762 => x"67696c61", |
00000763 => x"0064656e", |
00000764 => x"64616f4c", |
00000765 => x"64646120", |
00000766 => x"73736572", |
00000767 => x"73696d20", |
00000768 => x"67696c61", |
00000769 => x"0064656e", |
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00000774 => x"00000074", |
00000775 => x"726f7453", |
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00000777 => x"73657264", |
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00000779 => x"696c6173", |
00000780 => x"64656e67", |
00000781 => x"00000000", |
00000782 => x"726f7453", |
00000783 => x"63612065", |
00000784 => x"73736563", |
00000785 => x"75616620", |
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00000787 => x"69766e45", |
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00000794 => x"00000000", |
00000795 => x"69766e45", |
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00000798 => x"6c6c6163", |
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00000800 => x"2d4d206d", |
00000801 => x"65646f6d", |
00000802 => x"00000000", |
00000803 => x"6863614d", |
00000804 => x"20656e69", |
00000805 => x"74666f73", |
00000806 => x"65726177", |
00000807 => x"746e6920", |
00000808 => x"75727265", |
00000809 => x"00007470", |
00000765 => x"63636120", |
00000766 => x"20737365", |
00000767 => x"6c756166", |
00000768 => x"00000074", |
00000769 => x"726f7453", |
00000770 => x"64612065", |
00000771 => x"73657264", |
00000772 => x"696d2073", |
00000773 => x"696c6173", |
00000774 => x"64656e67", |
00000775 => x"00000000", |
00000776 => x"726f7453", |
00000777 => x"63612065", |
00000778 => x"73736563", |
00000779 => x"75616620", |
00000780 => x"0000746c", |
00000781 => x"69766e45", |
00000782 => x"6d6e6f72", |
00000783 => x"20746e65", |
00000784 => x"6c6c6163", |
00000785 => x"6f726620", |
00000786 => x"2d55206d", |
00000787 => x"65646f6d", |
00000788 => x"00000000", |
00000789 => x"69766e45", |
00000790 => x"6d6e6f72", |
00000791 => x"20746e65", |
00000792 => x"6c6c6163", |
00000793 => x"6f726620", |
00000794 => x"2d4d206d", |
00000795 => x"65646f6d", |
00000796 => x"00000000", |
00000797 => x"6863614d", |
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00000800 => x"65726177", |
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00000802 => x"75727265", |
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00000804 => x"6863614d", |
00000805 => x"20656e69", |
00000806 => x"656d6974", |
00000807 => x"6e692072", |
00000808 => x"72726574", |
00000809 => x"00747075", |
00000810 => x"6863614d", |
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00000812 => x"656d6974", |
00000813 => x"6e692072", |
00000814 => x"72726574", |
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00000816 => x"6863614d", |
00000817 => x"20656e69", |
00000818 => x"65747865", |
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00000825 => x"75727265", |
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00000838 => x"45434956", |
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00000840 => x"0000005d", |
00000841 => x"4d505b20", |
00000842 => x"52455f50", |
00000843 => x"00005d52", |
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00000846 => x"544d202c", |
00000847 => x"3d4c4156", |
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00000850 => x"003e4554", |
00000851 => x"000007bc", |
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00000854 => x"00000800", |
00000855 => x"0000080c", |
00000856 => x"00000818", |
00000857 => x"00000824", |
00000858 => x"00000830", |
00000859 => x"0000083c", |
00000860 => x"00000728", |
00000861 => x"00000728", |
00000862 => x"00000848", |
00000863 => x"33323130", |
00000864 => x"37363534", |
00000865 => x"42413938", |
00000866 => x"46454443" |
00000812 => x"65747865", |
00000813 => x"6c616e72", |
00000814 => x"746e6920", |
00000815 => x"75727265", |
00000816 => x"00007470", |
00000817 => x"74736146", |
00000818 => x"746e6920", |
00000819 => x"75727265", |
00000820 => x"00207470", |
00000821 => x"6e6b6e55", |
00000822 => x"206e776f", |
00000823 => x"70617274", |
00000824 => x"75616320", |
00000825 => x"203a6573", |
00000826 => x"00000000", |
00000827 => x"49545b20", |
00000828 => x"554f454d", |
00000829 => x"52455f54", |
00000830 => x"00005d52", |
00000831 => x"45445b20", |
00000832 => x"45434956", |
00000833 => x"5252455f", |
00000834 => x"0000005d", |
00000835 => x"4d505b20", |
00000836 => x"52455f50", |
00000837 => x"00005d52", |
00000838 => x"50204020", |
00000839 => x"00003d43", |
00000840 => x"544d202c", |
00000841 => x"3d4c4156", |
00000842 => x"00000000", |
00000843 => x"522f3c20", |
00000844 => x"0a3e4554", |
00000845 => x"00000000", |
00000846 => x"000007a0", |
00000847 => x"000007b0", |
00000848 => x"000007d8", |
00000849 => x"000007e4", |
00000850 => x"000007f0", |
00000851 => x"000007fc", |
00000852 => x"00000808", |
00000853 => x"00000814", |
00000854 => x"00000820", |
00000855 => x"0000070c", |
00000856 => x"0000070c", |
00000857 => x"0000082c", |
00000858 => x"33323130", |
00000859 => x"37363534", |
00000860 => x"42413938", |
00000861 => x"46454443" |
); |
|
end neorv32_application_image; |
/neorv32_bus_keeper.vhd
2,12 → 2,12
-- # << NEORV32 - Bus Keeper (BUSKEEPER) >> # |
-- # ********************************************************************************************* # |
-- # This unit monitors the processor-internal bus. If the accessed module does not respond within # |
-- # the defined number of cycles (VHDL package: max_proc_int_response_time_c) or issues an ERROR # |
-- # conditions the BUS KEEPER asserts the error signal to inform the CPU. # |
-- # the defined number of cycles (VHDL package: max_proc_int_response_time_c) or issues an ERROR # |
-- # condition, the BUS KEEPER asserts the error signal to inform the CPU. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
51,6 → 51,7
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
61,7 → 62,8
bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system |
bus_err_i : in std_ulogic; -- transfer error from bus system |
bus_tmo_i : in std_ulogic; -- transfer timeout (external interface) |
bus_ext_i : in std_ulogic -- external bus access |
bus_ext_i : in std_ulogic; -- external bus access |
bus_xip_i : in std_ulogic -- pending XIP access |
); |
end neorv32_bus_keeper; |
|
72,13 → 74,23
constant lo_abb_c : natural := index_size_f(buskeeper_size_c); -- low address boundary bit |
|
-- Control register -- |
constant ctrl_err_type_c : natural := 0; -- r/-: error type: 0=device error, 1=access timeout |
constant ctrl_err_flag_c : natural := 31; -- r/c: bus error encountered, sticky; cleared by writing zero |
constant ctrl_err_type_c : natural := 0; -- r/-: error type LSB: 0=device error, 1=access timeout |
constant ctrl_nul_check_en_c : natural := 16; -- r/w: enable NULL address check |
constant ctrl_err_flag_c : natural := 31; -- r/c: bus error encountered, sticky; cleared by writing zero |
-- |
signal ctrl_null_check_en : std_ulogic; |
|
-- error codes -- |
constant err_device_c : std_ulogic := '0'; -- device access error |
constant err_timeout_c : std_ulogic := '1'; -- timeout error |
|
-- sticky error flags -- |
signal err_flag : std_ulogic; |
signal err_type : std_ulogic; |
|
-- NULL address check -- |
signal null_check : std_ulogic; |
|
-- access control -- |
signal acc_en : std_ulogic; -- module access enable |
signal wren : std_ulogic; -- word write enable |
109,25 → 121,38
|
-- Read/Write Access ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
rw_access: process(clk_i) |
rw_access: process(rstn_i, clk_i) |
begin |
if rising_edge(clk_i) then |
if (rstn_i = '0') then |
ack_o <= '-'; |
data_o <= (others => '-'); |
ctrl_null_check_en <= '0'; -- required |
err_flag <= '0'; -- required |
err_type <= '0'; |
elsif rising_edge(clk_i) then |
-- bus handshake -- |
ack_o <= wren or rden; |
|
-- write access -- |
if (wren = '1') then |
ctrl_null_check_en <= data_i(ctrl_nul_check_en_c); |
end if; |
|
-- read access -- |
data_o <= (others => '0'); |
if (rden = '1') then |
data_o(ctrl_err_type_c) <= err_type; |
data_o(ctrl_err_flag_c) <= err_flag; |
data_o(ctrl_err_type_c) <= err_type; |
data_o(ctrl_nul_check_en_c) <= ctrl_null_check_en; |
data_o(ctrl_err_flag_c) <= err_flag; |
end if; |
-- |
if (control.bus_err = '1') then -- sticky error flag |
err_flag <= '1'; |
err_type <= control.err_type; |
elsif ((wren or rden) = '1') then -- clear on or read or write |
err_flag <= '0'; |
err_type <= '0'; |
else |
if ((wren or rden) = '1') then -- clear on read or write access |
err_flag <= '0'; |
end if; |
end if; |
end if; |
end process rw_access; |
138,10 → 163,10
keeper_control: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
control.pending <= '0'; |
control.bus_err <= '0'; |
control.err_type <= def_rst_val_c; |
control.timeout <= (others => def_rst_val_c); |
control.pending <= '0'; -- required |
control.bus_err <= '0'; -- required |
control.err_type <= '-'; |
control.timeout <= (others => '-'); |
elsif rising_edge(clk_i) then |
-- defaults -- |
control.bus_err <= '0'; |
151,17 → 176,20
control.timeout <= std_ulogic_vector(to_unsigned(max_proc_int_response_time_c, index_size_f(max_proc_int_response_time_c)+1)); |
if (bus_rden_i = '1') or (bus_wren_i = '1') then |
control.pending <= '1'; |
if (null_check = '1') then -- invalid access to NULL address |
control.bus_err <= '1'; |
end if; |
end if; |
-- access monitor: PENDING -- |
else |
control.timeout <= std_ulogic_vector(unsigned(control.timeout) - 1); -- countdown timer |
if (bus_err_i = '1') then -- error termination by bus system |
control.err_type <= '0'; -- device error |
if (bus_err_i = '1') or (control.bus_err = '1') then -- error termination by bus system |
control.err_type <= err_device_c; -- device error |
control.bus_err <= '1'; |
control.pending <= '0'; |
elsif ((or_reduce_f(control.timeout) = '0') and (bus_ext_i = '0')) or -- internal access timeout |
elsif ((or_reduce_f(control.timeout) = '0') and (bus_ext_i = '0') and (bus_xip_i = '0')) or -- valid internal access timeout |
(bus_tmo_i = '1') then -- external access timeout |
control.err_type <= '1'; -- timeout error |
control.err_type <= err_timeout_c; -- timeout error |
control.bus_err <= '1'; |
control.pending <= '0'; |
elsif (bus_ack_i = '1') then -- normal termination by bus system |
173,6 → 201,9
end if; |
end process keeper_control; |
|
-- NULL address check -- |
null_check <= '1' when (ctrl_null_check_en = '1') and (or_reduce_f(addr_i) = '0') else '0'; |
|
-- signal bus error to CPU -- |
err_o <= control.bus_err; |
|
/neorv32_busswitch.vhd
1,12 → 1,12
-- ################################################################################################# |
-- # << NEORV32 - Bus Switch >> # |
-- # ********************************************************************************************* # |
-- # Allows to access a single peripheral bus ("p_bus") by two controller busses. Controller port # |
-- # A ("ca_bus") has priority over controller port B ("cb_bus"). # |
-- # Allows to access a single peripheral bus ("p_bus") by two controller buses. Controller port A # |
-- # ("ca_bus") has priority over controller port B ("cb_bus"). # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
49,39 → 49,39
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- controller interface a -- |
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
ca_bus_we_i : in std_ulogic; -- write enable |
ca_bus_re_i : in std_ulogic; -- read enable |
ca_bus_lock_i : in std_ulogic; -- exclusive access request |
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
ca_bus_err_o : out std_ulogic; -- bus transfer error |
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
ca_bus_we_i : in std_ulogic; -- write enable |
ca_bus_re_i : in std_ulogic; -- read enable |
ca_bus_lock_i : in std_ulogic; -- exclusive access request |
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
ca_bus_err_o : out std_ulogic; -- bus transfer error |
-- controller interface b -- |
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
cb_bus_we_i : in std_ulogic; -- write enable |
cb_bus_re_i : in std_ulogic; -- read enable |
cb_bus_lock_i : in std_ulogic; -- exclusive access request |
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
cb_bus_we_i : in std_ulogic; -- write enable |
cb_bus_re_i : in std_ulogic; -- read enable |
cb_bus_lock_i : in std_ulogic; -- exclusive access request |
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus -- |
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B |
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
p_bus_we_o : out std_ulogic; -- write enable |
p_bus_re_o : out std_ulogic; -- read enable |
p_bus_lock_o : out std_ulogic; -- exclusive access request |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
p_bus_err_i : in std_ulogic -- bus transfer error |
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B |
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
p_bus_we_o : out std_ulogic; -- write enable |
p_bus_re_o : out std_ulogic; -- read enable |
p_bus_lock_o : out std_ulogic; -- exclusive access request |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
p_bus_err_i : in std_ulogic -- bus transfer error |
); |
end neorv32_busswitch; |
|
/neorv32_cfs.vhd
1,13 → 1,16
-- ################################################################################################# |
-- # << NEORV32 - Custom Functions Subsystem (CFS) >> # |
-- # ********************************************************************************************* # |
-- # For tightly-coupled custom co-processors. Provides 32x32-bit memory-mapped registers. # |
-- # This is just an "example/illustration template". Modify this file to implement your own # |
-- # custom design logic. # |
-- # Intended for tightly-coupled, application-specific custom co-processors. This module provides # |
-- # 32x 32-bit memory-mapped interface registers, one interrupt request signal and custom IO # |
-- # conduits for processor-external or chip-external interface. # |
-- # # |
-- # NOTE: This is just an example/illustration template. Modify/replace this file to implement # |
-- # your own custom design logic. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
92,36 → 95,30
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- These assignments are required to check if the CFS is accessed at all. |
-- This logic is required to handle the CPU accesses. |
-- DO NOT MODIFY this unless you really know what you are doing. |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
addr <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned |
wren <= acc_en and wren_i; -- full 32-bit word write enable |
rden <= acc_en and rden_i; -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU |
wren <= acc_en and wren_i; -- write accesses always write a full 32-bit word |
rden <= acc_en and rden_i; -- read accesses always return a full 32-bit word |
|
-- NOTE: Do not modify the CFS base address or the CFS' occupied address space as this might cause access |
-- collisions with other modules. |
|
-- This module provides an ERROR signal to signal a faulty access operation to the CPU. |
-- It can be used to indicate an invalid access (for example to an unused CFS register address) or to signal |
-- a faulty state (like "not operational yet"). The error signal can be checked be checked by the applications |
-- "bus access fault" exception handler (provided by the system's BUSKEEPER module). |
-- This signal may only be set when the module is actually accessed! Tie to zero if not explicitly used. |
err_o <= '0'; |
|
|
-- CFS Generics --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- In its default version, the CFS provides the configuration generics. single generic: |
-- CFS_IN_SIZE configures the size (in bits) of the CFS input conduit cfs_in_i |
-- CFS_OUT_SIZE configures the size (in bits) of the CFS output conduit cfs_out_o |
-- CFS_CONFIG is a blank 32-bit generic. It is intended as a "generic conduit" to propagate custom configuration flags from the top entity down to this entiy. |
-- In it's default version the CFS provides three configuration generics: |
-- CFS_IN_SIZE - configures the size (in bits) of the CFS input conduit cfs_in_i |
-- CFS_OUT_SIZE - configures the size (in bits) of the CFS output conduit cfs_out_o |
-- CFS_CONFIG - is a blank 32-bit generic. It is intended as a "generic conduit" to propagate |
-- custom configuration flags from the top entity down to this module. |
|
|
-- CFS IOs -------------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor top entity. |
-- These are intended as "conduits" to propagate custom signals this entity <=> processor top entity. |
-- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor's top entity. |
-- These are intended as "conduits" to propagate custom signals from this module and the processor top entity. |
|
cfs_out_o <= (others => '0'); -- not used for this minimal example |
|
129,29 → 126,29
-- Reset System --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- The CFS can be reset using the global rstn_i signal. This signal should be used as asynchronous reset and is active-low. |
-- Note that rstn_i can be asserted by an external reset and also by a watchdog-cause reset. |
-- Note that rstn_i can be asserted by a processor-external reset, the on-chip debugger and also by the watchdog. |
-- |
-- Most default peripheral devices of the NEORV32 do NOT use a dedicated reset at all. Instead, these units are reset by writing ZERO |
-- to a specific "control register" located right at the beginning of the device's address space (so this register is cleared at first). |
-- The crt0 start-up code write ZERO to every single address in the processor's IO space - including the CFS. |
-- Make sure that this clearing does not cause any unintended actions in the CFS. |
-- Most default peripheral devices of the NEORV32 do NOT use a dedicated hardware reset at all. Instead, these units are |
-- reset by writing ZERO to a specific "control register" located right at the beginning of the device's address space |
-- (so this register is cleared at first). The crt0 start-up code writes ZERO to every single address in the processor's |
-- IO space - including the CFS. Make sure that this initial clearing does not cause any unintended CFS actions. |
|
|
-- Clock System --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- The processor top unit implements a clock generator providing 8 "derived clocks" |
-- The processor top unit implements a clock generator providing 8 "derived clocks". |
-- Actually, these signals should not be used as direct clock signals, but as *clock enable* signals. |
-- clkgen_i is always synchronous to the main system clock (clk_i). |
-- |
-- The following clock divider rates are available: |
-- clkgen_i(clk_div2_c) -> MAIN_CLK/2 |
-- clkgen_i(clk_div4_c) -> MAIN_CLK/4 |
-- clkgen_i(clk_div8_c) -> MAIN_CLK/8 |
-- clkgen_i(clk_div64_c) -> MAIN_CLK/64 |
-- clkgen_i(clk_div128_c) -> MAIN_CLK/128 |
-- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024 |
-- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048 |
-- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096 |
-- The following clock dividers are available: |
-- + clkgen_i(clk_div2_c) -> MAIN_CLK/2 |
-- + clkgen_i(clk_div4_c) -> MAIN_CLK/4 |
-- + clkgen_i(clk_div8_c) -> MAIN_CLK/8 |
-- + clkgen_i(clk_div64_c) -> MAIN_CLK/64 |
-- + clkgen_i(clk_div128_c) -> MAIN_CLK/128 |
-- + clkgen_i(clk_div1024_c) -> MAIN_CLK/1024 |
-- + clkgen_i(clk_div2048_c) -> MAIN_CLK/2048 |
-- + clkgen_i(clk_div4096_c) -> MAIN_CLK/4096 |
-- |
-- For instance, if you want to drive a clock process at MAIN_CLK/8 clock speed you can use the following construct: |
-- |
163,10 → 160,11
-- end if; |
-- end if; |
-- |
-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the SPI) requires the clocks generated by the |
-- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high. |
-- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated. |
-- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption. |
-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the UART) requires the clocks |
-- generated by the clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high. |
-- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might |
-- still keep the generator activated. Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to |
-- reduce dynamic power consumption. |
|
clkgen_en_o <= '0'; -- not used for this minimal example |
|
173,11 → 171,10
|
-- Interrupt ------------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
-- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1. |
-- The interrupt is triggered by a one-shot rising edge. After triggering, the interrupt appears as "pending" in the CPU's mie register |
-- ready to trigger execution of the according interrupt handler. The interrupt request signal should be triggered |
-- whenever an interrupt condition is fulfilled. It is the task of the application to programmer to enable/clear the CFS interrupt |
-- using the CPU's mie and mip registers when reuqired. |
-- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1 (FIRQ1). |
-- The interrupt is triggered by a one-cycle high-level. After triggering, the interrupt appears as "pending" in the CPU's |
-- mip CSR ready to trigger execution of the according interrupt handler. It is the task of the application to programmer |
-- to enable/clear the CFS interrupt using the CPU's mie and mip registers when required. |
|
irq_o <= '0'; -- not used for this minimal example |
|
184,50 → 181,55
|
-- Read/Write Access ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO |
-- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte) |
-- will trigger a store bus access fault exception. |
-- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO modules |
-- of the NEORV32 can only be written in full word mode (32-bit). Any other write accesses (half-word or byte) will raise |
-- a store bus access fault exception. |
-- |
-- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide |
-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register> |
-- for issuing commands and a <status register> for status information. |
-- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide a |
-- <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a |
-- <command register> for issuing commands and a <status register> for status information. |
-- |
-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later |
-- if the module needs additional time; the maximum latency until an unacknowledged access will trigger a bus exception is defined via the package's |
-- global "bus_timeout_c" constant). If no ACK is generated at all, the bus access will time out and cause a bus access fault exception. |
-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o |
-- signal (or even later if the module needs additional time; exceeding the maximum ACK latency will raise a bus exception). |
-- If no ACK is generated at all, the bus access will time out and cause a bus access fault exception. |
-- |
-- This module also provides an optional ERROR signal to indicate a faulty access operation (for example when accessing an |
-- unused, read-only or "locked" CFS register address). This signal may only be set when the module is actually accessed |
-- and is asserted INSTEAD of the ACK signal. Setting the ERR signal will raise a bus access exception that can be handled |
-- by the application software. |
|
-- Host access: Read and write access to the interface registers + bus transfer acknowledge. |
-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not |
-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged. |
err_o <= '0'; -- Tie to zero if not explicitly used. |
|
-- Host access: Read and write access to the interface registers + bus transfer acknowledge. This example only implements |
-- four physical r/w register (the four lowest CFS registers). The remaining addresses of the CFS are not associated with |
-- any physical registers - any access to those is simply ignored but still acknowledged. |
|
host_access: process(clk_i) |
begin |
if rising_edge(clk_i) then -- synchronous interface for reads and writes |
if rising_edge(clk_i) then -- synchronous interface for read and write accesses |
-- transfer/access acknowledge -- |
ack_o <= rden or wren; -- default: required for the CPU to check the CFS is answering a bus read OR write request; all r/w accesses (to any cfs_reg) will succeed |
-- ack_o <= rden; -- use this construct if your CFS is read-only |
-- ack_o <= wren; -- use this construct if your CFS is write-only |
-- ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...) |
ack_o <= rden or wren; -- default: required for the CPU to check the CFS is answering a bus read OR write request; |
-- all r/w accesses (to any cfs_reg) will succeed |
|
-- write access -- |
if (wren = '1') then -- word-wide write-access only! |
if (wren = '1') then |
if (addr = cfs_reg0_addr_c) then -- make sure to use the internal "addr" signal for the read/write interface |
cfs_reg_wr(0) <= data_i; -- for example: control register |
cfs_reg_wr(0) <= data_i; -- physical register, for example: control register |
end if; |
if (addr = cfs_reg1_addr_c) then |
cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo |
cfs_reg_wr(1) <= data_i; -- physical register, for example: data in/out fifo |
end if; |
if (addr = cfs_reg2_addr_c) then |
cfs_reg_wr(2) <= data_i; -- for example: command fifo |
cfs_reg_wr(2) <= data_i; -- physical register, for example: command fifo |
end if; |
if (addr = cfs_reg3_addr_c) then |
cfs_reg_wr(3) <= data_i; -- for example: status register |
cfs_reg_wr(3) <= data_i; -- physical register, for example: status register |
end if; |
end if; |
|
-- read access -- |
data_o <= (others => '0'); -- the output has to be zero if there is no actual read access |
if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU |
if (rden = '1') then -- the read access is always a full 32-bit word wide |
case addr is -- make sure to use the internal 'addr' signal for the read/write interface |
when cfs_reg0_addr_c => data_o <= cfs_reg_rd(0); |
when cfs_reg1_addr_c => data_o <= cfs_reg_rd(1); |
245,13 → 247,13
-- This is where the actual functionality can be implemented. |
-- In this example we are just implementing four r/w registers that invert any value written to them. |
|
cfs_core: process(cfs_reg_wr) |
cfs_core_logic: process(cfs_reg_wr) |
begin |
cfs_reg_rd(0) <= not cfs_reg_wr(0); -- just invert the written value |
cfs_reg_rd(0) <= not cfs_reg_wr(0); |
cfs_reg_rd(1) <= not cfs_reg_wr(1); |
cfs_reg_rd(2) <= not cfs_reg_wr(2); |
cfs_reg_rd(3) <= not cfs_reg_wr(3); |
end process cfs_core; |
end process cfs_core_logic; |
|
|
end neorv32_cfs_rtl; |
/neorv32_cpu.vhd
21,7 → 21,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
182,7 → 182,7
cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") & |
cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") & |
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") & |
cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_Debug", "") & |
cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_DEBUG", "") & |
"" |
severity note; |
|
190,7 → 190,7
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- hardware reset notifier -- |
assert not (dedicated_reset_c = false) report "NEORV32 CPU CONFIG NOTE: Implementing NO dedicated hardware reset for uncritical registers (default, might reduce area). Set package constant <dedicated_reset_c> = TRUE to configure a DEFINED reset value for all CPU registers." severity note; |
assert not (dedicated_reset_c = false) report "NEORV32 CPU CONFIG NOTE: Implementing NO dedicated hardware reset for uncritical registers (default)." severity note; |
assert not (dedicated_reset_c = true) report "NEORV32 CPU CONFIG NOTE: Implementing defined hardware reset for uncritical registers (non-default, reset-to-zero, might increase area)." severity note; |
assert not ((def_rst_val_c /= '-') and (def_rst_val_c /= '0')) report "NEORV32 CPU CONFIG ERROR! Invalid configuration of package <def_rst_val_c> constant (has to be '-' or '0')." severity error; |
|
329,14 → 329,14
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
ctrl_i => ctrl, -- main control bus |
clk_i => clk_i, -- global clock, rising edge |
ctrl_i => ctrl, -- main control bus |
-- data input -- |
mem_i => mem_rdata, -- memory read data |
alu_i => alu_res, -- ALU result |
mem_i => mem_rdata, -- memory read data |
alu_i => alu_res, -- ALU result |
-- data output -- |
rs1_o => rs1, -- operand 1 |
rs2_o => rs2 -- operand 2 |
rs1_o => rs1, -- operand 1 |
rs2_o => rs2 -- operand 2 |
); |
|
|
355,23 → 355,23
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
-- data input -- |
rs1_i => rs1, -- rf source 1 |
rs2_i => rs2, -- rf source 2 |
pc_i => curr_pc, -- current PC |
pc2_i => next_pc, -- next PC |
imm_i => imm, -- immediate |
csr_i => csr_rdata, -- CSR read data |
rs1_i => rs1, -- rf source 1 |
rs2_i => rs2, -- rf source 2 |
pc_i => curr_pc, -- current PC |
pc2_i => next_pc, -- next PC |
imm_i => imm, -- immediate |
csr_i => csr_rdata, -- CSR read data |
-- data output -- |
cmp_o => comparator, -- comparator status |
res_o => alu_res, -- ALU result |
add_o => alu_add, -- address computation result |
fpu_flags_o => fpu_flags, -- FPU exception flags |
cmp_o => comparator, -- comparator status |
res_o => alu_res, -- ALU result |
add_o => alu_add, -- address computation result |
fpu_flags_o => fpu_flags, -- FPU exception flags |
-- status -- |
idone_o => alu_idone -- iterative processing units done? |
idone_o => alu_idone -- iterative processing units done? |
); |
|
|
387,53 → 387,53
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i => fetch_pc, -- PC for instruction fetch |
instr_o => instr, -- instruction |
i_wait_o => bus_i_wait, -- wait for fetch to complete |
fetch_pc_i => fetch_pc, -- PC for instruction fetch |
instr_o => instr, -- instruction |
i_wait_o => bus_i_wait, -- wait for fetch to complete |
-- |
ma_instr_o => ma_instr, -- misaligned instruction address |
be_instr_o => be_instr, -- bus error on instruction access |
ma_instr_o => ma_instr, -- misaligned instruction address |
be_instr_o => be_instr, -- bus error on instruction access |
-- cpu data access interface -- |
addr_i => alu_add, -- ALU.add result -> access address |
wdata_i => rs2, -- write data |
rdata_o => mem_rdata, -- read data |
mar_o => mar, -- current memory address register |
d_wait_o => bus_d_wait, -- wait for access to complete |
addr_i => alu_add, -- ALU.add result -> access address |
wdata_i => rs2, -- write data |
rdata_o => mem_rdata, -- read data |
mar_o => mar, -- current memory address register |
d_wait_o => bus_d_wait, -- wait for access to complete |
-- |
excl_state_o => excl_state, -- atomic/exclusive access status |
ma_load_o => ma_load, -- misaligned load data address |
ma_store_o => ma_store, -- misaligned store data address |
be_load_o => be_load, -- bus error on load data access |
be_store_o => be_store, -- bus error on store data access |
excl_state_o => excl_state, -- atomic/exclusive access status |
ma_load_o => ma_load, -- misaligned load data address |
ma_store_o => ma_store, -- misaligned store data address |
be_load_o => be_load, -- bus error on load data access |
be_store_o => be_store, -- bus error on store data access |
-- physical memory protection -- |
pmp_addr_i => pmp_addr, -- addresses |
pmp_ctrl_i => pmp_ctrl, -- configurations |
pmp_addr_i => pmp_addr, -- addresses |
pmp_ctrl_i => pmp_ctrl, -- configurations |
-- instruction bus -- |
i_bus_addr_o => i_bus_addr_o, -- bus access address |
i_bus_rdata_i => i_bus_rdata_i, -- bus read data |
i_bus_wdata_o => i_bus_wdata_o, -- bus write data |
i_bus_ben_o => i_bus_ben_o, -- byte enable |
i_bus_we_o => i_bus_we_o, -- write enable |
i_bus_re_o => i_bus_re_o, -- read enable |
i_bus_lock_o => i_bus_lock_o, -- exclusive access request |
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge |
i_bus_err_i => i_bus_err_i, -- bus transfer error |
i_bus_fence_o => i_bus_fence_o, -- fence operation |
i_bus_addr_o => i_bus_addr_o, -- bus access address |
i_bus_rdata_i => i_bus_rdata_i, -- bus read data |
i_bus_wdata_o => i_bus_wdata_o, -- bus write data |
i_bus_ben_o => i_bus_ben_o, -- byte enable |
i_bus_we_o => i_bus_we_o, -- write enable |
i_bus_re_o => i_bus_re_o, -- read enable |
i_bus_lock_o => i_bus_lock_o, -- exclusive access request |
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge |
i_bus_err_i => i_bus_err_i, -- bus transfer error |
i_bus_fence_o => i_bus_fence_o, -- fence operation |
-- data bus -- |
d_bus_addr_o => d_bus_addr_o, -- bus access address |
d_bus_rdata_i => d_bus_rdata_i, -- bus read data |
d_bus_wdata_o => d_bus_wdata_o, -- bus write data |
d_bus_ben_o => d_bus_ben_o, -- byte enable |
d_bus_we_o => d_bus_we_o, -- write enable |
d_bus_re_o => d_bus_re_o, -- read enable |
d_bus_lock_o => d_bus_lock_o, -- exclusive access request |
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge |
d_bus_err_i => d_bus_err_i, -- bus transfer error |
d_bus_fence_o => d_bus_fence_o -- fence operation |
d_bus_addr_o => d_bus_addr_o, -- bus access address |
d_bus_rdata_i => d_bus_rdata_i, -- bus read data |
d_bus_wdata_o => d_bus_wdata_o, -- bus write data |
d_bus_ben_o => d_bus_ben_o, -- byte enable |
d_bus_we_o => d_bus_we_o, -- write enable |
d_bus_re_o => d_bus_re_o, -- read enable |
d_bus_lock_o => d_bus_lock_o, -- exclusive access request |
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge |
d_bus_err_i => d_bus_err_i, -- bus transfer error |
d_bus_fence_o => d_bus_fence_o -- fence operation |
); |
|
-- current privilege level -- |
/neorv32_cpu_alu.vhd
5,7 → 5,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
240,16 → 240,16
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl_i, -- main control bus |
start_i => cp_start(0), -- trigger operation |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl_i, -- main control bus |
start_i => cp_start(0), -- trigger operation |
-- data input -- |
rs1_i => rs1_i, -- rf source 1 |
rs1_i => rs1_i, -- rf source 1 |
shamt_i => opb(index_size_f(data_width_c)-1 downto 0), -- shift amount |
-- result and status -- |
res_o => cp_result(0), -- operation result |
valid_o => cp_valid(0) -- data output valid |
res_o => cp_result(0), -- operation result |
valid_o => cp_valid(0) -- data output valid |
); |
|
|
264,16 → 264,16
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl_i, -- main control bus |
start_i => cp_start(1), -- trigger operation |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl_i, -- main control bus |
start_i => cp_start(1), -- trigger operation |
-- data input -- |
rs1_i => rs1_i, -- rf source 1 |
rs2_i => rs2_i, -- rf source 2 |
rs1_i => rs1_i, -- rf source 1 |
rs2_i => rs2_i, -- rf source 2 |
-- result and status -- |
res_o => cp_result(1), -- operation result |
valid_o => cp_valid(1) -- data output valid |
res_o => cp_result(1), -- operation result |
valid_o => cp_valid(1) -- data output valid |
); |
end generate; |
|
/neorv32_cpu_bus.vhd
5,7 → 5,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
51,53 → 51,53
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
i_wait_o : out std_ulogic; -- wait for fetch to complete |
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
i_wait_o : out std_ulogic; -- wait for fetch to complete |
-- |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
-- cpu data access interface -- |
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
d_wait_o : out std_ulogic; -- wait for access to complete |
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
d_wait_o : out std_ulogic; -- wait for access to complete |
-- |
excl_state_o : out std_ulogic; -- atomic/exclusive access status |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
excl_state_o : out std_ulogic; -- atomic/exclusive access status |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
-- physical memory protection -- |
pmp_addr_i : in pmp_addr_if_t; -- addresses |
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs |
pmp_addr_i : in pmp_addr_if_t; -- addresses |
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs |
-- instruction bus -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_lock_o : out std_ulogic; -- exclusive access request |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- fence operation |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_lock_o : out std_ulogic; -- exclusive access request |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- fence operation |
-- data bus -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_lock_o : out std_ulogic; -- exclusive access request |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic -- fence operation |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_lock_o : out std_ulogic; -- exclusive access request |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic -- fence operation |
); |
end neorv32_cpu_bus; |
|
321,7 → 321,7
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
d_arbiter.err_bus <= (d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and |
(not ctrl_i(ctrl_bus_derr_ack_c)); |
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort |
if ((d_bus_ack_i = '1') and (d_bus_err_i = '0')) or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
end if; |
410,7 → 410,7
else -- in progres |
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
i_arbiter.err_bus <= (i_arbiter.err_bus or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort |
if ((i_bus_ack_i = '1') and (i_bus_err_i = '0')) or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort |
i_arbiter.rd_req <= '0'; |
end if; |
end if; |
/neorv32_cpu_control.vhd
9,7 → 9,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
395,7 → 395,7
fetch_engine.state <= fetch_engine.state_nxt; |
fetch_engine.state_prev <= fetch_engine.state; |
fetch_engine.restart <= fetch_engine.restart_nxt or fetch_engine.reset; |
if (fetch_engine.restart = '1') then |
if (fetch_engine.restart = '1') and (fetch_engine.state = IFETCH_REQUEST) then -- only update PC if no fetch request is pending |
fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC |
else |
fetch_engine.pc <= fetch_engine.pc_nxt; |
421,7 → 421,7
-- instruction prefetch buffer defaults -- |
ipb.we <= '0'; |
ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word |
ipb.clear <= fetch_engine.restart; |
ipb.clear <= fetch_engine.restart; -- clear instruction buffer while being reset |
|
-- state machine -- |
case fetch_engine.state is |
438,10 → 438,9
-- ------------------------------------------------------------ |
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors |
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response |
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4); |
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset |
fetch_engine.restart_nxt <= '0'; |
fetch_engine.state_nxt <= IFETCH_REQUEST; |
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4); |
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset |
fetch_engine.state_nxt <= IFETCH_REQUEST; |
end if; |
|
when others => -- undefined |
725,7 → 724,7
execute_engine.i_reg_last <= execute_engine.i_reg; |
end if; |
|
-- next PC -- |
-- next PC logic -- |
case execute_engine.state is |
when TRAP_ENTER => -- ENTERING trap environment |
if (CPU_EXTENSION_RISCV_DEBUG = false) then -- normal trapping |
2405,8 → 2404,8
|
-- counter event trigger - RISC-V-specific -- |
cnt_event(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle |
cnt_event(hpmcnt_event_never_c) <= '0'; -- undefined (never) |
cnt_event(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- retired instruction |
cnt_event(hpmcnt_event_never_c) <= '0'; -- "never" |
cnt_event(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- (any) retired instruction |
|
-- counter event trigger - custom / NEORV32-specific -- |
cnt_event(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction |
/neorv32_gpio.vhd
1,11 → 1,12
-- ################################################################################################# |
-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> # |
-- # ********************************************************************************************* # |
-- # 64-bit general purpose parallel input & output port unit. # |
-- # 64-bit general purpose parallel input & output port unit. Input/outputs are split into two # |
-- # 32-bit memory-mapped registers each. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
51,6 → 52,7
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
-- parallel io -- |
gpio_o : out std_ulogic_vector(63 downto 0); |
gpio_i : in std_ulogic_vector(63 downto 0) |
70,8 → 72,8
signal rden : std_ulogic; -- read enable |
|
-- accessible regs -- |
signal din_lo, din_hi : std_ulogic_vector(31 downto 0); -- r/- |
signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0); -- r/w |
signal din_hi, din_lo : std_ulogic_vector(31 downto 0); -- r/-: parallel input hi/lo |
signal dout_hi, dout_lo : std_ulogic_vector(31 downto 0); -- r/w: parallel output hi/lo |
|
begin |
|
89,7 → 91,8
begin |
if rising_edge(clk_i) then |
-- bus handshake -- |
ack_o <= wren or rden; |
ack_o <= (wren and addr(3)) or rden; |
err_o <= wren and (not addr(3)); -- INPUT registers are read only! |
|
-- write access -- |
if (wren = '1') then |
101,7 → 104,7
end if; |
end if; |
|
-- input buffer -- |
-- input buffer (prevent metastability) -- |
din_lo <= gpio_i(31 downto 00); |
din_hi <= gpio_i(63 downto 32); |
|
/neorv32_icache.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
50,27 → 50,27
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clear_i : in std_ulogic; -- cache clear |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clear_i : in std_ulogic; -- cache clear |
-- host controller interface -- |
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
host_we_i : in std_ulogic; -- write enable |
host_re_i : in std_ulogic; -- read enable |
host_ack_o : out std_ulogic; -- bus transfer acknowledge |
host_err_o : out std_ulogic; -- bus transfer error |
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
host_we_i : in std_ulogic; -- write enable |
host_re_i : in std_ulogic; -- read enable |
host_ack_o : out std_ulogic; -- bus transfer acknowledge |
host_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
); |
end neorv32_icache; |
|
112,12 → 112,9
-- cache interface -- |
type cache_if_t is record |
clear : std_ulogic; -- cache clear |
-- |
host_addr : std_ulogic_vector(31 downto 0); -- cpu access address |
host_rdata : std_ulogic_vector(31 downto 0); -- cpu read data |
-- |
hit : std_ulogic; -- hit access |
-- |
ctrl_en : std_ulogic; -- control access enable |
ctrl_addr : std_ulogic_vector(31 downto 0); -- control access address |
ctrl_we : std_ulogic; -- control write enable |
136,10 → 133,8
state_nxt : ctrl_engine_state_t; -- next state |
addr_reg : std_ulogic_vector(31 downto 0); -- address register for block download |
addr_reg_nxt : std_ulogic_vector(31 downto 0); |
-- |
re_buf : std_ulogic; -- read request buffer |
re_buf_nxt : std_ulogic; |
-- |
clear_buf : std_ulogic; -- clear request buffer |
clear_buf_nxt : std_ulogic; |
end record; |
160,26 → 155,19
|
-- Control Engine FSM Sync ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- registers that REQUIRE a specific reset state -- |
ctrl_engine_fsm_sync_rst: process(rstn_i, clk_i) |
ctrl_engine_fsm_sync: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
ctrl.state <= S_CACHE_CLEAR; |
ctrl.re_buf <= '0'; |
ctrl.clear_buf <= '0'; |
ctrl.addr_reg <= (others => '-'); |
elsif rising_edge(clk_i) then |
ctrl.state <= ctrl.state_nxt; |
ctrl.re_buf <= ctrl.re_buf_nxt; |
ctrl.clear_buf <= ctrl.clear_buf_nxt; |
ctrl.addr_reg <= ctrl.addr_reg_nxt; |
end if; |
end process ctrl_engine_fsm_sync_rst; |
|
-- registers that do not require a specific reset state -- |
ctrl_engine_fsm_sync: process(clk_i) |
begin |
if rising_edge(clk_i) then |
ctrl.addr_reg <= ctrl.addr_reg_nxt; |
end if; |
end process ctrl_engine_fsm_sync; |
|
|
302,28 → 290,28
-- ------------------------------------------------------------------------------------------- |
neorv32_icache_memory_inst: neorv32_icache_memory |
generic map ( |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 |
ICACHE_NUM_SETS => ICACHE_NUM_SETS -- associativity; 0=direct-mapped, 1=2-way set-associative |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 |
ICACHE_NUM_SETS => ICACHE_NUM_SETS -- associativity; 0=direct-mapped, 1=2-way set-associative |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
invalidate_i => cache.clear, -- invalidate whole cache |
-- host cache access (read-only) -- |
host_addr_i => cache.host_addr, -- access address |
host_re_i => host_re_i, -- read enable |
host_rdata_o => cache.host_rdata, -- read data |
clk_i => clk_i, -- global clock, rising edge |
invalidate_i => cache.clear, -- invalidate whole cache |
-- host cache access (read-only) -- |
host_addr_i => cache.host_addr, -- access address |
host_re_i => host_re_i, -- read enable |
host_rdata_o => cache.host_rdata, -- read data |
-- access status (1 cycle delay to access) -- |
hit_o => cache.hit, -- hit access |
hit_o => cache.hit, -- hit access |
-- ctrl cache access (write-only) -- |
ctrl_en_i => cache.ctrl_en, -- control interface enable |
ctrl_addr_i => cache.ctrl_addr, -- access address |
ctrl_we_i => cache.ctrl_we, -- write enable (full-word) |
ctrl_wdata_i => cache.ctrl_wdata, -- write data |
ctrl_tag_we_i => cache.ctrl_tag_we, -- write tag to selected block |
ctrl_valid_i => cache.ctrl_valid_we, -- make selected block valid |
ctrl_invalid_i => cache.ctrl_invalid_we -- make selected block invalid |
ctrl_en_i => cache.ctrl_en, -- control interface enable |
ctrl_addr_i => cache.ctrl_addr, -- access address |
ctrl_we_i => cache.ctrl_we, -- write enable (full-word) |
ctrl_wdata_i => cache.ctrl_wdata, -- write data |
ctrl_tag_we_i => cache.ctrl_tag_we, -- write tag to selected block |
ctrl_valid_i => cache.ctrl_valid_we, -- make selected block valid |
ctrl_invalid_i => cache.ctrl_invalid_we -- make selected block invalid |
); |
|
end neorv32_icache_rtl; |
345,7 → 333,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
389,22 → 377,22
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
invalidate_i : in std_ulogic; -- invalidate whole cache |
clk_i : in std_ulogic; -- global clock, rising edge |
invalidate_i : in std_ulogic; -- invalidate whole cache |
-- host cache access (read-only) -- |
host_addr_i : in std_ulogic_vector(31 downto 0); -- access address |
host_re_i : in std_ulogic; -- read enable |
host_rdata_o : out std_ulogic_vector(31 downto 0); -- read data |
host_addr_i : in std_ulogic_vector(31 downto 0); -- access address |
host_re_i : in std_ulogic; -- read enable |
host_rdata_o : out std_ulogic_vector(31 downto 0); -- read data |
-- access status (1 cycle delay to access) -- |
hit_o : out std_ulogic; -- hit access |
hit_o : out std_ulogic; -- hit access |
-- ctrl cache access (write-only) -- |
ctrl_en_i : in std_ulogic; -- control interface enable |
ctrl_addr_i : in std_ulogic_vector(31 downto 0); -- access address |
ctrl_we_i : in std_ulogic; -- write enable (full-word) |
ctrl_wdata_i : in std_ulogic_vector(31 downto 0); -- write data |
ctrl_tag_we_i : in std_ulogic; -- write tag to selected block |
ctrl_valid_i : in std_ulogic; -- make selected block valid |
ctrl_invalid_i : in std_ulogic -- make selected block invalid |
ctrl_en_i : in std_ulogic; -- control interface enable |
ctrl_addr_i : in std_ulogic_vector(31 downto 0); -- access address |
ctrl_we_i : in std_ulogic; -- write enable (full-word) |
ctrl_wdata_i : in std_ulogic_vector(31 downto 0); -- write data |
ctrl_tag_we_i : in std_ulogic; -- write tag to selected block |
ctrl_valid_i : in std_ulogic; -- make selected block valid |
ctrl_invalid_i : in std_ulogic -- make selected block invalid |
); |
end neorv32_icache_memory; |
|
413,7 → 401,7
-- cache layout -- |
constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words |
constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS); |
constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset |
constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additional bits for byte offset |
constant cache_entries_c : natural := ICACHE_NUM_BLOCKS * (ICACHE_BLOCK_SIZE/4); -- number of 32-bit entries (per set) |
|
-- status flag memory -- |
/neorv32_package.vhd
3,7 → 3,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
64,7 → 64,7
-- Architecture Constants (do not modify!) ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- native data path width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060500"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060600"; -- no touchy! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
|
-- Check if we're inside the Matrix ------------------------------------------------------- |
122,7 → 122,7
|
-- Internal (auto-generated) Configurations ----------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-'); |
constant def_rst_val_c : std_ulogic; -- Use a deferred constant, prevents compile error with Questa, see IEEE 1076-2008 14.4.2.1 |
|
-- Processor-Internal Address Space Layout ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
149,7 → 149,7
constant dm_sreg_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff980"; |
|
-- IO: Peripheral Devices ("IO") Area -- |
-- Control register(s) (including the device-enable) should be located at the base address of each device |
-- Control register(s) (including the device-enable flag) should be located at the base address of each device |
constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; |
constant io_size_c : natural := 512; -- IO address space size in bytes, fixed! |
|
217,9 → 217,17
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address |
--constant reserved_size_c : natural := 16*4; -- module's address space size in bytes |
|
-- Execute In Place Module (XIP) -- |
constant xip_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40"; -- base address |
constant xip_size_c : natural := 4*4; -- module's address space size in bytes |
constant xip_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40"; |
constant xip_map_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff44"; |
constant xip_data_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff48"; |
constant xip_data_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff4C"; |
|
-- reserved -- |
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40"; -- base address |
--constant reserved_size_c : natural := 8*4; -- module's address space size in bytes |
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff50"; -- base address |
--constant reserved_size_c : natural := 4*4; -- module's address space size in bytes |
|
-- General Purpose Timer (GPTMR) -- |
constant gptmr_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60"; -- base address |
949,7 → 957,7
-- Internal Data memory (DMEM) -- |
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
-- Internal Cache memory (iCACHE) -- |
-- Internal Instruction Cache (iCACHE) -- |
ICACHE_EN : boolean := false; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
989,7 → 997,8
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits |
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two |
IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean := false -- implement execute in place module (XIP)? |
); |
port ( |
-- Global control -- |
1016,6 → 1025,11
-- Advanced memory control signals (available if MEM_EXT_EN = true) -- |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- |
xip_csn_o : out std_ulogic; -- chip-select, low-active |
xip_clk_o : out std_ulogic; -- serial clock |
xip_sdi_i : in std_ulogic := 'L'; -- device data input |
xip_sdo_o : out std_ulogic; -- controller data output |
-- TX stream interfaces (available if SLINK_NUM_TX > 0) -- |
slink_tx_dat_o : out sdata_8x32_t; -- output data |
slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output |
1046,7 → 1060,7
twi_sda_io : inout std_logic := 'U'; -- twi serial data line |
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line |
-- PWM (available if IO_PWM_NUM_CH > 0) -- |
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels |
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels |
-- Custom Functions Subsystem IO -- |
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit |
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit |
1056,7 → 1070,7
mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false) |
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) |
-- External platform interrupts (available if XIRQ_NUM_CH > 0) -- |
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels |
xirq_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels |
-- CPU Interrupts -- |
mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt |
1146,7 → 1160,7
component neorv32_cpu_control |
generic ( |
-- General -- |
HW_THREAD_ID : natural; -- hardware thread id (32-bit) |
HW_THREAD_ID : natural; -- hardware thread id (32-bit) |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address |
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address |
-- RISC-V CPU Extensions -- |
1372,53 → 1386,53
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
i_wait_o : out std_ulogic; -- wait for fetch to complete |
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
i_wait_o : out std_ulogic; -- wait for fetch to complete |
-- |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
-- cpu data access interface -- |
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
d_wait_o : out std_ulogic; -- wait for access to complete |
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
d_wait_o : out std_ulogic; -- wait for access to complete |
-- |
excl_state_o : out std_ulogic; -- atomic/exclusive access status |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
excl_state_o : out std_ulogic; -- atomic/exclusive access status |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
-- physical memory protection -- |
pmp_addr_i : in pmp_addr_if_t; -- addresses |
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs |
pmp_addr_i : in pmp_addr_if_t; -- addresses |
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs |
-- instruction bus -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_lock_o : out std_ulogic; -- exclusive access request |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- fence operation |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_lock_o : out std_ulogic; -- exclusive access request |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- fence operation |
-- data bus -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_lock_o : out std_ulogic; -- exclusive access request |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic -- fence operation |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_lock_o : out std_ulogic; -- exclusive access request |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic -- fence operation |
); |
end component; |
|
1432,6 → 1446,7
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
1442,7 → 1457,8
bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system |
bus_err_i : in std_ulogic; -- transfer error from bus system |
bus_tmo_i : in std_ulogic; -- transfer timeout (external interface) |
bus_ext_i : in std_ulogic -- external bus access |
bus_ext_i : in std_ulogic; -- external bus access |
bus_xip_i : in std_ulogic -- pending XIP access |
); |
end component; |
|
1456,27 → 1472,27
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clear_i : in std_ulogic; -- cache clear |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clear_i : in std_ulogic; -- cache clear |
-- host controller interface -- |
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
host_we_i : in std_ulogic; -- write enable |
host_re_i : in std_ulogic; -- read enable |
host_ack_o : out std_ulogic; -- bus transfer acknowledge |
host_err_o : out std_ulogic; -- bus transfer error |
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
host_we_i : in std_ulogic; -- write enable |
host_re_i : in std_ulogic; -- read enable |
host_ack_o : out std_ulogic; -- bus transfer acknowledge |
host_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
); |
end component; |
|
1489,43 → 1505,43
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- controller interface a -- |
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
ca_bus_we_i : in std_ulogic; -- write enable |
ca_bus_re_i : in std_ulogic; -- read enable |
ca_bus_lock_i : in std_ulogic; -- exclusive access request |
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
ca_bus_err_o : out std_ulogic; -- bus transfer error |
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
ca_bus_we_i : in std_ulogic; -- write enable |
ca_bus_re_i : in std_ulogic; -- read enable |
ca_bus_lock_i : in std_ulogic; -- exclusive access request |
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
ca_bus_err_o : out std_ulogic; -- bus transfer error |
-- controller interface b -- |
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
cb_bus_we_i : in std_ulogic; -- write enable |
cb_bus_re_i : in std_ulogic; -- read enable |
cb_bus_lock_i : in std_ulogic; -- exclusive access request |
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
cb_bus_we_i : in std_ulogic; -- write enable |
cb_bus_re_i : in std_ulogic; -- read enable |
cb_bus_lock_i : in std_ulogic; -- exclusive access request |
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus -- |
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B |
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
p_bus_we_o : out std_ulogic; -- write enable |
p_bus_re_o : out std_ulogic; -- read enable |
p_bus_lock_o : out std_ulogic; -- exclusive access request |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
p_bus_err_i : in std_ulogic -- bus transfer error |
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B |
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
p_bus_we_o : out std_ulogic; -- write enable |
p_bus_re_o : out std_ulogic; -- read enable |
p_bus_lock_o : out std_ulogic; -- exclusive access request |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
p_bus_err_i : in std_ulogic -- bus transfer error |
); |
end component; |
|
-- Component: CPU Compressed Instructions Decompressor ------------------------------------ |
-- Component: CPU Compressed Instructions De-Compressor ----------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu_decompressor |
port ( |
1622,6 → 1638,7
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
-- parallel io -- |
gpio_o : out std_ulogic_vector(63 downto 0); |
gpio_i : in std_ulogic_vector(63 downto 0) |
1754,7 → 1771,7
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0); |
-- pwm output channels -- |
pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0) |
pwm_o : out std_ulogic_vector(59 downto 0) |
); |
end component; |
|
1791,34 → 1808,37
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
-- host access -- |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
lock_i : in std_ulogic; -- exclusive access request |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
tmo_o : out std_ulogic; -- transfer timeout |
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level |
ext_o : out std_ulogic; -- active external access |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
lock_i : in std_ulogic; -- exclusive access request |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
tmo_o : out std_ulogic; -- transfer timeout |
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level |
ext_o : out std_ulogic; -- active external access |
-- xip configuration -- |
xip_en_i : in std_ulogic; -- XIP module enabled |
xip_page_i : in std_ulogic_vector(03 downto 0); -- XIP memory page |
-- wishbone interface -- |
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_lock_o : out std_ulogic; -- exclusive access request |
wb_ack_i : in std_ulogic; -- transfer acknowledge |
wb_err_i : in std_ulogic -- transfer error |
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_lock_o : out std_ulogic; -- exclusive access request |
wb_ack_i : in std_ulogic; -- transfer acknowledge |
wb_err_i : in std_ulogic -- transfer error |
); |
end component; |
|
1927,7 → 1947,7
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
-- external interrupt lines -- |
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); |
xirq_i : in std_ulogic_vector(31 downto 0); |
-- CPU interrupt -- |
cpu_irq_o : out std_ulogic |
); |
1953,6 → 1973,40
); |
end component; |
|
-- Component: Execute In Place Module (XIP) ----------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_xip |
port ( |
-- globals -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
-- host access: control register access port -- |
ct_addr_i : in std_ulogic_vector(31 downto 0); -- address |
ct_rden_i : in std_ulogic; -- read enable |
ct_wren_i : in std_ulogic; -- write enable |
ct_data_i : in std_ulogic_vector(31 downto 0); -- data in |
ct_data_o : out std_ulogic_vector(31 downto 0); -- data out |
ct_ack_o : out std_ulogic; -- transfer acknowledge |
-- host access: instruction fetch access port (read-only) -- |
if_addr_i : in std_ulogic_vector(31 downto 0); -- address |
if_rden_i : in std_ulogic; -- read enable |
if_data_o : out std_ulogic_vector(31 downto 0); -- data out |
if_ack_o : out std_ulogic; -- transfer acknowledge |
-- status -- |
xip_en_o : out std_ulogic; -- XIP enable |
xip_acc_o : out std_ulogic; -- pending XIP access |
xip_page_o : out std_ulogic_vector(03 downto 0); -- XIP page |
-- clock generator -- |
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0); |
-- SPI device interface -- |
spi_csn_o : out std_ulogic; -- chip-select, low-active |
spi_clk_o : out std_ulogic; -- serial clock |
spi_data_i : in std_ulogic; -- device data output |
spi_data_o : out std_ulogic -- controller data output |
); |
end component; |
|
-- Component: System Configuration Information Memory (SYSINFO) --------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_sysinfo |
2004,7 → 2058,8
IO_SLINK_EN : boolean; -- implement stream link interface? |
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN : boolean -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean -- implement execute in place module (XIP)? |
); |
port ( |
-- host access -- |
2011,8 → 2066,10
clk_i : in std_ulogic; -- global clock line |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic -- transfer error |
); |
end component; |
|
2423,4 → 2480,9
end function mem32_init_f; |
|
|
-- Finally set deferred constant, see IEEE 1076-2008 14.4.2.1 (NEORV32 Issue #242) -------- |
-- ------------------------------------------------------------------------------------------- |
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-'); |
|
|
end neorv32_package; |
/neorv32_pwm.vhd
59,7 → 59,7
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0); |
-- pwm output channels -- |
pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0) |
pwm_o : out std_ulogic_vector(59 downto 0) |
); |
end neorv32_pwm; |
|
186,6 → 186,7
end if; |
|
-- channels -- |
pwm_o <= (others => '0'); |
for i in 0 to NUM_CHANNELS-1 loop |
if (unsigned(pwm_cnt) >= unsigned(pwm_ch(i))) or (enable = '0') then |
pwm_o(i) <= '0'; |
/neorv32_spi.vhd
7,7 → 7,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
73,27 → 73,27
constant lo_abb_c : natural := index_size_f(spi_size_c); -- low address boundary bit |
|
-- control register -- |
constant ctrl_cs0_c : natural := 0; -- r/w: spi CS 0 |
constant ctrl_cs1_c : natural := 1; -- r/w: spi CS 1 |
constant ctrl_cs2_c : natural := 2; -- r/w: spi CS 2 |
constant ctrl_cs3_c : natural := 3; -- r/w: spi CS 3 |
constant ctrl_cs4_c : natural := 4; -- r/w: spi CS 4 |
constant ctrl_cs5_c : natural := 5; -- r/w: spi CS 5 |
constant ctrl_cs6_c : natural := 6; -- r/w: spi CS 6 |
constant ctrl_cs7_c : natural := 7; -- r/w: spi CS 7 |
constant ctrl_cs0_c : natural := 0; -- r/w: spi CS 0 |
constant ctrl_cs1_c : natural := 1; -- r/w: spi CS 1 |
constant ctrl_cs2_c : natural := 2; -- r/w: spi CS 2 |
constant ctrl_cs3_c : natural := 3; -- r/w: spi CS 3 |
constant ctrl_cs4_c : natural := 4; -- r/w: spi CS 4 |
constant ctrl_cs5_c : natural := 5; -- r/w: spi CS 5 |
constant ctrl_cs6_c : natural := 6; -- r/w: spi CS 6 |
constant ctrl_cs7_c : natural := 7; -- r/w: spi CS 7 |
constant ctrl_en_c : natural := 8; -- r/w: spi enable |
constant ctrl_cpha_c : natural := 9; -- r/w: spi clock phase |
constant ctrl_prsc0_c : natural := 10; -- r/w: spi prescaler select bit 0 |
constant ctrl_prsc1_c : natural := 11; -- r/w: spi prescaler select bit 1 |
constant ctrl_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2 |
constant ctrl_size0_c : natural := 13; -- r/w: data size lsb (00: 8-bit, 01: 16-bit) |
constant ctrl_size1_c : natural := 14; -- r/w: data size msb (10: 24-bit, 11: 32-bit) |
constant ctrl_cpol_c : natural := 15; -- r/w: spi clock polarity |
constant ctrl_highspeed_c : natural := 16; -- r/w: spi high-speed mode enable (ignoring ctrl_prsc) |
-- |
constant ctrl_en_c : natural := 8; -- r/w: spi enable |
constant ctrl_cpha_c : natural := 9; -- r/w: spi clock phase |
constant ctrl_prsc0_c : natural := 10; -- r/w: spi prescaler select bit 0 |
constant ctrl_prsc1_c : natural := 11; -- r/w: spi prescaler select bit 1 |
constant ctrl_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2 |
constant ctrl_size0_c : natural := 13; -- r/w: data size lsb (00: 8-bit, 01: 16-bit) |
constant ctrl_size1_c : natural := 14; -- r/w: data size msb (10: 24-bit, 11: 32-bit) |
constant ctrl_cpol_c : natural := 15; -- r/w: spi clock polarity |
constant ctrl_busy_c : natural := 31; -- r/-: spi transceiver is busy |
-- |
constant ctrl_busy_c : natural := 31; -- r/-: spi transceiver is busy |
-- |
signal ctrl : std_ulogic_vector(15 downto 0); |
signal ctrl : std_ulogic_vector(16 downto 0); |
|
-- access control -- |
signal acc_en : std_ulogic; -- module access enable |
112,7 → 112,7
sreg : std_ulogic_vector(31 downto 0); |
bitcnt : std_ulogic_vector(05 downto 0); |
bytecnt : std_ulogic_vector(02 downto 0); |
sdi_sync : std_ulogic_vector(01 downto 0); |
sdi_sync : std_ulogic; |
end record; |
signal rtx_engine : rtx_engine_t; |
|
137,23 → 137,23
-- write access -- |
if (wren = '1') then |
if (addr = spi_ctrl_addr_c) then -- control register |
ctrl(ctrl_cs0_c) <= data_i(ctrl_cs0_c); |
ctrl(ctrl_cs1_c) <= data_i(ctrl_cs1_c); |
ctrl(ctrl_cs2_c) <= data_i(ctrl_cs2_c); |
ctrl(ctrl_cs3_c) <= data_i(ctrl_cs3_c); |
ctrl(ctrl_cs4_c) <= data_i(ctrl_cs4_c); |
ctrl(ctrl_cs5_c) <= data_i(ctrl_cs5_c); |
ctrl(ctrl_cs6_c) <= data_i(ctrl_cs6_c); |
ctrl(ctrl_cs7_c) <= data_i(ctrl_cs7_c); |
-- |
ctrl(ctrl_en_c) <= data_i(ctrl_en_c); |
ctrl(ctrl_cpha_c) <= data_i(ctrl_cpha_c); |
ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c); |
ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c); |
ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c); |
ctrl(ctrl_size0_c) <= data_i(ctrl_size0_c); |
ctrl(ctrl_size1_c) <= data_i(ctrl_size1_c); |
ctrl(ctrl_cpol_c) <= data_i(ctrl_cpol_c); |
ctrl(ctrl_cs0_c) <= data_i(ctrl_cs0_c); |
ctrl(ctrl_cs1_c) <= data_i(ctrl_cs1_c); |
ctrl(ctrl_cs2_c) <= data_i(ctrl_cs2_c); |
ctrl(ctrl_cs3_c) <= data_i(ctrl_cs3_c); |
ctrl(ctrl_cs4_c) <= data_i(ctrl_cs4_c); |
ctrl(ctrl_cs5_c) <= data_i(ctrl_cs5_c); |
ctrl(ctrl_cs6_c) <= data_i(ctrl_cs6_c); |
ctrl(ctrl_cs7_c) <= data_i(ctrl_cs7_c); |
ctrl(ctrl_en_c) <= data_i(ctrl_en_c); |
ctrl(ctrl_cpha_c) <= data_i(ctrl_cpha_c); |
ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c); |
ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c); |
ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c); |
ctrl(ctrl_size0_c) <= data_i(ctrl_size0_c); |
ctrl(ctrl_size1_c) <= data_i(ctrl_size1_c); |
ctrl(ctrl_cpol_c) <= data_i(ctrl_cpol_c); |
ctrl(ctrl_highspeed_c) <= data_i(ctrl_highspeed_c); |
end if; |
end if; |
|
161,25 → 161,25
data_o <= (others => '0'); |
if (rden = '1') then |
if (addr = spi_ctrl_addr_c) then -- control register |
data_o(ctrl_cs0_c) <= ctrl(ctrl_cs0_c); |
data_o(ctrl_cs1_c) <= ctrl(ctrl_cs1_c); |
data_o(ctrl_cs2_c) <= ctrl(ctrl_cs2_c); |
data_o(ctrl_cs3_c) <= ctrl(ctrl_cs3_c); |
data_o(ctrl_cs4_c) <= ctrl(ctrl_cs4_c); |
data_o(ctrl_cs5_c) <= ctrl(ctrl_cs5_c); |
data_o(ctrl_cs6_c) <= ctrl(ctrl_cs6_c); |
data_o(ctrl_cs7_c) <= ctrl(ctrl_cs7_c); |
data_o(ctrl_cs0_c) <= ctrl(ctrl_cs0_c); |
data_o(ctrl_cs1_c) <= ctrl(ctrl_cs1_c); |
data_o(ctrl_cs2_c) <= ctrl(ctrl_cs2_c); |
data_o(ctrl_cs3_c) <= ctrl(ctrl_cs3_c); |
data_o(ctrl_cs4_c) <= ctrl(ctrl_cs4_c); |
data_o(ctrl_cs5_c) <= ctrl(ctrl_cs5_c); |
data_o(ctrl_cs6_c) <= ctrl(ctrl_cs6_c); |
data_o(ctrl_cs7_c) <= ctrl(ctrl_cs7_c); |
data_o(ctrl_en_c) <= ctrl(ctrl_en_c); |
data_o(ctrl_cpha_c) <= ctrl(ctrl_cpha_c); |
data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c); |
data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c); |
data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c); |
data_o(ctrl_size0_c) <= ctrl(ctrl_size0_c); |
data_o(ctrl_size1_c) <= ctrl(ctrl_size1_c); |
data_o(ctrl_cpol_c) <= ctrl(ctrl_cpol_c); |
data_o(ctrl_highspeed_c) <= ctrl(ctrl_highspeed_c); |
-- |
data_o(ctrl_en_c) <= ctrl(ctrl_en_c); |
data_o(ctrl_cpha_c) <= ctrl(ctrl_cpha_c); |
data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c); |
data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c); |
data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c); |
data_o(ctrl_size0_c) <= ctrl(ctrl_size0_c); |
data_o(ctrl_size1_c) <= ctrl(ctrl_size1_c); |
data_o(ctrl_cpol_c) <= ctrl(ctrl_cpol_c); |
-- |
data_o(ctrl_busy_c) <= rtx_engine.busy; |
data_o(ctrl_busy_c) <= rtx_engine.busy; |
else -- data register (spi_rtx_addr_c) |
data_o <= rtx_engine.sreg; |
end if; |
197,7 → 197,7
-- Clock Selection ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
clkgen_en_o <= ctrl(ctrl_en_c); -- clock generator enable |
spi_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c)))); -- clock select |
spi_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c)))) or ctrl(ctrl_highspeed_c); -- clock select |
|
|
-- Transmission Data Size ----------------------------------------------------------------- |
219,16 → 219,8
begin |
if rising_edge(clk_i) then |
-- input (sdi) synchronizer -- |
rtx_engine.sdi_sync <= rtx_engine.sdi_sync(0) & spi_sdi_i; |
rtx_engine.sdi_sync <= spi_sdi_i; |
|
-- output (sdo) buffer -- |
case ctrl(ctrl_size1_c downto ctrl_size0_c) is |
when "00" => spi_sdo_o <= rtx_engine.sreg(07); -- 8-bit mode |
when "01" => spi_sdo_o <= rtx_engine.sreg(15); -- 16-bit mode |
when "10" => spi_sdo_o <= rtx_engine.sreg(23); -- 24-bit mode |
when others => spi_sdo_o <= rtx_engine.sreg(31); -- 32-bit mode |
end case; |
|
-- defaults -- |
spi_sck_o <= ctrl(ctrl_cpol_c); |
irq_o <= '0'; |
263,7 → 255,7
-- ------------------------------------------------------------ |
spi_sck_o <= ctrl(ctrl_cpha_c) xnor ctrl(ctrl_cpol_c); |
if (spi_clk_en = '1') then |
rtx_engine.sreg <= rtx_engine.sreg(30 downto 0) & rtx_engine.sdi_sync(rtx_engine.sdi_sync'left); |
rtx_engine.sreg <= rtx_engine.sreg(30 downto 0) & rtx_engine.sdi_sync; |
if (rtx_engine.bitcnt(5 downto 3) = rtx_engine.bytecnt) then -- all bits transferred? |
irq_o <= '1'; -- interrupt! |
rtx_engine.state(1 downto 0) <= "00"; -- transmission done |
283,5 → 275,16
-- busy flag -- |
rtx_engine.busy <= '0' when (rtx_engine.state(1 downto 0) = "00") else '1'; |
|
-- output bit select -- |
spi_output: process(ctrl, rtx_engine) |
begin |
case ctrl(ctrl_size1_c downto ctrl_size0_c) is |
when "00" => spi_sdo_o <= rtx_engine.sreg(07); -- 8-bit mode |
when "01" => spi_sdo_o <= rtx_engine.sreg(15); -- 16-bit mode |
when "10" => spi_sdo_o <= rtx_engine.sreg(23); -- 24-bit mode |
when others => spi_sdo_o <= rtx_engine.sreg(31); -- 32-bit mode |
end case; |
end process spi_output; |
|
|
end neorv32_spi_rtl; |
/neorv32_sysinfo.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
91,7 → 91,8
IO_SLINK_EN : boolean; -- implement stream link interface? |
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN : boolean -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean -- implement execute in place module (XIP)? |
); |
port ( |
-- host access -- |
98,8 → 99,10
clk_i : in std_ulogic; -- global clock line |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic -- transfer error |
); |
end neorv32_sysinfo; |
|
110,10 → 113,10
constant lo_abb_c : natural := index_size_f(sysinfo_size_c); -- low address boundary bit |
|
-- access control -- |
signal acc_en : std_ulogic; -- module access enable |
signal addr : std_ulogic_vector(31 downto 0); |
signal rden : std_ulogic; |
signal info_addr : std_ulogic_vector(02 downto 0); |
signal acc_en : std_ulogic; -- module access enable |
signal rden : std_ulogic; |
signal wren : std_ulogic; |
signal iaddr : std_ulogic_vector(02 downto 0); |
|
-- system information ROM -- |
type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0); |
123,15 → 126,14
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
rden <= acc_en and rden_i; -- valid read access |
addr <= sysinfo_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned |
info_addr <= addr(index_size_f(sysinfo_size_c)-1 downto 2); |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
rden <= acc_en and rden_i; -- read access |
wren <= acc_en and wren_i; -- write access |
iaddr <= addr_i(index_size_f(sysinfo_size_c)-1 downto 2); |
|
|
-- Construct Info ROM --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
|
-- SYSINFO(0): Processor (primary) clock frequency -- |
sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); |
|
183,8 → 185,9
sysinfo_mem(2)(27) <= bool_to_ulogic_f(IO_NEOLED_EN); -- NeoPixel-compatible smart LED interface (NEOLED) implemented? |
sysinfo_mem(2)(28) <= bool_to_ulogic_f(boolean(IO_XIRQ_NUM_CH > 0)); -- external interrupt controller (XIRQ) implemented? |
sysinfo_mem(2)(29) <= bool_to_ulogic_f(IO_GPTMR_EN); -- general purpose timer (GPTMR) implemented? |
sysinfo_mem(2)(30) <= bool_to_ulogic_f(IO_XIP_EN); -- execute in place module (XIP) implemented? |
-- |
sysinfo_mem(2)(31 downto 30) <= (others => '0'); -- reserved |
sysinfo_mem(2)(31) <= '0'; -- reserved |
|
-- SYSINFO(3): Cache configuration -- |
sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes) |
216,9 → 219,10
begin |
if rising_edge(clk_i) then |
ack_o <= rden; |
err_o <= wren; |
data_o <= (others => '0'); |
if (rden = '1') then |
data_o <= sysinfo_mem(to_integer(unsigned(info_addr))); |
data_o <= sysinfo_mem(to_integer(unsigned(iaddr))); |
end if; |
end if; |
end process read_access; |
/neorv32_top.vhd
8,7 → 8,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
90,7 → 90,7
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
|
-- Internal Cache memory (iCACHE) -- |
-- Internal Instruction Cache (iCACHE) -- |
ICACHE_EN : boolean := false; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
134,7 → 134,8
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits |
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two |
IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean := false -- implement execute in place module (XIP)? |
); |
port ( |
-- Global control -- |
165,6 → 166,12
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
|
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- |
xip_csn_o : out std_ulogic; -- chip-select, low-active |
xip_clk_o : out std_ulogic; -- serial clock |
xip_sdi_i : in std_ulogic := 'L'; -- device data input |
xip_sdo_o : out std_ulogic; -- controller data output |
|
-- TX stream interfaces (available if SLINK_NUM_TX > 0) -- |
slink_tx_dat_o : out sdata_8x32_t; -- output data |
slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output |
202,7 → 209,7
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line |
|
-- PWM (available if IO_PWM_NUM_CH > 0) -- |
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels |
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels |
|
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit |
216,7 → 223,7
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) |
|
-- External platform interrupts (available if XIRQ_NUM_CH > 0) -- |
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels |
xirq_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels |
|
-- CPU interrupts -- |
mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false |
238,16 → 245,17
constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all? |
|
-- reset generator -- |
signal rstn_gen : std_ulogic_vector(7 downto 0) := (others => '0'); -- initialize (=reset) via (for FPGAs only) |
signal rstn_gen : std_ulogic_vector(7 downto 0) := (others => '0'); -- initialize (=reset) via bitstream (for FPGAs only) |
signal ext_rstn : std_ulogic; |
signal sys_rstn : std_ulogic; |
signal wdt_rstn : std_ulogic; |
|
-- clock generator -- |
signal clk_div : std_ulogic_vector(11 downto 0); |
signal clk_div_ff : std_ulogic_vector(11 downto 0); |
signal clk_gen : std_ulogic_vector(07 downto 0); |
signal clk_gen_en : std_ulogic_vector(08 downto 0); |
signal clk_div : std_ulogic_vector(11 downto 0); |
signal clk_div_ff : std_ulogic_vector(11 downto 0); |
signal clk_gen : std_ulogic_vector(07 downto 0); |
signal clk_gen_en : std_ulogic_vector(09 downto 0); |
signal clk_gen_en_ff : std_ulogic; |
-- |
signal wdt_cg_en : std_ulogic; |
signal uart0_cg_en : std_ulogic; |
258,21 → 266,22
signal cfs_cg_en : std_ulogic; |
signal neoled_cg_en : std_ulogic; |
signal gptmr_cg_en : std_ulogic; |
signal xip_cg_en : std_ulogic; |
|
-- bus interface -- |
type bus_interface_t is record |
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ben : std_ulogic_vector(03 downto 0); -- byte enable |
we : std_ulogic; -- write enable |
re : std_ulogic; -- read enable |
ack : std_ulogic; -- bus transfer acknowledge |
err : std_ulogic; -- bus transfer error |
fence : std_ulogic; -- fence(i) instruction executed |
priv : std_ulogic_vector(1 downto 0); -- current privilege level |
src : std_ulogic; -- access source (1=instruction fetch, 0=data access) |
lock : std_ulogic; -- exclusive access request |
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ben : std_ulogic_vector(03 downto 0); -- byte enable |
we : std_ulogic; -- write enable |
re : std_ulogic; -- read enable |
ack : std_ulogic; -- bus transfer acknowledge |
err : std_ulogic; -- bus transfer error |
fence : std_ulogic; -- fence(i) instruction executed |
priv : std_ulogic_vector(1 downto 0); -- current privilege level |
src : std_ulogic; -- access source (1=instruction fetch, 0=data access) |
lock : std_ulogic; -- exclusive access request |
end record; |
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t; |
|
312,8 → 321,9
constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => '0'), ack => '0', err => '0'); |
|
-- module response bus - device ID -- |
type resp_bus_id_t is (RESP_BUSKEEPER, RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, RESP_MTIME, RESP_UART0, RESP_UART1, RESP_SPI, |
RESP_TWI, RESP_PWM, RESP_WDT, RESP_TRNG, RESP_CFS, RESP_NEOLED, RESP_SYSINFO, RESP_OCD, RESP_SLINK, RESP_XIRQ, RESP_GPTMR); |
type resp_bus_id_t is (RESP_BUSKEEPER, RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, RESP_MTIME, |
RESP_UART0, RESP_UART1, RESP_SPI, RESP_TWI, RESP_PWM, RESP_WDT, RESP_TRNG, RESP_CFS, |
RESP_NEOLED, RESP_SYSINFO, RESP_OCD, RESP_SLINK, RESP_XIRQ, RESP_GPTMR, RESP_XIP_CT, RESP_XIP_IF); |
|
-- module response bus -- |
type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t; |
340,6 → 350,9
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME |
signal ext_timeout : std_ulogic; |
signal ext_access : std_ulogic; |
signal xip_access : std_ulogic; |
signal xip_enable : std_ulogic; |
signal xip_page : std_ulogic_vector(3 downto 0); |
signal debug_mode : std_ulogic; |
|
begin |
362,7 → 375,8
cond_sel_string_f(IO_NEOLED_EN, "NEOLED ", "") & |
cond_sel_string_f(boolean(XIRQ_NUM_CH > 0), "XIRQ ", "") & |
cond_sel_string_f(IO_GPTMR_EN, "GPTMR ", "") & |
"" |
cond_sel_string_f(IO_XIP_EN, "XIP ", "") & |
"" |
severity note; |
|
|
421,23 → 435,14
clock_generator: process(sys_rstn, clk_i) |
begin |
if (sys_rstn = '0') then |
clk_gen_en <= (others => '-'); |
clk_div <= (others => '0'); |
clk_div_ff <= (others => '-'); |
clk_gen <= (others => '-'); |
clk_gen_en_ff <= '-'; |
clk_div <= (others => '0'); -- reset required |
clk_div_ff <= (others => '-'); |
clk_gen <= (others => '-'); |
elsif rising_edge(clk_i) then |
-- fresh clocks anyone? -- |
clk_gen_en(0) <= wdt_cg_en; |
clk_gen_en(1) <= uart0_cg_en; |
clk_gen_en(2) <= uart1_cg_en; |
clk_gen_en(3) <= spi_cg_en; |
clk_gen_en(4) <= twi_cg_en; |
clk_gen_en(5) <= pwm_cg_en; |
clk_gen_en(6) <= cfs_cg_en; |
clk_gen_en(7) <= neoled_cg_en; |
clk_gen_en(8) <= gptmr_cg_en; |
clk_gen_en_ff <= or_reduce_f(clk_gen_en); |
-- actual clock generator -- |
if (or_reduce_f(clk_gen_en) = '1') then |
if (clk_gen_en_ff = '1') then |
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1); |
end if; |
-- clock enables: rising edge detectors -- |
453,21 → 458,33
end if; |
end process clock_generator; |
|
-- fresh clocks anyone? -- |
clk_gen_en(0) <= wdt_cg_en; |
clk_gen_en(1) <= uart0_cg_en; |
clk_gen_en(2) <= uart1_cg_en; |
clk_gen_en(3) <= spi_cg_en; |
clk_gen_en(4) <= twi_cg_en; |
clk_gen_en(5) <= pwm_cg_en; |
clk_gen_en(6) <= cfs_cg_en; |
clk_gen_en(7) <= neoled_cg_en; |
clk_gen_en(8) <= gptmr_cg_en; |
clk_gen_en(9) <= xip_cg_en; |
|
|
-- CPU Core ------------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_inst: neorv32_cpu |
generic map ( |
-- General -- |
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id |
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address |
CPU_DEBUG_ADDR => dm_base_c, -- cpu debug mode start address |
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id |
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address |
CPU_DEBUG_ADDR => dm_base_c, -- cpu debug mode start address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? |
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? |
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? |
477,57 → 494,57
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode? |
-- Extension Options -- |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations |
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) |
CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2 |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations |
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) |
CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2 |
-- Physical Memory Protection (PMP) -- |
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) |
HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (0..64) |
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) |
HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (0..64) |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
sleep_o => open, -- cpu is in sleep mode when set |
debug_o => debug_mode, -- cpu is in debug mode when set |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
sleep_o => open, -- cpu is in sleep mode when set |
debug_o => debug_mode, -- cpu is in debug mode when set |
-- instruction bus interface -- |
i_bus_addr_o => cpu_i.addr, -- bus access address |
i_bus_rdata_i => cpu_i.rdata, -- bus read data |
i_bus_wdata_o => cpu_i.wdata, -- bus write data |
i_bus_ben_o => cpu_i.ben, -- byte enable |
i_bus_we_o => cpu_i.we, -- write enable |
i_bus_re_o => cpu_i.re, -- read enable |
i_bus_lock_o => cpu_i.lock, -- exclusive access request |
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge |
i_bus_err_i => cpu_i.err, -- bus transfer error |
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation |
i_bus_priv_o => cpu_i.priv, -- privilege level |
i_bus_addr_o => cpu_i.addr, -- bus access address |
i_bus_rdata_i => cpu_i.rdata, -- bus read data |
i_bus_wdata_o => cpu_i.wdata, -- bus write data |
i_bus_ben_o => cpu_i.ben, -- byte enable |
i_bus_we_o => cpu_i.we, -- write enable |
i_bus_re_o => cpu_i.re, -- read enable |
i_bus_lock_o => cpu_i.lock, -- exclusive access request |
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge |
i_bus_err_i => cpu_i.err, -- bus transfer error |
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation |
i_bus_priv_o => cpu_i.priv, -- privilege level |
-- data bus interface -- |
d_bus_addr_o => cpu_d.addr, -- bus access address |
d_bus_rdata_i => cpu_d.rdata, -- bus read data |
d_bus_wdata_o => cpu_d.wdata, -- bus write data |
d_bus_ben_o => cpu_d.ben, -- byte enable |
d_bus_we_o => cpu_d.we, -- write enable |
d_bus_re_o => cpu_d.re, -- read enable |
d_bus_lock_o => cpu_d.lock, -- exclusive access request |
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge |
d_bus_err_i => cpu_d.err, -- bus transfer error |
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation |
d_bus_priv_o => cpu_d.priv, -- privilege level |
d_bus_addr_o => cpu_d.addr, -- bus access address |
d_bus_rdata_i => cpu_d.rdata, -- bus read data |
d_bus_wdata_o => cpu_d.wdata, -- bus write data |
d_bus_ben_o => cpu_d.ben, -- byte enable |
d_bus_we_o => cpu_d.we, -- write enable |
d_bus_re_o => cpu_d.re, -- read enable |
d_bus_lock_o => cpu_d.lock, -- exclusive access request |
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge |
d_bus_err_i => cpu_d.err, -- bus transfer error |
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation |
d_bus_priv_o => cpu_d.priv, -- privilege level |
-- system time input from MTIME -- |
time_i => mtime_time, -- current system time |
time_i => mtime_time, -- current system time |
-- non-maskable interrupt -- |
msw_irq_i => msw_irq_i, -- machine software interrupt |
mext_irq_i => mext_irq_i, -- machine external interrupt request |
mtime_irq_i => mtime_irq, -- machine timer interrupt |
msw_irq_i => msw_irq_i, -- machine software interrupt |
mext_irq_i => mext_irq_i, -- machine external interrupt request |
mtime_irq_i => mtime_irq, -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i => fast_irq, -- fast interrupt trigger |
firq_i => fast_irq, -- fast interrupt trigger |
-- debug mode (halt) request -- |
db_halt_req_i => dci_halt_req |
db_halt_req_i => dci_halt_req |
); |
|
-- misc -- |
538,8 → 555,7
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation |
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation |
|
-- fast interrupt requests (FIRQs) -- |
-- these signals are single-shot -- |
-- fast interrupt requests (FIRQs) - triggers are SINGLE-SHOT -- |
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog |
fast_irq(01) <= cfs_irq; -- custom functions subsystem |
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX |
546,17 → 562,17
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX |
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX |
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) TX |
fast_irq(06) <= spi_irq; -- SPI |
fast_irq(07) <= twi_irq; -- TWI |
fast_irq(06) <= spi_irq; -- SPI transfer done |
fast_irq(07) <= twi_irq; -- TWI transfer done |
fast_irq(08) <= xirq_irq; -- external interrupt controller |
fast_irq(09) <= neoled_irq; -- NEOLED buffer free |
fast_irq(09) <= neoled_irq; -- NEOLED buffer IRQ |
fast_irq(10) <= slink_rx_irq; -- SLINK RX |
fast_irq(11) <= slink_tx_irq; -- SLINK TX |
fast_irq(12) <= gptmr_irq; -- general purpose timer |
-- |
fast_irq(13) <= '0'; -- reserved |
fast_irq(14) <= '0'; -- reserved |
fast_irq(15) <= '0'; -- LOWEST PRIORITY - reserved |
fast_irq(13) <= '0'; -- reserved |
fast_irq(14) <= '0'; -- reserved |
fast_irq(15) <= '0'; -- LOWEST PRIORITY - reserved |
|
|
-- CPU Instruction Cache ------------------------------------------------------------------ |
571,27 → 587,27
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
clear_i => cpu_i.fence, -- cache clear |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
clear_i => cpu_i.fence, -- cache clear |
-- host controller interface -- |
host_addr_i => cpu_i.addr, -- bus access address |
host_rdata_o => cpu_i.rdata, -- bus read data |
host_wdata_i => cpu_i.wdata, -- bus write data |
host_ben_i => cpu_i.ben, -- byte enable |
host_we_i => cpu_i.we, -- write enable |
host_re_i => cpu_i.re, -- read enable |
host_ack_o => cpu_i.ack, -- bus transfer acknowledge |
host_err_o => cpu_i.err, -- bus transfer error |
host_addr_i => cpu_i.addr, -- bus access address |
host_rdata_o => cpu_i.rdata, -- bus read data |
host_wdata_i => cpu_i.wdata, -- bus write data |
host_ben_i => cpu_i.ben, -- byte enable |
host_we_i => cpu_i.we, -- write enable |
host_re_i => cpu_i.re, -- read enable |
host_ack_o => cpu_i.ack, -- bus transfer acknowledge |
host_err_o => cpu_i.err, -- bus transfer error |
-- peripheral bus interface -- |
bus_addr_o => i_cache.addr, -- bus access address |
bus_rdata_i => i_cache.rdata, -- bus read data |
bus_wdata_o => i_cache.wdata, -- bus write data |
bus_ben_o => i_cache.ben, -- byte enable |
bus_we_o => i_cache.we, -- write enable |
bus_re_o => i_cache.re, -- read enable |
bus_ack_i => i_cache.ack, -- bus transfer acknowledge |
bus_err_i => i_cache.err -- bus transfer error |
bus_addr_o => i_cache.addr, -- bus access address |
bus_rdata_i => i_cache.rdata, -- bus read data |
bus_wdata_o => i_cache.wdata, -- bus write data |
bus_ben_o => i_cache.ben, -- byte enable |
bus_we_o => i_cache.we, -- write enable |
bus_re_o => i_cache.re, -- read enable |
bus_ack_i => i_cache.ack, -- bus transfer acknowledge |
bus_err_i => i_cache.err -- bus transfer error |
); |
end generate; |
|
620,39 → 636,39
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
-- controller interface a -- |
ca_bus_addr_i => cpu_d.addr, -- bus access address |
ca_bus_rdata_o => cpu_d.rdata, -- bus read data |
ca_bus_wdata_i => cpu_d.wdata, -- bus write data |
ca_bus_ben_i => cpu_d.ben, -- byte enable |
ca_bus_we_i => cpu_d.we, -- write enable |
ca_bus_re_i => cpu_d.re, -- read enable |
ca_bus_lock_i => cpu_d.lock, -- exclusive access request |
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge |
ca_bus_err_o => cpu_d.err, -- bus transfer error |
ca_bus_addr_i => cpu_d.addr, -- bus access address |
ca_bus_rdata_o => cpu_d.rdata, -- bus read data |
ca_bus_wdata_i => cpu_d.wdata, -- bus write data |
ca_bus_ben_i => cpu_d.ben, -- byte enable |
ca_bus_we_i => cpu_d.we, -- write enable |
ca_bus_re_i => cpu_d.re, -- read enable |
ca_bus_lock_i => cpu_d.lock, -- exclusive access request |
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge |
ca_bus_err_o => cpu_d.err, -- bus transfer error |
-- controller interface b -- |
cb_bus_addr_i => i_cache.addr, -- bus access address |
cb_bus_rdata_o => i_cache.rdata, -- bus read data |
cb_bus_wdata_i => i_cache.wdata, -- bus write data |
cb_bus_ben_i => i_cache.ben, -- byte enable |
cb_bus_we_i => i_cache.we, -- write enable |
cb_bus_re_i => i_cache.re, -- read enable |
cb_bus_lock_i => i_cache.lock, -- exclusive access request |
cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge |
cb_bus_err_o => i_cache.err, -- bus transfer error |
cb_bus_addr_i => i_cache.addr, -- bus access address |
cb_bus_rdata_o => i_cache.rdata, -- bus read data |
cb_bus_wdata_i => i_cache.wdata, -- bus write data |
cb_bus_ben_i => i_cache.ben, -- byte enable |
cb_bus_we_i => i_cache.we, -- write enable |
cb_bus_re_i => i_cache.re, -- read enable |
cb_bus_lock_i => i_cache.lock, -- exclusive access request |
cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge |
cb_bus_err_o => i_cache.err, -- bus transfer error |
-- peripheral bus -- |
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions) |
p_bus_addr_o => p_bus.addr, -- bus access address |
p_bus_rdata_i => p_bus.rdata, -- bus read data |
p_bus_wdata_o => p_bus.wdata, -- bus write data |
p_bus_ben_o => p_bus.ben, -- byte enable |
p_bus_we_o => p_bus.we, -- write enable |
p_bus_re_o => p_bus.re, -- read enable |
p_bus_lock_o => p_bus.lock, -- exclusive access request |
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge |
p_bus_err_i => bus_error -- bus transfer error |
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions) |
p_bus_addr_o => p_bus.addr, -- bus access address |
p_bus_rdata_i => p_bus.rdata, -- bus read data |
p_bus_wdata_o => p_bus.wdata, -- bus write data |
p_bus_ben_o => p_bus.ben, -- byte enable |
p_bus_we_o => p_bus.we, -- write enable |
p_bus_re_o => p_bus.re, -- read enable |
p_bus_lock_o => p_bus.lock, -- exclusive access request |
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge |
p_bus_err_i => bus_error -- bus transfer error |
); |
|
-- current CPU privilege level -- |
691,6 → 707,7
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => resp_bus(RESP_BUSKEEPER).rdata, -- data out |
ack_o => resp_bus(RESP_BUSKEEPER).ack, -- transfer acknowledge |
err_o => bus_error, -- transfer error |
701,7 → 718,8
bus_ack_i => p_bus.ack, -- transfer acknowledge from bus system |
bus_err_i => p_bus.err, -- transfer error from bus system |
bus_tmo_i => ext_timeout, -- transfer timeout (external interface) |
bus_ext_i => ext_access -- external bus access |
bus_ext_i => ext_access, -- external bus access |
bus_xip_i => xip_access -- pending XIP access |
); |
|
-- unused, BUSKEEPER **directly** issues error to the CPU -- |
809,34 → 827,37
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active |
-- host access -- |
src_i => p_bus.src, -- access type (0: data, 1:instruction) |
addr_i => p_bus.addr, -- address |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => resp_bus(RESP_WISHBONE).rdata, -- data out |
lock_i => p_bus.lock, -- exclusive access request |
ack_o => resp_bus(RESP_WISHBONE).ack, -- transfer acknowledge |
err_o => resp_bus(RESP_WISHBONE).err, -- transfer error |
tmo_o => ext_timeout, -- transfer timeout |
priv_i => p_bus.priv, -- current CPU privilege level |
ext_o => ext_access, -- active external access |
src_i => p_bus.src, -- access type (0: data, 1:instruction) |
addr_i => p_bus.addr, -- address |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => resp_bus(RESP_WISHBONE).rdata, -- data out |
lock_i => p_bus.lock, -- exclusive access request |
ack_o => resp_bus(RESP_WISHBONE).ack, -- transfer acknowledge |
err_o => resp_bus(RESP_WISHBONE).err, -- transfer error |
tmo_o => ext_timeout, -- transfer timeout |
priv_i => p_bus.priv, -- current CPU privilege level |
ext_o => ext_access, -- active external access |
-- xip configuration -- |
xip_en_i => xip_enable, -- XIP module enabled |
xip_page_i => xip_page, -- XIP memory page |
-- wishbone interface -- |
wb_tag_o => wb_tag_o, -- request tag |
wb_adr_o => wb_adr_o, -- address |
wb_dat_i => wb_dat_i, -- read data |
wb_dat_o => wb_dat_o, -- write data |
wb_we_o => wb_we_o, -- read/write |
wb_sel_o => wb_sel_o, -- byte enable |
wb_stb_o => wb_stb_o, -- strobe |
wb_cyc_o => wb_cyc_o, -- valid cycle |
wb_lock_o => wb_lock_o, -- exclusive access request |
wb_ack_i => wb_ack_i, -- transfer acknowledge |
wb_err_i => wb_err_i -- transfer error |
wb_tag_o => wb_tag_o, -- request tag |
wb_adr_o => wb_adr_o, -- address |
wb_dat_i => wb_dat_i, -- read data |
wb_dat_o => wb_dat_o, -- write data |
wb_we_o => wb_we_o, -- read/write |
wb_sel_o => wb_sel_o, -- byte enable |
wb_stb_o => wb_stb_o, -- strobe |
wb_cyc_o => wb_cyc_o, -- valid cycle |
wb_lock_o => wb_lock_o, -- exclusive access request |
wb_ack_i => wb_ack_i, -- transfer acknowledge |
wb_err_i => wb_err_i -- transfer error |
); |
end generate; |
|
857,6 → 878,64
end generate; |
|
|
-- Execute In Place Module (XIP) ---------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_xip_inst_true: |
if (IO_XIP_EN = true) generate |
neorv32_xip_inst: neorv32_xip |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active |
-- host access: control register access port -- |
ct_addr_i => p_bus.addr, -- address |
ct_rden_i => io_rden, -- read enable |
ct_wren_i => io_wren, -- write enable |
ct_data_i => p_bus.wdata, -- data in |
ct_data_o => resp_bus(RESP_XIP_CT).rdata, -- data out |
ct_ack_o => resp_bus(RESP_XIP_CT).ack, -- transfer acknowledge |
-- host access: instruction fetch access port (read-only) -- |
if_addr_i => p_bus.addr, -- address |
if_rden_i => p_bus.re, -- read enable |
if_data_o => resp_bus(RESP_XIP_IF).rdata, -- data out |
if_ack_o => resp_bus(RESP_XIP_IF).ack, -- transfer acknowledge |
-- status -- |
xip_en_o => xip_enable, -- XIP enable |
xip_acc_o => xip_access, -- pending XIP access |
xip_page_o => xip_page, -- XIP page |
-- clock generator -- |
clkgen_en_o => xip_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- SPI device interface -- |
spi_csn_o => xip_csn_o, -- chip-select, low-active |
spi_clk_o => xip_clk_o, -- serial clock |
spi_data_i => xip_sdi_i, -- device data output |
spi_data_o => xip_sdo_o -- controller data output |
); |
resp_bus(RESP_XIP_CT).err <= '0'; -- no access error possible |
resp_bus(RESP_XIP_IF).err <= '0'; -- no access error possible |
end generate; |
|
neorv32_xip_inst_false: |
if (IO_XIP_EN = false) generate |
resp_bus(RESP_XIP_CT) <= resp_bus_entry_terminate_c; |
resp_bus(RESP_XIP_IF) <= resp_bus_entry_terminate_c; |
-- |
xip_enable <= '0'; |
xip_access <= '0'; |
xip_page <= (others => '0'); |
xip_cg_en <= '0'; |
xip_csn_o <= '1'; |
xip_clk_o <= '0'; |
xip_sdo_o <= '0'; |
end generate; |
|
|
-- **************************************************************************************************************************** |
-- IO/Peripheral Modules |
-- **************************************************************************************************************************** |
|
|
-- IO Access? ----------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0'; |
900,6 → 979,7
neorv32_cfs_inst_false: |
if (IO_CFS_EN = false) generate |
resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c; |
-- |
cfs_cg_en <= '0'; |
cfs_irq <= '0'; |
cfs_out_o <= (others => '0'); |
920,16 → 1000,17
data_i => p_bus.wdata, -- data in |
data_o => resp_bus(RESP_GPIO).rdata, -- data out |
ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge |
err_o => resp_bus(RESP_GPIO).err, -- transfer error |
-- parallel io -- |
gpio_o => gpio_o, |
gpio_i => gpio_i |
); |
resp_bus(RESP_GPIO).err <= '0'; -- no access error possible |
end generate; |
|
neorv32_gpio_inst_false: |
if (IO_GPIO_EN = false) generate |
resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c; |
-- |
gpio_o <= (others => '0'); |
end generate; |
|
967,6 → 1048,7
neorv32_wdt_inst_false: |
if (IO_WDT_EN = false) generate |
resp_bus(RESP_WDT) <= resp_bus_entry_terminate_c; |
-- |
wdt_irq <= '0'; |
wdt_rstn <= '1'; |
wdt_cg_en <= '0'; |
998,6 → 1080,7
neorv32_mtime_inst_false: |
if (IO_MTIME_EN = false) generate |
resp_bus(RESP_MTIME) <= resp_bus_entry_terminate_c; |
-- |
mtime_time <= mtime_i; -- use external machine timer time signal |
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt |
end generate; |
1061,6 → 1144,7
neorv32_uart0_inst_false: |
if (IO_UART0_EN = false) generate |
resp_bus(RESP_UART0) <= resp_bus_entry_terminate_c; |
-- |
uart0_txd_o <= '0'; |
uart0_rts_o <= '0'; |
uart0_cg_en <= '0'; |
1107,6 → 1191,7
neorv32_uart1_inst_false: |
if (IO_UART1_EN = false) generate |
resp_bus(RESP_UART1) <= resp_bus_entry_terminate_c; |
-- |
uart1_txd_o <= '0'; |
uart1_rts_o <= '0'; |
uart1_cg_en <= '0'; |
1146,6 → 1231,7
neorv32_spi_inst_false: |
if (IO_SPI_EN = false) generate |
resp_bus(RESP_SPI) <= resp_bus_entry_terminate_c; |
-- |
spi_sck_o <= '0'; |
spi_sdo_o <= '0'; |
spi_csn_o <= (others => '1'); -- CSn lines are low-active |
1183,6 → 1269,7
neorv32_twi_inst_false: |
if (IO_TWI_EN = false) generate |
resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c; |
-- |
twi_sda_io <= 'Z'; |
twi_scl_io <= 'Z'; |
twi_cg_en <= '0'; |
1219,6 → 1306,7
neorv32_pwm_inst_false: |
if (IO_PWM_NUM_CH = 0) generate |
resp_bus(RESP_PWM) <= resp_bus_entry_terminate_c; |
-- |
pwm_cg_en <= '0'; |
pwm_o <= (others => '0'); |
end generate; |
1279,6 → 1367,7
neorv32_neoled_inst_false: |
if (IO_NEOLED_EN = false) generate |
resp_bus(RESP_NEOLED) <= resp_bus_entry_terminate_c; |
-- |
neoled_cg_en <= '0'; |
neoled_irq <= '0'; |
neoled_o <= '0'; |
1323,6 → 1412,7
neorv32_slink_inst_false: |
if (io_slink_en_c = false) generate |
resp_bus(RESP_SLINK) <= resp_bus_entry_terminate_c; |
-- |
slink_tx_irq <= '0'; |
slink_rx_irq <= '0'; |
slink_tx_dat_o <= (others => (others => '0')); |
1361,6 → 1451,7
neorv32_xirq_inst_false: |
if (XIRQ_NUM_CH = 0) generate |
resp_bus(RESP_XIRQ) <= resp_bus_entry_terminate_c; |
-- |
xirq_irq <= '0'; |
end generate; |
|
1391,6 → 1482,7
neorv32_gptmr_inst_false: |
if (IO_GPTMR_EN = false) generate |
resp_bus(RESP_GPTMR) <= resp_bus_entry_terminate_c; |
-- |
gptmr_cg_en <= '0'; |
gptmr_irq <= '0'; |
end generate; |
1447,7 → 1539,8
IO_SLINK_EN => io_slink_en_c, -- implement stream link interface? |
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN => IO_GPTMR_EN -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)? |
IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)? |
) |
port map ( |
-- host access -- |
1454,13 → 1547,13
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
data_o => resp_bus(RESP_SYSINFO).rdata, -- data out |
ack_o => resp_bus(RESP_SYSINFO).ack -- transfer acknowledge |
ack_o => resp_bus(RESP_SYSINFO).ack, -- transfer acknowledge |
err_o => resp_bus(RESP_SYSINFO).err -- transfer error |
); |
|
resp_bus(RESP_SYSINFO).err <= '0'; -- no access error possible |
|
|
-- ************************************************************************************************************************** |
-- On-Chip Debugger Complex |
-- ************************************************************************************************************************** |
1502,6 → 1595,7
|
neorv32_debug_dm_false: |
if (ON_CHIP_DEBUGGER_EN = false) generate |
-- |
dmi.req_ready <= '0'; |
dmi.resp_valid <= '0'; |
dmi.resp_data <= (others => '0'); |
/neorv32_wishbone.vhd
11,7 → 11,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
63,34 → 63,37
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
-- host access -- |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
lock_i : in std_ulogic; -- exclusive access request |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
tmo_o : out std_ulogic; -- transfer timeout |
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level |
ext_o : out std_ulogic; -- active external access |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
lock_i : in std_ulogic; -- exclusive access request |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
tmo_o : out std_ulogic; -- transfer timeout |
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level |
ext_o : out std_ulogic; -- active external access |
-- xip configuration -- |
xip_en_i : in std_ulogic; -- XIP module enabled |
xip_page_i : in std_ulogic_vector(03 downto 0); -- XIP memory page |
-- wishbone interface -- |
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_lock_o : out std_ulogic; -- exclusive access request |
wb_ack_i : in std_ulogic; -- transfer acknowledge |
wb_err_i : in std_ulogic -- transfer error |
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_lock_o : out std_ulogic; -- exclusive access request |
wb_ack_i : in std_ulogic; -- transfer acknowledge |
wb_err_i : in std_ulogic -- transfer error |
); |
end neorv32_wishbone; |
|
103,6 → 106,7
signal int_imem_acc : std_ulogic; |
signal int_dmem_acc : std_ulogic; |
signal int_boot_acc : std_ulogic; |
signal xip_acc : std_ulogic; |
signal xbus_access : std_ulogic; |
|
-- bus arbiter |
160,8 → 164,10
int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_EN = true) else '0'; |
-- access to processor-internal BOOTROM or IO devices? -- |
int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky! |
-- XIP access? -- |
xip_acc <= '1' when (xip_en_i = '1') and (addr_i(31 downto 28) = xip_page_i) else '0'; |
-- actual external bus access? -- |
xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc); |
xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc) and (not xip_acc); |
|
|
-- Bus Arbiter ----------------------------------------------------------------------------- |
/neorv32_xip.vhd
0,0 → 1,563
-- ################################################################################################# |
-- # << NEORV32 - Execute In Place (XIP) Module >> # |
-- # ********************************************************************************************* # |
-- # This module allows the CPU to execute code (and read constant data) directly from an SPI # |
-- # flash memory. Two host ports are implemented: one for accessing the control and status # |
-- # registers (mapped to the processor's IO space) and one for the actual instruction/data fetch. # |
-- # The actual address space mapping of the "instruction/data interface" is done by programming # |
-- # special control register bits. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_xip is |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
-- host access: control register access port -- |
ct_addr_i : in std_ulogic_vector(31 downto 0); -- address |
ct_rden_i : in std_ulogic; -- read enable |
ct_wren_i : in std_ulogic; -- write enable |
ct_data_i : in std_ulogic_vector(31 downto 0); -- data in |
ct_data_o : out std_ulogic_vector(31 downto 0); -- data out |
ct_ack_o : out std_ulogic; -- transfer acknowledge |
-- host access: instruction fetch access port (read-only) -- |
if_addr_i : in std_ulogic_vector(31 downto 0); -- address |
if_rden_i : in std_ulogic; -- read enable |
if_data_o : out std_ulogic_vector(31 downto 0); -- data out |
if_ack_o : out std_ulogic; -- transfer acknowledge |
-- status -- |
xip_en_o : out std_ulogic; -- XIP enable |
xip_acc_o : out std_ulogic; -- pending XIP access |
xip_page_o : out std_ulogic_vector(03 downto 0); -- XIP page |
-- clock generator -- |
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0); |
-- SPI device interface -- |
spi_csn_o : out std_ulogic; -- chip-select, low-active |
spi_clk_o : out std_ulogic; -- serial clock |
spi_data_i : in std_ulogic; -- device data output |
spi_data_o : out std_ulogic -- controller data output |
); |
end neorv32_xip; |
|
architecture neorv32_xip_rtl of neorv32_xip is |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(xip_size_c); -- low address boundary bit |
|
-- CT register access control -- |
signal ct_acc_en : std_ulogic; -- module access enable |
signal ct_addr : std_ulogic_vector(31 downto 0); -- access address |
signal ct_wren : std_ulogic; -- word write enable |
signal ct_rden : std_ulogic; -- read enable |
|
-- control register -- |
constant ctrl_enable_c : natural := 0; -- r/w: module enable |
constant ctrl_spi_prsc0_c : natural := 1; -- r/w: SPI clock prescaler select - bit 0 |
constant ctrl_spi_prsc1_c : natural := 2; -- r/w: SPI clock prescaler select - bit 1 |
constant ctrl_spi_prsc2_c : natural := 3; -- r/w: SPI clock prescaler select - bit 2 |
constant ctrl_spi_cpol_c : natural := 4; -- r/w: SPI (idle) clock polarity |
constant ctrl_spi_cpha_c : natural := 5; -- r/w: SPI clock phase |
constant ctrl_spi_nbytes0_c : natural := 6; -- r/w: SPI number of bytes in transmission (1..9) - bit 0 |
constant ctrl_spi_nbytes3_c : natural := 9; -- r/w: SPI number of bytes in transmission (1..9) - bit 3 |
constant ctrl_xip_enable_c : natural := 10; -- r/w: XIP access mode enable |
constant ctrl_xip_abytes0_c : natural := 11; -- r/w: XIP number of address bytes (0=1,1=2,2=3,3=4) - bit 0 |
constant ctrl_xip_abytes1_c : natural := 12; -- r/w: XIP number of address bytes (0=1,1=2,2=3,3=4) - bit 1 |
constant ctrl_rd_cmd0_c : natural := 13; -- r/w: SPI flash read command - bit 0 |
constant ctrl_rd_cmd7_c : natural := 20; -- r/w: SPI flash read command - bit 7 |
constant ctrl_page0_c : natural := 21; -- r/w: XIP memory page - bit 0 |
constant ctrl_page3_c : natural := 24; -- r/w: XIP memory page - bit 3 |
constant ctrl_spi_csen_c : natural := 25; -- r/w: SPI chip-select enabled |
constant ctrl_highspeed_c : natural := 26; -- r/w: SPI high-speed mode enable (ignoring ctrl_spi_prsc) |
-- |
constant ctrl_phy_busy_c : natural := 30; -- r/-: SPI PHY is busy when set |
constant ctrl_xip_busy_c : natural := 31; -- r/-: XIP access in progress |
-- |
signal ctrl : std_ulogic_vector(26 downto 0); |
|
-- Direct SPI access registers -- |
signal spi_data_lo : std_ulogic_vector(31 downto 0); |
signal spi_data_hi : std_ulogic_vector(31 downto 0); -- write-only! |
signal spi_trigger : std_ulogic; -- trigger direct SPI operation |
|
-- XIP access address -- |
signal xip_addr : std_ulogic_vector(31 downto 0); |
|
-- SPI access fetch arbiter -- |
type arbiter_state_t is (S_DIRECT, S_IDLE, S_TRIG, S_BUSY); |
type arbiter_t is record |
state : arbiter_state_t; |
state_nxt : arbiter_state_t; |
addr : std_ulogic_vector(31 downto 0); |
busy : std_ulogic; |
end record; |
signal arbiter : arbiter_t; |
|
-- SPI clock -- |
signal spi_clk_en : std_ulogic; |
|
-- Component: SPI PHY -- |
component neorv32_xip_phy |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- clock |
spi_clk_en_i : in std_ulogic; -- pre-scaled SPI clock-enable |
-- operation configuration -- |
cf_enable_i : in std_ulogic; -- module enable (reset if low) |
cf_cpha_i : in std_ulogic; -- clock phase |
cf_cpol_i : in std_ulogic; -- clock idle polarity |
-- operation control -- |
op_start_i : in std_ulogic; -- trigger new transmission |
op_csen_i : in std_ulogic; -- actually enabled device for transmission |
op_busy_o : out std_ulogic; -- transmission in progress when set |
op_nbytes_i : in std_ulogic_vector(03 downto 0); -- actual number of bytes to transmit (1..9) |
op_wdata_i : in std_ulogic_vector(71 downto 0); -- write data |
op_rdata_o : out std_ulogic_vector(31 downto 0); -- read data |
-- SPI interface -- |
spi_csn_o : out std_ulogic; |
spi_clk_o : out std_ulogic; |
spi_data_i : in std_ulogic; |
spi_data_o : out std_ulogic |
); |
end component; |
|
-- PHY interface -- |
type phy_if_t is record |
start : std_ulogic; -- trigger new transmission |
busy : std_ulogic; -- transmission in progress when set |
wdata : std_ulogic_vector(71 downto 0); -- write data |
rdata : std_ulogic_vector(31 downto 0); -- read data |
end record; |
signal phy_if : phy_if_t; |
|
begin |
|
-- Access Control (IO/CTRL port) ---------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ct_acc_en <= '1' when (ct_addr_i(hi_abb_c downto lo_abb_c) = xip_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
ct_addr <= xip_base_c(31 downto lo_abb_c) & ct_addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned |
ct_wren <= ct_acc_en and ct_wren_i; |
ct_rden <= ct_acc_en and ct_rden_i; |
|
|
-- Control Read/Write Access -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ctrl_rw_access : process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
ctrl <= (others => '-'); |
ctrl(ctrl_enable_c) <= '0'; -- required |
ctrl(ctrl_xip_enable_c) <= '0'; -- required |
spi_data_lo <= (others => '-'); |
spi_data_hi <= (others => '-'); |
spi_trigger <= '-'; |
-- |
ct_data_o <= (others => '-'); |
ct_ack_o <= '-'; |
elsif rising_edge(clk_i) then |
-- access acknowledge -- |
ct_ack_o <= ct_wren or ct_rden; |
|
-- defaults -- |
spi_trigger <= '0'; |
|
-- write access -- |
if (ct_wren = '1') then -- only full-word writes! |
|
-- control register -- |
if (ct_addr = xip_ctrl_addr_c) then |
ctrl(ctrl_enable_c) <= ct_data_i(ctrl_enable_c); |
ctrl(ctrl_spi_prsc2_c downto ctrl_spi_prsc0_c) <= ct_data_i(ctrl_spi_prsc2_c downto ctrl_spi_prsc0_c); |
ctrl(ctrl_spi_cpol_c) <= ct_data_i(ctrl_spi_cpol_c); |
ctrl(ctrl_spi_cpha_c) <= ct_data_i(ctrl_spi_cpha_c); |
ctrl(ctrl_spi_nbytes3_c downto ctrl_spi_nbytes0_c) <= ct_data_i(ctrl_spi_nbytes3_c downto ctrl_spi_nbytes0_c); |
ctrl(ctrl_xip_enable_c) <= ct_data_i(ctrl_xip_enable_c); |
ctrl(ctrl_xip_abytes1_c downto ctrl_xip_abytes0_c) <= ct_data_i(ctrl_xip_abytes1_c downto ctrl_xip_abytes0_c); |
ctrl(ctrl_rd_cmd7_c downto ctrl_rd_cmd0_c) <= ct_data_i(ctrl_rd_cmd7_c downto ctrl_rd_cmd0_c); |
ctrl(ctrl_page3_c downto ctrl_page0_c) <= ct_data_i(ctrl_page3_c downto ctrl_page0_c); |
ctrl(ctrl_spi_csen_c) <= ct_data_i(ctrl_spi_csen_c); |
ctrl(ctrl_highspeed_c) <= ct_data_i(ctrl_highspeed_c); |
end if; |
|
-- SPI direct data access register lo -- |
if (ct_addr = xip_data_lo_addr_c) then |
spi_data_lo <= ct_data_i; |
end if; |
|
-- SPI direct data access register hi -- |
if (ct_addr = xip_data_hi_addr_c) then |
spi_data_hi <= ct_data_i; |
spi_trigger <= '1'; -- trigger direct SPI transaction |
end if; |
end if; |
|
-- read access -- |
ct_data_o <= (others => '0'); |
if (ct_rden = '1') then |
case ct_addr(3 downto 2) is |
when "00" => -- 'xip_ctrl_addr_c' - control register |
ct_data_o(ctrl_enable_c) <= ctrl(ctrl_enable_c); |
ct_data_o(ctrl_spi_prsc2_c downto ctrl_spi_prsc0_c) <= ctrl(ctrl_spi_prsc2_c downto ctrl_spi_prsc0_c); |
ct_data_o(ctrl_spi_cpol_c) <= ctrl(ctrl_spi_cpol_c); |
ct_data_o(ctrl_spi_cpha_c) <= ctrl(ctrl_spi_cpha_c); |
ct_data_o(ctrl_spi_nbytes3_c downto ctrl_spi_nbytes0_c) <= ctrl(ctrl_spi_nbytes3_c downto ctrl_spi_nbytes0_c); |
ct_data_o(ctrl_xip_enable_c) <= ctrl(ctrl_xip_enable_c); |
ct_data_o(ctrl_xip_abytes1_c downto ctrl_xip_abytes0_c) <= ctrl(ctrl_xip_abytes1_c downto ctrl_xip_abytes0_c); |
ct_data_o(ctrl_rd_cmd7_c downto ctrl_rd_cmd0_c) <= ctrl(ctrl_rd_cmd7_c downto ctrl_rd_cmd0_c); |
ct_data_o(ctrl_page3_c downto ctrl_page0_c) <= ctrl(ctrl_page3_c downto ctrl_page0_c); |
ct_data_o(ctrl_spi_csen_c) <= ctrl(ctrl_spi_csen_c); |
ct_data_o(ctrl_highspeed_c) <= ctrl(ctrl_highspeed_c); |
-- |
ct_data_o(ctrl_phy_busy_c) <= phy_if.busy; |
ct_data_o(ctrl_xip_busy_c) <= arbiter.busy; |
when "10" => -- 'xip_data_lo_addr_c' - SPI direct data access register lo |
ct_data_o <= phy_if.rdata; |
when others => -- unavailable (not implemented or write-only) |
ct_data_o <= (others => '0'); |
end case; |
end if; |
end if; |
end process ctrl_rw_access; |
|
-- XIP enabled -- |
xip_en_o <= ctrl(ctrl_enable_c); |
|
-- XIP page output -- |
xip_page_o <= ctrl(ctrl_page3_c downto ctrl_page0_c); |
|
|
-- XIP Address Computation Logic ---------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
xip_access_logic: process(arbiter.addr, ctrl) |
variable tmp_v : std_ulogic_vector(31 downto 0); |
begin |
tmp_v(31 downto 28) := "0000"; |
tmp_v(27 downto 00) := arbiter.addr(27 downto 00); |
case ctrl(ctrl_xip_abytes1_c downto ctrl_xip_abytes0_c) is -- shift address bits to be MSB-aligned |
when "00" => xip_addr <= tmp_v(07 downto 0) & x"000000"; -- 1 address byte |
when "01" => xip_addr <= tmp_v(15 downto 0) & x"0000"; -- 2 address bytes |
when "10" => xip_addr <= tmp_v(23 downto 0) & x"00"; -- 3 address bytes |
when others => xip_addr <= tmp_v(31 downto 0); -- 4 address bytes |
end case; |
end process xip_access_logic; |
|
|
-- SPI Access Arbiter --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
arbiter_sync: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (ctrl(ctrl_enable_c) = '0') or (ctrl(ctrl_xip_enable_c) = '0') then -- sync reset |
arbiter.state <= S_DIRECT; |
else |
arbiter.state <= arbiter.state_nxt; |
end if; |
arbiter.addr <= if_addr_i; -- buffer address (reducing fan-out on CPU's address net) |
end if; |
end process arbiter_sync; |
|
|
-- FSM - combinatorial part -- |
arbiter_comb: process(arbiter, ctrl, xip_addr, phy_if, if_rden_i, if_addr_i, spi_data_hi, spi_data_lo, spi_trigger) |
begin |
-- arbiter defaults -- |
arbiter.state_nxt <= arbiter.state; |
|
-- bus interface defaults -- |
if_data_o <= (others => '0'); |
if_ack_o <= '0'; |
|
-- SPI PHY interface defaults -- |
phy_if.start <= '0'; |
phy_if.wdata <= ctrl(ctrl_rd_cmd7_c downto ctrl_rd_cmd0_c) & xip_addr & x"00000000"; -- MSB-aligned: CMD + address + 32-bit zero data |
|
-- fsm -- |
case arbiter.state is |
|
when S_DIRECT => -- XIP access disabled: allow direct SPI access |
-- ------------------------------------------------------------ |
phy_if.wdata <= spi_data_hi & spi_data_lo & x"00"; -- MSB-aligned data |
phy_if.start <= spi_trigger; |
arbiter.state_nxt <= S_IDLE; |
|
when S_IDLE => -- XIP: wait for new bus request |
-- ------------------------------------------------------------ |
if (if_rden_i = '1') and (if_addr_i(31 downto 28) = ctrl(ctrl_page3_c downto ctrl_page0_c)) then |
arbiter.state_nxt <= S_TRIG; |
end if; |
|
when S_TRIG => -- XIP: trigger flash read |
-- ------------------------------------------------------------ |
phy_if.start <= '1'; |
arbiter.state_nxt <= S_BUSY; |
|
when S_BUSY => -- XIP: wait for PHY to complete operation |
-- ------------------------------------------------------------ |
if (phy_if.busy = '0') then |
if_data_o <= phy_if.rdata; |
if_ack_o <= '1'; |
arbiter.state_nxt <= S_IDLE; |
end if; |
|
when others => -- undefined |
-- ------------------------------------------------------------ |
arbiter.state_nxt <= S_IDLE; |
|
end case; |
end process arbiter_comb; |
|
-- arbiter status -- |
arbiter.busy <= '1' when (arbiter.state = S_TRIG) or (arbiter.state = S_BUSY) else '0'; -- actual XIP access in progress |
|
-- status output -- |
xip_acc_o <= arbiter.busy; |
|
|
-- SPI Clock Generator -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- enable clock generator -- |
clkgen_en_o <= ctrl(ctrl_enable_c); |
|
-- clock select -- |
spi_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_spi_prsc2_c downto ctrl_spi_prsc0_c)))) or ctrl(ctrl_highspeed_c); |
|
|
-- SPI Physical Interface ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_xip_phy_inst: neorv32_xip_phy |
port map ( |
-- global control -- |
clk_i => clk_i, |
spi_clk_en_i => spi_clk_en, |
-- operation configuration -- |
cf_enable_i => ctrl(ctrl_enable_c), -- module enable (reset if low) |
cf_cpha_i => ctrl(ctrl_spi_cpha_c), -- clock phase |
cf_cpol_i => ctrl(ctrl_spi_cpol_c), -- clock idle polarity |
-- operation control -- |
op_start_i => phy_if.start, -- trigger new transmission |
op_csen_i => ctrl(ctrl_spi_csen_c), -- actually enabled device for transmission |
op_busy_o => phy_if.busy, -- transmission in progress when set |
op_nbytes_i => ctrl(ctrl_spi_nbytes3_c downto ctrl_spi_nbytes0_c), -- actual number of bytes to transmit |
op_wdata_i => phy_if.wdata, -- write data |
op_rdata_o => phy_if.rdata, -- read data |
-- SPI interface -- |
spi_csn_o => spi_csn_o, |
spi_clk_o => spi_clk_o, |
spi_data_i => spi_data_i, |
spi_data_o => spi_data_o |
); |
|
|
end neorv32_xip_rtl; |
|
|
-- ############################################################################################################################ |
-- ############################################################################################################################ |
|
|
-- ################################################################################################# |
-- # << NEORV32 - XIP Module - SPI Physical Interface >> # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_xip_phy is |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- clock |
spi_clk_en_i : in std_ulogic; -- pre-scaled SPI clock-enable |
-- operation configuration -- |
cf_enable_i : in std_ulogic; -- module enable (reset if low) |
cf_cpha_i : in std_ulogic; -- clock phase |
cf_cpol_i : in std_ulogic; -- clock idle polarity |
-- operation control -- |
op_start_i : in std_ulogic; -- trigger new transmission |
op_csen_i : in std_ulogic; -- actually enabled device for transmission |
op_busy_o : out std_ulogic; -- transmission in progress when set |
op_nbytes_i : in std_ulogic_vector(03 downto 0); -- actual number of bytes to transmit (1..9) |
op_wdata_i : in std_ulogic_vector(71 downto 0); -- write data |
op_rdata_o : out std_ulogic_vector(31 downto 0); -- read data |
-- SPI interface -- |
spi_csn_o : out std_ulogic; |
spi_clk_o : out std_ulogic; |
spi_data_i : in std_ulogic; |
spi_data_o : out std_ulogic |
); |
end neorv32_xip_phy; |
|
architecture neorv32_xip_phy_rtl of neorv32_xip_phy is |
|
-- controller -- |
type ctrl_state_t is (S_IDLE, S_START, S_RTX_A, S_RTX_B, S_DONE); |
type ctrl_t is record |
state : ctrl_state_t; |
sreg : std_ulogic_vector(71 downto 0); -- only the lowest 32-bit are used as RX data |
bitcnt : std_ulogic_vector(06 downto 0); |
di_sync : std_ulogic; |
csen : std_ulogic; |
end record; |
signal ctrl : ctrl_t; |
|
begin |
|
-- Serial Interface Control Unit ---------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
control_unit: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (cf_enable_i = '0') then |
spi_clk_o <= '0'; |
spi_csn_o <= '1'; |
-- |
ctrl.state <= S_IDLE; |
ctrl.csen <= '-'; |
ctrl.sreg <= (others => '-'); |
ctrl.bitcnt <= (others => '-'); |
ctrl.di_sync <= '-'; |
else |
-- defaults -- |
spi_clk_o <= cf_cpol_i; |
spi_csn_o <= '1'; -- de-selected by default |
ctrl.di_sync <= spi_data_i; |
|
-- fsm -- |
case ctrl.state is |
|
when S_IDLE => -- wait for new transmission trigger |
-- ------------------------------------------------------------ |
ctrl.bitcnt <= op_nbytes_i & "000"; -- number of bytes |
ctrl.csen <= op_csen_i; |
if (op_start_i = '1') then |
ctrl.sreg <= op_wdata_i; |
ctrl.state <= S_START; |
end if; |
|
when S_START => -- sync start of transmission |
-- ------------------------------------------------------------ |
spi_csn_o <= not ctrl.csen; |
if (spi_clk_en_i = '1') then |
ctrl.state <= S_RTX_A; |
end if; |
|
when S_RTX_A => -- first half of bit transmission |
-- ------------------------------------------------------------ |
spi_csn_o <= not ctrl.csen; |
spi_clk_o <= cf_cpha_i xor cf_cpol_i; |
if (spi_clk_en_i = '1') then |
ctrl.bitcnt <= std_ulogic_vector(unsigned(ctrl.bitcnt) - 1); |
ctrl.state <= S_RTX_B; |
end if; |
|
when S_RTX_B => -- second half of bit transmission |
-- ------------------------------------------------------------ |
spi_csn_o <= not ctrl.csen; |
spi_clk_o <= not (cf_cpha_i xor cf_cpol_i); |
if (spi_clk_en_i = '1') then |
ctrl.sreg <= ctrl.sreg(ctrl.sreg'left-1 downto 0) & ctrl.di_sync; |
if (or_reduce_f(ctrl.bitcnt) = '0') then -- all bits transferred? |
ctrl.state <= S_DONE; -- transmission done |
else |
ctrl.state <= S_RTX_A; -- next bit |
end if; |
end if; |
|
when S_DONE => -- transmission done |
-- ------------------------------------------------------------ |
spi_csn_o <= not ctrl.csen; |
if (spi_clk_en_i = '1') then |
ctrl.state <= S_IDLE; |
end if; |
|
when others => -- undefined |
-- ------------------------------------------------------------ |
ctrl.state <= S_IDLE; |
|
end case; |
end if; |
end if; |
end process control_unit; |
|
-- serial unit busy -- |
op_busy_o <= '0' when (ctrl.state = S_IDLE) else '1'; |
|
-- serial data output -- |
spi_data_o <= ctrl.sreg(ctrl.sreg'left); |
|
-- RX data -- |
op_rdata_o <= ctrl.sreg(31 downto 0); |
|
|
end neorv32_xip_phy_rtl; |
/neorv32_xirq.vhd
62,7 → 62,7
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
-- external interrupt lines -- |
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); |
xirq_i : in std_ulogic_vector(31 downto 0); |
-- CPU interrupt -- |
cpu_irq_o : out std_ulogic |
); |
155,7 → 155,7
irq_trigger: process(clk_i) |
begin |
if rising_edge(clk_i) then |
irq_sync <= xirq_i; |
irq_sync <= xirq_i(XIRQ_NUM_CH-1 downto 0); |
irq_sync2 <= irq_sync; |
end if; |
end process irq_trigger; |