URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/rtl/core
- from Rev 70 to Rev 71
- ↔ Reverse comparison
Rev 70 → Rev 71
/neorv32_application_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin> |
-- Size: 3448 bytes |
-- Size: 3424 bytes |
|
library ieee; |
use ieee.std_logic_1164.all; |
67,7 → 67,7
00000053 => x"00158593", |
00000054 => x"ff5ff06f", |
00000055 => x"00001597", |
00000056 => x"c9c58593", |
00000056 => x"c8458593", |
00000057 => x"80000617", |
00000058 => x"f1c60613", |
00000059 => x"80000697", |
114,15 → 114,15
00000100 => x"b0050513", |
00000101 => x"00112623", |
00000102 => x"088000ef", |
00000103 => x"768000ef", |
00000103 => x"750000ef", |
00000104 => x"00050c63", |
00000105 => x"714000ef", |
00000105 => x"6fc000ef", |
00000106 => x"00001537", |
00000107 => x"ab050513", |
00000107 => x"a9850513", |
00000108 => x"134000ef", |
00000109 => x"020000ef", |
00000110 => x"00001537", |
00000111 => x"a8c50513", |
00000111 => x"a7450513", |
00000112 => x"124000ef", |
00000113 => x"00c12083", |
00000114 => x"00100513", |
133,14 → 133,14
00000119 => x"00000593", |
00000120 => x"00112623", |
00000121 => x"00812423", |
00000122 => x"72c000ef", |
00000122 => x"714000ef", |
00000123 => x"00000513", |
00000124 => x"00150413", |
00000125 => x"00000593", |
00000126 => x"0ff57513", |
00000127 => x"718000ef", |
00000127 => x"700000ef", |
00000128 => x"0c800513", |
00000129 => x"164000ef", |
00000129 => x"14c000ef", |
00000130 => x"00040513", |
00000131 => x"fe5ff06f", |
00000132 => x"fe802503", |
157,7 → 157,7
00000143 => x"00151593", |
00000144 => x"00078513", |
00000145 => x"00060493", |
00000146 => x"798000ef", |
00000146 => x"780000ef", |
00000147 => x"01051513", |
00000148 => x"000017b7", |
00000149 => x"01055513", |
218,661 → 218,655
00000204 => x"00048513", |
00000205 => x"f99ff0ef", |
00000206 => x"fc9ff06f", |
00000207 => x"ff010113", |
00000208 => x"c81026f3", |
00000209 => x"c0102773", |
00000210 => x"c81027f3", |
00000211 => x"fed79ae3", |
00000212 => x"00e12023", |
00000213 => x"00f12223", |
00000214 => x"00012503", |
00000215 => x"00412583", |
00000216 => x"01010113", |
00000217 => x"00008067", |
00000218 => x"fd010113", |
00000219 => x"00a12623", |
00000220 => x"fe002503", |
00000221 => x"3e800593", |
00000222 => x"02112623", |
00000223 => x"02812423", |
00000224 => x"02912223", |
00000225 => x"03212023", |
00000226 => x"01312e23", |
00000227 => x"654000ef", |
00000228 => x"00c12603", |
00000229 => x"00000693", |
00000230 => x"00000593", |
00000231 => x"5ac000ef", |
00000232 => x"00050413", |
00000233 => x"00058993", |
00000234 => x"f95ff0ef", |
00000235 => x"00058913", |
00000236 => x"00050493", |
00000237 => x"f89ff0ef", |
00000238 => x"00b96663", |
00000239 => x"05259263", |
00000240 => x"04a4f063", |
00000241 => x"008484b3", |
00000242 => x"0084b433", |
00000243 => x"01390933", |
00000244 => x"01240433", |
00000245 => x"f69ff0ef", |
00000246 => x"fe85eee3", |
00000247 => x"00b41463", |
00000248 => x"fe956ae3", |
00000249 => x"02c12083", |
00000250 => x"02812403", |
00000251 => x"02412483", |
00000252 => x"02012903", |
00000253 => x"01c12983", |
00000254 => x"03010113", |
00000255 => x"00008067", |
00000256 => x"01c99913", |
00000257 => x"00445413", |
00000258 => x"00896433", |
00000259 => x"00040a63", |
00000260 => x"00040863", |
00000261 => x"fff40413", |
00000262 => x"00000013", |
00000263 => x"ff1ff06f", |
00000264 => x"fc5ff06f", |
00000265 => x"fc010113", |
00000266 => x"02112e23", |
00000267 => x"02512c23", |
00000268 => x"02612a23", |
00000269 => x"02712823", |
00000270 => x"02a12623", |
00000271 => x"02b12423", |
00000272 => x"02c12223", |
00000273 => x"02d12023", |
00000274 => x"00e12e23", |
00000275 => x"00f12c23", |
00000276 => x"01012a23", |
00000277 => x"01112823", |
00000278 => x"01c12623", |
00000279 => x"01d12423", |
00000280 => x"01e12223", |
00000281 => x"01f12023", |
00000282 => x"34102773", |
00000283 => x"34071073", |
00000284 => x"342027f3", |
00000285 => x"0407c463", |
00000286 => x"00071683", |
00000287 => x"00300593", |
00000288 => x"0036f693", |
00000289 => x"00270613", |
00000290 => x"00b69463", |
00000291 => x"00470613", |
00000292 => x"34161073", |
00000293 => x"00b00713", |
00000294 => x"00f77663", |
00000295 => x"69000793", |
00000296 => x"0500006f", |
00000297 => x"00001737", |
00000298 => x"00279793", |
00000299 => x"acc70713", |
00000300 => x"00e787b3", |
00000301 => x"0007a783", |
00000302 => x"00078067", |
00000303 => x"80000737", |
00000304 => x"ffd74713", |
00000207 => x"c81027f3", |
00000208 => x"c0102573", |
00000209 => x"c81025f3", |
00000210 => x"fef59ae3", |
00000211 => x"00008067", |
00000212 => x"fd010113", |
00000213 => x"00a12623", |
00000214 => x"fe002503", |
00000215 => x"3e800593", |
00000216 => x"02112623", |
00000217 => x"02812423", |
00000218 => x"02912223", |
00000219 => x"03212023", |
00000220 => x"01312e23", |
00000221 => x"654000ef", |
00000222 => x"00c12603", |
00000223 => x"00000693", |
00000224 => x"00000593", |
00000225 => x"5ac000ef", |
00000226 => x"00050413", |
00000227 => x"00058993", |
00000228 => x"fadff0ef", |
00000229 => x"00058913", |
00000230 => x"00050493", |
00000231 => x"fa1ff0ef", |
00000232 => x"00b96663", |
00000233 => x"05259263", |
00000234 => x"04a4f063", |
00000235 => x"008484b3", |
00000236 => x"0084b433", |
00000237 => x"01390933", |
00000238 => x"01240433", |
00000239 => x"f81ff0ef", |
00000240 => x"fe85eee3", |
00000241 => x"00b41463", |
00000242 => x"fe956ae3", |
00000243 => x"02c12083", |
00000244 => x"02812403", |
00000245 => x"02412483", |
00000246 => x"02012903", |
00000247 => x"01c12983", |
00000248 => x"03010113", |
00000249 => x"00008067", |
00000250 => x"01c99913", |
00000251 => x"00445413", |
00000252 => x"00896433", |
00000253 => x"00040a63", |
00000254 => x"00040863", |
00000255 => x"fff40413", |
00000256 => x"00000013", |
00000257 => x"ff1ff06f", |
00000258 => x"fc5ff06f", |
00000259 => x"fc010113", |
00000260 => x"02112e23", |
00000261 => x"02512c23", |
00000262 => x"02612a23", |
00000263 => x"02712823", |
00000264 => x"02a12623", |
00000265 => x"02b12423", |
00000266 => x"02c12223", |
00000267 => x"02d12023", |
00000268 => x"00e12e23", |
00000269 => x"00f12c23", |
00000270 => x"01012a23", |
00000271 => x"01112823", |
00000272 => x"01c12623", |
00000273 => x"01d12423", |
00000274 => x"01e12223", |
00000275 => x"01f12023", |
00000276 => x"34102773", |
00000277 => x"34071073", |
00000278 => x"342027f3", |
00000279 => x"0407c463", |
00000280 => x"00071683", |
00000281 => x"00300593", |
00000282 => x"0036f693", |
00000283 => x"00270613", |
00000284 => x"00b69463", |
00000285 => x"00470613", |
00000286 => x"34161073", |
00000287 => x"00b00713", |
00000288 => x"00f77663", |
00000289 => x"67800793", |
00000290 => x"0500006f", |
00000291 => x"00001737", |
00000292 => x"00279793", |
00000293 => x"ab470713", |
00000294 => x"00e787b3", |
00000295 => x"0007a783", |
00000296 => x"00078067", |
00000297 => x"80000737", |
00000298 => x"ffd74713", |
00000299 => x"00e787b3", |
00000300 => x"01c00713", |
00000301 => x"fcf768e3", |
00000302 => x"00001737", |
00000303 => x"00279793", |
00000304 => x"ae470713", |
00000305 => x"00e787b3", |
00000306 => x"01c00713", |
00000307 => x"fcf768e3", |
00000308 => x"00001737", |
00000309 => x"00279793", |
00000310 => x"afc70713", |
00000311 => x"00e787b3", |
00000312 => x"0007a783", |
00000313 => x"00078067", |
00000314 => x"800007b7", |
00000315 => x"0007a783", |
00000316 => x"000780e7", |
00000317 => x"03c12083", |
00000318 => x"03812283", |
00000319 => x"03412303", |
00000320 => x"03012383", |
00000321 => x"02c12503", |
00000322 => x"02812583", |
00000323 => x"02412603", |
00000324 => x"02012683", |
00000325 => x"01c12703", |
00000326 => x"01812783", |
00000327 => x"01412803", |
00000328 => x"01012883", |
00000329 => x"00c12e03", |
00000330 => x"00812e83", |
00000331 => x"00412f03", |
00000332 => x"00012f83", |
00000333 => x"04010113", |
00000334 => x"30200073", |
00000335 => x"800007b7", |
00000336 => x"0047a783", |
00000337 => x"fadff06f", |
00000338 => x"8081a783", |
00000339 => x"fa5ff06f", |
00000340 => x"80c1a783", |
00000341 => x"f9dff06f", |
00000342 => x"8101a783", |
00000343 => x"f95ff06f", |
00000344 => x"8141a783", |
00000345 => x"f8dff06f", |
00000346 => x"8181a783", |
00000347 => x"f85ff06f", |
00000348 => x"81c1a783", |
00000349 => x"f7dff06f", |
00000350 => x"8201a783", |
00000351 => x"f75ff06f", |
00000352 => x"8241a783", |
00000353 => x"f6dff06f", |
00000354 => x"8281a783", |
00000355 => x"f65ff06f", |
00000356 => x"82c1a783", |
00000357 => x"f5dff06f", |
00000358 => x"8301a783", |
00000359 => x"f55ff06f", |
00000360 => x"8341a783", |
00000361 => x"f4dff06f", |
00000362 => x"8381a783", |
00000363 => x"f45ff06f", |
00000364 => x"83c1a783", |
00000365 => x"f3dff06f", |
00000366 => x"8401a783", |
00000367 => x"f35ff06f", |
00000368 => x"8441a783", |
00000369 => x"f2dff06f", |
00000370 => x"8481a783", |
00000371 => x"f25ff06f", |
00000372 => x"84c1a783", |
00000373 => x"f1dff06f", |
00000374 => x"8501a783", |
00000375 => x"f15ff06f", |
00000376 => x"8541a783", |
00000377 => x"f0dff06f", |
00000378 => x"8581a783", |
00000379 => x"f05ff06f", |
00000380 => x"85c1a783", |
00000381 => x"efdff06f", |
00000382 => x"8601a783", |
00000383 => x"ef5ff06f", |
00000384 => x"8641a783", |
00000385 => x"eedff06f", |
00000386 => x"8681a783", |
00000387 => x"ee5ff06f", |
00000388 => x"86c1a783", |
00000389 => x"eddff06f", |
00000390 => x"8701a783", |
00000391 => x"ed5ff06f", |
00000392 => x"fe010113", |
00000393 => x"01212823", |
00000394 => x"00050913", |
00000395 => x"00001537", |
00000396 => x"00912a23", |
00000397 => x"b7050513", |
00000398 => x"000014b7", |
00000399 => x"00812c23", |
00000400 => x"01312623", |
00000401 => x"00112e23", |
00000402 => x"01c00413", |
00000403 => x"c99ff0ef", |
00000404 => x"d6848493", |
00000405 => x"ffc00993", |
00000406 => x"008957b3", |
00000407 => x"00f7f793", |
00000408 => x"00f487b3", |
00000409 => x"0007c503", |
00000410 => x"ffc40413", |
00000411 => x"c61ff0ef", |
00000412 => x"ff3414e3", |
00000413 => x"01c12083", |
00000414 => x"01812403", |
00000415 => x"01412483", |
00000416 => x"01012903", |
00000417 => x"00c12983", |
00000418 => x"02010113", |
00000419 => x"00008067", |
00000420 => x"ff010113", |
00000421 => x"00112623", |
00000422 => x"00812423", |
00000423 => x"00912223", |
00000424 => x"b71ff0ef", |
00000425 => x"1c050863", |
00000426 => x"00001537", |
00000427 => x"b7450513", |
00000428 => x"c35ff0ef", |
00000429 => x"34202473", |
00000430 => x"00900713", |
00000431 => x"00f47793", |
00000432 => x"03078493", |
00000433 => x"00f77463", |
00000434 => x"05778493", |
00000435 => x"00b00793", |
00000436 => x"0087ee63", |
00000437 => x"00001737", |
00000438 => x"00241793", |
00000439 => x"d3870713", |
00000440 => x"00e787b3", |
00000441 => x"0007a783", |
00000442 => x"00078067", |
00000443 => x"800007b7", |
00000444 => x"00b78713", |
00000445 => x"14e40e63", |
00000446 => x"02876a63", |
00000447 => x"00378713", |
00000448 => x"12e40c63", |
00000449 => x"00778793", |
00000450 => x"12f40e63", |
00000451 => x"00001537", |
00000452 => x"cd450513", |
00000453 => x"bd1ff0ef", |
00000454 => x"00040513", |
00000455 => x"f05ff0ef", |
00000456 => x"00100793", |
00000457 => x"08f40c63", |
00000458 => x"0280006f", |
00000459 => x"ff07c793", |
00000460 => x"00f407b3", |
00000461 => x"00f00713", |
00000462 => x"fcf76ae3", |
00000463 => x"00001537", |
00000464 => x"cc450513", |
00000465 => x"ba1ff0ef", |
00000466 => x"00048513", |
00000467 => x"b81ff0ef", |
00000468 => x"ffd47413", |
00000469 => x"00500793", |
00000470 => x"06f40263", |
00000471 => x"00001537", |
00000472 => x"d1850513", |
00000473 => x"b81ff0ef", |
00000474 => x"34002573", |
00000475 => x"eb5ff0ef", |
00000476 => x"00001537", |
00000477 => x"d2050513", |
00000478 => x"b6dff0ef", |
00000479 => x"34302573", |
00000480 => x"ea1ff0ef", |
00000481 => x"00812403", |
00000482 => x"00c12083", |
00000483 => x"00412483", |
00000484 => x"00001537", |
00000485 => x"d2c50513", |
00000486 => x"01010113", |
00000487 => x"b49ff06f", |
00000488 => x"00001537", |
00000489 => x"b7c50513", |
00000490 => x"b3dff0ef", |
00000491 => x"fb1ff06f", |
00000492 => x"00001537", |
00000493 => x"b9c50513", |
00000494 => x"b2dff0ef", |
00000495 => x"f7c02783", |
00000496 => x"0a07d463", |
00000497 => x"0017f793", |
00000498 => x"08078a63", |
00000306 => x"0007a783", |
00000307 => x"00078067", |
00000308 => x"800007b7", |
00000309 => x"0007a783", |
00000310 => x"000780e7", |
00000311 => x"03c12083", |
00000312 => x"03812283", |
00000313 => x"03412303", |
00000314 => x"03012383", |
00000315 => x"02c12503", |
00000316 => x"02812583", |
00000317 => x"02412603", |
00000318 => x"02012683", |
00000319 => x"01c12703", |
00000320 => x"01812783", |
00000321 => x"01412803", |
00000322 => x"01012883", |
00000323 => x"00c12e03", |
00000324 => x"00812e83", |
00000325 => x"00412f03", |
00000326 => x"00012f83", |
00000327 => x"04010113", |
00000328 => x"30200073", |
00000329 => x"800007b7", |
00000330 => x"0047a783", |
00000331 => x"fadff06f", |
00000332 => x"8081a783", |
00000333 => x"fa5ff06f", |
00000334 => x"80c1a783", |
00000335 => x"f9dff06f", |
00000336 => x"8101a783", |
00000337 => x"f95ff06f", |
00000338 => x"8141a783", |
00000339 => x"f8dff06f", |
00000340 => x"8181a783", |
00000341 => x"f85ff06f", |
00000342 => x"81c1a783", |
00000343 => x"f7dff06f", |
00000344 => x"8201a783", |
00000345 => x"f75ff06f", |
00000346 => x"8241a783", |
00000347 => x"f6dff06f", |
00000348 => x"8281a783", |
00000349 => x"f65ff06f", |
00000350 => x"82c1a783", |
00000351 => x"f5dff06f", |
00000352 => x"8301a783", |
00000353 => x"f55ff06f", |
00000354 => x"8341a783", |
00000355 => x"f4dff06f", |
00000356 => x"8381a783", |
00000357 => x"f45ff06f", |
00000358 => x"83c1a783", |
00000359 => x"f3dff06f", |
00000360 => x"8401a783", |
00000361 => x"f35ff06f", |
00000362 => x"8441a783", |
00000363 => x"f2dff06f", |
00000364 => x"8481a783", |
00000365 => x"f25ff06f", |
00000366 => x"84c1a783", |
00000367 => x"f1dff06f", |
00000368 => x"8501a783", |
00000369 => x"f15ff06f", |
00000370 => x"8541a783", |
00000371 => x"f0dff06f", |
00000372 => x"8581a783", |
00000373 => x"f05ff06f", |
00000374 => x"85c1a783", |
00000375 => x"efdff06f", |
00000376 => x"8601a783", |
00000377 => x"ef5ff06f", |
00000378 => x"8641a783", |
00000379 => x"eedff06f", |
00000380 => x"8681a783", |
00000381 => x"ee5ff06f", |
00000382 => x"86c1a783", |
00000383 => x"eddff06f", |
00000384 => x"8701a783", |
00000385 => x"ed5ff06f", |
00000386 => x"fe010113", |
00000387 => x"01212823", |
00000388 => x"00050913", |
00000389 => x"00001537", |
00000390 => x"00912a23", |
00000391 => x"b5850513", |
00000392 => x"000014b7", |
00000393 => x"00812c23", |
00000394 => x"01312623", |
00000395 => x"00112e23", |
00000396 => x"01c00413", |
00000397 => x"cb1ff0ef", |
00000398 => x"d5048493", |
00000399 => x"ffc00993", |
00000400 => x"008957b3", |
00000401 => x"00f7f793", |
00000402 => x"00f487b3", |
00000403 => x"0007c503", |
00000404 => x"ffc40413", |
00000405 => x"c79ff0ef", |
00000406 => x"ff3414e3", |
00000407 => x"01c12083", |
00000408 => x"01812403", |
00000409 => x"01412483", |
00000410 => x"01012903", |
00000411 => x"00c12983", |
00000412 => x"02010113", |
00000413 => x"00008067", |
00000414 => x"ff010113", |
00000415 => x"00112623", |
00000416 => x"00812423", |
00000417 => x"00912223", |
00000418 => x"b89ff0ef", |
00000419 => x"1c050863", |
00000420 => x"00001537", |
00000421 => x"b5c50513", |
00000422 => x"c4dff0ef", |
00000423 => x"34202473", |
00000424 => x"00900713", |
00000425 => x"00f47793", |
00000426 => x"03078493", |
00000427 => x"00f77463", |
00000428 => x"05778493", |
00000429 => x"00b00793", |
00000430 => x"0087ee63", |
00000431 => x"00001737", |
00000432 => x"00241793", |
00000433 => x"d2070713", |
00000434 => x"00e787b3", |
00000435 => x"0007a783", |
00000436 => x"00078067", |
00000437 => x"800007b7", |
00000438 => x"00b78713", |
00000439 => x"14e40e63", |
00000440 => x"02876a63", |
00000441 => x"00378713", |
00000442 => x"12e40c63", |
00000443 => x"00778793", |
00000444 => x"12f40e63", |
00000445 => x"00001537", |
00000446 => x"cbc50513", |
00000447 => x"be9ff0ef", |
00000448 => x"00040513", |
00000449 => x"f05ff0ef", |
00000450 => x"00100793", |
00000451 => x"08f40c63", |
00000452 => x"0280006f", |
00000453 => x"ff07c793", |
00000454 => x"00f407b3", |
00000455 => x"00f00713", |
00000456 => x"fcf76ae3", |
00000457 => x"00001537", |
00000458 => x"cac50513", |
00000459 => x"bb9ff0ef", |
00000460 => x"00048513", |
00000461 => x"b99ff0ef", |
00000462 => x"ffd47413", |
00000463 => x"00500793", |
00000464 => x"06f40263", |
00000465 => x"00001537", |
00000466 => x"d0050513", |
00000467 => x"b99ff0ef", |
00000468 => x"34002573", |
00000469 => x"eb5ff0ef", |
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00000817 => x"74736146", |
00000818 => x"746e6920", |
00000819 => x"75727265", |
00000820 => x"00207470", |
00000821 => x"6e6b6e55", |
00000822 => x"206e776f", |
00000823 => x"70617274", |
00000824 => x"75616320", |
00000825 => x"203a6573", |
00000826 => x"00000000", |
00000827 => x"49545b20", |
00000828 => x"554f454d", |
00000829 => x"52455f54", |
00000830 => x"00005d52", |
00000831 => x"45445b20", |
00000832 => x"45434956", |
00000833 => x"5252455f", |
00000834 => x"0000005d", |
00000835 => x"4d505b20", |
00000836 => x"52455f50", |
00000837 => x"00005d52", |
00000838 => x"50204020", |
00000839 => x"00003d43", |
00000840 => x"544d202c", |
00000841 => x"3d4c4156", |
00000842 => x"00000000", |
00000843 => x"522f3c20", |
00000844 => x"0a3e4554", |
00000845 => x"00000000", |
00000846 => x"000007a0", |
00000847 => x"000007b0", |
00000848 => x"000007d8", |
00000849 => x"000007e4", |
00000850 => x"000007f0", |
00000851 => x"000007fc", |
00000852 => x"00000808", |
00000853 => x"00000814", |
00000854 => x"00000820", |
00000855 => x"0000070c", |
00000856 => x"0000070c", |
00000857 => x"0000082c", |
00000858 => x"33323130", |
00000859 => x"37363534", |
00000860 => x"42413938", |
00000861 => x"46454443" |
00000806 => x"65747865", |
00000807 => x"6c616e72", |
00000808 => x"746e6920", |
00000809 => x"75727265", |
00000810 => x"00007470", |
00000811 => x"74736146", |
00000812 => x"746e6920", |
00000813 => x"75727265", |
00000814 => x"00207470", |
00000815 => x"6e6b6e55", |
00000816 => x"206e776f", |
00000817 => x"70617274", |
00000818 => x"75616320", |
00000819 => x"203a6573", |
00000820 => x"00000000", |
00000821 => x"49545b20", |
00000822 => x"554f454d", |
00000823 => x"52455f54", |
00000824 => x"00005d52", |
00000825 => x"45445b20", |
00000826 => x"45434956", |
00000827 => x"5252455f", |
00000828 => x"0000005d", |
00000829 => x"4d505b20", |
00000830 => x"52455f50", |
00000831 => x"00005d52", |
00000832 => x"50204020", |
00000833 => x"00003d43", |
00000834 => x"544d202c", |
00000835 => x"3d4c4156", |
00000836 => x"00000000", |
00000837 => x"522f3c20", |
00000838 => x"0a3e4554", |
00000839 => x"00000000", |
00000840 => x"00000788", |
00000841 => x"00000798", |
00000842 => x"000007c0", |
00000843 => x"000007cc", |
00000844 => x"000007d8", |
00000845 => x"000007e4", |
00000846 => x"000007f0", |
00000847 => x"000007fc", |
00000848 => x"00000808", |
00000849 => x"000006f4", |
00000850 => x"000006f4", |
00000851 => x"00000814", |
00000852 => x"33323130", |
00000853 => x"37363534", |
00000854 => x"42413938", |
00000855 => x"46454443" |
); |
|
end neorv32_application_image; |
/neorv32_bootloader_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for BOOTLOADER) from source file <bootloader/main.bin> |
-- Size: 4040 bytes |
-- Size: 4016 bytes |
|
library ieee; |
use ieee.std_logic_1164.all; |
51,7 → 51,7
00000037 => x"00158593", |
00000038 => x"ff5ff06f", |
00000039 => x"00001597", |
00000040 => x"f2c58593", |
00000040 => x"f1458593", |
00000041 => x"80010617", |
00000042 => x"f5c60613", |
00000043 => x"80010697", |
111,13 → 111,13
00000097 => x"00000613", |
00000098 => x"00000593", |
00000099 => x"00200513", |
00000100 => x"369000ef", |
00000101 => x"3fd000ef", |
00000100 => x"351000ef", |
00000101 => x"3e5000ef", |
00000102 => x"00048493", |
00000103 => x"00050863", |
00000104 => x"00100513", |
00000105 => x"00000593", |
00000106 => x"429000ef", |
00000106 => x"411000ef", |
00000107 => x"00005537", |
00000108 => x"00000613", |
00000109 => x"00000593", |
136,46 → 136,46
00000122 => x"30479073", |
00000123 => x"30046073", |
00000124 => x"ffff1537", |
00000125 => x"ef850513", |
00000125 => x"ee050513", |
00000126 => x"27d000ef", |
00000127 => x"f1302573", |
00000128 => x"23c000ef", |
00000129 => x"ffff1537", |
00000130 => x"f3050513", |
00000130 => x"f1850513", |
00000131 => x"269000ef", |
00000132 => x"fe002503", |
00000133 => x"228000ef", |
00000134 => x"ffff1537", |
00000135 => x"f3850513", |
00000135 => x"f2050513", |
00000136 => x"255000ef", |
00000137 => x"30102573", |
00000138 => x"214000ef", |
00000139 => x"ffff1537", |
00000140 => x"f4050513", |
00000140 => x"f2850513", |
00000141 => x"241000ef", |
00000142 => x"fe402503", |
00000143 => x"ffff1437", |
00000144 => x"1fc000ef", |
00000145 => x"ffff1537", |
00000146 => x"f4850513", |
00000146 => x"f3050513", |
00000147 => x"229000ef", |
00000148 => x"fe802503", |
00000149 => x"1e8000ef", |
00000150 => x"ffff1537", |
00000151 => x"f5050513", |
00000151 => x"f3850513", |
00000152 => x"215000ef", |
00000153 => x"ff802503", |
00000154 => x"1d4000ef", |
00000155 => x"f5840513", |
00000155 => x"f4040513", |
00000156 => x"205000ef", |
00000157 => x"ff002503", |
00000158 => x"1c4000ef", |
00000159 => x"ffff1537", |
00000160 => x"f6450513", |
00000160 => x"f4c50513", |
00000161 => x"1f1000ef", |
00000162 => x"ffc02503", |
00000163 => x"1b0000ef", |
00000164 => x"f5840513", |
00000164 => x"f4040513", |
00000165 => x"1e1000ef", |
00000166 => x"ff402503", |
00000167 => x"1a0000ef", |
182,7 → 182,7
00000168 => x"0bd000ef", |
00000169 => x"06050663", |
00000170 => x"ffff1537", |
00000171 => x"f6c50513", |
00000171 => x"f5450513", |
00000172 => x"1c5000ef", |
00000173 => x"219000ef", |
00000174 => x"fe002403", |
199,13 → 199,13
00000185 => x"00100513", |
00000186 => x"4c8000ef", |
00000187 => x"ffff1537", |
00000188 => x"f9450513", |
00000188 => x"f7c50513", |
00000189 => x"181000ef", |
00000190 => x"0d4000ef", |
00000191 => x"16d000ef", |
00000192 => x"fc050ae3", |
00000193 => x"ffff1537", |
00000194 => x"f9850513", |
00000194 => x"f8050513", |
00000195 => x"169000ef", |
00000196 => x"0b0000ef", |
00000197 => x"ffff19b7", |
216,12 → 216,12
00000202 => x"07300c13", |
00000203 => x"ffff1937", |
00000204 => x"ffff1cb7", |
00000205 => x"fa498513", |
00000205 => x"f8c98513", |
00000206 => x"13d000ef", |
00000207 => x"11d000ef", |
00000208 => x"00050413", |
00000209 => x"0e1000ef", |
00000210 => x"f94a0513", |
00000210 => x"f7ca0513", |
00000211 => x"129000ef", |
00000212 => x"0ed000ef", |
00000213 => x"fe051ee3", |
246,19 → 246,19
00000232 => x"00f41c63", |
00000233 => x"0004a783", |
00000234 => x"f40798e3", |
00000235 => x"ea0c8513", |
00000235 => x"e88c8513", |
00000236 => x"0c5000ef", |
00000237 => x"f81ff06f", |
00000238 => x"fac90513", |
00000238 => x"f9490513", |
00000239 => x"ff5ff06f", |
00000240 => x"ffff1537", |
00000241 => x"de050513", |
00000241 => x"dc850513", |
00000242 => x"0ad0006f", |
00000243 => x"ff010113", |
00000244 => x"00112623", |
00000245 => x"30047073", |
00000246 => x"ffff1537", |
00000247 => x"e4450513", |
00000247 => x"e2c50513", |
00000248 => x"095000ef", |
00000249 => x"059000ef", |
00000250 => x"fe051ee3", |
269,7 → 269,7
00000255 => x"00812423", |
00000256 => x"00050413", |
00000257 => x"ffff1537", |
00000258 => x"e5450513", |
00000258 => x"e3c50513", |
00000259 => x"00112623", |
00000260 => x"065000ef", |
00000261 => x"03040513", |
276,11 → 276,11
00000262 => x"0ff57513", |
00000263 => x"009000ef", |
00000264 => x"30047073", |
00000265 => x"16d000ef", |
00000265 => x"155000ef", |
00000266 => x"00050863", |
00000267 => x"00100513", |
00000268 => x"00000593", |
00000269 => x"19d000ef", |
00000269 => x"185000ef", |
00000270 => x"0000006f", |
00000271 => x"fe010113", |
00000272 => x"01212823", |
287,7 → 287,7
00000273 => x"00050913", |
00000274 => x"ffff1537", |
00000275 => x"00912a23", |
00000276 => x"e6050513", |
00000276 => x"e4850513", |
00000277 => x"ffff14b7", |
00000278 => x"00812c23", |
00000279 => x"01312623", |
294,7 → 294,7
00000280 => x"00112e23", |
00000281 => x"01c00413", |
00000282 => x"00d000ef", |
00000283 => x"fb848493", |
00000283 => x"fa048493", |
00000284 => x"ffc00993", |
00000285 => x"008957b3", |
00000286 => x"00f7f793", |
333,10 → 333,10
00000319 => x"800007b7", |
00000320 => x"00778793", |
00000321 => x"08f49463", |
00000322 => x"089000ef", |
00000322 => x"071000ef", |
00000323 => x"00050663", |
00000324 => x"00000513", |
00000325 => x"08d000ef", |
00000325 => x"075000ef", |
00000326 => x"644000ef", |
00000327 => x"02050063", |
00000328 => x"7ac000ef", |
376,7 → 376,7
00000362 => x"5dc000ef", |
00000363 => x"04050263", |
00000364 => x"ffff1537", |
00000365 => x"e6450513", |
00000365 => x"e4c50513", |
00000366 => x"6bc000ef", |
00000367 => x"00048513", |
00000368 => x"e7dff0ef", |
389,7 → 389,7
00000375 => x"34302573", |
00000376 => x"e5dff0ef", |
00000377 => x"ffff1537", |
00000378 => x"e6c50513", |
00000378 => x"e5450513", |
00000379 => x"688000ef", |
00000380 => x"00440413", |
00000381 => x"34141073", |
398,14 → 398,14
00000384 => x"00000513", |
00000385 => x"00112623", |
00000386 => x"00812423", |
00000387 => x"72c000ef", |
00000387 => x"714000ef", |
00000388 => x"09e00513", |
00000389 => x"768000ef", |
00000389 => x"750000ef", |
00000390 => x"00000513", |
00000391 => x"760000ef", |
00000391 => x"748000ef", |
00000392 => x"00050413", |
00000393 => x"00000513", |
00000394 => x"730000ef", |
00000394 => x"718000ef", |
00000395 => x"00c12083", |
00000396 => x"0ff47513", |
00000397 => x"00812403", |
415,15 → 415,15
00000401 => x"00112623", |
00000402 => x"00812423", |
00000403 => x"00000513", |
00000404 => x"6e8000ef", |
00000404 => x"6d0000ef", |
00000405 => x"00500513", |
00000406 => x"724000ef", |
00000406 => x"70c000ef", |
00000407 => x"00000513", |
00000408 => x"71c000ef", |
00000408 => x"704000ef", |
00000409 => x"00050413", |
00000410 => x"00147413", |
00000411 => x"00000513", |
00000412 => x"6e8000ef", |
00000412 => x"6d0000ef", |
00000413 => x"fc041ce3", |
00000414 => x"00c12083", |
00000415 => x"00812403", |
432,13 → 432,13
00000418 => x"ff010113", |
00000419 => x"00000513", |
00000420 => x"00112623", |
00000421 => x"6a4000ef", |
00000421 => x"68c000ef", |
00000422 => x"00600513", |
00000423 => x"6e0000ef", |
00000423 => x"6c8000ef", |
00000424 => x"00c12083", |
00000425 => x"00000513", |
00000426 => x"01010113", |
00000427 => x"6ac0006f", |
00000427 => x"6940006f", |
00000428 => x"ff010113", |
00000429 => x"00812423", |
00000430 => x"00050413", |
445,30 → 445,30
00000431 => x"01055513", |
00000432 => x"0ff57513", |
00000433 => x"00112623", |
00000434 => x"6b4000ef", |
00000434 => x"69c000ef", |
00000435 => x"00845513", |
00000436 => x"0ff57513", |
00000437 => x"6a8000ef", |
00000437 => x"690000ef", |
00000438 => x"0ff47513", |
00000439 => x"00812403", |
00000440 => x"00c12083", |
00000441 => x"01010113", |
00000442 => x"6940006f", |
00000442 => x"67c0006f", |
00000443 => x"ff010113", |
00000444 => x"00812423", |
00000445 => x"00050413", |
00000446 => x"00000513", |
00000447 => x"00112623", |
00000448 => x"638000ef", |
00000448 => x"620000ef", |
00000449 => x"00300513", |
00000450 => x"674000ef", |
00000450 => x"65c000ef", |
00000451 => x"00040513", |
00000452 => x"fa1ff0ef", |
00000453 => x"00000513", |
00000454 => x"664000ef", |
00000454 => x"64c000ef", |
00000455 => x"00050413", |
00000456 => x"00000513", |
00000457 => x"634000ef", |
00000457 => x"61c000ef", |
00000458 => x"00c12083", |
00000459 => x"0ff47513", |
00000460 => x"00812403", |
521,7 → 521,7
00000507 => x"80418a13", |
00000508 => x"02051863", |
00000509 => x"ffff1537", |
00000510 => x"e7050513", |
00000510 => x"e5850513", |
00000511 => x"478000ef", |
00000512 => x"080005b7", |
00000513 => x"00040513", |
532,7 → 532,7
00000518 => x"00000513", |
00000519 => x"01c0006f", |
00000520 => x"ffff1537", |
00000521 => x"e9050513", |
00000521 => x"e7850513", |
00000522 => x"44c000ef", |
00000523 => x"dd1ff0ef", |
00000524 => x"fc0518e3", |
558,7 → 558,7
00000544 => x"00200513", |
00000545 => x"fa049ae3", |
00000546 => x"ffff1537", |
00000547 => x"e9c50513", |
00000547 => x"e8450513", |
00000548 => x"3e4000ef", |
00000549 => x"02c12083", |
00000550 => x"02812403", |
590,15 → 590,15
00000576 => x"00050493", |
00000577 => x"d85ff0ef", |
00000578 => x"00000513", |
00000579 => x"42c000ef", |
00000579 => x"414000ef", |
00000580 => x"00200513", |
00000581 => x"468000ef", |
00000581 => x"450000ef", |
00000582 => x"00048513", |
00000583 => x"d95ff0ef", |
00000584 => x"00040513", |
00000585 => x"458000ef", |
00000585 => x"440000ef", |
00000586 => x"00000513", |
00000587 => x"42c000ef", |
00000587 => x"414000ef", |
00000588 => x"00812403", |
00000589 => x"00c12083", |
00000590 => x"00412483", |
632,13 → 632,13
00000618 => x"00050413", |
00000619 => x"cddff0ef", |
00000620 => x"00000513", |
00000621 => x"384000ef", |
00000621 => x"36c000ef", |
00000622 => x"0d800513", |
00000623 => x"3c0000ef", |
00000623 => x"3a8000ef", |
00000624 => x"00040513", |
00000625 => x"cedff0ef", |
00000626 => x"00000513", |
00000627 => x"38c000ef", |
00000627 => x"374000ef", |
00000628 => x"00812403", |
00000629 => x"00c12083", |
00000630 => x"01010113", |
655,7 → 655,7
00000641 => x"01512223", |
00000642 => x"02041863", |
00000643 => x"ffff1537", |
00000644 => x"ea050513", |
00000644 => x"e8850513", |
00000645 => x"01812403", |
00000646 => x"01c12083", |
00000647 => x"01412483", |
666,17 → 666,17
00000652 => x"02010113", |
00000653 => x"2400006f", |
00000654 => x"ffff1537", |
00000655 => x"ebc50513", |
00000655 => x"ea450513", |
00000656 => x"234000ef", |
00000657 => x"00040513", |
00000658 => x"9f5ff0ef", |
00000659 => x"ffff1537", |
00000660 => x"ec450513", |
00000660 => x"eac50513", |
00000661 => x"220000ef", |
00000662 => x"08000537", |
00000663 => x"9e1ff0ef", |
00000664 => x"ffff1537", |
00000665 => x"edc50513", |
00000665 => x"ec450513", |
00000666 => x"20c000ef", |
00000667 => x"1ec000ef", |
00000668 => x"00050493", |
688,7 → 688,7
00000674 => x"00300513", |
00000675 => x"96dff0ef", |
00000676 => x"ffff1537", |
00000677 => x"ee850513", |
00000677 => x"ed050513", |
00000678 => x"01045493", |
00000679 => x"1d8000ef", |
00000680 => x"00148493", |
718,7 → 718,7
00000704 => x"412005b3", |
00000705 => x"e41ff0ef", |
00000706 => x"ffff1537", |
00000707 => x"e9c50513", |
00000707 => x"e8450513", |
00000708 => x"f05ff06f", |
00000709 => x"00090513", |
00000710 => x"e85ff0ef", |
830,197 → 830,191
00000816 => x"00048513", |
00000817 => x"f61ff0ef", |
00000818 => x"fc9ff06f", |
00000819 => x"ff010113", |
00000820 => x"c81026f3", |
00000821 => x"c0102773", |
00000822 => x"c81027f3", |
00000823 => x"fed79ae3", |
00000824 => x"00e12023", |
00000825 => x"00f12223", |
00000826 => x"00012503", |
00000827 => x"00412583", |
00000828 => x"01010113", |
00000829 => x"00008067", |
00000830 => x"00757513", |
00000831 => x"0036f793", |
00000832 => x"00167613", |
00000833 => x"00a51513", |
00000834 => x"00d79793", |
00000835 => x"0015f593", |
00000836 => x"00f567b3", |
00000837 => x"00f61613", |
00000838 => x"00c7e7b3", |
00000839 => x"00959593", |
00000819 => x"c81027f3", |
00000820 => x"c0102573", |
00000821 => x"c81025f3", |
00000822 => x"fef59ae3", |
00000823 => x"00008067", |
00000824 => x"00757513", |
00000825 => x"0036f793", |
00000826 => x"00167613", |
00000827 => x"00a51513", |
00000828 => x"00d79793", |
00000829 => x"0015f593", |
00000830 => x"00f567b3", |
00000831 => x"00f61613", |
00000832 => x"00c7e7b3", |
00000833 => x"00959593", |
00000834 => x"fa800713", |
00000835 => x"00b7e7b3", |
00000836 => x"00072023", |
00000837 => x"1007e793", |
00000838 => x"00f72023", |
00000839 => x"00008067", |
00000840 => x"fa800713", |
00000841 => x"00b7e7b3", |
00000842 => x"00072023", |
00000843 => x"1007e793", |
00000844 => x"00f72023", |
00000845 => x"00008067", |
00000846 => x"fa800713", |
00000847 => x"00072683", |
00000848 => x"00757793", |
00000849 => x"00100513", |
00000850 => x"00f51533", |
00000851 => x"00d56533", |
00000852 => x"00a72023", |
00000853 => x"00008067", |
00000854 => x"fa800713", |
00000855 => x"00072683", |
00000856 => x"00757513", |
00000857 => x"00100793", |
00000858 => x"00a797b3", |
00000859 => x"fff7c793", |
00000860 => x"00d7f7b3", |
00000861 => x"00f72023", |
00000862 => x"00008067", |
00000863 => x"faa02623", |
00000864 => x"fa802783", |
00000865 => x"fe07cee3", |
00000866 => x"fac02503", |
00000867 => x"00008067", |
00000868 => x"fe802503", |
00000869 => x"01055513", |
00000870 => x"00157513", |
00000871 => x"00008067", |
00000872 => x"00100793", |
00000873 => x"01f00713", |
00000874 => x"00a797b3", |
00000875 => x"00a74a63", |
00000876 => x"fc802703", |
00000877 => x"00f747b3", |
00000878 => x"fcf02423", |
00000879 => x"00008067", |
00000880 => x"fcc02703", |
00000881 => x"00f747b3", |
00000882 => x"fcf02623", |
00000883 => x"00008067", |
00000884 => x"fc000793", |
00000885 => x"00a7a423", |
00000886 => x"00b7a623", |
00000887 => x"00008067", |
00000888 => x"69617641", |
00000889 => x"6c62616c", |
00000890 => x"4d432065", |
00000891 => x"0a3a7344", |
00000892 => x"203a6820", |
00000893 => x"706c6548", |
00000894 => x"3a72200a", |
00000895 => x"73655220", |
00000896 => x"74726174", |
00000897 => x"3a75200a", |
00000898 => x"6c705520", |
00000899 => x"0a64616f", |
00000900 => x"203a7320", |
00000901 => x"726f7453", |
00000902 => x"6f742065", |
00000903 => x"616c6620", |
00000904 => x"200a6873", |
00000905 => x"4c203a6c", |
00000906 => x"2064616f", |
00000907 => x"6d6f7266", |
00000908 => x"616c6620", |
00000909 => x"200a6873", |
00000910 => x"45203a65", |
00000911 => x"75636578", |
00000912 => x"00006574", |
00000913 => x"746f6f42", |
00000914 => x"2e676e69", |
00000915 => x"0a0a2e2e", |
00000916 => x"00000000", |
00000917 => x"52450a07", |
00000918 => x"5f524f52", |
00000919 => x"00000000", |
00000920 => x"00007830", |
00000921 => x"52455b0a", |
00000922 => x"00002052", |
00000923 => x"00000a5d", |
00000924 => x"69617741", |
00000925 => x"676e6974", |
00000926 => x"6f656e20", |
00000927 => x"32337672", |
00000928 => x"6578655f", |
00000929 => x"6e69622e", |
00000930 => x"202e2e2e", |
00000931 => x"00000000", |
00000932 => x"64616f4c", |
00000933 => x"2e676e69", |
00000934 => x"00202e2e", |
00000935 => x"00004b4f", |
00000936 => x"65206f4e", |
00000937 => x"75636578", |
00000938 => x"6c626174", |
00000939 => x"76612065", |
00000940 => x"616c6961", |
00000941 => x"2e656c62", |
00000942 => x"00000000", |
00000943 => x"74697257", |
00000944 => x"00002065", |
00000945 => x"74796220", |
00000946 => x"74207365", |
00000947 => x"5053206f", |
00000948 => x"6c662049", |
00000949 => x"20687361", |
00000950 => x"00783040", |
00000951 => x"7928203f", |
00000952 => x"20296e2f", |
00000953 => x"00000000", |
00000954 => x"616c460a", |
00000955 => x"6e696873", |
00000956 => x"2e2e2e67", |
00000957 => x"00000020", |
00000958 => x"3c0a0a0a", |
00000959 => x"454e203c", |
00000960 => x"3356524f", |
00000961 => x"6f422032", |
00000962 => x"6f6c746f", |
00000963 => x"72656461", |
00000964 => x"0a3e3e20", |
00000965 => x"444c420a", |
00000966 => x"4e203a56", |
00000967 => x"3220766f", |
00000968 => x"30322038", |
00000969 => x"480a3132", |
00000970 => x"203a5657", |
00000971 => x"00000020", |
00000972 => x"4b4c430a", |
00000841 => x"00072683", |
00000842 => x"00757793", |
00000843 => x"00100513", |
00000844 => x"00f51533", |
00000845 => x"00d56533", |
00000846 => x"00a72023", |
00000847 => x"00008067", |
00000848 => x"fa800713", |
00000849 => x"00072683", |
00000850 => x"00757513", |
00000851 => x"00100793", |
00000852 => x"00a797b3", |
00000853 => x"fff7c793", |
00000854 => x"00d7f7b3", |
00000855 => x"00f72023", |
00000856 => x"00008067", |
00000857 => x"faa02623", |
00000858 => x"fa802783", |
00000859 => x"fe07cee3", |
00000860 => x"fac02503", |
00000861 => x"00008067", |
00000862 => x"fe802503", |
00000863 => x"01055513", |
00000864 => x"00157513", |
00000865 => x"00008067", |
00000866 => x"00100793", |
00000867 => x"01f00713", |
00000868 => x"00a797b3", |
00000869 => x"00a74a63", |
00000870 => x"fc802703", |
00000871 => x"00f747b3", |
00000872 => x"fcf02423", |
00000873 => x"00008067", |
00000874 => x"fcc02703", |
00000875 => x"00f747b3", |
00000876 => x"fcf02623", |
00000877 => x"00008067", |
00000878 => x"fc000793", |
00000879 => x"00a7a423", |
00000880 => x"00b7a623", |
00000881 => x"00008067", |
00000882 => x"69617641", |
00000883 => x"6c62616c", |
00000884 => x"4d432065", |
00000885 => x"0a3a7344", |
00000886 => x"203a6820", |
00000887 => x"706c6548", |
00000888 => x"3a72200a", |
00000889 => x"73655220", |
00000890 => x"74726174", |
00000891 => x"3a75200a", |
00000892 => x"6c705520", |
00000893 => x"0a64616f", |
00000894 => x"203a7320", |
00000895 => x"726f7453", |
00000896 => x"6f742065", |
00000897 => x"616c6620", |
00000898 => x"200a6873", |
00000899 => x"4c203a6c", |
00000900 => x"2064616f", |
00000901 => x"6d6f7266", |
00000902 => x"616c6620", |
00000903 => x"200a6873", |
00000904 => x"45203a65", |
00000905 => x"75636578", |
00000906 => x"00006574", |
00000907 => x"746f6f42", |
00000908 => x"2e676e69", |
00000909 => x"0a0a2e2e", |
00000910 => x"00000000", |
00000911 => x"52450a07", |
00000912 => x"5f524f52", |
00000913 => x"00000000", |
00000914 => x"00007830", |
00000915 => x"52455b0a", |
00000916 => x"00002052", |
00000917 => x"00000a5d", |
00000918 => x"69617741", |
00000919 => x"676e6974", |
00000920 => x"6f656e20", |
00000921 => x"32337672", |
00000922 => x"6578655f", |
00000923 => x"6e69622e", |
00000924 => x"202e2e2e", |
00000925 => x"00000000", |
00000926 => x"64616f4c", |
00000927 => x"2e676e69", |
00000928 => x"00202e2e", |
00000929 => x"00004b4f", |
00000930 => x"65206f4e", |
00000931 => x"75636578", |
00000932 => x"6c626174", |
00000933 => x"76612065", |
00000934 => x"616c6961", |
00000935 => x"2e656c62", |
00000936 => x"00000000", |
00000937 => x"74697257", |
00000938 => x"00002065", |
00000939 => x"74796220", |
00000940 => x"74207365", |
00000941 => x"5053206f", |
00000942 => x"6c662049", |
00000943 => x"20687361", |
00000944 => x"00783040", |
00000945 => x"7928203f", |
00000946 => x"20296e2f", |
00000947 => x"00000000", |
00000948 => x"616c460a", |
00000949 => x"6e696873", |
00000950 => x"2e2e2e67", |
00000951 => x"00000020", |
00000952 => x"3c0a0a0a", |
00000953 => x"454e203c", |
00000954 => x"3356524f", |
00000955 => x"6f422032", |
00000956 => x"6f6c746f", |
00000957 => x"72656461", |
00000958 => x"0a3e3e20", |
00000959 => x"444c420a", |
00000960 => x"4a203a56", |
00000961 => x"32206e61", |
00000962 => x"30322037", |
00000963 => x"480a3232", |
00000964 => x"203a5657", |
00000965 => x"00000020", |
00000966 => x"4b4c430a", |
00000967 => x"0020203a", |
00000968 => x"53494d0a", |
00000969 => x"00203a41", |
00000970 => x"5550430a", |
00000971 => x"0020203a", |
00000972 => x"434f530a", |
00000973 => x"0020203a", |
00000974 => x"53494d0a", |
00000975 => x"00203a41", |
00000976 => x"5550430a", |
00000977 => x"0020203a", |
00000978 => x"434f530a", |
00000979 => x"0020203a", |
00000980 => x"454d490a", |
00000981 => x"00203a4d", |
00000982 => x"74796220", |
00000983 => x"40207365", |
00000984 => x"00000000", |
00000985 => x"454d440a", |
00000986 => x"00203a4d", |
00000987 => x"75410a0a", |
00000988 => x"6f626f74", |
00000989 => x"6920746f", |
00000990 => x"7338206e", |
00000991 => x"7250202e", |
00000992 => x"20737365", |
00000993 => x"2079656b", |
00000994 => x"61206f74", |
00000995 => x"74726f62", |
00000996 => x"00000a2e", |
00000997 => x"0000000a", |
00000998 => x"726f6241", |
00000999 => x"2e646574", |
00001000 => x"00000a0a", |
00001001 => x"444d430a", |
00001002 => x"00203e3a", |
00001003 => x"61766e49", |
00001004 => x"2064696c", |
00001005 => x"00444d43", |
00001006 => x"33323130", |
00001007 => x"37363534", |
00001008 => x"62613938", |
00001009 => x"66656463" |
00000974 => x"454d490a", |
00000975 => x"00203a4d", |
00000976 => x"74796220", |
00000977 => x"40207365", |
00000978 => x"00000000", |
00000979 => x"454d440a", |
00000980 => x"00203a4d", |
00000981 => x"75410a0a", |
00000982 => x"6f626f74", |
00000983 => x"6920746f", |
00000984 => x"7338206e", |
00000985 => x"7250202e", |
00000986 => x"20737365", |
00000987 => x"2079656b", |
00000988 => x"61206f74", |
00000989 => x"74726f62", |
00000990 => x"00000a2e", |
00000991 => x"0000000a", |
00000992 => x"726f6241", |
00000993 => x"2e646574", |
00000994 => x"00000a0a", |
00000995 => x"444d430a", |
00000996 => x"00203e3a", |
00000997 => x"61766e49", |
00000998 => x"2064696c", |
00000999 => x"00444d43", |
00001000 => x"33323130", |
00001001 => x"37363534", |
00001002 => x"62613938", |
00001003 => x"66656463" |
); |
|
end neorv32_bootloader_image; |
/neorv32_cfs.vhd
244,15 → 244,16
|
-- CFS Function Core ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
|
-- This is where the actual functionality can be implemented. |
-- In this example we are just implementing four r/w registers that invert any value written to them. |
|
-- The logic below is just a very simple example that transforms data |
-- from an inpout register into data in an output register. |
cfs_core_logic: process(cfs_reg_wr) |
begin |
cfs_reg_rd(0) <= not cfs_reg_wr(0); |
cfs_reg_rd(1) <= not cfs_reg_wr(1); |
cfs_reg_rd(2) <= not cfs_reg_wr(2); |
cfs_reg_rd(3) <= not cfs_reg_wr(3); |
cfs_reg_rd(0) <= bin_to_gray_f(cfs_reg_wr(0)); -- convert binary to gray code |
cfs_reg_rd(1) <= gray_to_bin_f(cfs_reg_wr(1)); -- convert gray to binary code |
cfs_reg_rd(2) <= bit_rev_f(cfs_reg_wr(2)); -- bit reversal |
cfs_reg_rd(3) <= bswap32_f(cfs_reg_wr(3)); -- byte swap (endianness conversion) |
end process cfs_core_logic; |
|
|
/neorv32_cpu.vhd
91,44 → 91,44
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
sleep_o : out std_ulogic; -- cpu is in sleep mode when set |
debug_o : out std_ulogic; -- cpu is in debug mode when set |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
sleep_o : out std_ulogic; -- cpu is in sleep mode when set |
debug_o : out std_ulogic; -- cpu is in debug mode when set |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_lock_o : out std_ulogic; -- exclusive access request |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_lock_o : out std_ulogic; -- exclusive access request |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_lock_o : out std_ulogic; -- exclusive access request |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_lock_o : out std_ulogic; -- exclusive access request |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic;-- machine software interrupt |
mext_irq_i : in std_ulogic;-- machine external interrupt |
mtime_irq_i : in std_ulogic;-- machine timer interrupt |
msw_irq_i : in std_ulogic;-- machine software interrupt |
mext_irq_i : in std_ulogic;-- machine external interrupt |
mtime_irq_i : in std_ulogic;-- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(15 downto 0); |
firq_i : in std_ulogic_vector(15 downto 0); |
-- debug mode (halt) request -- |
db_halt_req_i : in std_ulogic |
db_halt_req_i : in std_ulogic |
); |
end neorv32_cpu; |
|
194,6 → 194,9
assert not (dedicated_reset_c = true) report "NEORV32 CPU CONFIG NOTE: Implementing defined hardware reset for uncritical registers (non-default, reset-to-zero, might increase area)." severity note; |
assert not ((def_rst_val_c /= '-') and (def_rst_val_c /= '0')) report "NEORV32 CPU CONFIG ERROR! Invalid configuration of package <def_rst_val_c> constant (has to be '-' or '0')." severity error; |
|
-- CPU boot address alignment -- |
assert not (CPU_BOOT_ADDR(1 downto 0) /= "00") report "NEORV32 CPU CONFIG ERROR! <CPU_BOOT_ADDR> has to be 32-bit aligned." severity error; |
|
-- CSR system -- |
assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/privileged features available when <CPU_EXTENSION_RISCV_Zicsr> = false." severity warning; |
|
207,9 → 210,6
-- Instruction prefetch buffer size -- |
assert not (is_power_of_two_f(CPU_IPB_ENTRIES) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <CPU_IPB_ENTRIES> has to be a power of two." severity error; |
|
-- Co-processor timeout counter (for debugging only) -- |
assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning; |
|
-- PMP regions check -- |
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error; |
-- PMP granularity -- |
387,53 → 387,53
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i => fetch_pc, -- PC for instruction fetch |
instr_o => instr, -- instruction |
i_wait_o => bus_i_wait, -- wait for fetch to complete |
fetch_pc_i => fetch_pc, -- PC for instruction fetch |
instr_o => instr, -- instruction |
i_wait_o => bus_i_wait, -- wait for fetch to complete |
-- |
ma_instr_o => ma_instr, -- misaligned instruction address |
be_instr_o => be_instr, -- bus error on instruction access |
ma_instr_o => ma_instr, -- misaligned instruction address |
be_instr_o => be_instr, -- bus error on instruction access |
-- cpu data access interface -- |
addr_i => alu_add, -- ALU.add result -> access address |
wdata_i => rs2, -- write data |
rdata_o => mem_rdata, -- read data |
mar_o => mar, -- current memory address register |
d_wait_o => bus_d_wait, -- wait for access to complete |
addr_i => alu_add, -- ALU.add result -> access address |
wdata_i => rs2, -- write data |
rdata_o => mem_rdata, -- read data |
mar_o => mar, -- current memory address register |
d_wait_o => bus_d_wait, -- wait for access to complete |
-- |
excl_state_o => excl_state, -- atomic/exclusive access status |
ma_load_o => ma_load, -- misaligned load data address |
ma_store_o => ma_store, -- misaligned store data address |
be_load_o => be_load, -- bus error on load data access |
be_store_o => be_store, -- bus error on store data access |
excl_state_o => excl_state, -- atomic/exclusive access status |
ma_load_o => ma_load, -- misaligned load data address |
ma_store_o => ma_store, -- misaligned store data address |
be_load_o => be_load, -- bus error on load data access |
be_store_o => be_store, -- bus error on store data access |
-- physical memory protection -- |
pmp_addr_i => pmp_addr, -- addresses |
pmp_ctrl_i => pmp_ctrl, -- configurations |
pmp_addr_i => pmp_addr, -- addresses |
pmp_ctrl_i => pmp_ctrl, -- configurations |
-- instruction bus -- |
i_bus_addr_o => i_bus_addr_o, -- bus access address |
i_bus_rdata_i => i_bus_rdata_i, -- bus read data |
i_bus_wdata_o => i_bus_wdata_o, -- bus write data |
i_bus_ben_o => i_bus_ben_o, -- byte enable |
i_bus_we_o => i_bus_we_o, -- write enable |
i_bus_re_o => i_bus_re_o, -- read enable |
i_bus_lock_o => i_bus_lock_o, -- exclusive access request |
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge |
i_bus_err_i => i_bus_err_i, -- bus transfer error |
i_bus_fence_o => i_bus_fence_o, -- fence operation |
i_bus_addr_o => i_bus_addr_o, -- bus access address |
i_bus_rdata_i => i_bus_rdata_i, -- bus read data |
i_bus_wdata_o => i_bus_wdata_o, -- bus write data |
i_bus_ben_o => i_bus_ben_o, -- byte enable |
i_bus_we_o => i_bus_we_o, -- write enable |
i_bus_re_o => i_bus_re_o, -- read enable |
i_bus_lock_o => i_bus_lock_o, -- exclusive access request |
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge |
i_bus_err_i => i_bus_err_i, -- bus transfer error |
i_bus_fence_o => i_bus_fence_o, -- fence operation |
-- data bus -- |
d_bus_addr_o => d_bus_addr_o, -- bus access address |
d_bus_rdata_i => d_bus_rdata_i, -- bus read data |
d_bus_wdata_o => d_bus_wdata_o, -- bus write data |
d_bus_ben_o => d_bus_ben_o, -- byte enable |
d_bus_we_o => d_bus_we_o, -- write enable |
d_bus_re_o => d_bus_re_o, -- read enable |
d_bus_lock_o => d_bus_lock_o, -- exclusive access request |
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge |
d_bus_err_i => d_bus_err_i, -- bus transfer error |
d_bus_fence_o => d_bus_fence_o -- fence operation |
d_bus_addr_o => d_bus_addr_o, -- bus access address |
d_bus_rdata_i => d_bus_rdata_i, -- bus read data |
d_bus_wdata_o => d_bus_wdata_o, -- bus write data |
d_bus_ben_o => d_bus_ben_o, -- byte enable |
d_bus_we_o => d_bus_we_o, -- write enable |
d_bus_re_o => d_bus_re_o, -- read enable |
d_bus_lock_o => d_bus_lock_o, -- exclusive access request |
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge |
d_bus_err_i => d_bus_err_i, -- bus transfer error |
d_bus_fence_o => d_bus_fence_o -- fence operation |
); |
|
-- current privilege level -- |
/neorv32_cpu_alu.vhd
91,18 → 91,17
|
-- co-processor arbiter and interface -- |
type cp_ctrl_t is record |
cmd : std_ulogic; |
cmd_ff : std_ulogic; |
start : std_ulogic; |
busy : std_ulogic; |
timeout : std_ulogic_vector(9 downto 0); |
cmd : std_ulogic; |
cmd_ff : std_ulogic; |
start : std_ulogic; |
end record; |
signal cp_ctrl : cp_ctrl_t; |
|
-- co-processor interface -- |
signal cp_start : std_ulogic_vector(3 downto 0); -- trigger co-processor i |
signal cp_valid : std_ulogic_vector(3 downto 0); -- co-processor i done |
type cp_data_if_t is array (0 to 7) of std_ulogic_vector(data_width_c-1 downto 0); |
signal cp_result : cp_data_if_t; -- co-processor result |
signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i |
signal cp_valid : std_ulogic_vector(7 downto 0); -- co-processor i done |
|
begin |
|
182,36 → 181,21
|
|
-- ************************************************************************************************************************** |
-- Co-Processors |
-- CPU Co-Processors |
-- ************************************************************************************************************************** |
|
-- Co-Processor Interface -- |
-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data |
-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered |
|
-- Co-Processor Arbiter ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- Interface: |
-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data |
-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered |
cp_arbiter: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
cp_ctrl.cmd_ff <= '0'; |
cp_ctrl.busy <= '0'; |
cp_ctrl.timeout <= (others => '0'); |
cp_ctrl.cmd_ff <= '0'; |
elsif rising_edge(clk_i) then |
cp_ctrl.cmd_ff <= cp_ctrl.cmd; |
-- timeout counter -- |
if (cp_ctrl.start = '1') then |
cp_ctrl.busy <= '1'; |
elsif (or_reduce_f(cp_valid) = '1') then |
cp_ctrl.busy <= '0'; |
end if; |
if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then |
cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1); |
else |
cp_ctrl.timeout <= (others => '0'); |
end if; |
if (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout |
assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning; |
end if; |
end if; |
end process cp_arbiter; |
|
219,17 → 203,21
cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_copro_c) else '0'; |
cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0'; |
|
-- co-processor select / star trigger -- |
cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0'; |
cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0'; |
cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0'; |
cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0'; |
-- co-processor select / start trigger -- |
cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "000") else '0'; |
cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "001") else '0'; |
cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "010") else '0'; |
cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "011") else '0'; |
cp_start(4) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "100") else '0'; |
cp_start(5) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "101") else '0'; |
cp_start(6) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "110") else '0'; |
cp_start(7) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "111") else '0'; |
|
-- co-processor operation done? -- |
idone_o <= or_reduce_f(cp_valid); |
|
-- co-processor result - only the *actually selected* co-processor may output data != 0 -- |
cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3); |
cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3) or cp_result(4) or cp_result(5) or cp_result(6) or cp_result(7); |
|
|
-- Co-Processor 0: Shifter (CPU Core ISA) -------------------------------------------------- |
280,7 → 268,7
neorv32_cpu_cp_muldiv_inst_false: |
if (CPU_EXTENSION_RISCV_M = false) and (CPU_EXTENSION_RISCV_Zmmul = false) generate |
cp_result(1) <= (others => '0'); |
cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access |
cp_valid(1) <= '0'; |
end generate; |
|
|
312,7 → 300,7
neorv32_cpu_cp_bitmanip_inst_false: |
if (CPU_EXTENSION_RISCV_B = false) generate |
cp_result(2) <= (others => '0'); |
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access |
cp_valid(2) <= '0'; |
end generate; |
|
|
342,8 → 330,32
if (CPU_EXTENSION_RISCV_Zfinx = false) generate |
cp_result(3) <= (others => '0'); |
fpu_flags_o <= (others => '0'); |
cp_valid(3) <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access |
cp_valid(3) <= '0'; |
end generate; |
|
|
-- Co-Processor 4: Reserved --------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cp_result(4) <= (others => '0'); |
cp_valid(4) <= '0'; |
|
|
-- Co-Processor 5: Reserved --------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cp_result(5) <= (others => '0'); |
cp_valid(5) <= '0'; |
|
|
-- Co-Processor 6: Reserved --------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cp_result(6) <= (others => '0'); |
cp_valid(6) <= '0'; |
|
|
-- Co-Processor 7: Reserved --------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cp_result(7) <= (others => '0'); |
cp_valid(7) <= '0'; |
|
|
end neorv32_cpu_cpu_rtl; |
/neorv32_cpu_bus.vhd
193,14 → 193,12
end if; |
end process mem_adr_reg; |
|
-- read-back for exception controller -- |
-- address read-back for exception controller -- |
mar_o <= mar; |
|
-- alignment check -- |
misaligned_d_check: process(mar, ctrl_i) |
begin |
-- check data access -- |
d_misaligned <= '0'; -- default |
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size |
when "00" => -- byte |
d_misaligned <= '0'; |
207,10 → 205,14
when "01" => -- half-word |
if (mar(0) /= '0') then |
d_misaligned <= '1'; |
else |
d_misaligned <= '0'; |
end if; |
when others => -- word |
if (mar(1 downto 0) /= "00") then |
d_misaligned <= '1'; |
else |
d_misaligned <= '0'; |
end if; |
end case; |
end process misaligned_d_check; |
230,14 → 232,14
end process mem_do_reg; |
|
-- byte enable and output data alignment -- |
byte_enable: process(mar, mdo, ctrl_i) |
write_align: process(mar, mdo, ctrl_i) |
begin |
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size |
when "00" => -- byte |
d_bus_wdata(07 downto 00) <= mdo(07 downto 00); |
d_bus_wdata(15 downto 08) <= mdo(07 downto 00); |
d_bus_wdata(23 downto 16) <= mdo(07 downto 00); |
d_bus_wdata(31 downto 24) <= mdo(07 downto 00); |
d_bus_wdata(07 downto 00) <= mdo(7 downto 0); |
d_bus_wdata(15 downto 08) <= mdo(7 downto 0); |
d_bus_wdata(23 downto 16) <= mdo(7 downto 0); |
d_bus_wdata(31 downto 24) <= mdo(7 downto 0); |
case mar(1 downto 0) is |
when "00" => d_bus_ben <= "0001"; |
when "01" => d_bus_ben <= "0010"; |
245,8 → 247,8
when others => d_bus_ben <= "1000"; |
end case; |
when "01" => -- half-word |
d_bus_wdata(31 downto 16) <= mdo(15 downto 00); |
d_bus_wdata(15 downto 00) <= mdo(15 downto 00); |
d_bus_wdata(31 downto 16) <= mdo(15 downto 0); |
d_bus_wdata(15 downto 00) <= mdo(15 downto 0); |
if (mar(1) = '0') then |
d_bus_ben <= "0011"; -- low half-word |
else |
256,7 → 258,7
d_bus_wdata <= mdo; |
d_bus_ben <= "1111"; -- full word |
end case; |
end process byte_enable; |
end process write_align; |
|
|
-- Data Interface: Read Data -------------------------------------------------------------- |
274,26 → 276,25
|
-- input data alignment and sign extension -- |
read_align: process(mdi, mar, ctrl_i) |
variable byte_in_v : std_ulogic_vector(07 downto 0); |
variable hword_in_v : std_ulogic_vector(15 downto 0); |
variable shifted_data_v : std_ulogic_vector(31 downto 0); |
begin |
-- sub-word input -- |
-- align input word -- |
case mar(1 downto 0) is |
when "00" => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0 |
when "01" => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0 |
when "10" => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1 |
when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1 |
when "00" => shifted_data_v := mdi(31 downto 00); |
when "01" => shifted_data_v := x"00" & mdi(31 downto 08); |
when "10" => shifted_data_v := x"0000" & mdi(31 downto 16); |
when others => shifted_data_v := x"000000" & mdi(31 downto 24); |
end case; |
-- actual data size -- |
-- actual data size and sign-extension -- |
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is |
when "00" => -- byte |
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension |
rdata_align(07 downto 00) <= byte_in_v; |
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and shifted_data_v(7))); -- sign extension |
rdata_align(07 downto 00) <= shifted_data_v(07 downto 00); |
when "01" => -- half-word |
rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension |
rdata_align(15 downto 00) <= hword_in_v; -- high half-word |
rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and shifted_data_v(15))); -- sign extension |
rdata_align(15 downto 00) <= shifted_data_v(15 downto 00); -- high half-word |
when others => -- word |
rdata_align <= mdi; -- full word |
rdata_align <= shifted_data_v; -- full word |
end case; |
end process read_align; |
|
319,8 → 320,7
d_arbiter.err_bus <= '0'; |
else -- in progress |
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
d_arbiter.err_bus <= (d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and |
(not ctrl_i(ctrl_bus_derr_ack_c)); |
d_arbiter.err_bus <= (d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
if ((d_bus_ack_i = '1') and (d_bus_err_i = '0')) or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
407,7 → 407,7
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c); |
i_arbiter.err_align <= i_misaligned; |
i_arbiter.err_bus <= '0'; |
else -- in progres |
else -- in progress |
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
i_arbiter.err_bus <= (i_arbiter.err_bus or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
if ((i_bus_ack_i = '1') and (i_bus_err_i = '0')) or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort |
/neorv32_cpu_control.vhd
1,11 → 1,14
-- ################################################################################################# |
-- # << NEORV32 - CPU Control >> # |
-- # << NEORV32 - CPU Operations Control Unit >> # |
-- # ********************************************************************************************* # |
-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an # |
-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction # |
-- # words) and an execute engine (responsible for actually executing the instructions), a trap # |
-- # handling controller and the RISC-V status and control register set (CSRs) including the # |
-- # hardware performance monitor counters. # |
-- # CPU operations are controlled by several "engines" (modules). These engines operate in # |
-- # parallel to implement a simple pipeline: # |
-- # + Fetch engine: Fetches 32-bit chunks of instruction words # |
-- # + Issue engine: Decodes compressed instructions, aligns and queues instruction words # |
-- # + Execute engine: Multi-cycle execution of instructions (generate control signals) # |
-- # + Trap engine: Handles interrupts and exceptions # |
-- # + CSR module: Read/write accesses to CSRs & HW counters # |
-- # + Debug module: CPU debug mode handling (on-chip debugger) # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
166,14 → 169,13
signal ci_illegal : std_ulogic; |
|
-- instruction issue engine -- |
type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN); |
type issue_engine_t is record |
state : issue_engine_state_t; |
state_nxt : issue_engine_state_t; |
align : std_ulogic; |
align_nxt : std_ulogic; |
buf : std_ulogic_vector(2+15 downto 0); |
buf_nxt : std_ulogic_vector(2+15 downto 0); |
realign : std_ulogic; |
realign_nxt : std_ulogic; |
align : std_ulogic; |
align_nxt : std_ulogic; |
buf : std_ulogic_vector(2+15 downto 0); |
buf_nxt : std_ulogic_vector(2+15 downto 0); |
end record; |
signal issue_engine : issue_engine_t; |
|
186,17 → 188,17
|
-- instruction decoding helper logic -- |
type decode_aux_t is record |
is_atomic_lr : std_ulogic; |
is_atomic_sc : std_ulogic; |
is_float_op : std_ulogic; |
sys_env_cmd : std_ulogic_vector(11 downto 0); |
is_m_mul : std_ulogic; |
is_m_div : std_ulogic; |
is_bitmanip_imm : std_ulogic; |
is_bitmanip_reg : std_ulogic; |
rs1_zero : std_ulogic; |
rs2_zero : std_ulogic; |
rd_zero : std_ulogic; |
is_a_lr : std_ulogic; |
is_a_sc : std_ulogic; |
is_f_op : std_ulogic; |
sys_env_cmd : std_ulogic_vector(11 downto 0); |
is_m_mul : std_ulogic; |
is_m_div : std_ulogic; |
is_b_imm : std_ulogic; |
is_b_reg : std_ulogic; |
rs1_zero : std_ulogic; |
rs2_zero : std_ulogic; |
rd_zero : std_ulogic; |
end record; |
signal decode_aux : decode_aux_t; |
|
238,7 → 240,7
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer |
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0); |
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer |
exc_ack : std_ulogic; -- acknowledge all exceptions |
exc_clr : std_ulogic; -- clear all buffered exceptions |
cause : std_ulogic_vector(6 downto 0); -- trap ID for mcause CSR |
cause_nxt : std_ulogic_vector(6 downto 0); |
db_irq_fire : std_ulogic; -- set if there is a valid IRQ source in the "enter debug mode" trap buffer |
251,8 → 253,8
instr_be : std_ulogic; -- instruction fetch bus error |
instr_ma : std_ulogic; -- instruction fetch misaligned address |
instr_il : std_ulogic; -- illegal instruction |
env_call : std_ulogic; |
break_point : std_ulogic; |
env_call : std_ulogic; -- ecall instruction |
break_point : std_ulogic; -- ebreak instruction |
end record; |
signal trap_ctrl : trap_ctrl_t; |
|
424,30 → 426,24
ipb.clear <= fetch_engine.restart; -- clear instruction buffer while being reset |
|
-- state machine -- |
case fetch_engine.state is |
if (fetch_engine.state = IFETCH_REQUEST) then -- IFETCH_REQUEST: request new 32-bit-aligned instruction word |
-- ------------------------------------------------------------ |
if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request? |
bus_fast_ir <= '1'; -- fast instruction fetch request |
fetch_engine.state_nxt <= IFETCH_ISSUE; |
end if; |
fetch_engine.restart_nxt <= '0'; |
|
when IFETCH_REQUEST => -- request new 32-bit-aligned instruction word |
-- ------------------------------------------------------------ |
if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request? |
bus_fast_ir <= '1'; -- fast instruction fetch request |
fetch_engine.state_nxt <= IFETCH_ISSUE; |
end if; |
fetch_engine.restart_nxt <= '0'; |
|
when IFETCH_ISSUE => -- store instruction data to prefetch buffer |
-- ------------------------------------------------------------ |
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors |
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response |
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4); |
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset |
fetch_engine.state_nxt <= IFETCH_REQUEST; |
end if; |
|
when others => -- undefined |
-- ------------------------------------------------------------ |
else -- IFETCH_ISSUE: store instruction data to prefetch buffer |
-- ------------------------------------------------------------ |
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors |
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response |
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4); |
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset |
fetch_engine.state_nxt <= IFETCH_REQUEST; |
end if; |
|
end case; |
end if; |
end process fetch_engine_fsm_comb; |
|
|
490,22 → 486,22
-- ------------------------------------------------------------------------------------------- |
issue_engine_fsm_sync: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
issue_engine.state <= ISSUE_ACTIVE; |
issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary |
issue_engine.buf <= (others => '0'); |
if (rstn_i = '0') then -- always start aligned after reset |
issue_engine.align <= '0'; |
issue_engine.realign <= '0'; |
issue_engine.buf <= (others => def_rst_val_c); |
elsif rising_edge(clk_i) then |
if (ipb.clear = '1') then |
if (CPU_EXTENSION_RISCV_C = true) and (execute_engine.pc(1) = '1') then -- branch to unaligned address? |
issue_engine.state <= ISSUE_REALIGN; |
issue_engine.align <= '1'; -- aligned on 16-bit boundary |
issue_engine.align <= '1'; -- aligned on 16-bit boundary |
issue_engine.realign <= '1'; |
else |
issue_engine.state <= issue_engine.state_nxt; |
issue_engine.align <= '0'; -- aligned on 32-bit boundary |
issue_engine.align <= '0'; -- aligned on 32-bit boundary |
issue_engine.realign <= '0'; |
end if; |
else |
issue_engine.state <= issue_engine.state_nxt; |
issue_engine.align <= issue_engine.align_nxt; |
issue_engine.align <= issue_engine.align_nxt; |
issue_engine.realign <= issue_engine.realign_nxt; |
end if; |
issue_engine.buf <= issue_engine.buf_nxt; |
end if; |
517,67 → 513,70
issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32) |
begin |
-- arbiter defaults -- |
issue_engine.state_nxt <= issue_engine.state; |
issue_engine.align_nxt <= issue_engine.align; |
issue_engine.buf_nxt <= issue_engine.buf; |
issue_engine.realign_nxt <= issue_engine.realign; |
issue_engine.align_nxt <= issue_engine.align; |
issue_engine.buf_nxt <= issue_engine.buf; |
|
-- instruction prefetch buffer interface defaults -- |
ipb.re <= '0'; |
|
-- instruction issue interface defaults -- |
-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word> |
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
cmd_issue.valid <= '0'; |
|
|
-- construct instruction data -- |
-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word> |
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned |
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed |
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
else -- compressed |
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
end if; |
else -- not 32-bit aligned |
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed |
cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0)); |
else -- compressed |
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
end if; |
end if; |
|
|
-- store high half-word - we might need it for an unaligned uncompressed instruction -- |
if (execute_engine.state = DISPATCH) and (ipb.avail = '1') and (CPU_EXTENSION_RISCV_C = true) then |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); |
end if; |
|
|
-- state machine -- |
case issue_engine.state is |
if (ipb.avail = '1') then -- instruction data available? |
|
when ISSUE_ACTIVE => -- issue instruction if available |
if (issue_engine.realign = '0') then -- issue instruction if available |
-- ------------------------------------------------------------ |
if (ipb.avail = '1') then -- instructions available? |
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word |
if (execute_engine.state = DISPATCH) then -- ready to issue new command? |
ipb.re <= '1'; |
cmd_issue.valid <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned" |
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
else -- compressed |
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
issue_engine.align_nxt <= '1'; |
end if; |
cmd_issue.valid <= '1'; |
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word |
if (execute_engine.state = DISPATCH) then -- ready to issue new command? |
ipb.re <= '1'; |
if (ipb.rdata(1 downto 0) /= "11") and (CPU_EXTENSION_RISCV_C = true) then -- compressed |
issue_engine.align_nxt <= '1'; |
end if; |
|
else -- begin check in HIGH instruction half-word |
if (execute_engine.state = DISPATCH) then -- ready to issue new command? |
cmd_issue.valid <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned" |
ipb.re <= '1'; |
cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0)); |
else -- compressed |
-- do not read from ipb here! |
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
issue_engine.align_nxt <= '0'; |
end if; |
end if; |
else -- begin check in HIGH instruction half-word |
if (execute_engine.state = DISPATCH) then -- ready to issue new command? |
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and unaligned |
ipb.re <= '1'; |
else -- compressed - do not read from ipb here! |
issue_engine.align_nxt <= '0'; |
end if; |
end if; |
end if; |
|
when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address |
else -- re-align input fifo and half-word buffer after a branch to an unaligned address |
-- ------------------------------------------------------------ |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); |
if (ipb.avail = '1') then -- instructions available? |
ipb.re <= '1'; |
issue_engine.state_nxt <= ISSUE_ACTIVE; |
end if; |
ipb.re <= '1'; |
issue_engine.realign_nxt <= '0'; |
end if; |
|
when others => -- undefined |
-- ------------------------------------------------------------ |
issue_engine.state_nxt <= ISSUE_ACTIVE; |
|
end case; |
end if; |
end process issue_engine_fsm_comb; |
|
-- 16-bit instructions: half-word select -- |
671,10 → 670,8
execute_engine.branch_taken <= not cmp_i(cmp_equal_c); |
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned) |
execute_engine.branch_taken <= cmp_i(cmp_less_c); |
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned) |
when others => -- branch if greater or equal (signed/unsigned), invalid funct3 are checked by illegal instr. logic |
execute_engine.branch_taken <= not cmp_i(cmp_less_c); |
when others => -- invalid |
execute_engine.branch_taken <= '0'; |
end case; |
end process branch_check; |
|
813,21 → 810,21
variable sys_env_cmd_mask_v : std_ulogic_vector(11 downto 0); |
begin |
-- defaults -- |
decode_aux.is_atomic_lr <= '0'; |
decode_aux.is_atomic_sc <= '0'; |
decode_aux.is_float_op <= '0'; |
decode_aux.is_m_mul <= '0'; |
decode_aux.is_m_div <= '0'; |
decode_aux.is_bitmanip_imm <= '0'; |
decode_aux.is_bitmanip_reg <= '0'; |
decode_aux.rs1_zero <= '0'; |
decode_aux.rs2_zero <= '0'; |
decode_aux.rd_zero <= '0'; |
decode_aux.is_a_lr <= '0'; |
decode_aux.is_a_sc <= '0'; |
decode_aux.is_f_op <= '0'; |
decode_aux.is_m_mul <= '0'; |
decode_aux.is_m_div <= '0'; |
decode_aux.is_b_imm <= '0'; |
decode_aux.is_b_reg <= '0'; |
decode_aux.rs1_zero <= '0'; |
decode_aux.rs2_zero <= '0'; |
decode_aux.rd_zero <= '0'; |
|
-- is atomic load-reservate/store-conditional? -- |
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode |
decode_aux.is_atomic_lr <= not execute_engine.i_reg(instr_funct5_lsb_c); |
decode_aux.is_atomic_sc <= execute_engine.i_reg(instr_funct5_lsb_c); |
decode_aux.is_a_lr <= not execute_engine.i_reg(instr_funct5_lsb_c); |
decode_aux.is_a_sc <= execute_engine.i_reg(instr_funct5_lsb_c); |
end if; |
|
-- is BITMANIP instruction? -- |
844,13 → 841,24
) or |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00111")) or -- ORCB |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "11000")) then -- REV8 |
decode_aux.is_bitmanip_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all? |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- REV8 |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BCLRI |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- BEXTI |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BINVI |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) then -- BSETI |
decode_aux.is_b_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all? |
end if; |
-- register operation -- |
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U] |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- ZEXTH |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BCLR |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- BEXT |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BINV |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BSET |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- CLMUL |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "011")) or -- CLMULH |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010")) or -- CLMULR |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and |
( |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN |
865,7 → 873,7
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") -- SH3ADD |
) |
) then |
decode_aux.is_bitmanip_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all? |
decode_aux.is_b_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all? |
end if; |
|
-- floating-point operations (Zfinx) -- |
877,7 → 885,7
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "10100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FEQ.S / FLT.S / FLE.S |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11010") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) or -- FCVT.S.W* |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11000") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.W*.S |
decode_aux.is_float_op <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- FPU implemented at all? |
decode_aux.is_f_op <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- FPU implemented at all? |
end if; |
|
-- system/environment instructions -- |
946,7 → 954,7
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU) |
end if; |
-- atomic store-conditional instruction (evaluate lock status) -- |
ctrl_nxt(ctrl_bus_ch_lock_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A) and decode_aux.is_atomic_sc; |
ctrl_nxt(ctrl_bus_ch_lock_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A) and decode_aux.is_a_sc; |
|
|
-- state machine -- |
1036,20 → 1044,20
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_and_c; |
end case; |
|
-- co-processor MULDIV operation (multi-cycle)? -- |
-- co-processor MULDIV operation (multi-cycle) -- |
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV |
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; |
execute_engine.state_nxt <= ALU_WAIT; |
-- co-processor BIT-MANIPULATION operation (multi-cycle)? -- |
-- co-processor BIT-MANIPULATION operation (multi-cycle) -- |
elsif (CPU_EXTENSION_RISCV_B = true) and |
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- register operation |
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation |
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_b_reg = '1')) or -- register operation |
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_b_imm = '1'))) then -- immediate operation |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; |
execute_engine.state_nxt <= ALU_WAIT; |
-- co-processor SHIFT operation (multi-cycle)? -- |
-- co-processor SHIFT operation (multi-cycle) -- |
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- use SHIFTER CP (only relevant for shift operations) |
1099,7 → 1107,7
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE |
ctrl_nxt(ctrl_bus_fence_c) <= '1'; |
execute_engine.state_nxt <= SYS_WAIT; |
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I |
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I |
ctrl_nxt(ctrl_bus_fencei_c) <= '1'; |
execute_engine.branched_nxt <= '1'; -- this is an actual branch |
execute_engine.state_nxt <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (PC <= PC) |
1108,19 → 1116,6
end if; |
|
|
when opcode_syscsr_c => -- system/csr access |
-- ------------------------------------------------------------ |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment |
execute_engine.state_nxt <= SYS_ENV; |
else -- CSR access |
execute_engine.state_nxt <= CSR_ACCESS; |
end if; |
else |
execute_engine.state_nxt <= SYS_WAIT; |
end if; |
|
|
when opcode_fop_c => -- floating-point operations |
-- ------------------------------------------------------------ |
if (CPU_EXTENSION_RISCV_Zfinx = true) then |
1132,14 → 1127,22
end if; |
|
|
when others => -- illegal opcode |
when others => -- system/csr access OR illegal opcode - nothing bad (= no commits) will happen here if there is an illegal opcode |
-- ------------------------------------------------------------ |
execute_engine.state_nxt <= SYS_WAIT; |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment |
execute_engine.state_nxt <= SYS_ENV; |
else -- CSR access |
execute_engine.state_nxt <= CSR_ACCESS; |
end if; |
else |
execute_engine.state_nxt <= SYS_WAIT; |
end if; |
|
end case; |
|
|
when SYS_ENV => -- system environment operation - execution |
when SYS_ENV => -- system environment operation - no action if illegal instruction |
-- ------------------------------------------------------------ |
execute_engine.state_nxt <= SYS_WAIT; -- default |
if (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction |
1155,18 → 1158,17
NULL; -- executed as NOP (and raise illegal instruction exception) |
end if; |
when funct12_wfi_c => -- WFI |
if (CPU_EXTENSION_RISCV_DEBUG = true) and |
((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then -- act as NOP when in debug-mode or during single-stepping |
if (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then -- NOP when in debug-mode or during single-stepping |
NULL; -- executed as NOP |
else |
execute_engine.sleep_nxt <= '1'; -- go to sleep mode |
end if; |
when others => NULL; -- undefined / execute as NOP |
when others => NULL; -- undefined, execute as NOP |
end case; |
end if; |
|
|
when CSR_ACCESS => -- read & write status and control register (CSR) |
when CSR_ACCESS => -- read & write status and control register (CSR) - no read/write if illegal instruction |
-- ------------------------------------------------------------ |
-- CSR write access -- |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or |
1184,7 → 1186,8
when ALU_WAIT => -- wait for multi-cycle ALU operation (co-processor) to finish |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; |
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then -- completed or exception |
-- wait for completion or abort on illegal instruction exception (the co-processor will also terminate operations) |
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
execute_engine.state_nxt <= DISPATCH; |
end if; |
1210,11 → 1213,11
|
when LOADSTORE_0 => -- trigger memory request |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_atomic_lr; -- atomic.LR: set lock |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') then -- normal load or atomic load-reservate |
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_a_lr; -- atomic.LR: set lock |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_a_lr = '1') then -- normal load or atomic load-reservate |
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request |
else -- store |
if (decode_aux.is_atomic_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request |
if (decode_aux.is_a_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request |
ctrl_nxt(ctrl_bus_wr_c) <= '1'; |
else -- evaluate lock state |
ctrl_nxt(ctrl_bus_wr_c) <= excl_state_i; -- write request if lock is still ok |
1239,12 → 1242,12
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction |
-- data write-back -- |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load |
(decode_aux.is_atomic_lr = '1') or -- atomic load-reservate |
(decode_aux.is_atomic_sc = '1') then -- atomic store-conditional |
(decode_aux.is_a_lr = '1') or -- atomic load-reservate |
(decode_aux.is_a_sc = '1') then -- atomic store-conditional |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; |
end if; |
-- remove atomic lock if this is NOT the LR.W instruction used to SET the lock -- |
if (decode_aux.is_atomic_lr = '0') then -- execute and evaluate atomic store-conditional |
if (decode_aux.is_a_lr = '0') then -- execute and evaluate atomic store-conditional |
ctrl_nxt(ctrl_bus_de_lock_c) <= '1'; |
end if; |
execute_engine.state_nxt <= DISPATCH; |
1260,7 → 1263,7
|
|
-- **************************************************************************************************************************** |
-- Invalid Instruction / CSR access check |
-- Illegal Instruction and CSR Access Check |
-- **************************************************************************************************************************** |
|
-- CSR Access Check ----------------------------------------------------------------------- |
1386,7 → 1389,7
-- ------------------------------------------------------------ |
illegal_instruction <= '0'; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and execute_engine.i_reg(instr_rd_msb_c); |
illegal_register <= execute_engine.i_reg(instr_rd_msb_c); |
|
when opcode_alu_c => -- check ALU.funct3 & ALU.funct7 |
-- ------------------------------------------------------------ |
1404,13 → 1407,13
illegal_instruction <= '0'; |
elsif (CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1') then -- valid DIV instruction? |
illegal_instruction <= '0'; |
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_reg = '1') then -- valid BITMANIP instruction? |
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_reg = '1') then -- valid BITMANIP instruction? |
illegal_instruction <= '0'; |
else |
illegal_instruction <= '1'; |
end if; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c); |
|
when opcode_alui_c => -- check ALUI.funct7 |
-- ------------------------------------------------------------ |
1425,13 → 1428,13
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and -- shift right |
((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0'))) then -- valid base ALUI instruction? |
illegal_instruction <= '0'; |
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_imm = '1') then -- valid BITMANIP immediate instruction? |
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_imm = '1') then -- valid BITMANIP immediate instruction? |
illegal_instruction <= '0'; |
else |
illegal_instruction <= '1'; |
end if; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
|
when opcode_load_c => -- check LOAD.funct3 |
-- ------------------------------------------------------------ |
1445,7 → 1448,7
illegal_instruction <= '1'; |
end if; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
|
when opcode_store_c => -- check STORE.funct3 |
-- ------------------------------------------------------------ |
1457,7 → 1460,7
illegal_instruction <= '1'; |
end if; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c); |
|
when opcode_atomic_c => -- atomic instructions |
-- ------------------------------------------------------------ |
1465,11 → 1468,11
if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00010") then -- LR |
illegal_instruction <= '0'; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
elsif (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00011") then -- SC |
illegal_instruction <= '0'; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
else |
illegal_instruction <= '1'; |
end if; |
1490,7 → 1493,7
illegal_instruction <= '1'; |
end if; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c); |
|
when opcode_jalr_c => -- check JALR.funct3 |
-- ------------------------------------------------------------ |
1500,7 → 1503,7
illegal_instruction <= '1'; |
end if; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
|
when opcode_fence_c => -- check FENCE.funct3 |
-- ------------------------------------------------------------ |
1510,8 → 1513,7
else |
illegal_instruction <= '1'; |
end if; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
-- NOTE: ignore all remaining bit fields here |
|
when opcode_syscsr_c => -- check system instructions |
-- ------------------------------------------------------------ |
1525,14 → 1527,12
(csr_acc_valid = '1') then -- valid CSR access? |
illegal_instruction <= '0'; |
-- illegal E-CPU register? -- |
if (CPU_EXTENSION_RISCV_E = true) then |
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
else -- reg-imm CSR |
illegal_register <= execute_engine.i_reg(instr_rd_msb_c); |
end if; |
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
else -- reg-imm CSR |
illegal_register <= execute_engine.i_reg(instr_rd_msb_c); |
end if; |
-- ecall, ebreak, mret, wfi, dret -- |
-- system: ecall, ebreak, mret, wfi, dret -- |
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") and |
(decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') and |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL |
1549,7 → 1549,7
-- ------------------------------------------------------------ |
if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented |
(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only |
(decode_aux.is_float_op = '1') then -- is correct/supported floating-point instruction |
(decode_aux.is_f_op = '1') then -- is correct/supported floating-point instruction |
illegal_instruction <= '0'; |
else |
illegal_instruction <= '1'; |
1556,7 → 1556,7
end if; |
-- illegal E-CPU register? -- |
-- FIXME: rs2 is not checked! |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
|
when others => -- undefined instruction -> illegal! |
-- ------------------------------------------------------------ |
1572,11 → 1572,14
end process illegal_instruction_check; |
|
-- any illegal condition? -- |
trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed; |
trap_ctrl.instr_il <= illegal_opcode_lsbs or -- illegal opcode MSB bits |
illegal_instruction or -- illegal instruction format/layout |
(bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and illegal_register) or -- illegal register access in E extension |
illegal_compressed; -- illegal compressed instruction |
|
|
-- **************************************************************************************************************************** |
-- Exception and Interrupt (= Trap) Control |
-- Exception and Interrupt (= Traps) Control |
-- **************************************************************************************************************************** |
|
-- Trap Controller ------------------------------------------------------------------------ |
1587,7 → 1590,7
if (rstn_i = '0') then |
trap_ctrl.exc_buf <= (others => '0'); |
trap_ctrl.irq_buf <= (others => '0'); |
trap_ctrl.exc_ack <= '0'; |
trap_ctrl.exc_clr <= '0'; |
trap_ctrl.env_start <= '0'; |
trap_ctrl.cause <= (others => '0'); |
elsif rising_edge(clk_i) then |
1594,31 → 1597,31
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
|
-- exception queue: misaligned load/store/instruction address -- |
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_clr); |
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_clr); |
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_clr); |
|
-- exception queue: load/store/instruction bus access error -- |
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_clr); |
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_clr); |
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_clr); |
|
-- exception queue: illegal instruction / environment calls -- |
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_clr); |
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_clr); |
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_clr); |
|
-- exception queue: break point -- |
if (CPU_EXTENSION_RISCV_DEBUG = true) then |
trap_ctrl.exc_buf(exception_break_c) <= (not trap_ctrl.exc_ack) and (trap_ctrl.exc_buf(exception_break_c) or |
((trap_ctrl.break_point and csr.priv_m_mode and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- enable break to machine-trap-handler when in machine mode on "ebreak" |
(trap_ctrl.break_point and csr.priv_u_mode and (not csr.dcsr_ebreaku) and (not debug_ctrl.running)))); -- enable break to machine-trap-handler when in user mode on "ebreak" |
trap_ctrl.exc_buf(exception_break_c) <= (not trap_ctrl.exc_clr) and (trap_ctrl.exc_buf(exception_break_c) or |
(trap_ctrl.break_point and csr.priv_m_mode and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- break to machine-trap-handler when in machine mode on "ebreak" |
(trap_ctrl.break_point and csr.priv_u_mode and (not csr.dcsr_ebreaku) and (not debug_ctrl.running))); -- break to machine-trap-handler when in user mode on "ebreak" |
else |
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_clr); |
end if; |
|
-- exception buffer: enter debug mode -- |
trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_ack); |
-- exception/interrupt buffer: enter debug mode -- |
trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_clr); |
trap_ctrl.irq_buf(interrupt_db_halt_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_halt; |
trap_ctrl.irq_buf(interrupt_db_step_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_step; |
|
1635,12 → 1638,12
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception triggered! |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ |
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr) |
trap_ctrl.exc_ack <= '1'; -- clear exceptions (no ack mask: these have highest priority and are always evaluated first!) |
trap_ctrl.exc_clr <= '1'; -- clear exceptions (no ack mask: these have highest priority and are always evaluated first!) |
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler |
end if; |
else -- trap waiting to get started |
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine |
trap_ctrl.exc_ack <= '0'; |
trap_ctrl.exc_clr <= '0'; |
trap_ctrl.env_start <= '0'; |
end if; |
end if; |
1661,12 → 1664,6
-- ------------------------------------------------------------------------------------------- |
trap_priority: process(trap_ctrl) |
begin |
-- defaults -- |
trap_ctrl.cause_nxt <= (others => '0'); |
|
-- NOTE: Synchronous exceptions (from trap_ctrl.exc_buf) have higher priority than asynchronous |
-- exceptions (from trap_ctrl.irq_buf). |
|
-- ---------------------------------------------------------------------------------------- |
-- the following traps are caused by *synchronous* exceptions; we do not need a |
-- specific acknowledge mask since only _one_ exception (the one with highest priority) |
1715,7 → 1712,6
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then |
trap_ctrl.cause_nxt <= trap_lbe_c; |
|
|
-- ---------------------------------------------------------------------------------------- |
-- (re-)enter debug mode requests: basically, these are standard traps that have some |
-- special handling - they have the highest INTERRUPT priority in order to go to debug when requested |
1722,25 → 1718,22
-- even if other IRQs are pending right now |
-- ---------------------------------------------------------------------------------------- |
|
-- break instruction -- |
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.exc_buf(exception_db_break_c) = '1') then |
-- break instruction (sync) -- |
elsif (trap_ctrl.exc_buf(exception_db_break_c) = '1') then |
trap_ctrl.cause_nxt <= trap_db_break_c; |
|
-- external halt request -- |
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_halt_c) = '1') then |
-- external halt request (async) -- |
elsif (trap_ctrl.irq_buf(interrupt_db_halt_c) = '1') then |
trap_ctrl.cause_nxt <= trap_db_halt_c; |
|
-- single stepping -- |
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_step_c) = '1') then |
-- single stepping (async) -- |
elsif (trap_ctrl.irq_buf(interrupt_db_step_c) = '1') then |
trap_ctrl.cause_nxt <= trap_db_step_c; |
|
|
-- ---------------------------------------------------------------------------------------- |
-- the following traps are caused by *asynchronous* exceptions (= interrupts) |
-- custom FAST interrupts (*asynchronous* exceptions) |
-- ---------------------------------------------------------------------------------------- |
|
-- custom FAST interrupt requests -- |
|
-- interrupt: 1.16 fast interrupt channel 0 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq0_c; |
1805,9 → 1798,10
elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq15_c; |
|
-- ---------------------------------------------------------------------------------------- |
-- standard RISC-V interrupts (*asynchronous* exceptions) |
-- ---------------------------------------------------------------------------------------- |
|
-- standard RISC-V interrupts -- |
|
-- interrupt: 1.11 machine external interrupt -- |
elsif (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then |
trap_ctrl.cause_nxt <= trap_mei_c; |
1817,7 → 1811,7
trap_ctrl.cause_nxt <= trap_msi_c; |
|
-- interrupt: 1.7 machine timer interrupt -- |
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then |
else--if (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then -- last condition, so NO IF required |
trap_ctrl.cause_nxt <= trap_mti_c; |
|
end if; |
1828,23 → 1822,22
-- Control and Status Registers (CSRs) |
-- **************************************************************************************************************************** |
|
-- Control and Status Registers Write Data ------------------------------------------------ |
-- Control and Status Registers - Write Data ---------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i) |
variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0); |
variable csr_imm_v : std_ulogic_vector(data_width_c-1 downto 0); |
begin |
-- CSR operand source -- |
if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate |
csr_operand_v := (others => '0'); |
csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5 |
else -- register |
csr_operand_v := rs1_i; |
end if; |
-- tiny ALU for CSR write operations -- |
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is |
when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I) |
when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I) |
when others => csr.wdata <= csr_operand_v; -- CSRRW(I) |
-- tiny ALU to compute CSR write data -- |
csr_imm_v := (others => '0'); |
csr_imm_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5 |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is |
when funct3_csrrw_c => csr.wdata <= rs1_i; |
when funct3_csrrs_c => csr.wdata <= csr.rdata or rs1_i; |
when funct3_csrrc_c => csr.wdata <= csr.rdata and (not rs1_i); |
when funct3_csrrwi_c => csr.wdata <= csr_imm_v; |
when funct3_csrrsi_c => csr.wdata <= csr.rdata or csr_imm_v; |
when funct3_csrrci_c => csr.wdata <= csr.rdata and (not csr_imm_v); |
when others => csr.wdata <= (others => '-'); -- undefined |
end case; |
end process csr_write_data; |
|
1854,8 → 1847,8
csr_write_access: process(rstn_i, clk_i) |
variable cause_v : std_ulogic_vector(6 downto 0); |
begin |
-- NOTE: If <dedicated_reset_c> = true then <def_rst_val_c> evaluates to '-'. Register that reset to <def_rst_val_c> do |
-- NOT actually have a real reset by default (def_rst_val_c = '-') and have to be explicitly initialized by software! |
-- NOTE: If <dedicated_reset_c> = true then <def_rst_val_c> evaluates to '-'. Registers that reset to <def_rst_val_c> |
-- do NOT actually have a real reset by default and have to be explicitly initialized by software! |
-- see: https://forums.xilinx.com/t5/General-Technical-Discussion/quot-Don-t-care-quot-reset-value/td-p/412845 |
if (rstn_i = '0') then |
csr.we <= '0'; |
1979,7 → 1972,7
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier |
end if; |
-- R/W: mip - machine interrupt pending -- |
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then |
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then |
csr.mip_clr <= csr.wdata(31 downto 16); |
end if; |
end if; |
2080,7 → 2073,7
csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags") |
end if; |
|
-- mcause, mepc, mtval: write machine trap cause, PC and trap value register -- |
-- TRAP ENTER: write machine trap cause, PC and trap value register -- |
-- -------------------------------------------------------------------- |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting? |
|
2431,7 → 2424,7
variable csr_addr_v : std_ulogic_vector(11 downto 0); |
begin |
if rising_edge(clk_i) then |
csr.rdata <= (others => '0'); -- default output |
csr.rdata <= (others => '0'); -- default output, unimplemented CSRs are hardwired to zero |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
csr_addr_v(11 downto 10) := csr.addr(11 downto 10); |
csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) registers ONLY !!! |
2737,6 → 2730,10
csr_rdata_o <= csr.rdata; |
|
|
-- **************************************************************************************************************************** |
-- CPU Debug Mode (Part of the On-Chip Debugger) |
-- **************************************************************************************************************************** |
|
-- Debug Control -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
debug_control: process(rstn_i, clk_i) |
2800,29 → 2797,21
|
-- Debug Control and Status Register (dcsr) - Read-Back ----------------------------------- |
-- ------------------------------------------------------------------------------------------- |
dcsr_readback_false: |
if (CPU_EXTENSION_RISCV_DEBUG = false) generate |
csr.dcsr_rd <= (others => '-'); |
end generate; |
csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec |
csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved |
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter) |
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented |
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented |
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter) |
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping |
csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME/TODO ??? |
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual FIXME/TODO ??? |
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause |
csr.dcsr_rd(05) <= '0'; -- reserved |
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode |
csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt |
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode |
csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered |
|
dcsr_readback_true: |
if (CPU_EXTENSION_RISCV_DEBUG = true) generate |
csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec |
csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved |
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter) |
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented |
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented |
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter) |
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping |
csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME ??? |
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual |
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause |
csr.dcsr_rd(05) <= '0'; -- reserved |
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode |
csr.dcsr_rd(03) <= '0'; -- nmip: pending non-maskable interrupt |
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode |
csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered |
end generate; |
|
|
end neorv32_cpu_control_rtl; |
/neorv32_cpu_cp_bitmanip.vhd
1,18 → 1,18
-- ################################################################################################# |
-- # << NEORV32 - CPU Co-Processor: Bit-Manipulation Co-Processor Unit (RISC-V "B" Extension) >> # |
-- # ********************************************************************************************* # |
-- # The bit manipulation unit is implemented as co-processor that has a processing latency of 1 # |
-- # cycle for logic/arithmetic operations and 3+shamt (=shift amount) cycles for shift(-related) # |
-- # operations. Use the FAST_SHIFT_EN option to reduce shift-related instruction's latency to a # |
-- # fixed value of 3 cycles latency (using barrel shifters). # |
-- # Supported B sub-extensions (Zb*): # |
-- # - Zba: Address-generation instructions # |
-- # - Zbb: Basic bit-manipulation instructions # |
-- # - Zbs: Single-bit instructions # |
-- # - Zbc: Carry-less multiplication instructions # |
-- # # |
-- # Supported sub-extensions (Zb*): # |
-- # - Zba: Address generation instructions # |
-- # - Zbb: Basic bit-manipulation instructions # |
-- # NOTE: This is a first implementation of the bit-manipulation co-processor that supports all # |
-- # sub-sets of the B extension. Hence, it is not yet optimized for area, latency or speed. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
71,43 → 71,55
|
architecture neorv32_cpu_cp_bitmanip_rtl of neorv32_cpu_cp_bitmanip is |
|
-- Sub-extension configuration -- |
-- Sub-extension configuration ---------------------------- |
-- Note that this configurations does NOT effect the CPU's (illegal) instruction decoding logic! |
constant zbb_en_c : boolean := true; |
constant zba_en_c : boolean := true; |
-- --------------------------- -- |
constant zbc_en_c : boolean := true; |
constant zbs_en_c : boolean := true; |
-- -------------------------------------------------------- |
|
-- commands: Zbb - logic with negate -- |
-- Zbb - logic with negate -- |
constant op_andn_c : natural := 0; |
constant op_orn_c : natural := 1; |
constant op_xnor_c : natural := 2; |
-- commands: Zbb - count leading/trailing zero bits -- |
-- Zbb - count leading/trailing zero bits -- |
constant op_clz_c : natural := 3; |
constant op_ctz_c : natural := 4; |
-- commands: Zbb - count population -- |
-- Zbb - count population -- |
constant op_cpop_c : natural := 5; |
-- commands: Zbb - integer minimum/maximum -- |
-- Zbb - integer minimum/maximum -- |
constant op_max_c : natural := 6; -- signed/unsigned |
constant op_min_c : natural := 7; -- signed/unsigned |
-- commands: Zbb - sign- and zero-extension -- |
-- Zbb - sign- and zero-extension -- |
constant op_sextb_c : natural := 8; |
constant op_sexth_c : natural := 9; |
constant op_zexth_c : natural := 10; |
-- commands: Zbb - bitwise rotation -- |
-- Zbb - bitwise rotation -- |
constant op_rol_c : natural := 11; |
constant op_ror_c : natural := 12; -- rori |
-- commands: Zbb - or-combine -- |
constant op_ror_c : natural := 12; -- also rori |
-- Zbb - or-combine -- |
constant op_orcb_c : natural := 13; |
-- commands: Zbb - byte-reverse -- |
-- Zbb - byte-reverse -- |
constant op_rev8_c : natural := 14; |
-- commands: Zba - shifted add -- |
-- Zba - shifted-add -- |
constant op_sh1add_c : natural := 15; |
constant op_sh2add_c : natural := 16; |
constant op_sh3add_c : natural := 17; |
-- Zbs - single-bit operations -- |
constant op_bclr_c : natural := 18; |
constant op_bext_c : natural := 19; |
constant op_binv_c : natural := 20; |
constant op_bset_c : natural := 21; |
-- Zbc - carry-less multiplication -- |
constant op_clmul_c : natural := 22; |
constant op_clmulh_c : natural := 23; |
constant op_clmulr_c : natural := 24; |
-- |
constant op_width_c : natural := 18; |
constant op_width_c : natural := 25; |
|
-- controller -- |
type ctrl_state_t is (S_IDLE, S_START_SHIFT, S_BUSY_SHIFT); |
type ctrl_state_t is (S_IDLE, S_START_SHIFT, S_BUSY_SHIFT, S_START_CLMUL, S_BUSY_CLMUL); |
signal ctrl_state : ctrl_state_t; |
signal cmd, cmd_buf : std_ulogic_vector(op_width_c-1 downto 0); |
signal valid : std_ulogic; |
140,14 → 152,29
-- shifted-add unit -- |
signal adder_core : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- one-hot shifter -- |
signal one_hot_core : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- carry-less multiplier -- |
type clmultiplier_t is record |
start : std_ulogic; |
busy : std_ulogic; |
rs2 : std_ulogic_vector(data_width_c-1 downto 0); |
cnt : std_ulogic_vector(index_size_f(data_width_c) downto 0); |
prod : std_ulogic_vector(2*data_width_c-1 downto 0); |
end record; |
signal clmul : clmultiplier_t; |
|
begin |
|
-- Sub-Extension Configuration ------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
assert false report |
"Implementing bit-manipulation (B) sub-extensions: " & |
cond_sel_string_f(zbb_en_c, "Zbb", "") & |
cond_sel_string_f(zba_en_c, "Zba", "") & |
"NEORV32 CPU: Implementing bit-manipulation (B) sub-extensions " & |
cond_sel_string_f(zba_en_c, "Zba ", "") & |
cond_sel_string_f(zbb_en_c, "Zbb ", "") & |
cond_sel_string_f(zbc_en_c, "Zbc ", "") & |
cond_sel_string_f(zbs_en_c, "Zbs ", "") & |
"" |
severity note; |
|
154,28 → 181,28
|
-- Instruction Decoding (One-Hot) --------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- a minimal decoding logic is used here -> just to distinguish between B.Zbb instructions |
-- a more specific decoding and instruction check is done by the CPU control unit |
-- a minimal decoding logic is used here just to distinguish between the different B instruction |
-- a more precise decoding and valid-instruction check is done by the CPU control unit |
|
-- Zbb - Basic bit-manipulation instructions -- |
cmd(op_andn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "11") else '0'; |
cmd(op_orn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "10") else '0'; |
cmd(op_xnor_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "00") else '0'; |
cmd(op_andn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "11") else '0'; |
cmd(op_orn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "10") else '0'; |
cmd(op_xnor_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "00") else '0'; |
-- |
cmd(op_max_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_1_c) = '1') else '0'; |
cmd(op_min_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_1_c) = '0') else '0'; |
cmd(op_max_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "11") else '0'; |
cmd(op_min_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "10") else '0'; |
cmd(op_zexth_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '0') else '0'; |
-- |
cmd(op_orcb_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') else '0'; |
cmd(op_orcb_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0'; |
-- |
cmd(op_clz_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "000") else '0'; |
cmd(op_ctz_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "001") else '0'; |
cmd(op_cpop_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "010") else '0'; |
cmd(op_cpop_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "010") and (ctrl_i(ctrl_ir_opcode7_5_c) = '0') else '0'; |
cmd(op_sextb_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "100") else '0'; |
cmd(op_sexth_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "101") else '0'; |
cmd(op_rol_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_opcode7_5_c) = '1') else '0'; |
cmd(op_ror_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0'; |
cmd(op_rev8_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') else '0'; |
cmd(op_rev8_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0'; |
|
-- Zba - Address generation instructions -- |
cmd(op_sh1add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "01") else '0'; |
182,7 → 209,18
cmd(op_sh2add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "10") else '0'; |
cmd(op_sh3add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "11") else '0'; |
|
-- Zbs - Single-bit instructions -- |
cmd(op_bclr_c) <= '1' when (zbs_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') else '0'; |
cmd(op_bext_c) <= '1' when (zbs_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c) = '1') else '0'; |
cmd(op_binv_c) <= '1' when (zbs_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') else '0'; |
cmd(op_bset_c) <= '1' when (zbs_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') else '0'; |
|
-- Zbc - Carry-less multiplication instructions -- |
cmd(op_clmul_c) <= '1' when (zbc_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") else '0'; |
cmd(op_clmulh_c) <= '1' when (zbc_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "011") else '0'; |
cmd(op_clmulr_c) <= '1' when (zbc_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "010") else '0'; |
|
|
-- Co-Processor Controller ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
coprocessor_ctrl: process(rstn_i, clk_i) |
194,11 → 232,13
rs2_reg <= (others => def_rst_val_c); |
sha_reg <= (others => def_rst_val_c); |
less_ff <= def_rst_val_c; |
clmul.start <= '0'; |
shifter.start <= '0'; |
valid <= '0'; |
elsif rising_edge(clk_i) then |
-- defaults -- |
shifter.start <= '0'; |
clmul.start <= '0'; |
valid <= '0'; |
|
-- fsm -- |
219,6 → 259,9
else -- full-parallel computation |
ctrl_state <= S_BUSY_SHIFT; |
end if; |
elsif (zbc_en_c = true) and ((cmd(op_clmul_c) or cmd(op_clmulh_c) or cmd(op_clmulr_c)) = '1') then -- multi-cycle clmul operation |
clmul.start <= '1'; |
ctrl_state <= S_START_CLMUL; |
else |
valid <= '1'; |
ctrl_state <= S_IDLE; |
231,11 → 274,22
|
when S_BUSY_SHIFT => -- wait for multi-cycle shift operation to finish |
-- ------------------------------------------------------------ |
if (shifter.run = '0') then |
if (shifter.run = '0') or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap |
valid <= '1'; |
ctrl_state <= S_IDLE; |
end if; |
|
when S_START_CLMUL => -- one cycle delay to start clmul operation |
-- ------------------------------------------------------------ |
ctrl_state <= S_BUSY_CLMUL; |
|
when S_BUSY_CLMUL => -- wait for multi-cycle clmul operation to finish |
-- ------------------------------------------------------------ |
if (clmul.busy = '0') or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap |
valid <= '1'; |
ctrl_state <= S_IDLE; |
end if; |
|
when others => -- undefined |
-- ------------------------------------------------------------ |
ctrl_state <= S_IDLE; |
366,18 → 420,65
when "01" => opb_v := rs1_reg(rs1_reg'left-1 downto 0) & '0'; -- << 1 |
when "10" => opb_v := rs1_reg(rs1_reg'left-2 downto 0) & "00"; -- << 2 |
when "11" => opb_v := rs1_reg(rs1_reg'left-3 downto 0) & "000"; -- << 3 |
when others => opb_v := rs1_reg(rs1_reg'left-1 downto 0) & '0'; -- undefined |
when others => opb_v := (others => '-'); -- undefined |
end case; |
adder_core <= std_ulogic_vector(unsigned(rs2_reg) + unsigned(opb_v)); |
end process shift_adder; |
|
|
-- One-Hot Generator Core ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
shift_one_hot: process(sha_reg) |
begin |
one_hot_core <= (others => '0'); |
if (zbs_en_c = true) then |
one_hot_core(to_integer(unsigned(sha_reg))) <= '1'; |
end if; |
end process shift_one_hot; |
|
|
-- Carry-Less Multiplication Core --------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
clmul_core: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
clmul.cnt <= (others => def_rst_val_c); |
clmul.prod <= (others => def_rst_val_c); |
elsif rising_edge(clk_i) then |
if (clmul.start = '1') then -- start new multiplication |
clmul.cnt <= (others => '0'); |
clmul.cnt(clmul.cnt'left) <= '1'; |
clmul.prod(63 downto 32) <= (others => '0'); |
if (cmd_buf(op_clmulr_c) = '1') then -- reverse input operands? |
clmul.prod(31 downto 00) <= bit_rev_f(rs1_reg); |
else |
clmul.prod(31 downto 00) <= rs1_reg; |
end if; |
elsif (clmul.busy = '1') then -- processing |
clmul.cnt <= std_ulogic_vector(unsigned(clmul.cnt) - 1); |
if (clmul.prod(0) = '1') then |
clmul.prod(62 downto 31) <= clmul.prod(63 downto 32) xor clmul.rs2; |
else |
clmul.prod(62 downto 31) <= clmul.prod(63 downto 32); |
end if; |
clmul.prod(30 downto 00) <= clmul.prod(31 downto 1); |
end if; |
end if; |
end process clmul_core; |
|
-- reverse input operands? -- |
clmul.rs2 <= bit_rev_f(rs2_reg) when (cmd_buf(op_clmulr_c) = '1') else rs2_reg; |
|
-- multiplier busy? -- |
clmul.busy <= or_reduce_f(clmul.cnt); |
|
|
-- Operation Results ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- logic with negate -- |
res_int(op_andn_c) <= rs1_reg and (not rs2_reg); -- logical and-not |
res_int(op_orn_c) <= rs1_reg or (not rs2_reg); -- logical or-not |
res_int(op_xnor_c) <= rs1_reg xor (not rs2_reg); -- logical xor-not |
res_int(op_andn_c) <= rs1_reg and (not rs2_reg); |
res_int(op_orn_c) <= rs1_reg or (not rs2_reg); |
res_int(op_xnor_c) <= rs1_reg xor (not rs2_reg); |
|
-- count leading/trailing zeros -- |
res_int(op_clz_c)(data_width_c-1 downto shifter.cnt'left+1) <= (others => '0'); |
418,7 → 519,19
res_int(op_sh2add_c) <= (others => '0'); -- unused/redundant |
res_int(op_sh3add_c) <= (others => '0'); -- unused/redundant |
|
-- single-bit instructions -- |
res_int(op_bclr_c) <= rs1_reg and (not one_hot_core); |
res_int(op_bext_c)(data_width_c-1 downto 1) <= (others => '0'); |
res_int(op_bext_c)(0) <= or_reduce_f(rs1_reg and one_hot_core); |
res_int(op_binv_c) <= rs1_reg xor one_hot_core; |
res_int(op_bset_c) <= rs1_reg or one_hot_core; |
|
-- carry-less multiplication instructions -- |
res_int(op_clmul_c) <= clmul.prod(31 downto 00); |
res_int(op_clmulh_c) <= clmul.prod(63 downto 32); |
res_int(op_clmulr_c) <= bit_rev_f(clmul.prod(31 downto 00)); |
|
|
-- Output Selector ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
res_out(op_andn_c) <= res_int(op_andn_c) when (cmd_buf(op_andn_c) = '1') else (others => '0'); |
440,6 → 553,15
res_out(op_sh1add_c) <= res_int(op_sh1add_c) when ((cmd_buf(op_sh1add_c) or cmd_buf(op_sh2add_c) or cmd_buf(op_sh3add_c)) = '1') else (others => '0'); |
res_out(op_sh2add_c) <= (others => '0'); -- unused/redundant |
res_out(op_sh3add_c) <= (others => '0'); -- unused/redundant |
-- |
res_out(op_bclr_c) <= res_int(op_bclr_c) when (cmd_buf(op_bclr_c) = '1') else (others => '0'); |
res_out(op_bext_c) <= res_int(op_bext_c) when (cmd_buf(op_bext_c) = '1') else (others => '0'); |
res_out(op_binv_c) <= res_int(op_binv_c) when (cmd_buf(op_binv_c) = '1') else (others => '0'); |
res_out(op_bset_c) <= res_int(op_bset_c) when (cmd_buf(op_bset_c) = '1') else (others => '0'); |
-- |
res_out(op_clmul_c) <= res_int(op_clmul_c) when (cmd_buf(op_clmul_c) = '1') else (others => '0'); |
res_out(op_clmulh_c) <= res_int(op_clmulh_c) when (cmd_buf(op_clmulh_c) = '1') else (others => '0'); |
res_out(op_clmulr_c) <= res_int(op_clmulr_c) when (cmd_buf(op_clmulr_c) = '1') else (others => '0'); |
|
|
-- Output Gate ---------------------------------------------------------------------------- |
451,13 → 573,15
elsif rising_edge(clk_i) then |
res_o <= (others => '0'); |
if (valid = '1') then |
res_o <= res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or |
res_out(op_clz_c) or res_out(op_cpop_c) or -- res_out(op_ctz_c) is unused here |
res_out(op_min_c) or -- res_out(op_max_c) is unused here |
res_out(op_sextb_c) or res_out(op_sexth_c) or res_out(op_zexth_c) or |
res_out(op_ror_c) or res_out(op_rol_c) or |
res_out(op_orcb_c) or res_out(op_rev8_c) or |
res_out(op_sh1add_c); -- res_out(op_sh2add_c) and res_out(op_sh3add_c) are unused here |
res_o <= res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or |
res_out(op_clz_c) or res_out(op_cpop_c) or -- res_out(op_ctz_c) is unused here |
res_out(op_min_c) or -- res_out(op_max_c) is unused here |
res_out(op_sextb_c) or res_out(op_sexth_c) or res_out(op_zexth_c) or |
res_out(op_ror_c) or res_out(op_rol_c) or |
res_out(op_orcb_c) or res_out(op_rev8_c) or |
res_out(op_sh1add_c) or -- res_out(op_sh2add_c) and res_out(op_sh3add_c) are unused here |
res_out(op_bclr_c) or res_out(op_bext_c) or res_out(op_binv_c) or res_out(op_bset_c) or |
res_out(op_clmul_c) or res_out(op_clmulh_c) or res_out(op_clmulr_c); |
end if; |
end if; |
end process output_gate; |
/neorv32_cpu_cp_fpu.vhd
19,7 → 19,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
384,7 → 384,7
|
when S_BUSY => -- operation in progress (multi-cycle) |
-- ----------------------------------------------------------- |
if (fu_core_done = '1') then -- processing done? |
if (fu_core_done = '1') or (ctrl_i(ctrl_trap_c) = '1') then -- processing done? abort if trap |
ctrl_engine.valid <= '1'; |
ctrl_engine.state <= S_IDLE; |
end if; |
/neorv32_cpu_cp_muldiv.vhd
10,7 → 10,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
174,7 → 174,7
|
when PROCESSING => |
cnt <= std_ulogic_vector(unsigned(cnt) - 1); |
if (cnt = "00000") then |
if (cnt = "00000") or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap |
valid_o <= '1'; |
state <= FINALIZE; |
end if; |
/neorv32_cpu_cp_shifter.vhd
7,7 → 7,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
97,7 → 97,7
shifter.busy_ff <= shifter.busy; |
if (start_i = '1') then |
shifter.busy <= '1'; |
elsif (shifter.done = '1') then |
elsif (shifter.done = '1') or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap |
shifter.busy <= '0'; |
end if; |
-- |
/neorv32_debug_dm.vhd
19,7 → 19,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
72,6 → 72,7
dmi_resp_data_o : out std_ulogic_vector(31 downto 0); |
dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error |
-- CPU bus access -- |
cpu_debug_i : in std_ulogic; -- CPU is in debug mode |
cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address |
cpu_rden_i : in std_ulogic; -- read enable |
cpu_wren_i : in std_ulogic; -- write enable |
240,14 → 241,14
begin |
if rising_edge(clk_i) then |
if (dm_reg.dmcontrol_dmactive = '0') or (dmi_rstn_i = '0') then -- DM reset / DM disabled |
dm_ctrl.state <= CMD_IDLE; |
dm_ctrl.ldsw_progbuf <= (others => '-'); |
dci.execute_req <= '0'; |
dm_ctrl.pbuf_en <= '-'; |
dm_ctrl.state <= CMD_IDLE; |
dm_ctrl.ldsw_progbuf <= (others => '-'); |
dci.execute_req <= '0'; |
dm_ctrl.pbuf_en <= '-'; |
-- |
dm_ctrl.illegal_cmd <= '-'; |
dm_ctrl.illegal_state <= '-'; |
dm_ctrl.cmderr <= "000"; |
dm_ctrl.illegal_cmd <= '-'; |
dm_ctrl.illegal_state <= '-'; |
dm_ctrl.cmderr <= "000"; |
-- |
dm_ctrl.hart_reset <= '0'; |
dm_ctrl.hart_halted <= '0'; |
668,8 → 669,8
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (cpu_addr_i(hi_abb_c downto lo_abb_c) = dm_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
maddr <= cpu_addr_i(lo_abb_c-1 downto lo_abb_c-2); -- (sub-)module select address |
rden <= acc_en and cpu_rden_i; |
wren <= acc_en and cpu_wren_i; |
rden <= acc_en and cpu_debug_i and cpu_rden_i; -- allow access only when in debug mode |
wren <= acc_en and cpu_debug_i and cpu_wren_i; -- allow access only when in debug mode |
|
|
-- Write Access --------------------------------------------------------------------------- |
/neorv32_fifo.vhd
3,7 → 3,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
96,8 → 96,8
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
fifo.re <= re_i when (FIFO_SAFE = false) else (re_i and fifo.avail); -- read only if data available |
fifo.we <= we_i when (FIFO_SAFE = false) else (we_i and fifo.free); -- write only if space left |
fifo.re <= re_i when (FIFO_SAFE = false) else (re_i and fifo.avail); -- SAFE = read only if data available |
fifo.we <= we_i when (FIFO_SAFE = false) else (we_i and fifo.free); -- SAFE = write only if space left |
|
|
-- FIFO Control --------------------------------------------------------------------------- |
163,7 → 163,7
end if; |
end process fifo_memory_write; |
|
-- asynchronous read -- |
-- "asynchronous" read -- |
fifo_read_async: |
if (FIFO_RSYNC = false) generate |
rdata_o <= fifo.datas when (FIFO_DEPTH = 1) else fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0)))); |
/neorv32_mtime.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
104,6 → 104,9
wr_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
-- bus handshake -- |
ack_o <= rden or wren; |
|
-- mtimecmp -- |
if (wren = '1') then |
if (addr = mtime_cmp_lo_addr_c) then |
114,10 → 117,18
end if; |
end if; |
|
-- mtime access buffer -- |
-- wdata_buf <= data_i; -- not required, CPU wdata (=data_i) is stable until transfer is acknowledged |
mtime_lo_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_lo_addr_c)); |
mtime_hi_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_hi_addr_c)); |
-- mtime write access buffer -- |
if (wren = '1') and (addr = mtime_time_lo_addr_c) then |
mtime_lo_we <= '1'; |
else |
mtime_lo_we <= '0'; |
end if; |
-- |
if (wren = '1') and (addr = mtime_time_hi_addr_c) then |
mtime_hi_we <= '1'; |
else |
mtime_hi_we <= '0'; |
end if; |
|
-- mtime low -- |
if (mtime_lo_we = '1') then -- write access |
145,14 → 156,13
rd_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
ack_o <= rden or wren; |
data_o <= (others => '0'); -- default |
if (rden = '1') then |
case addr(3 downto 2) is |
when "00" => data_o <= mtime_lo; -- mtime LOW |
when "01" => data_o <= mtime_hi; -- mtime HIGH |
when "10" => data_o <= mtimecmp_lo; -- mtimecmp LOW |
when others => data_o <= mtimecmp_hi; -- mtimecmp HIGH |
when "00" => data_o <= mtime_lo; -- mtime low |
when "01" => data_o <= mtime_hi; -- mtime high |
when "10" => data_o <= mtimecmp_lo; -- mtimecmp low |
when others => data_o <= mtimecmp_hi; -- mtimecmp high |
end case; |
end if; |
end if; |
/neorv32_package.vhd
46,7 → 46,6
|
-- CPU core -- |
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value) |
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false |
|
-- "critical" number of implemented PMP regions -- |
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces |
64,7 → 63,7
-- Architecture Constants (do not modify!) ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- native data path width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060600"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060700"; -- no touchy! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
|
-- Check if we're inside the Matrix ------------------------------------------------------- |
90,7 → 89,6
-- ------------------------------------------------------------------------------------------- |
type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0); |
type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0); |
type cp_data_if_t is array (0 to 3) of std_ulogic_vector(data_width_c-1 downto 0); |
|
-- Internal Memory Types Configuration Types ---------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
106,6 → 104,8
function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic; |
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string; |
function bool_to_ulogic_f(cond : boolean) return std_ulogic; |
function bin_to_gray_f(input : std_ulogic_vector) return std_ulogic_vector; |
function gray_to_bin_f(input : std_ulogic_vector) return std_ulogic_vector; |
function or_reduce_f(a : std_ulogic_vector) return std_ulogic; |
function and_reduce_f(a : std_ulogic_vector) return std_ulogic; |
function xor_reduce_f(a : std_ulogic_vector) return std_ulogic; |
369,38 → 369,39
constant ctrl_bus_ch_lock_c : natural := 44; -- evaluate atomic/exclusive lock (SC operation) |
-- co-processors -- |
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select ID lsb |
constant ctrl_cp_id_msb_c : natural := 46; -- cp select ID msb |
constant ctrl_cp_id_hsb_c : natural := 46; -- cp select ID "half" significant bit |
constant ctrl_cp_id_msb_c : natural := 47; -- cp select ID msb |
-- instruction's control blocks (used by cpu co-processors) -- |
constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0 |
constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1 |
constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2 |
constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0 |
constant ctrl_ir_funct12_1_c : natural := 51; -- funct12 bit 1 |
constant ctrl_ir_funct12_2_c : natural := 52; -- funct12 bit 2 |
constant ctrl_ir_funct12_3_c : natural := 53; -- funct12 bit 3 |
constant ctrl_ir_funct12_4_c : natural := 54; -- funct12 bit 4 |
constant ctrl_ir_funct12_5_c : natural := 55; -- funct12 bit 5 |
constant ctrl_ir_funct12_6_c : natural := 56; -- funct12 bit 6 |
constant ctrl_ir_funct12_7_c : natural := 57; -- funct12 bit 7 |
constant ctrl_ir_funct12_8_c : natural := 58; -- funct12 bit 8 |
constant ctrl_ir_funct12_9_c : natural := 59; -- funct12 bit 9 |
constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10 |
constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11 |
constant ctrl_ir_opcode7_0_c : natural := 62; -- opcode7 bit 0 |
constant ctrl_ir_opcode7_1_c : natural := 63; -- opcode7 bit 1 |
constant ctrl_ir_opcode7_2_c : natural := 64; -- opcode7 bit 2 |
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3 |
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4 |
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5 |
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6 |
constant ctrl_ir_funct3_0_c : natural := 48; -- funct3 bit 0 |
constant ctrl_ir_funct3_1_c : natural := 49; -- funct3 bit 1 |
constant ctrl_ir_funct3_2_c : natural := 50; -- funct3 bit 2 |
constant ctrl_ir_funct12_0_c : natural := 51; -- funct12 bit 0 |
constant ctrl_ir_funct12_1_c : natural := 52; -- funct12 bit 1 |
constant ctrl_ir_funct12_2_c : natural := 53; -- funct12 bit 2 |
constant ctrl_ir_funct12_3_c : natural := 54; -- funct12 bit 3 |
constant ctrl_ir_funct12_4_c : natural := 55; -- funct12 bit 4 |
constant ctrl_ir_funct12_5_c : natural := 56; -- funct12 bit 5 |
constant ctrl_ir_funct12_6_c : natural := 57; -- funct12 bit 6 |
constant ctrl_ir_funct12_7_c : natural := 58; -- funct12 bit 7 |
constant ctrl_ir_funct12_8_c : natural := 59; -- funct12 bit 8 |
constant ctrl_ir_funct12_9_c : natural := 60; -- funct12 bit 9 |
constant ctrl_ir_funct12_10_c : natural := 61; -- funct12 bit 10 |
constant ctrl_ir_funct12_11_c : natural := 62; -- funct12 bit 11 |
constant ctrl_ir_opcode7_0_c : natural := 63; -- opcode7 bit 0 |
constant ctrl_ir_opcode7_1_c : natural := 64; -- opcode7 bit 1 |
constant ctrl_ir_opcode7_2_c : natural := 65; -- opcode7 bit 2 |
constant ctrl_ir_opcode7_3_c : natural := 66; -- opcode7 bit 3 |
constant ctrl_ir_opcode7_4_c : natural := 67; -- opcode7 bit 4 |
constant ctrl_ir_opcode7_5_c : natural := 68; -- opcode7 bit 5 |
constant ctrl_ir_opcode7_6_c : natural := 69; -- opcode7 bit 6 |
-- CPU status -- |
constant ctrl_priv_lvl_lsb_c : natural := 69; -- privilege level lsb |
constant ctrl_priv_lvl_msb_c : natural := 70; -- privilege level msb |
constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode |
constant ctrl_trap_c : natural := 72; -- set when CPU is entering trap execution |
constant ctrl_debug_running_c : natural := 73; -- CPU is in debug mode when set |
constant ctrl_priv_lvl_lsb_c : natural := 70; -- privilege level lsb |
constant ctrl_priv_lvl_msb_c : natural := 71; -- privilege level msb |
constant ctrl_sleep_c : natural := 72; -- set when CPU is in sleep mode |
constant ctrl_trap_c : natural := 73; -- set when CPU is entering trap execution |
constant ctrl_debug_running_c : natural := 74; -- CPU is in debug mode when set |
-- control bus size -- |
constant ctrl_width_c : natural := 74; -- control bus size |
constant ctrl_width_c : natural := 75; -- control bus size |
|
-- Comparator Bus ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
775,10 → 776,14
|
-- Co-Processor IDs ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant cp_sel_shifter_c : std_ulogic_vector(1 downto 0) := "00"; -- shift operations (base ISA) |
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "01"; -- multiplication/division operations ('M' extensions) |
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extensions) |
constant cp_sel_fpu_c : std_ulogic_vector(1 downto 0) := "11"; -- floating-point unit ('Zfinx' extension) |
constant cp_sel_shifter_c : std_ulogic_vector(2 downto 0) := "000"; -- CP0: shift operations (base ISA) |
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- CP1: multiplication/division operations ('M' extensions) |
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- CP2: bit manipulation ('B' extensions) |
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- CP3: floating-point unit ('Zfinx' extension) |
--constant cp_sel_res0_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: reserved |
--constant cp_sel_res1_c : std_ulogic_vector(2 downto 0) := "101"; -- CP5: reserved |
--constant cp_sel_res2_c : std_ulogic_vector(2 downto 0) := "110"; -- CP6: reserved |
--constant cp_sel_res3_c : std_ulogic_vector(2 downto 0) := "111"; -- CP7: reserved |
|
-- ALU Function Codes --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
1114,44 → 1119,44
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
sleep_o : out std_ulogic; -- cpu is in sleep mode when set |
debug_o : out std_ulogic; -- cpu is in debug mode when set |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
sleep_o : out std_ulogic; -- cpu is in sleep mode when set |
debug_o : out std_ulogic; -- cpu is in debug mode when set |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_lock_o : out std_ulogic; -- exclusive access request |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_lock_o : out std_ulogic; -- exclusive access request |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_lock_o : out std_ulogic; -- exclusive access request |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_lock_o : out std_ulogic; -- exclusive access request |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic; -- machine software interrupt |
mext_irq_i : in std_ulogic; -- machine external interrupt |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
msw_irq_i : in std_ulogic; -- machine software interrupt |
mext_irq_i : in std_ulogic; -- machine external interrupt |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(15 downto 0); |
firq_i : in std_ulogic_vector(15 downto 0); |
-- debug mode (halt) request -- |
db_halt_req_i : in std_ulogic |
db_halt_req_i : in std_ulogic |
); |
end component; |
|
2119,6 → 2124,7
dmi_resp_data_o : out std_ulogic_vector(31 downto 0); |
dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error |
-- CPU bus access -- |
cpu_debug_i : in std_ulogic; -- CPU is in debug mode |
cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address |
cpu_rden_i : in std_ulogic; -- read enable |
cpu_wren_i : in std_ulogic; -- write enable |
2245,6 → 2251,30
end if; |
end function bool_to_ulogic_f; |
|
-- Function: Convert binary to gray ------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function bin_to_gray_f(input : std_ulogic_vector) return std_ulogic_vector is |
variable tmp_v : std_ulogic_vector(input'range); |
begin |
tmp_v(input'length-1) := input(input'length-1); -- keep MSB |
for i in input'length-2 downto 0 loop |
tmp_v(i) := input(i) xor input(i+1); |
end loop; -- i |
return tmp_v; |
end function bin_to_gray_f; |
|
-- Function: Convert gray to binary ------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function gray_to_bin_f(input : std_ulogic_vector) return std_ulogic_vector is |
variable tmp_v : std_ulogic_vector(input'range); |
begin |
tmp_v(input'length-1) := input(input'length-1); -- keep MSB |
for i in input'length-2 downto 0 loop |
tmp_v(i) := tmp_v(i+1) xor input(i); |
end loop; -- i |
return tmp_v; |
end function gray_to_bin_f; |
|
-- Function: OR-reduce all bits ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function or_reduce_f(a : std_ulogic_vector) return std_ulogic is |
/neorv32_top.vhd
686,6 → 686,8
rdata_v := (others => '0'); |
ack_v := '0'; |
err_v := '0'; |
-- OR all module's response signals: only the module that is actually |
-- been accessed is allowed to set it's bus output signals |
for i in resp_bus'range loop |
rdata_v := rdata_v or resp_bus(i).rdata; -- read data |
ack_v := ack_v or resp_bus(i).ack; -- acknowledge |
940,8 → 942,7
-- ------------------------------------------------------------------------------------------- |
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0'; |
io_rden <= io_acc and p_bus.re and (not p_bus.src); -- PMA: no_execute for IO region |
-- the default NEORV32 peripheral/IO devices in the IO area can only be written in word mode (reduces HW complexity) |
io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben) and (not p_bus.src); -- PMA: write32 only, no_execute for IO region |
io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben); -- only full-word write accesses are allowed (reduces HW complexity) |
|
|
-- Custom Functions Subsystem (CFS) ------------------------------------------------------- |
1580,6 → 1581,7
dmi_resp_data_o => dmi.resp_data, |
dmi_resp_err_o => dmi.resp_err, -- 0=ok, 1=error |
-- CPU bus access -- |
cpu_debug_i => debug_mode, -- CPU is in debug mode |
cpu_addr_i => p_bus.addr, -- address |
cpu_rden_i => p_bus.re, -- read enable |
cpu_wren_i => p_bus.we, -- write enable |