URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/rtl/core
- from Rev 71 to Rev 72
- ↔ Reverse comparison
Rev 71 → Rev 72
/mem/neorv32_imem.default.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
166,8 → 166,10
rden <= acc_en and rden_i; |
if (IMEM_AS_IROM = true) then |
ack_o <= acc_en and rden_i; |
err_o <= acc_en and wren_i; |
else |
ack_o <= acc_en and (rden_i or wren_i); |
err_o <= '0'; |
end if; |
end if; |
end process bus_feedback; |
/mem/neorv32_imem.legacy.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
163,8 → 163,10
rden <= acc_en and rden_i; |
if (IMEM_AS_IROM = true) then |
ack_o <= acc_en and rden_i; |
err_o <= acc_en and wren_i; |
else |
ack_o <= acc_en and (rden_i or wren_i); |
err_o <= '0'; |
end if; |
end if; |
end process bus_feedback; |
/neorv32_application_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin> |
-- Size: 3424 bytes |
-- Size: 3400 bytes |
|
library ieee; |
use ieee.std_logic_1164.all; |
67,7 → 67,7
00000053 => x"00158593", |
00000054 => x"ff5ff06f", |
00000055 => x"00001597", |
00000056 => x"c8458593", |
00000056 => x"c6c58593", |
00000057 => x"80000617", |
00000058 => x"f1c60613", |
00000059 => x"80000697", |
113,17 → 113,17
00000099 => x"00000593", |
00000100 => x"b0050513", |
00000101 => x"00112623", |
00000102 => x"088000ef", |
00000103 => x"750000ef", |
00000102 => x"57c000ef", |
00000103 => x"694000ef", |
00000104 => x"00050c63", |
00000105 => x"6fc000ef", |
00000105 => x"500000ef", |
00000106 => x"00001537", |
00000107 => x"a9850513", |
00000108 => x"134000ef", |
00000107 => x"a8050513", |
00000108 => x"628000ef", |
00000109 => x"020000ef", |
00000110 => x"00001537", |
00000111 => x"a7450513", |
00000112 => x"124000ef", |
00000111 => x"a5c50513", |
00000112 => x"618000ef", |
00000113 => x"00c12083", |
00000114 => x"00100513", |
00000115 => x"01010113", |
133,740 → 133,734
00000119 => x"00000593", |
00000120 => x"00112623", |
00000121 => x"00812423", |
00000122 => x"714000ef", |
00000122 => x"658000ef", |
00000123 => x"00000513", |
00000124 => x"00150413", |
00000125 => x"00000593", |
00000126 => x"0ff57513", |
00000127 => x"700000ef", |
00000127 => x"644000ef", |
00000128 => x"0c800513", |
00000129 => x"14c000ef", |
00000129 => x"64c000ef", |
00000130 => x"00040513", |
00000131 => x"fe5ff06f", |
00000132 => x"fe802503", |
00000133 => x"01255513", |
00000134 => x"00157513", |
00000135 => x"00008067", |
00000136 => x"ff010113", |
00000137 => x"00812423", |
00000138 => x"00912223", |
00000139 => x"00112623", |
00000140 => x"fa002023", |
00000141 => x"fe002783", |
00000142 => x"00058413", |
00000143 => x"00151593", |
00000144 => x"00078513", |
00000145 => x"00060493", |
00000146 => x"780000ef", |
00000147 => x"01051513", |
00000148 => x"000017b7", |
00000149 => x"01055513", |
00000150 => x"00000713", |
00000151 => x"ffe78793", |
00000152 => x"04a7e463", |
00000153 => x"0034f793", |
00000154 => x"00347413", |
00000155 => x"fff50513", |
00000156 => x"01479793", |
00000157 => x"01641413", |
00000158 => x"00f567b3", |
00000159 => x"0087e7b3", |
00000160 => x"01871713", |
00000161 => x"00c12083", |
00000162 => x"00812403", |
00000163 => x"00e7e7b3", |
00000164 => x"10000737", |
00000165 => x"00e7e7b3", |
00000166 => x"faf02023", |
00000167 => x"00412483", |
00000168 => x"01010113", |
00000169 => x"00008067", |
00000170 => x"ffe70693", |
00000171 => x"0fd6f693", |
00000172 => x"00069a63", |
00000173 => x"00355513", |
00000174 => x"00170713", |
00000175 => x"0ff77713", |
00000176 => x"fa1ff06f", |
00000177 => x"00155513", |
00000178 => x"ff1ff06f", |
00000179 => x"00040737", |
00000180 => x"fa002783", |
00000181 => x"00e7f7b3", |
00000182 => x"fe079ce3", |
00000183 => x"faa02223", |
00000184 => x"00008067", |
00000185 => x"ff010113", |
00000186 => x"00812423", |
00000187 => x"01212023", |
00000188 => x"00112623", |
00000189 => x"00912223", |
00000190 => x"00050413", |
00000191 => x"00a00913", |
00000192 => x"00044483", |
00000193 => x"00140413", |
00000194 => x"00049e63", |
00000195 => x"00c12083", |
00000196 => x"00812403", |
00000197 => x"00412483", |
00000198 => x"00012903", |
00000199 => x"01010113", |
00000200 => x"00008067", |
00000201 => x"01249663", |
00000202 => x"00d00513", |
00000203 => x"fa1ff0ef", |
00000204 => x"00048513", |
00000205 => x"f99ff0ef", |
00000206 => x"fc9ff06f", |
00000207 => x"c81027f3", |
00000208 => x"c0102573", |
00000209 => x"c81025f3", |
00000210 => x"fef59ae3", |
00000211 => x"00008067", |
00000212 => x"fd010113", |
00000213 => x"00a12623", |
00000214 => x"fe002503", |
00000215 => x"3e800593", |
00000216 => x"02112623", |
00000217 => x"02812423", |
00000218 => x"02912223", |
00000219 => x"03212023", |
00000220 => x"01312e23", |
00000221 => x"654000ef", |
00000222 => x"00c12603", |
00000223 => x"00000693", |
00000224 => x"00000593", |
00000225 => x"5ac000ef", |
00000226 => x"00050413", |
00000227 => x"00058993", |
00000228 => x"fadff0ef", |
00000229 => x"00058913", |
00000230 => x"00050493", |
00000231 => x"fa1ff0ef", |
00000232 => x"00b96663", |
00000233 => x"05259263", |
00000234 => x"04a4f063", |
00000235 => x"008484b3", |
00000236 => x"0084b433", |
00000237 => x"01390933", |
00000238 => x"01240433", |
00000239 => x"f81ff0ef", |
00000240 => x"fe85eee3", |
00000241 => x"00b41463", |
00000242 => x"fe956ae3", |
00000243 => x"02c12083", |
00000244 => x"02812403", |
00000245 => x"02412483", |
00000246 => x"02012903", |
00000247 => x"01c12983", |
00000248 => x"03010113", |
00000249 => x"00008067", |
00000250 => x"01c99913", |
00000251 => x"00445413", |
00000252 => x"00896433", |
00000253 => x"00040a63", |
00000254 => x"00040863", |
00000255 => x"fff40413", |
00000256 => x"00000013", |
00000257 => x"ff1ff06f", |
00000258 => x"fc5ff06f", |
00000259 => x"fc010113", |
00000260 => x"02112e23", |
00000261 => x"02512c23", |
00000262 => x"02612a23", |
00000263 => x"02712823", |
00000264 => x"02a12623", |
00000265 => x"02b12423", |
00000266 => x"02c12223", |
00000267 => x"02d12023", |
00000268 => x"00e12e23", |
00000269 => x"00f12c23", |
00000270 => x"01012a23", |
00000271 => x"01112823", |
00000272 => x"01c12623", |
00000273 => x"01d12423", |
00000274 => x"01e12223", |
00000275 => x"01f12023", |
00000276 => x"34102773", |
00000277 => x"34071073", |
00000278 => x"342027f3", |
00000279 => x"0407c463", |
00000280 => x"00071683", |
00000281 => x"00300593", |
00000282 => x"0036f693", |
00000283 => x"00270613", |
00000284 => x"00b69463", |
00000285 => x"00470613", |
00000286 => x"34161073", |
00000287 => x"00b00713", |
00000288 => x"00f77663", |
00000289 => x"67800793", |
00000290 => x"0500006f", |
00000291 => x"00001737", |
00000292 => x"00279793", |
00000293 => x"ab470713", |
00000294 => x"00e787b3", |
00000295 => x"0007a783", |
00000296 => x"00078067", |
00000297 => x"80000737", |
00000298 => x"ffd74713", |
00000299 => x"00e787b3", |
00000300 => x"01c00713", |
00000301 => x"fcf768e3", |
00000302 => x"00001737", |
00000303 => x"00279793", |
00000304 => x"ae470713", |
00000305 => x"00e787b3", |
00000306 => x"0007a783", |
00000307 => x"00078067", |
00000308 => x"800007b7", |
00000309 => x"0007a783", |
00000310 => x"000780e7", |
00000311 => x"03c12083", |
00000312 => x"03812283", |
00000313 => x"03412303", |
00000314 => x"03012383", |
00000315 => x"02c12503", |
00000316 => x"02812583", |
00000317 => x"02412603", |
00000318 => x"02012683", |
00000319 => x"01c12703", |
00000320 => x"01812783", |
00000321 => x"01412803", |
00000322 => x"01012883", |
00000323 => x"00c12e03", |
00000324 => x"00812e83", |
00000325 => x"00412f03", |
00000326 => x"00012f83", |
00000327 => x"04010113", |
00000328 => x"30200073", |
00000329 => x"800007b7", |
00000330 => x"0047a783", |
00000331 => x"fadff06f", |
00000332 => x"8081a783", |
00000333 => x"fa5ff06f", |
00000334 => x"80c1a783", |
00000335 => x"f9dff06f", |
00000336 => x"8101a783", |
00000337 => x"f95ff06f", |
00000338 => x"8141a783", |
00000339 => x"f8dff06f", |
00000340 => x"8181a783", |
00000341 => x"f85ff06f", |
00000342 => x"81c1a783", |
00000343 => x"f7dff06f", |
00000344 => x"8201a783", |
00000345 => x"f75ff06f", |
00000346 => x"8241a783", |
00000347 => x"f6dff06f", |
00000348 => x"8281a783", |
00000349 => x"f65ff06f", |
00000350 => x"82c1a783", |
00000351 => x"f5dff06f", |
00000352 => x"8301a783", |
00000353 => x"f55ff06f", |
00000354 => x"8341a783", |
00000355 => x"f4dff06f", |
00000356 => x"8381a783", |
00000357 => x"f45ff06f", |
00000358 => x"83c1a783", |
00000359 => x"f3dff06f", |
00000360 => x"8401a783", |
00000361 => x"f35ff06f", |
00000362 => x"8441a783", |
00000363 => x"f2dff06f", |
00000364 => x"8481a783", |
00000365 => x"f25ff06f", |
00000366 => x"84c1a783", |
00000367 => x"f1dff06f", |
00000368 => x"8501a783", |
00000369 => x"f15ff06f", |
00000370 => x"8541a783", |
00000371 => x"f0dff06f", |
00000372 => x"8581a783", |
00000373 => x"f05ff06f", |
00000374 => x"85c1a783", |
00000375 => x"efdff06f", |
00000376 => x"8601a783", |
00000377 => x"ef5ff06f", |
00000378 => x"8641a783", |
00000379 => x"eedff06f", |
00000380 => x"8681a783", |
00000381 => x"ee5ff06f", |
00000382 => x"86c1a783", |
00000383 => x"eddff06f", |
00000384 => x"8701a783", |
00000385 => x"ed5ff06f", |
00000386 => x"fe010113", |
00000387 => x"01212823", |
00000388 => x"00050913", |
00000389 => x"00001537", |
00000390 => x"00912a23", |
00000391 => x"b5850513", |
00000392 => x"000014b7", |
00000393 => x"00812c23", |
00000394 => x"01312623", |
00000395 => x"00112e23", |
00000396 => x"01c00413", |
00000397 => x"cb1ff0ef", |
00000398 => x"d5048493", |
00000399 => x"ffc00993", |
00000400 => x"008957b3", |
00000401 => x"00f7f793", |
00000402 => x"00f487b3", |
00000403 => x"0007c503", |
00000404 => x"ffc40413", |
00000405 => x"c79ff0ef", |
00000406 => x"ff3414e3", |
00000407 => x"01c12083", |
00000408 => x"01812403", |
00000409 => x"01412483", |
00000410 => x"01012903", |
00000411 => x"00c12983", |
00000412 => x"02010113", |
00000413 => x"00008067", |
00000414 => x"ff010113", |
00000415 => x"00112623", |
00000416 => x"00812423", |
00000417 => x"00912223", |
00000418 => x"b89ff0ef", |
00000419 => x"1c050863", |
00000420 => x"00001537", |
00000421 => x"b5c50513", |
00000422 => x"c4dff0ef", |
00000423 => x"34202473", |
00000424 => x"00900713", |
00000425 => x"00f47793", |
00000426 => x"03078493", |
00000427 => x"00f77463", |
00000428 => x"05778493", |
00000429 => x"00b00793", |
00000430 => x"0087ee63", |
00000431 => x"00001737", |
00000432 => x"00241793", |
00000433 => x"d2070713", |
00000434 => x"00e787b3", |
00000435 => x"0007a783", |
00000436 => x"00078067", |
00000437 => x"800007b7", |
00000438 => x"00b78713", |
00000439 => x"14e40e63", |
00000440 => x"02876a63", |
00000441 => x"00378713", |
00000442 => x"12e40c63", |
00000443 => x"00778793", |
00000444 => x"12f40e63", |
00000445 => x"00001537", |
00000446 => x"cbc50513", |
00000447 => x"be9ff0ef", |
00000448 => x"00040513", |
00000449 => x"f05ff0ef", |
00000450 => x"00100793", |
00000451 => x"08f40c63", |
00000452 => x"0280006f", |
00000453 => x"ff07c793", |
00000454 => x"00f407b3", |
00000455 => x"00f00713", |
00000456 => x"fcf76ae3", |
00000457 => x"00001537", |
00000458 => x"cac50513", |
00000459 => x"bb9ff0ef", |
00000460 => x"00048513", |
00000461 => x"b99ff0ef", |
00000462 => x"ffd47413", |
00000463 => x"00500793", |
00000464 => x"06f40263", |
00000465 => x"00001537", |
00000466 => x"d0050513", |
00000467 => x"b99ff0ef", |
00000468 => x"34002573", |
00000469 => x"eb5ff0ef", |
00000470 => x"00001537", |
00000471 => x"d0850513", |
00000472 => x"b85ff0ef", |
00000473 => x"34302573", |
00000474 => x"ea1ff0ef", |
00000475 => x"00812403", |
00000476 => x"00c12083", |
00000477 => x"00412483", |
00000478 => x"00001537", |
00000479 => x"d1450513", |
00000480 => x"01010113", |
00000481 => x"b61ff06f", |
00000482 => x"00001537", |
00000483 => x"b6450513", |
00000484 => x"b55ff0ef", |
00000485 => x"fb1ff06f", |
00000486 => x"00001537", |
00000487 => x"b8450513", |
00000488 => x"b45ff0ef", |
00000489 => x"f7c02783", |
00000490 => x"0a07d463", |
00000491 => x"0017f793", |
00000492 => x"08078a63", |
00000493 => x"00001537", |
00000494 => x"cd450513", |
00000495 => x"fd5ff06f", |
00000496 => x"00001537", |
00000497 => x"ba050513", |
00000498 => x"fc9ff06f", |
00000499 => x"00001537", |
00000500 => x"bb450513", |
00000501 => x"fbdff06f", |
00000502 => x"00001537", |
00000503 => x"bc050513", |
00000504 => x"fb1ff06f", |
00000505 => x"00001537", |
00000506 => x"bd850513", |
00000507 => x"fb5ff06f", |
00000508 => x"00001537", |
00000509 => x"bec50513", |
00000510 => x"f99ff06f", |
00000511 => x"00001537", |
00000512 => x"c0850513", |
00000513 => x"f9dff06f", |
00000514 => x"00001537", |
00000515 => x"c1c50513", |
00000516 => x"f81ff06f", |
00000517 => x"00001537", |
00000518 => x"c3c50513", |
00000519 => x"f75ff06f", |
00000520 => x"00001537", |
00000521 => x"c5c50513", |
00000522 => x"f69ff06f", |
00000523 => x"00001537", |
00000524 => x"c7850513", |
00000525 => x"f5dff06f", |
00000526 => x"00001537", |
00000527 => x"c9050513", |
00000528 => x"f51ff06f", |
00000529 => x"00001537", |
00000530 => x"ce450513", |
00000531 => x"f45ff06f", |
00000532 => x"00001537", |
00000533 => x"cf450513", |
00000534 => x"f39ff06f", |
00000535 => x"00c12083", |
00000536 => x"00812403", |
00000537 => x"00412483", |
00000538 => x"01010113", |
00000539 => x"00008067", |
00000540 => x"01f00793", |
00000541 => x"02a7e263", |
00000542 => x"800007b7", |
00000543 => x"00078793", |
00000544 => x"00251513", |
00000545 => x"00a78533", |
00000546 => x"67800793", |
00000547 => x"00f52023", |
00000548 => x"00000513", |
00000549 => x"00008067", |
00000550 => x"00100513", |
00000551 => x"00008067", |
00000552 => x"ff010113", |
00000553 => x"00112623", |
00000554 => x"00812423", |
00000555 => x"00912223", |
00000556 => x"40c00793", |
00000557 => x"30579073", |
00000558 => x"00000413", |
00000559 => x"01d00493", |
00000560 => x"00040513", |
00000561 => x"00140413", |
00000562 => x"0ff47413", |
00000563 => x"fa5ff0ef", |
00000564 => x"fe9418e3", |
00000565 => x"00c12083", |
00000566 => x"00812403", |
00000567 => x"f6002e23", |
00000568 => x"00412483", |
00000569 => x"01010113", |
00000570 => x"00008067", |
00000571 => x"fe802503", |
00000572 => x"01055513", |
00000573 => x"00157513", |
00000574 => x"00008067", |
00000575 => x"fc000793", |
00000576 => x"00a7a423", |
00000577 => x"00b7a623", |
00000578 => x"00008067", |
00000579 => x"00050613", |
00000580 => x"00000513", |
00000581 => x"0015f693", |
00000582 => x"00068463", |
00000583 => x"00c50533", |
00000584 => x"0015d593", |
00000585 => x"00161613", |
00000586 => x"fe0596e3", |
00000587 => x"00008067", |
00000588 => x"00050313", |
00000589 => x"ff010113", |
00000590 => x"00060513", |
00000591 => x"00068893", |
00000592 => x"00112623", |
00000593 => x"00030613", |
00000594 => x"00050693", |
00000595 => x"00000713", |
00000596 => x"00000793", |
00000597 => x"00000813", |
00000598 => x"0016fe13", |
00000599 => x"00171e93", |
00000600 => x"000e0c63", |
00000601 => x"01060e33", |
00000602 => x"010e3833", |
00000603 => x"00e787b3", |
00000604 => x"00f807b3", |
00000605 => x"000e0813", |
00000606 => x"01f65713", |
00000607 => x"0016d693", |
00000608 => x"00eee733", |
00000609 => x"00161613", |
00000610 => x"fc0698e3", |
00000611 => x"00058663", |
00000612 => x"f7dff0ef", |
00000613 => x"00a787b3", |
00000614 => x"00088a63", |
00000615 => x"00030513", |
00000616 => x"00088593", |
00000617 => x"f69ff0ef", |
00000618 => x"00f507b3", |
00000619 => x"00c12083", |
00000620 => x"00080513", |
00000621 => x"00078593", |
00000622 => x"01010113", |
00000623 => x"00008067", |
00000624 => x"06054063", |
00000625 => x"0605c663", |
00000626 => x"00058613", |
00000627 => x"00050593", |
00000628 => x"fff00513", |
00000629 => x"02060c63", |
00000630 => x"00100693", |
00000631 => x"00b67a63", |
00000632 => x"00c05863", |
00000633 => x"00161613", |
00000634 => x"00169693", |
00000635 => x"feb66ae3", |
00000636 => x"00000513", |
00000637 => x"00c5e663", |
00000638 => x"40c585b3", |
00000639 => x"00d56533", |
00000640 => x"0016d693", |
00000641 => x"00165613", |
00000642 => x"fe0696e3", |
00000643 => x"00008067", |
00000644 => x"00008293", |
00000645 => x"fb5ff0ef", |
00000646 => x"00058513", |
00000647 => x"00028067", |
00000648 => x"40a00533", |
00000649 => x"00b04863", |
00000650 => x"40b005b3", |
00000651 => x"f9dff06f", |
00000652 => x"40b005b3", |
00000653 => x"00008293", |
00000654 => x"f91ff0ef", |
00000655 => x"40a00533", |
00000132 => x"fc010113", |
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00000676 => x"7270206f", |
00000677 => x"6172676f", |
00000678 => x"00000a6d", |
00000679 => x"000002d4", |
00000680 => x"00000328", |
00000681 => x"00000334", |
00000682 => x"0000033c", |
00000683 => x"00000344", |
00000684 => x"0000034c", |
00000685 => x"00000354", |
00000686 => x"0000035c", |
00000687 => x"00000364", |
00000688 => x"00000288", |
00000689 => x"00000288", |
00000690 => x"0000036c", |
00000691 => x"00000374", |
00000692 => x"00000288", |
00000693 => x"00000288", |
00000694 => x"00000288", |
00000695 => x"0000037c", |
00000696 => x"00000288", |
00000697 => x"00000288", |
00000698 => x"00000288", |
00000699 => x"00000384", |
00000700 => x"00000288", |
00000701 => x"00000288", |
00000702 => x"00000288", |
00000703 => x"00000288", |
00000704 => x"0000038c", |
00000705 => x"00000394", |
00000706 => x"0000039c", |
00000707 => x"000003a4", |
00000708 => x"000003ac", |
00000709 => x"000003b4", |
00000710 => x"000003bc", |
00000711 => x"000003c4", |
00000712 => x"000003cc", |
00000713 => x"000003d4", |
00000714 => x"000003dc", |
00000715 => x"000003e4", |
00000716 => x"000003ec", |
00000717 => x"000003f4", |
00000718 => x"000003fc", |
00000719 => x"00000404", |
00000720 => x"00007830", |
00000721 => x"4554523c", |
00000722 => x"0000203e", |
00000723 => x"74736e49", |
00000724 => x"74637572", |
00000725 => x"206e6f69", |
00000726 => x"72646461", |
00000727 => x"20737365", |
00000728 => x"6173696d", |
00000729 => x"6e67696c", |
00000730 => x"00006465", |
00000731 => x"74736e49", |
00000732 => x"74637572", |
00000733 => x"206e6f69", |
00000734 => x"65636361", |
00000735 => x"66207373", |
00000736 => x"746c7561", |
00000737 => x"00000000", |
00000738 => x"656c6c49", |
00000739 => x"206c6167", |
00000740 => x"74736e69", |
00000741 => x"74637572", |
00000742 => x"006e6f69", |
00000743 => x"61657242", |
00000744 => x"696f706b", |
00000745 => x"0000746e", |
00000746 => x"64616f4c", |
00000747 => x"64646120", |
00000748 => x"73736572", |
00000749 => x"73696d20", |
00000750 => x"67696c61", |
00000751 => x"0064656e", |
00000752 => x"64616f4c", |
00000753 => x"64646120", |
00000754 => x"73736572", |
00000755 => x"73696d20", |
00000756 => x"67696c61", |
00000757 => x"0064656e", |
00000758 => x"64616f4c", |
00000759 => x"63636120", |
00000760 => x"20737365", |
00000761 => x"6c756166", |
00000762 => x"00000074", |
00000763 => x"726f7453", |
00000764 => x"64612065", |
00000765 => x"73657264", |
00000766 => x"696d2073", |
00000767 => x"696c6173", |
00000768 => x"64656e67", |
00000769 => x"00000000", |
00000770 => x"726f7453", |
00000771 => x"63612065", |
00000772 => x"73736563", |
00000773 => x"75616620", |
00000774 => x"0000746c", |
00000775 => x"69766e45", |
00000776 => x"6d6e6f72", |
00000777 => x"20746e65", |
00000778 => x"6c6c6163", |
00000779 => x"6f726620", |
00000780 => x"2d55206d", |
00000781 => x"65646f6d", |
00000782 => x"00000000", |
00000783 => x"69766e45", |
00000784 => x"6d6e6f72", |
00000785 => x"20746e65", |
00000786 => x"6c6c6163", |
00000787 => x"6f726620", |
00000788 => x"2d4d206d", |
00000789 => x"65646f6d", |
00000790 => x"00000000", |
00000791 => x"6863614d", |
00000792 => x"20656e69", |
00000793 => x"74666f73", |
00000794 => x"65726177", |
00000795 => x"746e6920", |
00000796 => x"75727265", |
00000797 => x"00007470", |
00000753 => x"63636120", |
00000754 => x"20737365", |
00000755 => x"6c756166", |
00000756 => x"00000074", |
00000757 => x"726f7453", |
00000758 => x"64612065", |
00000759 => x"73657264", |
00000760 => x"696d2073", |
00000761 => x"696c6173", |
00000762 => x"64656e67", |
00000763 => x"00000000", |
00000764 => x"726f7453", |
00000765 => x"63612065", |
00000766 => x"73736563", |
00000767 => x"75616620", |
00000768 => x"0000746c", |
00000769 => x"69766e45", |
00000770 => x"6d6e6f72", |
00000771 => x"20746e65", |
00000772 => x"6c6c6163", |
00000773 => x"6f726620", |
00000774 => x"2d55206d", |
00000775 => x"65646f6d", |
00000776 => x"00000000", |
00000777 => x"69766e45", |
00000778 => x"6d6e6f72", |
00000779 => x"20746e65", |
00000780 => x"6c6c6163", |
00000781 => x"6f726620", |
00000782 => x"2d4d206d", |
00000783 => x"65646f6d", |
00000784 => x"00000000", |
00000785 => x"6863614d", |
00000786 => x"20656e69", |
00000787 => x"74666f73", |
00000788 => x"65726177", |
00000789 => x"746e6920", |
00000790 => x"75727265", |
00000791 => x"00007470", |
00000792 => x"6863614d", |
00000793 => x"20656e69", |
00000794 => x"656d6974", |
00000795 => x"6e692072", |
00000796 => x"72726574", |
00000797 => x"00747075", |
00000798 => x"6863614d", |
00000799 => x"20656e69", |
00000800 => x"656d6974", |
00000801 => x"6e692072", |
00000802 => x"72726574", |
00000803 => x"00747075", |
00000804 => x"6863614d", |
00000805 => x"20656e69", |
00000806 => x"65747865", |
00000807 => x"6c616e72", |
00000808 => x"746e6920", |
00000809 => x"75727265", |
00000810 => x"00007470", |
00000811 => x"74736146", |
00000812 => x"746e6920", |
00000813 => x"75727265", |
00000814 => x"00207470", |
00000815 => x"6e6b6e55", |
00000816 => x"206e776f", |
00000817 => x"70617274", |
00000818 => x"75616320", |
00000819 => x"203a6573", |
00000820 => x"00000000", |
00000821 => x"49545b20", |
00000822 => x"554f454d", |
00000823 => x"52455f54", |
00000824 => x"00005d52", |
00000825 => x"45445b20", |
00000826 => x"45434956", |
00000827 => x"5252455f", |
00000828 => x"0000005d", |
00000829 => x"4d505b20", |
00000830 => x"52455f50", |
00000831 => x"00005d52", |
00000832 => x"50204020", |
00000833 => x"00003d43", |
00000834 => x"544d202c", |
00000835 => x"3d4c4156", |
00000836 => x"00000000", |
00000837 => x"522f3c20", |
00000838 => x"0a3e4554", |
00000839 => x"00000000", |
00000840 => x"00000788", |
00000841 => x"00000798", |
00000842 => x"000007c0", |
00000843 => x"000007cc", |
00000844 => x"000007d8", |
00000845 => x"000007e4", |
00000846 => x"000007f0", |
00000847 => x"000007fc", |
00000848 => x"00000808", |
00000849 => x"000006f4", |
00000850 => x"000006f4", |
00000851 => x"00000814", |
00000852 => x"33323130", |
00000853 => x"37363534", |
00000854 => x"42413938", |
00000855 => x"46454443" |
00000800 => x"65747865", |
00000801 => x"6c616e72", |
00000802 => x"746e6920", |
00000803 => x"75727265", |
00000804 => x"00007470", |
00000805 => x"74736146", |
00000806 => x"746e6920", |
00000807 => x"75727265", |
00000808 => x"00207470", |
00000809 => x"6e6b6e55", |
00000810 => x"206e776f", |
00000811 => x"70617274", |
00000812 => x"75616320", |
00000813 => x"203a6573", |
00000814 => x"00000000", |
00000815 => x"49545b20", |
00000816 => x"554f454d", |
00000817 => x"52455f54", |
00000818 => x"00005d52", |
00000819 => x"45445b20", |
00000820 => x"45434956", |
00000821 => x"5252455f", |
00000822 => x"0000005d", |
00000823 => x"4d505b20", |
00000824 => x"52455f50", |
00000825 => x"00005d52", |
00000826 => x"50204020", |
00000827 => x"00003d43", |
00000828 => x"544d202c", |
00000829 => x"3d4c4156", |
00000830 => x"00000000", |
00000831 => x"522f3c20", |
00000832 => x"0a3e4554", |
00000833 => x"00000000", |
00000834 => x"0000058c", |
00000835 => x"0000059c", |
00000836 => x"000005c4", |
00000837 => x"000005d0", |
00000838 => x"000005dc", |
00000839 => x"000005e8", |
00000840 => x"000005f4", |
00000841 => x"00000600", |
00000842 => x"0000060c", |
00000843 => x"000004f8", |
00000844 => x"000004f8", |
00000845 => x"00000618", |
00000846 => x"33323130", |
00000847 => x"37363534", |
00000848 => x"42413938", |
00000849 => x"46454443" |
); |
|
end neorv32_application_image; |
/neorv32_boot_rom.vhd
3,7 → 3,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
47,9 → 47,11
port ( |
clk_i : in std_ulogic; -- global clock line |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic -- transfer error |
); |
end neorv32_boot_rom; |
|
91,7 → 93,8
mem_file_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
rden <= rden_i and acc_en; |
rden <= acc_en and rden_i; |
err_o <= acc_en and wren_i; |
if (acc_en = '1') then -- reduce switching activity when not accessed |
rdata <= mem_rom(to_integer(unsigned(addr))); |
end if; |
/neorv32_bootloader_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for BOOTLOADER) from source file <bootloader/main.bin> |
-- Size: 4016 bytes |
-- Size: 3924 bytes |
|
library ieee; |
use ieee.std_logic_1164.all; |
51,7 → 51,7
00000037 => x"00158593", |
00000038 => x"ff5ff06f", |
00000039 => x"00001597", |
00000040 => x"f1458593", |
00000040 => x"eb858593", |
00000041 => x"80010617", |
00000042 => x"f5c60613", |
00000043 => x"80010697", |
88,933 → 88,910
00000074 => x"00412483", |
00000075 => x"00810113", |
00000076 => x"30200073", |
00000077 => x"fd010113", |
00000078 => x"02912223", |
00000077 => x"fb010113", |
00000078 => x"04912223", |
00000079 => x"800004b7", |
00000080 => x"00048793", |
00000081 => x"02112623", |
00000082 => x"02812423", |
00000083 => x"03212023", |
00000084 => x"01312e23", |
00000085 => x"01412c23", |
00000086 => x"01512a23", |
00000087 => x"01612823", |
00000088 => x"01712623", |
00000089 => x"01812423", |
00000090 => x"01912223", |
00000091 => x"0007a023", |
00000092 => x"8001a223", |
00000093 => x"ffff07b7", |
00000094 => x"4ac78793", |
00000095 => x"30579073", |
00000096 => x"00000693", |
00000097 => x"00000613", |
00000098 => x"00000593", |
00000099 => x"00200513", |
00000100 => x"351000ef", |
00000101 => x"3e5000ef", |
00000102 => x"00048493", |
00000103 => x"00050863", |
00000104 => x"00100513", |
00000105 => x"00000593", |
00000106 => x"411000ef", |
00000107 => x"00005537", |
00000108 => x"00000613", |
00000109 => x"00000593", |
00000110 => x"b0050513", |
00000111 => x"1d9000ef", |
00000112 => x"19d000ef", |
00000113 => x"02050663", |
00000114 => x"305000ef", |
00000115 => x"fe002783", |
00000116 => x"0027d793", |
00000117 => x"00a78533", |
00000118 => x"00f537b3", |
00000119 => x"00b785b3", |
00000120 => x"18d000ef", |
00000121 => x"08000793", |
00000122 => x"30479073", |
00000123 => x"30046073", |
00000124 => x"ffff1537", |
00000125 => x"ee050513", |
00000126 => x"27d000ef", |
00000127 => x"f1302573", |
00000128 => x"23c000ef", |
00000129 => x"ffff1537", |
00000130 => x"f1850513", |
00000131 => x"269000ef", |
00000132 => x"fe002503", |
00000133 => x"228000ef", |
00000134 => x"ffff1537", |
00000135 => x"f2050513", |
00000136 => x"255000ef", |
00000137 => x"30102573", |
00000138 => x"214000ef", |
00000139 => x"ffff1537", |
00000140 => x"f2850513", |
00000141 => x"241000ef", |
00000142 => x"fe402503", |
00000143 => x"ffff1437", |
00000144 => x"1fc000ef", |
00000145 => x"ffff1537", |
00000146 => x"f3050513", |
00000147 => x"229000ef", |
00000148 => x"fe802503", |
00000149 => x"1e8000ef", |
00000150 => x"ffff1537", |
00000151 => x"f3850513", |
00000152 => x"215000ef", |
00000153 => x"ff802503", |
00000154 => x"1d4000ef", |
00000155 => x"f4040513", |
00000156 => x"205000ef", |
00000157 => x"ff002503", |
00000158 => x"1c4000ef", |
00000159 => x"ffff1537", |
00000160 => x"f4c50513", |
00000161 => x"1f1000ef", |
00000162 => x"ffc02503", |
00000163 => x"1b0000ef", |
00000164 => x"f4040513", |
00000165 => x"1e1000ef", |
00000166 => x"ff402503", |
00000167 => x"1a0000ef", |
00000168 => x"0bd000ef", |
00000169 => x"06050663", |
00000170 => x"ffff1537", |
00000171 => x"f5450513", |
00000172 => x"1c5000ef", |
00000173 => x"219000ef", |
00000174 => x"fe002403", |
00000175 => x"00341413", |
00000176 => x"00a40933", |
00000177 => x"00893433", |
00000178 => x"00b40433", |
00000179 => x"0b9000ef", |
00000180 => x"02051663", |
00000181 => x"1f9000ef", |
00000182 => x"fe85eae3", |
00000183 => x"00b41463", |
00000184 => x"ff2566e3", |
00000185 => x"00100513", |
00000186 => x"4c8000ef", |
00000187 => x"ffff1537", |
00000188 => x"f7c50513", |
00000189 => x"181000ef", |
00000190 => x"0d4000ef", |
00000191 => x"16d000ef", |
00000192 => x"fc050ae3", |
00000193 => x"ffff1537", |
00000194 => x"f8050513", |
00000195 => x"169000ef", |
00000196 => x"0b0000ef", |
00000197 => x"ffff19b7", |
00000198 => x"ffff1a37", |
00000199 => x"07200a93", |
00000200 => x"06800b13", |
00000201 => x"07500b93", |
00000202 => x"07300c13", |
00000203 => x"ffff1937", |
00000204 => x"ffff1cb7", |
00000205 => x"f8c98513", |
00000206 => x"13d000ef", |
00000207 => x"11d000ef", |
00000208 => x"00050413", |
00000209 => x"0e1000ef", |
00000210 => x"f7ca0513", |
00000211 => x"129000ef", |
00000212 => x"0ed000ef", |
00000213 => x"fe051ee3", |
00000214 => x"01541863", |
00000215 => x"ffff02b7", |
00000216 => x"00028067", |
00000217 => x"fd1ff06f", |
00000218 => x"01641663", |
00000219 => x"054000ef", |
00000220 => x"fc5ff06f", |
00000221 => x"01741663", |
00000222 => x"438000ef", |
00000223 => x"fb9ff06f", |
00000224 => x"01841663", |
00000225 => x"65c000ef", |
00000226 => x"fadff06f", |
00000227 => x"06c00793", |
00000228 => x"00f41663", |
00000229 => x"00100513", |
00000230 => x"fe1ff06f", |
00000231 => x"06500793", |
00000232 => x"00f41c63", |
00000233 => x"0004a783", |
00000234 => x"f40798e3", |
00000235 => x"e88c8513", |
00000236 => x"0c5000ef", |
00000237 => x"f81ff06f", |
00000238 => x"f9490513", |
00000239 => x"ff5ff06f", |
00000240 => x"ffff1537", |
00000241 => x"dc850513", |
00000242 => x"0ad0006f", |
00000243 => x"ff010113", |
00000244 => x"00112623", |
00000245 => x"30047073", |
00000246 => x"ffff1537", |
00000247 => x"e2c50513", |
00000248 => x"095000ef", |
00000249 => x"059000ef", |
00000250 => x"fe051ee3", |
00000251 => x"ff002783", |
00000252 => x"00078067", |
00000253 => x"0000006f", |
00000254 => x"ff010113", |
00000255 => x"00812423", |
00000256 => x"00050413", |
00000257 => x"ffff1537", |
00000258 => x"e3c50513", |
00000259 => x"00112623", |
00000260 => x"065000ef", |
00000261 => x"03040513", |
00000262 => x"0ff57513", |
00000263 => x"009000ef", |
00000264 => x"30047073", |
00000265 => x"155000ef", |
00000266 => x"00050863", |
00000267 => x"00100513", |
00000268 => x"00000593", |
00000269 => x"185000ef", |
00000270 => x"0000006f", |
00000271 => x"fe010113", |
00000272 => x"01212823", |
00000273 => x"00050913", |
00000274 => x"ffff1537", |
00000275 => x"00912a23", |
00000276 => x"e4850513", |
00000277 => x"ffff14b7", |
00000278 => x"00812c23", |
00000279 => x"01312623", |
00000280 => x"00112e23", |
00000281 => x"01c00413", |
00000282 => x"00d000ef", |
00000283 => x"fa048493", |
00000284 => x"ffc00993", |
00000285 => x"008957b3", |
00000286 => x"00f7f793", |
00000287 => x"00f487b3", |
00000288 => x"0007c503", |
00000289 => x"ffc40413", |
00000290 => x"79c000ef", |
00000291 => x"ff3414e3", |
00000292 => x"01c12083", |
00000293 => x"01812403", |
00000294 => x"01412483", |
00000295 => x"01012903", |
00000296 => x"00c12983", |
00000297 => x"02010113", |
00000298 => x"00008067", |
00000299 => x"fb010113", |
00000300 => x"04112623", |
00000301 => x"04512423", |
00000302 => x"04612223", |
00000303 => x"04712023", |
00000304 => x"02812e23", |
00000305 => x"02912c23", |
00000306 => x"02a12a23", |
00000307 => x"02b12823", |
00000308 => x"02c12623", |
00000309 => x"02d12423", |
00000310 => x"02e12223", |
00000311 => x"02f12023", |
00000312 => x"01012e23", |
00000313 => x"01112c23", |
00000314 => x"01c12a23", |
00000315 => x"01d12823", |
00000316 => x"01e12623", |
00000317 => x"01f12423", |
00000318 => x"342024f3", |
00000319 => x"800007b7", |
00000320 => x"00778793", |
00000321 => x"08f49463", |
00000322 => x"071000ef", |
00000323 => x"00050663", |
00000324 => x"00000513", |
00000325 => x"075000ef", |
00000326 => x"644000ef", |
00000327 => x"02050063", |
00000328 => x"7ac000ef", |
00000329 => x"fe002783", |
00000330 => x"0027d793", |
00000331 => x"00a78533", |
00000332 => x"00f537b3", |
00000333 => x"00b785b3", |
00000334 => x"634000ef", |
00000335 => x"03c12403", |
00000336 => x"04c12083", |
00000337 => x"04812283", |
00000338 => x"04412303", |
00000339 => x"04012383", |
00000340 => x"03812483", |
00000341 => x"03412503", |
00000342 => x"03012583", |
00000343 => x"02c12603", |
00000344 => x"02812683", |
00000345 => x"02412703", |
00000346 => x"02012783", |
00000347 => x"01c12803", |
00000348 => x"01812883", |
00000349 => x"01412e03", |
00000350 => x"01012e83", |
00000351 => x"00c12f03", |
00000352 => x"00812f83", |
00000353 => x"05010113", |
00000354 => x"30200073", |
00000355 => x"00700793", |
00000356 => x"00f49a63", |
00000357 => x"8041a783", |
00000358 => x"00078663", |
00000359 => x"00100513", |
00000360 => x"e59ff0ef", |
00000361 => x"34102473", |
00000362 => x"5dc000ef", |
00000363 => x"04050263", |
00000364 => x"ffff1537", |
00000365 => x"e4c50513", |
00000366 => x"6bc000ef", |
00000367 => x"00048513", |
00000368 => x"e7dff0ef", |
00000369 => x"02000513", |
00000370 => x"65c000ef", |
00000371 => x"00040513", |
00000372 => x"e6dff0ef", |
00000373 => x"02000513", |
00000374 => x"64c000ef", |
00000375 => x"34302573", |
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00000725 => x"00040513", |
00000726 => x"ec1ff0ef", |
00000727 => x"00050a93", |
00000728 => x"00898593", |
00000729 => x"00040513", |
00000730 => x"eb1ff0ef", |
00000731 => x"ff002c03", |
00000732 => x"00050b13", |
00000733 => x"ffcafb93", |
00000734 => x"00000913", |
00000735 => x"00000493", |
00000736 => x"00c98993", |
00000737 => x"013905b3", |
00000738 => x"05791c63", |
00000739 => x"016484b3", |
00000740 => x"00200513", |
00000741 => x"fa049ae3", |
00000742 => x"ffff1537", |
00000743 => x"d2850513", |
00000744 => x"a59ff0ef", |
00000745 => x"02c12083", |
00000746 => x"02812403", |
00000747 => x"800007b7", |
00000748 => x"0157a023", |
00000749 => x"000a2023", |
00000750 => x"02412483", |
00000751 => x"02012903", |
00000752 => x"01c12983", |
00000753 => x"01812a03", |
00000754 => x"01412a83", |
00000755 => x"01012b03", |
00000756 => x"00c12b83", |
00000757 => x"00812c03", |
00000758 => x"03010113", |
00000759 => x"00008067", |
00000760 => x"00040513", |
00000761 => x"e35ff0ef", |
00000762 => x"012c07b3", |
00000763 => x"00a484b3", |
00000764 => x"00a7a023", |
00000765 => x"00490913", |
00000766 => x"f8dff06f", |
00000767 => x"fd010113", |
00000768 => x"02812423", |
00000769 => x"02912223", |
00000770 => x"03212023", |
00000771 => x"02112623", |
00000772 => x"01312e23", |
00000773 => x"00050413", |
00000774 => x"00b12623", |
00000775 => x"00c10913", |
00000776 => x"00350493", |
00000777 => x"00094983", |
00000778 => x"d75ff0ef", |
00000779 => x"fa802783", |
00000780 => x"00200513", |
00000781 => x"00190913", |
00000782 => x"0017e793", |
00000783 => x"faf02423", |
00000784 => x"cb9ff0ef", |
00000785 => x"00048513", |
00000786 => x"d95ff0ef", |
00000787 => x"00098513", |
00000788 => x"ca9ff0ef", |
00000789 => x"fa802783", |
00000790 => x"ffe7f793", |
00000791 => x"faf02423", |
00000792 => x"cf9ff0ef", |
00000793 => x"00048793", |
00000794 => x"fff48493", |
00000795 => x"faf41ce3", |
00000796 => x"02c12083", |
00000797 => x"02812403", |
00000798 => x"02412483", |
00000799 => x"02012903", |
00000800 => x"01c12983", |
00000801 => x"03010113", |
00000802 => x"00008067", |
00000803 => x"746f6f42", |
00000804 => x"2e676e69", |
00000805 => x"0a0a2e2e", |
00000806 => x"00000000", |
00000807 => x"52450a07", |
00000808 => x"5f524f52", |
00000809 => x"00000000", |
00000810 => x"00007830", |
00000811 => x"52455b0a", |
00000812 => x"20524f52", |
00000813 => x"6e55202d", |
00000814 => x"65707865", |
00000815 => x"64657463", |
00000816 => x"63786520", |
00000817 => x"69747065", |
00000818 => x"20216e6f", |
00000819 => x"7561636d", |
00000820 => x"003d6573", |
00000821 => x"70656d20", |
00000822 => x"00003d63", |
00000823 => x"76746d20", |
00000824 => x"003d6c61", |
00000825 => x"7274205d", |
00000826 => x"676e6979", |
00000827 => x"206f7420", |
00000828 => x"75736572", |
00000829 => x"2e2e656d", |
00000830 => x"00000a2e", |
00000831 => x"69617741", |
00000832 => x"676e6974", |
00000833 => x"6f656e20", |
00000834 => x"32337672", |
00000835 => x"6578655f", |
00000836 => x"6e69622e", |
00000837 => x"202e2e2e", |
00000838 => x"00000000", |
00000839 => x"64616f4c", |
00000840 => x"2e676e69", |
00000841 => x"00202e2e", |
00000842 => x"00004b4f", |
00000843 => x"3c0a0a0a", |
00000844 => x"454e203c", |
00000845 => x"3356524f", |
00000846 => x"6f422032", |
00000847 => x"6f6c746f", |
00000848 => x"72656461", |
00000849 => x"0a3e3e20", |
00000850 => x"444c420a", |
00000851 => x"46203a56", |
00000852 => x"31206265", |
00000853 => x"30322036", |
00000854 => x"480a3232", |
00000855 => x"203a5657", |
00000856 => x"00000020", |
00000857 => x"4b4c430a", |
00000858 => x"0020203a", |
00000859 => x"4153490a", |
00000860 => x"0020203a", |
00000861 => x"00202b20", |
00000862 => x"434f530a", |
00000863 => x"0020203a", |
00000864 => x"454d490a", |
00000865 => x"00203a4d", |
00000866 => x"74796220", |
00000867 => x"40207365", |
00000868 => x"00000000", |
00000869 => x"454d440a", |
00000870 => x"00203a4d", |
00000871 => x"75410a0a", |
00000872 => x"6f626f74", |
00000873 => x"6920746f", |
00000874 => x"7338206e", |
00000875 => x"7250202e", |
00000876 => x"20737365", |
00000877 => x"20796e61", |
00000878 => x"2079656b", |
00000879 => x"61206f74", |
00000880 => x"74726f62", |
00000881 => x"00000a2e", |
00000882 => x"726f6241", |
00000883 => x"2e646574", |
00000884 => x"00000a0a", |
00000885 => x"0000000a", |
00000886 => x"69617641", |
00000887 => x"6c62616c", |
00000888 => x"4d432065", |
00000889 => x"0a3a7344", |
00000890 => x"203a6820", |
00000891 => x"706c6548", |
00000892 => x"3a72200a", |
00000893 => x"73655220", |
00000894 => x"74726174", |
00000895 => x"3a75200a", |
00000896 => x"6c705520", |
00000897 => x"0a64616f", |
00000898 => x"203a7320", |
00000899 => x"726f7453", |
00000900 => x"6f742065", |
00000901 => x"616c6620", |
00000902 => x"200a6873", |
00000903 => x"4c203a6c", |
00000904 => x"2064616f", |
00000905 => x"6d6f7266", |
00000906 => x"616c6620", |
00000907 => x"200a6873", |
00000908 => x"45203a65", |
00000909 => x"75636578", |
00000910 => x"00006574", |
00000911 => x"444d430a", |
00000912 => x"00203e3a", |
00000913 => x"65206f4e", |
00000914 => x"75636578", |
00000915 => x"6c626174", |
00000916 => x"76612065", |
00000917 => x"616c6961", |
00000918 => x"2e656c62", |
00000919 => x"00000000", |
00000920 => x"74697257", |
00000921 => x"00002065", |
00000922 => x"74796220", |
00000923 => x"74207365", |
00000924 => x"5053206f", |
00000925 => x"6c662049", |
00000926 => x"20687361", |
00000927 => x"00783040", |
00000928 => x"7928203f", |
00000929 => x"20296e2f", |
00000930 => x"00000000", |
00000931 => x"616c460a", |
00000932 => x"6e696873", |
00000933 => x"2e2e2e67", |
00000934 => x"00000020", |
00000935 => x"20296328", |
00000936 => x"53207962", |
00000937 => x"68706574", |
00000938 => x"4e206e61", |
00000939 => x"69746c6f", |
00000940 => x"680a676e", |
00000941 => x"73707474", |
00000942 => x"672f2f3a", |
00000943 => x"75687469", |
00000944 => x"6f632e62", |
00000945 => x"74732f6d", |
00000946 => x"746c6f6e", |
00000947 => x"2f676e69", |
00000948 => x"726f656e", |
00000949 => x"00323376", |
00000950 => x"61766e49", |
00000951 => x"2064696c", |
00000952 => x"00444d43", |
00000953 => x"20657865", |
00000954 => x"6e676973", |
00000955 => x"72757461", |
00000956 => x"61662065", |
00000957 => x"00006c69", |
00000958 => x"00000000", |
00000959 => x"65637865", |
00000960 => x"6e696465", |
00000961 => x"4d492067", |
00000962 => x"63204d45", |
00000963 => x"63617061", |
00000964 => x"00797469", |
00000965 => x"63656863", |
00000966 => x"6d75736b", |
00000967 => x"69616620", |
00000968 => x"0000006c", |
00000969 => x"00000000", |
00000970 => x"00000000", |
00000971 => x"20495053", |
00000972 => x"73616c66", |
00000973 => x"63612068", |
00000974 => x"73736563", |
00000975 => x"69616620", |
00000976 => x"0064656c", |
00000977 => x"33323130", |
00000978 => x"37363534", |
00000979 => x"62613938", |
00000980 => x"66656463" |
); |
|
end neorv32_bootloader_image; |
/neorv32_cpu.vhd
5,6 → 5,7
-- # * neorv32_cpu.vhd - CPU top entity # |
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit # |
-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor # |
-- # * neorv32_cpu_cp_cfu.vhd - Custom instructions co-processor # |
-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor # |
-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor # |
-- # * neorv32_cpu_cp_shifter.vhd - Base ISA shifter unit # |
76,6 → 77,7
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit? |
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? |
-- Extension Options -- |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier |
182,6 → 184,7
cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") & |
cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") & |
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") & |
cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "") & |
cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_DEBUG", "") & |
"" |
severity note; |
225,6 → 228,9
-- Mul-extension -- |
assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error; |
|
-- Custom Functions Unit -- |
assert not (CPU_EXTENSION_RISCV_Zxcfu = true) report "NEORV32 CPU CONFIG NOTE: Implementing Custom Functions Unit (CFU) as <Zxcfu> ISA extension." severity note; |
|
-- Debug mode -- |
assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error; |
assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zifencei> extension to be enabled." severity error; |
257,8 → 263,11
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit? |
CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode? |
-- Extension Options -- |
-- Tuning Options -- |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations |
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) |
CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2 |
-- Physical memory protection (PMP) -- |
349,6 → 358,7
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? |
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) |
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit? |
-- Extension Options -- |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations |
/neorv32_cpu_alu.vhd
1,7 → 1,7
-- ################################################################################################# |
-- # << NEORV32 - Arithmetical/Logical Unit >> # |
-- # ********************************************************************************************* # |
-- # Main data and address ALU and co-processor interface/arbiter. # |
-- # Main data/address ALU and ALU co-processor (= multi-cycle function units). # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
48,6 → 48,7
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension? |
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) |
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit? |
-- Extension Options -- |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations |
334,12 → 335,33
end generate; |
|
|
-- Co-Processor 4: Reserved --------------------------------------------------------------- |
-- Co-Processor 4: Custom (Instructions) Functions Unit ('Zxcfu' Extension) --------------- |
-- ------------------------------------------------------------------------------------------- |
cp_result(4) <= (others => '0'); |
cp_valid(4) <= '0'; |
neorv32_cpu_cp_cfu_inst_true: |
if (CPU_EXTENSION_RISCV_Zxcfu = true) generate |
neorv32_cpu_cp_cfu_inst: neorv32_cpu_cp_cfu |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl_i, -- main control bus |
start_i => cp_start(4), -- trigger operation |
-- data input -- |
rs1_i => rs1_i, -- rf source 1 |
rs2_i => rs2_i, -- rf source 2 |
-- result and status -- |
res_o => cp_result(4), -- operation result |
valid_o => cp_valid(4) -- data output valid |
); |
end generate; |
|
neorv32_cpu_cp_cfu_inst_false: |
if (CPU_EXTENSION_RISCV_Zxcfu = false) generate |
cp_result(4) <= (others => '0'); |
cp_valid(4) <= '0'; |
end generate; |
|
|
-- Co-Processor 5: Reserved --------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cp_result(5) <= (others => '0'); |
/neorv32_cpu_control.vhd
7,8 → 7,9
-- # + Issue engine: Decodes compressed instructions, aligns and queues instruction words # |
-- # + Execute engine: Multi-cycle execution of instructions (generate control signals) # |
-- # + Trap engine: Handles interrupts and exceptions # |
-- # + CSR module: Read/write accesses to CSRs & HW counters # |
-- # + CSR module: Read/write access to control and status registers # |
-- # + Debug module: CPU debug mode handling (on-chip debugger) # |
-- # + Trigger module: Hardware-assisted breakpoints (on-chip debugger) # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
67,8 → 68,11
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit? |
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? |
-- Extension Options -- |
-- Tuning Options -- |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations |
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) |
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2 |
-- Physical memory protection (PMP) -- |
344,6 → 348,10
dcsr_rd : std_ulogic_vector(data_width_c-1 downto 0); -- dcsr (R/(W)): debug mode control and status register |
dpc : std_ulogic_vector(data_width_c-1 downto 0); -- dpc (R/W): debug mode program counter |
dscratch0 : std_ulogic_vector(data_width_c-1 downto 0); -- dscratch0 (R/W): debug mode scratch register 0 |
-- |
tdata1_exe : std_ulogic; -- enable (match) trigger |
tdata1_rd : std_ulogic_vector(data_width_c-1 downto 0); -- tdata1 (R/(W)): trigger register read-back |
tdata2 : std_ulogic_vector(data_width_c-1 downto 0); -- tdata2 (R/W): address-match register |
end record; |
signal csr : csr_t; |
|
355,6 → 363,7
running : std_ulogic; -- debug mode active |
pending : std_ulogic; -- waiting to start debug mode |
-- entering triggers -- |
trig_hw : std_ulogic; -- hardware trigger |
trig_break : std_ulogic; -- ebreak instruction |
trig_halt : std_ulogic; -- external request |
trig_step : std_ulogic; -- single-stepping mode |
378,6 → 387,9
-- access (privilege) check -- |
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights) |
|
-- hardware trigger module -- |
signal hw_trigger_fire : std_ulogic; |
|
begin |
|
-- **************************************************************************************************************************** |
681,11 → 693,6
execute_engine_fsm_sync: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
-- registers that DO require a specific reset state -- |
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned! |
execute_engine.state <= SYS_WAIT; |
execute_engine.sleep <= '0'; |
execute_engine.branched <= '1'; -- reset is a branch from "somewhere" |
-- no dedicated RESET required -- |
execute_engine.state_prev <= SYS_WAIT; -- actual reset value is not relevant |
execute_engine.i_reg <= (others => def_rst_val_c); |
695,6 → 702,11
execute_engine.i_reg_last <= (others => def_rst_val_c); |
execute_engine.next_pc <= (others => def_rst_val_c); |
ctrl <= (others => def_rst_val_c); |
-- registers that DO require a specific reset state -- |
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned! |
execute_engine.state <= SYS_WAIT; |
execute_engine.sleep <= '0'; |
execute_engine.branched <= '1'; -- reset is a branch from "somewhere" |
ctrl(ctrl_bus_rd_c) <= '0'; |
ctrl(ctrl_bus_wr_c) <= '0'; |
elsif rising_edge(clk_i) then |
983,9 → 995,9
execute_engine.is_ici_nxt <= cmd_issue.data(35); -- invalid decompressed instruction |
-- any reason to go to trap state? -- |
if (execute_engine.sleep = '1') or -- enter sleep state |
(trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (illegal instruction) |
(trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (e.g. illegal instruction) |
(trap_ctrl.env_start = '1') or -- pending trap (IRQ or exception) |
((cmd_issue.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address, if C disabled |
((cmd_issue.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address (if C disabled) |
(cmd_issue.data(34) = '1') then -- bus access fault during instruction fetch |
execute_engine.state_nxt <= TRAP_ENTER; |
else |
1127,6 → 1139,17
end if; |
|
|
when opcode_cust0_c => -- CFU: custom RISC-V instructions (CUSTOM0 OPCODE space) |
-- ------------------------------------------------------------ |
if (CPU_EXTENSION_RISCV_Zxcfu = true) then |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_cfu_c; -- trigger CFU CP |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; |
execute_engine.state_nxt <= ALU_WAIT; |
else |
execute_engine.state_nxt <= SYS_WAIT; |
end if; |
|
|
when others => -- system/csr access OR illegal opcode - nothing bad (= no commits) will happen here if there is an illegal opcode |
-- ------------------------------------------------------------ |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
1188,7 → 1211,7
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; |
-- wait for completion or abort on illegal instruction exception (the co-processor will also terminate operations) |
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (won't happen in case of an illegal instruction) |
execute_engine.state_nxt <= DISPATCH; |
end if; |
|
1296,8 → 1319,8
-- Machine-level code should read-back those CSRs after writing them to realize they are read-only. |
csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
|
-- machine information registers, read-only -- |
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mconfigptr_c => |
-- machine information registers & NEORV32-specific registers, read-only -- |
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mconfigptr_c | csr_mxisa_c => |
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only |
|
-- user-mode registers -- |
1348,6 → 1371,11
when csr_dcsr_c | csr_dpc_c | csr_dscratch0_c => |
csr_acc_valid <= debug_ctrl.running and bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- access only in debug-mode |
|
-- trigger module CSRs -- |
when csr_tselect_c | csr_tdata1_c | csr_tdata2_c | csr_tdata3_c | csr_tinfo_c | csr_tcontrol_c | csr_mcontext_c | csr_scontext_c => |
-- access in debug-mode or M-mode (M-mode: writes are ignored as DMODE is hardwired to 1) |
csr_acc_valid <= (debug_ctrl.running or csr.priv_m_mode) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); |
|
-- undefined / not implemented -- |
when others => |
csr_acc_valid <= '0'; -- invalid access |
1556,8 → 1584,18
end if; |
-- illegal E-CPU register? -- |
-- FIXME: rs2 is not checked! |
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
|
when opcode_cust0_c => -- CFU: custom instructions |
-- ------------------------------------------------------------ |
if (CPU_EXTENSION_RISCV_Zxcfu = true) then -- CFU extension implemented |
illegal_instruction <= '0'; |
else |
illegal_instruction <= '1'; |
end if; |
-- illegal E-CPU register? -- |
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); |
|
when others => -- undefined instruction -> illegal! |
-- ------------------------------------------------------------ |
illegal_instruction <= '1'; |
1620,8 → 1658,9
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_clr); |
end if; |
|
-- exception/interrupt buffer: enter debug mode -- |
-- exception queue / interrupt buffer: enter debug mode -- |
trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_clr); |
trap_ctrl.exc_buf(exception_db_hw_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_hw_c) or debug_ctrl.trig_hw) and (not trap_ctrl.exc_clr); |
trap_ctrl.irq_buf(interrupt_db_halt_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_halt; |
trap_ctrl.irq_buf(interrupt_db_step_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_step; |
|
1630,7 → 1669,7
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and mext_irq_i; |
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and mtime_irq_i; |
|
-- interrupt queue: NEORV32-specific fast interrupts (FIRQ) -- |
-- interrupt *queue*: NEORV32-specific fast interrupts (FIRQ) - require manual ACK/clear -- |
trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) <= (trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) or (csr.mie_firqe and firq_i)) and (not csr.mip_clr); |
|
-- trap environment control -- |
1718,6 → 1757,10
-- even if other IRQs are pending right now |
-- ---------------------------------------------------------------------------------------- |
|
-- hardware trigger (sync) -- |
elsif (trap_ctrl.exc_buf(exception_db_hw_c) = '1') then |
trap_ctrl.cause_nxt <= trap_db_hw_c; |
|
-- break instruction (sync) -- |
elsif (trap_ctrl.exc_buf(exception_db_break_c) = '1') then |
trap_ctrl.cause_nxt <= trap_db_break_c; |
1891,6 → 1934,9
csr.dcsr_cause <= (others => def_rst_val_c); |
csr.dpc <= (others => def_rst_val_c); |
csr.dscratch0 <= (others => def_rst_val_c); |
-- |
csr.tdata1_exe <= '0'; |
csr.tdata2 <= (others => def_rst_val_c); |
|
elsif rising_edge(clk_i) then |
-- write access? -- |
2061,7 → 2107,24
end if; |
end if; |
|
-- trigger module CSRs - only writable in DEBUG MODE (dmode == 1) -- |
-- -------------------------------------------------------------------- |
if (CPU_EXTENSION_RISCV_DEBUG = true) then |
if (csr.addr(11 downto 4) = csr_class_trigger_c) then -- trigger CSR class |
if (debug_ctrl.running = '1') then -- actual write only in debug mode |
-- R/W: tdata1 - match control -- |
if (csr.addr(3 downto 0) = csr_tdata1_c(3 downto 0)) then |
csr.tdata1_exe <= csr.wdata(2); |
end if; |
-- R/W: tdata2 - address compare -- |
if (csr.addr(3 downto 0) = csr_tdata2_c(3 downto 0)) then |
csr.tdata2 <= csr.wdata(data_width_c-1 downto 1) & '0'; |
end if; |
end if; |
end if; |
end if; |
|
|
-- -------------------------------------------------------------------------------- |
-- CSR access by hardware |
-- -------------------------------------------------------------------------------- |
2214,6 → 2277,12
csr.dscratch0 <= (others => '0'); |
end if; |
|
-- trigger module disabled -- |
if (CPU_EXTENSION_RISCV_DEBUG = false) then |
csr.tdata1_exe <= '0'; |
csr.tdata2 <= (others => '0'); |
end if; |
|
end if; |
end process csr_write_access; |
|
2270,7 → 2339,7
csr.mcycle_ovfl(0) <= csr.mcycle_nxt(csr.mcycle_nxt'left) and (not csr.mcountinhibit_cy); |
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access |
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0); |
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update |
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode |
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle_nxt(cpu_cnt_lo_width_c-1 downto 0); |
end if; |
else |
2295,7 → 2364,7
csr.minstret_ovfl(0) <= csr.minstret_nxt(csr.minstret_nxt'left) and (not csr.mcountinhibit_ir); |
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access |
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0); |
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') then -- non-inhibited automatic update |
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode |
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret_nxt(cpu_cnt_lo_width_c-1 downto 0); |
end if; |
else |
2389,7 → 2458,8
hpmcnt_trigger <= (others => '0'); -- default |
if (HPM_NUM_CNTS /= 0) then |
for i in 0 to HPM_NUM_CNTS-1 loop |
hpmcnt_trigger(i) <= or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0)); |
-- do not increment if CPU is in debug mode -- |
hpmcnt_trigger(i) <= or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0)) and (not debug_ctrl.running); |
end loop; -- i |
end if; |
end if; |
2716,6 → 2786,38
when csr_dpc_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dpc; else NULL; end if; -- dpc (r/w): debug mode program counter |
when csr_dscratch0_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dscratch0; else NULL; end if; -- dscratch0 (r/w): debug mode scratch register 0 |
|
-- trigger module CSRs -- |
-- -------------------------------------------------------------------- |
-- when csr_tselect_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- tselect (r/w): always zero = only 1 trigger available |
when csr_tdata1_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.tdata1_rd; else NULL; end if; -- tdata1 (r/w): match control |
when csr_tdata2_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.tdata2; else NULL; end if; -- tdata2 (r/w): address-compare |
-- when csr_tdata3_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- tdata3 (r/w): implemented but always zero |
when csr_tinfo_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= x"00000004"; else NULL; end if; -- tinfo (r/w): address-match trigger only |
-- when csr_tcontrol_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- tcontrol (r/w): implemented but always zero |
-- when csr_mcontext_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- mcontext (r/w): implemented but always zero |
-- when csr_scontext_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- scontext (r/w): implemented but always zero |
|
-- NEORV32-specific (RISC-V "custom") read-only CSRs -- |
-- -------------------------------------------------------------------- |
-- machine extended ISA extensions information -- |
when csr_mxisa_c => |
-- ISA (sub-)extensions -- |
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr: privileged architecture (!!!) |
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei: instruction stream sync. |
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul: mul/div |
csr.rdata(03) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- Zxcfu: custom RISC-V instructions |
csr.rdata(04) <= '0'; -- reserved |
csr.rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers, "F-alternative" |
csr.rdata(06) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and |
bool_to_ulogic_f(boolean(CPU_CNT_WIDTH /= 64)); -- Zxscnt: reduced-size CPU counters (from Zicntr) |
csr.rdata(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base instructions, cycle and time CSRs |
csr.rdata(08) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP: physical memory protection (Zspmp) |
csr.rdata(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- Zihpm: hardware performance monitors |
csr.rdata(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- RISC-V debug mode |
-- ISA options -- |
csr.rdata(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extensions only) |
csr.rdata(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters) |
|
-- undefined/unavailable -- |
-- -------------------------------------------------------------------- |
when others => |
2751,8 → 2853,9
case debug_ctrl.state is |
|
when DEBUG_OFFLINE => -- not in debug mode, waiting for entering request |
if (debug_ctrl.trig_halt = '1') or -- external request (from DM) |
(debug_ctrl.trig_break = '1') or -- ebreak instruction |
if (debug_ctrl.trig_halt = '1') or -- external request (from DM) |
(debug_ctrl.trig_break = '1') or -- ebreak instruction |
(debug_ctrl.trig_hw = '1') or -- hardware trigger module |
(debug_ctrl.trig_step = '1') then -- single-stepping mode |
debug_ctrl.state <= DEBUG_PENDING; |
end if; |
2788,11 → 2891,12
debug_ctrl.running <= '1' when ((debug_ctrl.state = DEBUG_ONLINE) or (debug_ctrl.state = DEBUG_EXIT)) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; |
|
-- entry debug mode triggers -- |
debug_ctrl.trig_break <= trap_ctrl.break_point and (debug_ctrl.running or -- we are in debug mode: re-enter debug mode |
debug_ctrl.trig_hw <= hw_trigger_fire and (not debug_ctrl.running); -- enter debug mode by HW trigger module request |
debug_ctrl.trig_break <= trap_ctrl.break_point and (debug_ctrl.running or -- re-enter debug mode |
(csr.priv_m_mode and csr.dcsr_ebreakm and (not debug_ctrl.running)) or -- enabled goto-debug-mode in machine mode on "ebreak" |
(csr.priv_u_mode and csr.dcsr_ebreaku and (not debug_ctrl.running))); -- enabled goto-debug-mode in user mode on "ebreak" |
debug_ctrl.trig_halt <= debug_ctrl.ext_halt_req and (not debug_ctrl.running); -- external halt request (if not halted already) |
debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode) |
debug_ctrl.trig_halt <= debug_ctrl.ext_halt_req and (not debug_ctrl.running); -- external halt request (if not halted already) |
debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode) |
|
|
-- Debug Control and Status Register (dcsr) - Read-Back ----------------------------------- |
2799,19 → 2903,49
-- ------------------------------------------------------------------------------------------- |
csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec |
csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved |
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter) |
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented |
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented |
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter) |
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping |
csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME/TODO ??? |
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual FIXME/TODO ??? |
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter) |
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented |
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented |
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter) |
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping |
csr.dcsr_rd(10) <= '1'; -- stopcount: standard counters and HPMs are stopped when in debug mode |
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual |
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause |
csr.dcsr_rd(05) <= '0'; -- reserved |
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode |
csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt |
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode |
csr.dcsr_rd(05) <= '0'; -- reserved |
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode |
csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt |
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode |
csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered |
|
|
-- **************************************************************************************************************************** |
-- Hardware Trigger Module (Part of the On-Chip Debugger) |
-- **************************************************************************************************************************** |
|
-- trigger to enter debug-mode: instruction address match (fire AFTER execution) -- |
hw_trigger_fire <= '1' when (CPU_EXTENSION_RISCV_DEBUG = true) and (csr.tdata1_exe = '1') and |
(csr.tdata2(data_width_c-1 downto 1) = execute_engine.pc(data_width_c-1 downto 1)) else '0'; |
|
|
-- Match Control CSR (mcontrol @ tdata1) - Read-Back -------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
csr.tdata1_rd(31 downto 28) <= "0010"; -- type: address(/data) match trigger |
csr.tdata1_rd(27) <= '1'; -- dmode: only debug-mode can write tdata* registers |
csr.tdata1_rd(26 downto 21) <= "000000"; -- maskmax: only exact values |
csr.tdata1_rd(20) <= '0'; -- hit: feature not implemented |
csr.tdata1_rd(19) <= '0'; -- select: fire on address match |
csr.tdata1_rd(18) <= '1'; -- timing: trigger **after** executing the triggering instruction |
csr.tdata1_rd(17 downto 16) <= "00"; -- sizelo: match against an access of any size |
csr.tdata1_rd(15 downto 12) <= "0001"; -- action: enter debug mode on trigger |
csr.tdata1_rd(11) <= '0'; -- chain: chaining not supported - there is only one trigger |
csr.tdata1_rd(10 downto 07) <= "0000"; -- match: only full-address-match |
csr.tdata1_rd(6) <= '1'; -- m: trigger enabled when in machine mode |
csr.tdata1_rd(5) <= '0'; -- h: hypervisor mode not supported |
csr.tdata1_rd(4) <= '0'; -- s: supervisor mode not supported |
csr.tdata1_rd(3) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- u: trigger enabled when in user mode |
csr.tdata1_rd(2) <= csr.tdata1_exe; -- execute: enable trigger |
csr.tdata1_rd(1) <= '0'; -- store: store address or data matching not supported |
csr.tdata1_rd(0) <= '0'; -- load: load address or data matching not supported |
|
|
end neorv32_cpu_control_rtl; |
/neorv32_cpu_cp_cfu.vhd
0,0 → 1,189
-- ################################################################################################# |
-- # << NEORV32 - CPU Co-Processor: Custom (Instructions) Functions Unit >> # |
-- # ********************************************************************************************* # |
-- # Intended for user-defined custom RISC-V instructions (R2-type format only). See the CPU's # |
-- # documentation for more information. # |
-- # # |
-- # NOTE: Take a look at the "software-counterpart" of this CFU example in 'sw/example/demo_cfu'. # |
-- # # |
-- # TODO: Maybe turn this into a wrapper for CFU-playground templates. # |
-- # -> https://github.com/google/CFU-Playground # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_cpu_cp_cfu is |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
start_i : in std_ulogic; -- trigger operation |
-- data input -- |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 |
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 |
-- result and status -- |
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result |
valid_o : out std_ulogic -- data output valid |
); |
end neorv32_cpu_cp_cfu; |
|
architecture neorv32_cpu_cp_cfu_rtl of neorv32_cpu_cp_cfu is |
|
-- CFU controller - do not modify -- |
type control_t is record |
busy : std_ulogic; -- CFU is busy |
done : std_ulogic; -- set to '1' when processing is done |
result : std_ulogic_vector(data_width_c-1 downto 0); -- user's processing result (for write-back to register file) |
funct3 : std_ulogic_vector(2 downto 0); -- "funct3" bit-field from custom instruction |
funct7 : std_ulogic_vector(6 downto 0); -- "funct7" bit-field from custom instruction |
end record; |
signal control : control_t; |
|
begin |
|
-- CFU Controller ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- This controller is required to handle the CPU/pipeline interface. Do not modify! |
cfu_control: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
res_o <= (others => '0'); |
control.busy <= '0'; |
elsif rising_edge(clk_i) then |
res_o <= (others => '0'); -- default |
if (control.busy = '0') then -- idle |
if (start_i = '1') then |
control.busy <= '1'; |
end if; |
else -- busy |
if (control.done = '1') or (ctrl_i(ctrl_trap_c) = '1') then -- processing done? abort if trap |
res_o <= control.result; -- actual output for only one cycle |
control.busy <= '0'; |
end if; |
end if; |
end if; |
end process cfu_control; |
|
-- CPU feedback -- |
valid_o <= control.busy and control.done; -- set one cycle before result data |
|
-- pack user-defined instruction function bits -- |
control.funct3 <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c); |
control.funct7 <= ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_5_c); |
|
|
-- **************************************************************************************************************************** |
-- Actual CFU user logic - Add your custom logic below |
-- **************************************************************************************************************************** |
|
-- The CFU only supports the R2-type RISC-V instruction format. This format consists of two source registers (rs1 and rs2), |
-- a destination register (rd) and two "immediate" bit-fields (funct7 and funct3). It is up to the user to decide which |
-- of these fields are actually used by the CFU logic. |
-- |
-- The user logic of the CFU has access to the following pre-defined signals: |
-- |
-- ------------------------------------------------------------------------------------------- |
-- Input Operands |
-- ------------------------------------------------------------------------------------------- |
-- > rs1_i (input, 32-bit): source register 1 |
-- > rs2_i (input, 32-bit): source register 2 |
-- > control.funct3 (input, 3-bit): 3-bit function select / immediate, driven by instruction word's funct3 bit field |
-- > control.funct7 (input, 7-bit): 7-bit function select / immediate, driven by instruction word's funct7 bit field |
-- |
-- The two signal rs1_i and rs2_i provide the data read from the CPU's register file, which is adressed by the |
-- instruction word's rs1 and rs2 bit-fields. |
-- |
-- The actual CFU operation can be defined by using the funct3 and funct7 signals. Both signals are directly driven by |
-- the according bit-fields of the custom instruction. Note that these signals represent "immediates" that have to be |
-- static already at compile time. These immediates can be used to select the actual function to be executed or they |
-- can be used as immediates for certain operations (like shift amounts, addresses or offsets). |
-- |
-- [NOTE]: rs1_i and rs2_i are directly driven by the register file (block RAM). It is recommended to buffer these signals |
-- using CFU-internal registers before using them for computations as the rs1 and rs2 nets need to drive a lot of logic |
-- in the CPU. |
-- |
-- [NOTE]: It is not possible for the CFU and it's according instruction words to cause any kind of exception. The CPU |
-- control logic only verifies the custom instructions OPCODE and checks if the CFU is implemented at all. No combination |
-- of funct7 and funct3 will cause an exception. |
-- |
-- ------------------------------------------------------------------------------------------- |
-- Result output |
-- ------------------------------------------------------------------------------------------- |
-- > control.result (output, 32-bit): processing result |
-- |
-- When the CFU has finished computation, the data in the control.result signal will be written to the CPU's register |
-- file. The destination register is addressed by the rd bit-field in the instruction. The CFU result output is |
-- registered in the CFU controller (see above) so do not worry too much about increasing the CPU's critical path. ;) |
-- |
-- ------------------------------------------------------------------------------------------- |
-- Control |
-- ------------------------------------------------------------------------------------------- |
-- > rstn_i (input, 1-bit): asynchronous reset, low-active |
-- > clk_i (input, 1-bit): main clock, triggering on rising edge |
-- > start_i (input, 1-bit): operation trigger (start processing, high for one cycle) |
-- > control.done (output, 1-bit): set high when processing is done |
-- |
-- For pure-combinatorial instructions (without internal state) a subset of those signals is sufficient; see the minimal |
-- example below. If the CFU shall also include states (like memories, registers or "buffers") the start_i signal can be |
-- used to trigger a new CFU operation. As soon as all internal computations have completed, the control.done signal has |
-- to be set to indicate completion. This will write the result data (control.result) to the CPU register file. |
-- |
-- [IMPORTANT]: The control.done *has to be set at some time*, otherwise the CPU will be halted forever. |
|
|
-- User Logic Example --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
user_logic_function_select: process(control, rs1_i, rs2_i) |
begin |
-- This is a simple ALU that implements four pure-combinatorial instructions. |
-- The actual function to-be-executed is selected by the "funct3" bit-field of the custom instruction. |
case control.funct3 is |
when "000" => control.result <= bin_to_gray_f(rs1_i); -- funct3 = "000": convert rs1 from binary to gray |
when "001" => control.result <= gray_to_bin_f(rs1_i); -- funct3 = "001": convert rs1 from gray to binary |
when "010" => control.result <= bit_rev_f(rs1_i); -- funct3 = "010": bit-reversal of rs1 |
when "011" => control.result <= rs1_i xnor rs2_i; -- funct3 = "011": XNOR input operands |
when others => control.result <= (others => '0'); -- not implemented, set to zero |
end case; |
end process user_logic_function_select; |
|
-- processing done? -- |
control.done <= '1'; -- we are just doing pure-combinatorial data processing here, which is done "immediately" |
|
|
end neorv32_cpu_cp_cfu_rtl; |
/neorv32_imem.entity.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
53,6 → 53,7
addr_i : in std_ulogic_vector(31 downto 0); -- address |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic -- transfer error |
); |
end neorv32_imem; |
/neorv32_package.vhd
44,8 → 44,9
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address |
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address |
|
-- CPU core -- |
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value) |
-- use dedicated hardware reset value for UNCRITICAL registers -- |
-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value |
constant dedicated_reset_c : boolean := false; |
|
-- "critical" number of implemented PMP regions -- |
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces |
53,7 → 54,8
constant pmp_num_regions_critical_c : natural := 8; -- default=8 |
|
-- "response time window" for processor-internal modules -- |
constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2) |
-- = cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2) |
constant max_proc_int_response_time_c : natural := 15; |
|
-- jtag tap - identifier -- |
constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version |
63,7 → 65,7
-- Architecture Constants (do not modify!) ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- native data path width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060700"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060800"; -- no touchy! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
|
-- Check if we're inside the Matrix ------------------------------------------------------- |
82,8 → 84,8
|
-- External Interface Types --------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0); |
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type |
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0); |
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type |
|
-- Internal Interface Types --------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
408,7 → 410,7
constant cmp_equal_c : natural := 0; |
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons |
|
-- RISC-V Opcode Layout ------------------------------------------------------------------- |
-- RISC-V 32-Bit Instruction Word Layout -------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0 |
constant instr_opcode_msb_c : natural := 6; -- opcode bit 6 |
454,6 → 456,9
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension) |
-- floating point operations (Zfinx-only) (F/D/H/Q) -- |
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single operand instruction |
-- official "custom0/1" RISC-V opcodes - free for custom instructions -- |
constant opcode_cust0_c : std_ulogic_vector(6 downto 0) := "0001011"; -- custom instructions 0 |
--constant opcode_cust1_c : std_ulogic_vector(6 downto 0) := "0101011"; -- custom instructions 1 |
|
-- RISC-V Funct3 -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
484,12 → 489,12
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and |
-- system/csr -- |
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi, ... |
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w |
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit |
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit |
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate |
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate |
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate |
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- csr r/w |
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- csr read & set bit |
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- csr read & clear bit |
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- csr r/w immediate |
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- csr read & set bit immediate |
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- csr read & clear bit immediate |
-- fence -- |
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP) |
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instruction stream sync |
497,25 → 502,25
-- RISC-V Funct12 ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- system -- |
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL |
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK |
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET |
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI |
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- DRET |
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ecall |
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- ebreak |
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- mret |
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- wfi |
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- dret |
|
-- RISC-V Funct5 -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- atomic operations -- |
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR |
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC |
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- lr.w |
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- sc.w |
|
-- RISC-V Floating-Point Stuff ------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
-- formats -- |
constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit) |
constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit) |
constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit) |
constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit) |
--constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit) |
--constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit) |
--constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit) |
|
-- number class flags -- |
constant fp_class_neg_inf_c : natural := 0; -- negative infinity |
687,6 → 692,16
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed"; |
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee"; |
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef"; |
-- trigger module registers -- |
constant csr_class_trigger_c : std_ulogic_vector(07 downto 0) := x"7a"; -- trigger registers |
constant csr_tselect_c : std_ulogic_vector(11 downto 0) := x"7a0"; |
constant csr_tdata1_c : std_ulogic_vector(11 downto 0) := x"7a1"; |
constant csr_tdata2_c : std_ulogic_vector(11 downto 0) := x"7a2"; |
constant csr_tdata3_c : std_ulogic_vector(11 downto 0) := x"7a3"; |
constant csr_tinfo_c : std_ulogic_vector(11 downto 0) := x"7a4"; |
constant csr_tcontrol_c : std_ulogic_vector(11 downto 0) := x"7a5"; |
constant csr_mcontext_c : std_ulogic_vector(11 downto 0) := x"7a8"; |
constant csr_scontext_c : std_ulogic_vector(11 downto 0) := x"7aa"; |
-- debug mode registers -- |
constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers |
constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0"; |
774,13 → 789,17
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; |
constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := x"f15"; |
|
-- Co-Processor IDs ----------------------------------------------------------------------- |
-- <<< NEORV32-specific (custom) read-only CSRs >>> --- |
-- machine extended ISA extensionss information -- |
constant csr_mxisa_c : std_ulogic_vector(11 downto 0) := x"fc0"; |
|
-- CPU Co-Processor IDs ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant cp_sel_shifter_c : std_ulogic_vector(2 downto 0) := "000"; -- CP0: shift operations (base ISA) |
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- CP1: multiplication/division operations ('M' extensions) |
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- CP2: bit manipulation ('B' extensions) |
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- CP3: floating-point unit ('Zfinx' extension) |
--constant cp_sel_res0_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: reserved |
constant cp_sel_cfu_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: custom instructions CFU ('Zxcfu' extension) |
--constant cp_sel_res1_c : std_ulogic_vector(2 downto 0) := "101"; -- CP5: reserved |
--constant cp_sel_res2_c : std_ulogic_vector(2 downto 0) := "110"; -- CP6: reserved |
--constant cp_sel_res3_c : std_ulogic_vector(2 downto 0) := "111"; -- CP7: reserved |
806,7 → 825,7
-- ------------------------------------------------------------------------------------------- |
-- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak) |
-- MSB-1: 1 = entry to debug mode, 0 = normal trapping |
-- RISC-V compliant sync. exceptions -- |
-- RISC-V compliant synchronous exceptions -- |
constant trap_ima_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00000"; -- 0.0: instruction misaligned |
constant trap_iba_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00001"; -- 0.1: instruction access fault |
constant trap_iil_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00010"; -- 0.2: illegal instruction |
816,12 → 835,20
constant trap_sma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00110"; -- 0.6: store address misaligned |
constant trap_sbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00111"; -- 0.7: store access fault |
constant trap_uenv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01000"; -- 0.8: environment call from u-mode |
--constant trap_senv_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01001"; -- 0.9: environment call from s-mode |
--constant trap_henv_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01010"; -- 0.10: environment call from h-mode |
constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"; -- 0.11: environment call from m-mode |
-- RISC-V compliant interrupts (async. exceptions) -- |
--constant trap_ipf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01100"; -- 0.12: instruction page fault |
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01101"; -- 0.13: load page fault |
--constant trap_???_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01110"; -- 0.14: reserved |
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01111"; -- 0.15: store page fault |
-- NEORV32-specific (custom) synchronous exceptions -- |
-- none implemented yet |
-- RISC-V compliant asynchronous exceptions (interrupts) -- |
constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"; -- 1.3: machine software interrupt |
constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"; -- 1.7: machine timer interrupt |
constant trap_mei_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "01011"; -- 1.11: machine external interrupt |
-- NEORV32-specific (custom) interrupts (async. exceptions) -- |
-- NEORV32-specific (custom) asynchronous exceptions (interrupts) -- |
constant trap_firq0_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10000"; -- 1.16: fast interrupt 0 |
constant trap_firq1_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10001"; -- 1.17: fast interrupt 1 |
constant trap_firq2_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10010"; -- 1.18: fast interrupt 2 |
838,10 → 865,11
constant trap_firq13_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11101"; -- 1.29: fast interrupt 13 |
constant trap_firq14_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11110"; -- 1.30: fast interrupt 14 |
constant trap_firq15_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11111"; -- 1.31: fast interrupt 15 |
-- entering debug mode - cause -- |
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- break instruction (sync / EXCEPTION) |
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async / IRQ) |
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async / IRQ) |
-- entering debug mode (sync./async. exceptions) -- |
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00001"; -- break instruction (sync) |
constant trap_db_hw_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- hardware trigger (sync) |
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async) |
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async) |
|
-- CPU Control Exception System ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
858,8 → 886,9
constant exception_laccess_c : natural := 9; -- load access fault |
-- for debug mode only -- |
constant exception_db_break_c : natural := 10; -- enter debug mode via ebreak instruction ("sync EXCEPTION") |
constant exception_db_hw_c : natural := 11; -- enter debug mode via hw trigger ("sync EXCEPTION") |
-- |
constant exception_width_c : natural := 11; -- length of this list in bits |
constant exception_width_c : natural := 12; -- length of this list in bits |
-- interrupt source bits -- |
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt |
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt |
911,7 → 940,7
-- |
constant hpmcnt_event_size_c : natural := 15; -- length of this list |
|
-- Clock Generator ------------------------------------------------------------------------ |
-- SoC Clock Generator -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant clk_div2_c : natural := 0; |
constant clk_div4_c : natural := 1; |
945,7 → 974,8
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? |
-- Extension Options -- |
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit? |
-- Tuning Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) |
1062,8 → 1092,8
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
-- TWI (available if IO_TWI_EN = true) -- |
twi_sda_io : inout std_logic := 'U'; -- twi serial data line |
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line |
twi_sda_io : inout std_logic; -- twi serial data line |
twi_scl_io : inout std_logic; -- twi serial clock line |
-- PWM (available if IO_PWM_NUM_CH > 0) -- |
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels |
-- Custom Functions Subsystem IO -- |
1104,8 → 1134,9
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit? |
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? |
-- Extension Options -- |
-- Tuning Options -- |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations |
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) |
1181,8 → 1212,11
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit? |
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? |
-- Extension Options -- |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations |
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) |
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2 |
-- Physical memory protection (PMP) -- |
1267,6 → 1301,7
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension? |
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) |
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit? |
-- Extension Options -- |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations |
1379,6 → 1414,24
); |
end component; |
|
-- Component: CPU Co-Processor Custom (Instr.) Functions Unit ('Zxcfu' extension) --------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu_cp_cfu |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
start_i : in std_ulogic; -- trigger operation |
-- data input -- |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 |
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 |
-- result and status -- |
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result |
valid_o : out std_ulogic -- data output valid |
); |
end component; |
|
-- Component: CPU Bus Interface ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu_bus |
1574,7 → 1627,8
addr_i : in std_ulogic_vector(31 downto 0); -- address |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic -- transfer error |
); |
end component; |
|
1606,9 → 1660,11
port ( |
clk_i : in std_ulogic; -- global clock line |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic -- transfer error |
); |
end component; |
|
2017,54 → 2073,42
component neorv32_sysinfo |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz |
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) |
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters? |
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? |
-- Extension Options -- |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations |
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) |
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz |
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM |
-- Physical memory protection (PMP) -- |
PMP_NUM_REGIONS : natural; -- number of regions (0..64) |
PMP_NUM_REGIONS : natural; -- number of regions (0..64) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes |
-- Internal Data memory -- |
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes |
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_EN : boolean; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2 |
ICACHE_EN : boolean; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2 |
-- External memory interface -- |
MEM_EXT_EN : boolean; -- implement external memory bus interface? |
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian |
MEM_EXT_EN : boolean; -- implement external memory bus interface? |
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian |
-- On-Chip Debugger -- |
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD? |
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD? |
-- Processor peripherals -- |
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)? |
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)? |
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)? |
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement |
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)? |
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)? |
IO_SLINK_EN : boolean; -- implement stream link interface? |
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean -- implement execute in place module (XIP)? |
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)? |
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)? |
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)? |
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement |
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)? |
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)? |
IO_SLINK_EN : boolean; -- implement stream link interface? |
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean -- implement execute in place module (XIP)? |
); |
port ( |
-- host access -- |
/neorv32_sysinfo.vhd
45,54 → 45,42
entity neorv32_sysinfo is |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz |
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) |
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters? |
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? |
-- Extension Options -- |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations |
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) |
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz |
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM |
-- Physical memory protection (PMP) -- |
PMP_NUM_REGIONS : natural; -- number of regions (0..64) |
PMP_NUM_REGIONS : natural; -- number of regions (0..64) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes |
-- Internal Data memory -- |
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes |
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_EN : boolean; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2 |
ICACHE_EN : boolean; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2 |
-- External memory interface -- |
MEM_EXT_EN : boolean; -- implement external memory bus interface? |
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian |
MEM_EXT_EN : boolean; -- implement external memory bus interface? |
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian |
-- On-Chip Debugger -- |
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD? |
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD? |
-- Processor peripherals -- |
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)? |
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)? |
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)? |
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement |
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)? |
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)? |
IO_SLINK_EN : boolean; -- implement stream link interface? |
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean -- implement execute in place module (XIP)? |
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)? |
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)? |
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)? |
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement |
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)? |
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)? |
IO_SLINK_EN : boolean; -- implement stream link interface? |
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean -- implement execute in place module (XIP)? |
); |
port ( |
-- host access -- |
137,24 → 125,8
-- SYSINFO(0): Processor (primary) clock frequency -- |
sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); |
|
-- SYSINFO(1): CPU configuration -- |
sysinfo_mem(1)(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr |
sysinfo_mem(1)(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei |
sysinfo_mem(1)(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul |
-- |
sysinfo_mem(1)(04 downto 03) <= (others => '0'); -- reserved |
-- |
sysinfo_mem(1)(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx ("F-alternative") |
sysinfo_mem(1)(06) <= bool_to_ulogic_f(boolean(CPU_CNT_WIDTH /= 64)); -- reduced-size CPU counters (Zxscnt) |
sysinfo_mem(1)(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- base CPU counter |
sysinfo_mem(1)(08) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP (physical memory protection) |
sysinfo_mem(1)(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- HPM (hardware performance monitors) |
sysinfo_mem(1)(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- RISC-V debug mode |
-- |
sysinfo_mem(1)(29 downto 11) <= (others => '0'); -- reserved |
-- misc -- |
sysinfo_mem(1)(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extension only) |
sysinfo_mem(1)(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (like barrel shifters) |
-- SYSINFO(1): reserved -- |
sysinfo_mem(1) <= (others => '0'); -- reserved |
|
-- SYSINFO(2): Implemented processor devices/features -- |
-- Memory -- |
/neorv32_top.vhd
67,8 → 67,9
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit? |
|
-- Extension Options -- |
-- Tuning Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) |
205,8 → 206,8
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select |
|
-- TWI (available if IO_TWI_EN = true) -- |
twi_sda_io : inout std_logic := 'U'; -- twi serial data line |
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line |
twi_sda_io : inout std_logic; -- twi serial data line |
twi_scl_io : inout std_logic; -- twi serial clock line |
|
-- PWM (available if IO_PWM_NUM_CH > 0) -- |
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels |
492,6 → 493,7
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit? |
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode? |
-- Extension Options -- |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier |
746,9 → 748,9
addr_i => p_bus.addr, -- address |
data_i => p_bus.wdata, -- data in |
data_o => resp_bus(RESP_IMEM).rdata, -- data out |
ack_o => resp_bus(RESP_IMEM).ack -- transfer acknowledge |
ack_o => resp_bus(RESP_IMEM).ack, -- transfer acknowledge |
err_o => resp_bus(RESP_IMEM).err -- transfer error |
); |
resp_bus(RESP_IMEM).err <= '0'; -- no access error possible |
end generate; |
|
neorv32_int_imem_inst_false: |
796,11 → 798,12
port map ( |
clk_i => clk_i, -- global clock line |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
addr_i => p_bus.addr, -- address |
data_o => resp_bus(RESP_BOOTROM).rdata, -- data out |
ack_o => resp_bus(RESP_BOOTROM).ack -- transfer acknowledge |
ack_o => resp_bus(RESP_BOOTROM).ack, -- transfer acknowledge |
err_o => resp_bus(RESP_BOOTROM).err -- transfer error |
); |
resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible |
end generate; |
|
neorv32_boot_rom_inst_false: |
1494,54 → 1497,42
neorv32_sysinfo_inst: neorv32_sysinfo |
generic map ( |
-- General -- |
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader? |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? |
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters? |
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode? |
-- Extension Options -- |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations |
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) |
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader? |
-- Physical memory protection (PMP) -- |
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) |
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) |
-- internal Instruction memory -- |
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
-- Internal Data memory -- |
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_EN => ICACHE_EN, -- implement instruction cache |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2 |
ICACHE_EN => ICACHE_EN, -- implement instruction cache |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2 |
-- External memory interface -- |
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface? |
MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian |
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface? |
MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian |
-- On-Chip Debugger -- |
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD? |
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD? |
-- Processor peripherals -- |
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? |
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? |
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? |
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement |
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? |
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? |
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? |
IO_SLINK_EN => io_slink_en_c, -- implement stream link interface? |
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)? |
IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)? |
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? |
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? |
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? |
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? |
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? |
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement |
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? |
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? |
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? |
IO_SLINK_EN => io_slink_en_c, -- implement stream link interface? |
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement |
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)? |
IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)? |
) |
port map ( |
-- host access -- |