URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/rtl/system_integration
- from Rev 69 to Rev 70
- ↔ Reverse comparison
Rev 69 → Rev 70
/neorv32_ProcessorTop_stdlogic.vhd
3,7 → 3,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
114,7 → 114,8
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits |
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits |
IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean := false -- implement execute in place module (XIP)? |
); |
port ( |
-- Global control -- |
141,6 → 142,11
-- Advanced memory control signals (available if MEM_EXT_EN = true) -- |
fence_o : out std_logic; -- indicates an executed FENCE operation |
fencei_o : out std_logic; -- indicates an executed FENCEI operation |
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- |
xip_csn_o : out std_logic; -- chip-select, low-active |
xip_clk_o : out std_logic; -- serial clock |
xip_sdi_i : in std_logic := 'L'; -- device data input |
xip_sdo_o : out std_logic; -- controller data output |
-- TX stream interfaces (available if SLINK_NUM_TX > 0) -- |
slink_tx_dat_o : out sdata_8x32r_t; -- output data |
slink_tx_val_o : out std_logic_vector(7 downto 0); -- valid output |
171,7 → 177,7
twi_sda_io : inout std_logic; -- twi serial data line |
twi_scl_io : inout std_logic; -- twi serial clock line |
-- PWM (available if IO_PWM_NUM_CH > 0) -- |
pwm_o : out std_logic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels |
pwm_o : out std_logic_vector(59 downto 0); -- pwm channels |
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs |
cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs |
181,7 → 187,7
mtime_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false) |
mtime_o : out std_logic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) |
-- External platform interrupts (available if XIRQ_NUM_CH > 0) -- |
xirq_i : in std_logic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels |
xirq_i : in std_logic_vector(31 downto 0) := (others => '0'); -- IRQ channels |
-- CPU Interrupts -- |
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_logic := '0'; -- machine software interrupt |
220,6 → 226,11
signal fence_o_int : std_ulogic; |
signal fencei_o_int : std_ulogic; |
-- |
signal xip_csn_o_int : std_ulogic; |
signal xip_clk_o_int : std_ulogic; |
signal xip_sdi_i_int : std_ulogic; |
signal xip_sdo_o_int : std_ulogic; |
-- |
signal slink_tx_dat_o_int : sdata_8x32_t; |
signal slink_tx_val_o_int : std_logic_vector(7 downto 0); |
signal slink_tx_rdy_i_int : std_logic_vector(7 downto 0); |
245,7 → 256,7
signal spi_sdi_i_int : std_ulogic; |
signal spi_csn_o_int : std_ulogic_vector(07 downto 0); |
-- |
signal pwm_o_int : std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); |
signal pwm_o_int : std_ulogic_vector(59 downto 0); |
-- |
signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); |
signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); |
255,7 → 266,7
signal mtime_i_int : std_ulogic_vector(63 downto 0); |
signal mtime_o_int : std_ulogic_vector(63 downto 0); |
-- |
signal xirq_i_int : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); |
signal xirq_i_int : std_ulogic_vector(31 downto 0); |
-- |
signal mtime_irq_i_int : std_ulogic; |
signal msw_irq_i_int : std_ulogic; |
340,7 → 351,8
IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits |
IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits |
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_GPTMR_EN => IO_GPTMR_EN -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)? |
IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)? |
) |
port map ( |
-- Global control -- |
367,6 → 379,11
-- Advanced memory control signals (available if MEM_EXT_EN = true) -- |
fence_o => fence_o_int, -- indicates an executed FENCE operation |
fencei_o => fencei_o_int, -- indicates an executed FENCEI operation |
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- |
xip_csn_o => xip_csn_o_int, -- chip-select, low-active |
xip_clk_o => xip_clk_o_int, -- serial clock |
xip_sdi_i => xip_sdi_i_int, -- device data input |
xip_sdo_o => xip_sdo_o_int, -- controller data output |
-- TX stream interfaces (available if SLINK_NUM_TX > 0) -- |
slink_tx_dat_o => slink_tx_dat_o_int, -- output data |
slink_tx_val_o => slink_tx_val_o_int, -- valid output |
439,6 → 456,11
fence_o <= std_logic(fence_o_int); |
fencei_o <= std_logic(fencei_o_int); |
|
xip_csn_o <= std_logic(xip_csn_o_int); |
xip_clk_o <= std_logic(xip_clk_o_int); |
xip_sdi_i_int <= std_ulogic(xip_sdi_i); |
xip_sdo_o <= std_logic(xip_sdo_o_int); |
|
slink_tx_val_o <= std_logic_vector(slink_tx_val_o_int); |
slink_tx_rdy_i_int <= std_ulogic_vector(slink_tx_rdy_i); |
slink_rx_val_i_int <= std_ulogic_vector(slink_rx_val_i); |
/neorv32_SystemTop_AvalonMM.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
125,7 → 125,8
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits |
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two |
IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean := false -- implement execute in place module (XIP)? |
); |
port ( |
-- Global control -- |
142,16 → 143,22
-- AvalonMM interface |
read_o : out std_logic; |
write_o : out std_logic; |
waitrequest_i : in std_logic := '0'; |
waitrequest_i : in std_logic := '0'; |
byteenable_o : out std_logic_vector(3 downto 0); |
address_o : out std_logic_vector(31 downto 0); |
writedata_o : out std_logic_vector(31 downto 0); |
readdata_i : in std_logic_vector(31 downto 0) := (others => '0'); |
readdata_i : in std_logic_vector(31 downto 0) := (others => '0'); |
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) -- |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
|
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- |
xip_csn_o : out std_ulogic; -- chip-select, low-active |
xip_clk_o : out std_ulogic; -- serial clock |
xip_sdi_i : in std_ulogic := 'L'; -- device data input |
xip_sdo_o : out std_ulogic; -- controller data output |
|
-- TX stream interfaces (available if SLINK_NUM_TX > 0) -- |
slink_tx_dat_o : out sdata_8x32_t; -- output data |
slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output |
189,7 → 196,7
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line |
|
-- PWM (available if IO_PWM_NUM_CH > 0) -- |
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels |
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels |
|
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit |
203,7 → 210,7
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) |
|
-- External platform interrupts (available if XIRQ_NUM_CH > 0) -- |
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels |
xirq_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels |
|
-- CPU interrupts -- |
mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false |
319,7 → 326,8
IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, |
IO_NEOLED_EN => IO_NEOLED_EN, |
IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO, |
IO_GPTMR_EN => IO_GPTMR_EN |
IO_GPTMR_EN => IO_GPTMR_EN, |
IO_XIP_EN => IO_XIP_EN |
) |
port map ( |
-- Global control -- |
350,6 → 358,12
fence_o => fence_o, |
fencei_o => fencei_o, |
|
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- |
xip_csn_o => xip_csn_o, |
xip_clk_o => xip_clk_o, |
xip_sdi_i => xip_sdi_i, |
xip_sdo_o => xip_sdo_o, |
|
-- TX stream interfaces (available if SLINK_NUM_TX > 0) -- |
slink_tx_dat_o => slink_tx_dat_o, |
slink_tx_val_o => slink_tx_val_o, |
/neorv32_SystemTop_axi4lite.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
110,7 → 110,8
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits |
IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two |
IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)? |
IO_XIP_EN : boolean := false -- implement execute in place module (XIP)? |
); |
port ( |
-- ------------------------------------------------------------ |
154,6 → 155,11
-- ------------------------------------------------------------ |
-- Processor IO -- |
-- ------------------------------------------------------------ |
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- |
xip_csn_o : out std_logic; -- chip-select, low-active |
xip_clk_o : out std_logic; -- serial clock |
xip_sdi_i : in std_logic := 'L'; -- device data input |
xip_sdo_o : out std_logic; -- controller data output |
-- GPIO (available if IO_GPIO_EN = true) -- |
gpio_o : out std_logic_vector(63 downto 0); -- parallel output |
gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel input |
176,7 → 182,7
twi_sda_io : inout std_logic; -- twi serial data line |
twi_scl_io : inout std_logic; -- twi serial clock line |
-- PWM (available if IO_PWM_NUM_CH > 0) -- |
pwm_o : out std_logic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels |
pwm_o : out std_logic_vector(59 downto 0); -- pwm channels |
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs |
cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs |
183,7 → 189,7
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- |
neoled_o : out std_logic; -- async serial data line |
-- External platform interrupts (available if XIRQ_NUM_CH > 0) -- |
xirq_i : in std_logic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels |
xirq_i : in std_logic_vector(31 downto 0) := (others => '0'); -- IRQ channels |
-- CPU Interrupts -- |
msw_irq_i : in std_logic := '0'; -- machine software interrupt |
mext_irq_i : in std_logic := '0' -- machine external interrupt |
206,6 → 212,11
signal jtag_tdo_o_int :std_ulogic; |
signal jtag_tms_i_int :std_ulogic; |
-- |
signal xip_csn_o_int : std_ulogic; |
signal xip_clk_o_int : std_ulogic; |
signal xip_sdi_i_int : std_ulogic; |
signal xip_sdo_o_int : std_ulogic; |
-- |
signal gpio_o_int : std_ulogic_vector(63 downto 0); |
signal gpio_i_int : std_ulogic_vector(63 downto 0); |
-- |
224,7 → 235,7
signal spi_sdi_i_int : std_ulogic; |
signal spi_csn_o_int : std_ulogic_vector(07 downto 0); |
-- |
signal pwm_o_int : std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); |
signal pwm_o_int : std_ulogic_vector(59 downto 0); |
-- |
signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); |
signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); |
231,7 → 242,7
-- |
signal neoled_o_int : std_ulogic; |
-- |
signal xirq_i_int : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); |
signal xirq_i_int : std_ulogic_vector(31 downto 0); |
-- |
signal msw_irq_i_int : std_ulogic; |
signal mext_irq_i_int : std_ulogic; |
343,7 → 354,8
IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits |
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? |
IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two |
IO_GPTMR_EN => IO_GPTMR_EN -- implement general purpose timer (GPTMR)? |
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)? |
IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)? |
) |
port map ( |
-- Global control -- |
370,6 → 382,11
-- Advanced memory control signals (available if MEM_EXT_EN = true) -- |
fence_o => open, -- indicates an executed FENCE operation |
fencei_o => open, -- indicates an executed FENCEI operation |
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- |
xip_csn_o => xip_csn_o_int, -- chip-select, low-active |
xip_clk_o => xip_clk_o_int, -- serial clock |
xip_sdi_i => xip_sdi_i_int, -- device data input |
xip_sdo_o => xip_sdo_o_int, -- controller data output |
-- GPIO (available if IO_GPIO_EN = true) -- |
gpio_o => gpio_o_int, -- parallel output |
gpio_i => gpio_i_int, -- parallel input |
410,6 → 427,11
); |
|
-- type conversion -- |
xip_csn_o <= std_logic(xip_csn_o_int); |
xip_clk_o <= std_logic(xip_clk_o_int); |
xip_sdi_i_int <= std_ulogic(xip_sdi_i); |
xip_sdo_o <= std_logic(xip_sdo_o_int); |
|
gpio_o <= std_logic_vector(gpio_o_int); |
gpio_i_int <= std_ulogic_vector(gpio_i); |
|