OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/core/neorv32_application_image.vhd
40,8 → 40,8
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00000930 => x"00000020",
00000931 => x"70696b73",
00000932 => x"20646570",
00000933 => x"746f6e28",
00000934 => x"736f7020",
00000935 => x"6c626973",
00000936 => x"68772065",
00000937 => x"43206e65",
00000938 => x"5458452d",
00000939 => x"616e6520",
00000940 => x"64656c62",
00000941 => x"00000a29",
00000942 => x"20435845",
00000943 => x"43415f49",
00000944 => x"20203a43",
00000945 => x"00000020",
00000946 => x"20435845",
00000947 => x"4c495f49",
00000948 => x"3a47454c",
00000949 => x"00000020",
00000950 => x"20435845",
00000951 => x"41455242",
00000952 => x"20203a4b",
00000953 => x"00000020",
00000954 => x"20435845",
00000955 => x"4c415f4c",
00000956 => x"3a4e4749",
00000957 => x"00000020",
00000958 => x"20435845",
00000959 => x"43415f4c",
00000960 => x"20203a43",
00000961 => x"00000020",
00000962 => x"20435845",
00000963 => x"4c415f53",
00000964 => x"3a4e4749",
00000965 => x"00000020",
00000966 => x"20435845",
00000967 => x"43415f53",
00000968 => x"20203a43",
00000969 => x"00000020",
00000970 => x"20435845",
00000971 => x"43564e45",
00000972 => x"3a4c4c41",
00000973 => x"00000020",
00000974 => x"20515249",
00000975 => x"3a49544d",
00000976 => x"20202020",
00000977 => x"00000020",
00000978 => x"20515249",
00000979 => x"3a49454d",
00000980 => x"20202020",
00000981 => x"00000020",
00000982 => x"3a494657",
00000983 => x"20202020",
00000984 => x"20202020",
00000985 => x"00000020",
00000986 => x"65540a0a",
00000987 => x"3a737473",
00000988 => x"0a692520",
00000989 => x"203a4b4f",
00000990 => x"25202020",
00000991 => x"41460a69",
00000992 => x"203a4c49",
00000993 => x"0a692520",
00000994 => x"0000000a",
00000995 => x"54534554",
00000996 => x"214b4f20",
00000997 => x"0000000a",
00000998 => x"54534554",
00000999 => x"49414620",
00001000 => x"2144454c",
00001001 => x"0000000a",
00001002 => x"65757254",
00001003 => x"0000000a",
00001004 => x"736c6146",
00001005 => x"00000a65",
00001006 => x"3c3c0a0a",
00001007 => x"4f454e20",
00001008 => x"32335652",
00001009 => x"72614820",
00001010 => x"72617764",
00001011 => x"6f432065",
00001012 => x"6769666e",
00001013 => x"74617275",
00001014 => x"206e6f69",
00001015 => x"7265764f",
00001016 => x"77656976",
00001017 => x"0a3e3e20",
00001018 => x"00000000",
00001019 => x"202d2d0a",
00001020 => x"746e6543",
00001021 => x"206c6172",
00001022 => x"636f7250",
00001023 => x"69737365",
00001024 => x"5520676e",
00001025 => x"2074696e",
00001026 => x"000a2d2d",
00001027 => x"74726148",
00001028 => x"3a444920",
00001029 => x"20202020",
00001030 => x"20202020",
00001031 => x"78302020",
00001032 => x"000a7825",
00001033 => x"72657355",
00001034 => x"646f6320",
00001035 => x"20203a65",
00001036 => x"20202020",
00001037 => x"78302020",
00001038 => x"000a7825",
00001039 => x"64726148",
00001040 => x"65726177",
00001041 => x"72657620",
00001042 => x"6e6f6973",
00001043 => x"0000203a",
00001044 => x"78302820",
00001045 => x"0a297825",
00001046 => x"00000000",
00001047 => x"68637241",
00001048 => x"63657469",
00001049 => x"65727574",
00001050 => x"2020203a",
00001051 => x"00002020",
00001052 => x"6e6b6e75",
00001053 => x"006e776f",
00001054 => x"32335652",
00001055 => x"00000000",
00001056 => x"32315652",
00001057 => x"00000038",
00001058 => x"34365652",
00001059 => x"00000000",
00001060 => x"5550430a",
00001061 => x"74786520",
00001062 => x"69736e65",
00001063 => x"3a736e6f",
00001064 => x"00202020",
00001065 => x"25783028",
00001066 => x"000a2978",
00001067 => x"636f6c43",
00001068 => x"7073206b",
00001069 => x"3a646565",
00001070 => x"20202020",
00001071 => x"75252020",
00001072 => x"0a7a4820",
00001073 => x"00000000",
00001074 => x"202d2d0a",
00001075 => x"6f6d654d",
00001076 => x"43207972",
00001077 => x"69666e6f",
00001078 => x"61727567",
00001079 => x"6e6f6974",
00001080 => x"0a2d2d20",
00001081 => x"00000000",
00001082 => x"74736e49",
00001083 => x"74637572",
00001084 => x"206e6f69",
00001085 => x"6f6d656d",
00001086 => x"203a7972",
00001087 => x"75252020",
00001088 => x"74796220",
00001089 => x"40207365",
00001090 => x"25783020",
00001091 => x"00000a78",
00001092 => x"65746e49",
00001093 => x"6c616e72",
00001094 => x"454d4920",
00001095 => x"20203a4d",
00001096 => x"20202020",
00001097 => x"00002020",
00001098 => x"65746e49",
00001099 => x"6c616e72",
00001100 => x"454d4920",
00001101 => x"7361204d",
00001102 => x"4d4f5220",
00001103 => x"0000203a",
00001104 => x"61746144",
00001105 => x"6d656d20",
00001106 => x"3a79726f",
00001107 => x"20202020",
00001108 => x"20202020",
00001109 => x"75252020",
00001110 => x"74796220",
00001111 => x"40207365",
00001112 => x"25783020",
00001113 => x"00000a78",
00001114 => x"65746e49",
00001115 => x"6c616e72",
00001116 => x"454d4420",
00001117 => x"20203a4d",
00001118 => x"20202020",
00001119 => x"00002020",
00001120 => x"746f6f42",
00001121 => x"64616f6c",
00001122 => x"203a7265",
00001123 => x"20202020",
00001124 => x"20202020",
00001125 => x"00002020",
00001126 => x"65747845",
00001127 => x"6c616e72",
00001128 => x"746e6920",
00001129 => x"61667265",
00001130 => x"203a6563",
00001131 => x"00002020",
00001132 => x"202d2d0a",
00001133 => x"69726550",
00001134 => x"72656870",
00001135 => x"20736c61",
00001136 => x"000a2d2d",
00001137 => x"4f495047",
00001138 => x"2020203a",
00001139 => x"00000020",
00001140 => x"4d49544d",
00001141 => x"20203a45",
00001142 => x"00000020",
00001143 => x"54524155",
00001144 => x"2020203a",
00001145 => x"00000020",
00001146 => x"3a495053",
00001147 => x"20202020",
00001148 => x"00000020",
00001149 => x"3a495754",
00001150 => x"20202020",
00001151 => x"00000020",
00001152 => x"3a4d5750",
00001153 => x"20202020",
00001154 => x"00000020",
00001155 => x"3a544457",
00001156 => x"20202020",
00001157 => x"00000020",
00001158 => x"43494c43",
00001159 => x"2020203a",
00001160 => x"00000020",
00001161 => x"474e5254",
00001162 => x"2020203a",
00001163 => x"00000020",
00001164 => x"4e564544",
00001165 => x"3a4c4c55",
00001166 => x"00000020",
00001167 => x"68540a0a",
00001168 => x"454e2065",
00001169 => x"3356524f",
00001170 => x"72502032",
00001171 => x"7365636f",
00001172 => x"20726f73",
00001173 => x"6a6f7250",
00001174 => x"0a746365",
00001175 => x"53207962",
00001176 => x"68706574",
00001177 => x"4e206e61",
00001178 => x"69746c6f",
00001179 => x"680a676e",
00001180 => x"73707474",
00001181 => x"672f2f3a",
00001182 => x"75687469",
00001183 => x"6f632e62",
00001184 => x"74732f6d",
00001185 => x"746c6f6e",
00001186 => x"2f676e69",
00001187 => x"726f656e",
00001188 => x"0a323376",
00001189 => x"6564616d",
00001190 => x"206e6920",
00001191 => x"6e6e6148",
00001192 => x"7265766f",
00001193 => x"6547202c",
00001194 => x"6e616d72",
00001195 => x"000a0a79",
00001196 => x"33323130",
00001197 => x"37363534",
00001198 => x"00003938",
00001199 => x"33323130",
00001200 => x"37363534",
00001201 => x"62613938",
00001202 => x"66656463",
00001203 => x"dead007f",
00001204 => x"00008067",
others => x"00000000"
);
 
/core/neorv32_bootloader_image.vhd
8,13 → 8,13
 
type bootloader_init_image_t is array (0 to 65535) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"fc5015f3",
00000001 => x"fc701673",
00000000 => x"ff402583",
00000001 => x"ffc02603",
00000002 => x"00c58133",
00000003 => x"ffc10113",
00000004 => x"00000597",
00000005 => x"05058593",
00000006 => x"30559073",
00000004 => x"00000697",
00000005 => x"04468693",
00000006 => x"30569073",
00000007 => x"00000013",
00000008 => x"00000093",
00000009 => x"00000193",
25,1004 → 25,1002
00000014 => x"00000413",
00000015 => x"00000493",
00000016 => x"00000513",
00000017 => x"00000593",
00000018 => x"00000613",
00000019 => x"00000693",
00000020 => x"00000713",
00000021 => x"00000793",
00000022 => x"028000ef",
00000023 => x"fa5ff06f",
00000024 => x"ffc10113",
00000025 => x"00112023",
00000026 => x"341010f3",
00000027 => x"00408093",
00000028 => x"34109073",
00000029 => x"00012083",
00000030 => x"00410113",
00000031 => x"30200073",
00000032 => x"fd010113",
00000033 => x"00000513",
00000034 => x"00000593",
00000035 => x"02112623",
00000036 => x"02812423",
00000037 => x"02912223",
00000038 => x"03212023",
00000039 => x"01312e23",
00000040 => x"01412c23",
00000041 => x"01512a23",
00000042 => x"01612823",
00000043 => x"01712623",
00000044 => x"01812423",
00000045 => x"2c1000ef",
00000046 => x"4f9000ef",
00000047 => x"4cd000ef",
00000048 => x"435000ef",
00000049 => x"299000ef",
00000050 => x"4d5000ef",
00000051 => x"281000ef",
00000052 => x"fc102473",
00000053 => x"026267b7",
00000054 => x"9ff78793",
00000055 => x"00000713",
00000056 => x"00000693",
00000057 => x"00000613",
00000058 => x"00000593",
00000059 => x"00200513",
00000060 => x"0087f463",
00000061 => x"00400513",
00000062 => x"3b1000ef",
00000063 => x"00005537",
00000064 => x"00000613",
00000065 => x"00000593",
00000066 => x"b0050513",
00000067 => x"299000ef",
00000068 => x"271000ef",
00000069 => x"00245793",
00000070 => x"00a78533",
00000071 => x"00f537b3",
00000072 => x"00b785b3",
00000073 => x"269000ef",
00000074 => x"ffff07b7",
00000075 => x"43478793",
00000076 => x"30579073",
00000077 => x"08000793",
00000078 => x"30479073",
00000079 => x"30046073",
00000080 => x"00100513",
00000081 => x"43d000ef",
00000082 => x"00000793",
00000083 => x"34079073",
00000084 => x"ffff1537",
00000085 => x"ef450513",
00000086 => x"2f9000ef",
00000087 => x"3d0000ef",
00000088 => x"ffff1537",
00000089 => x"f2c50513",
00000090 => x"2e9000ef",
00000091 => x"fc102573",
00000092 => x"254000ef",
00000093 => x"ffff1537",
00000094 => x"f3450513",
00000095 => x"2d5000ef",
00000096 => x"f1402573",
00000097 => x"240000ef",
00000098 => x"ffff1537",
00000099 => x"f4050513",
00000100 => x"2c1000ef",
00000101 => x"30102573",
00000102 => x"22c000ef",
00000103 => x"ffff1537",
00000104 => x"f4850513",
00000105 => x"2ad000ef",
00000106 => x"fc002573",
00000107 => x"218000ef",
00000017 => x"00000713",
00000018 => x"00000793",
00000019 => x"030000ef",
00000020 => x"0000006f",
00000021 => x"ffc10113",
00000022 => x"00812023",
00000023 => x"34202473",
00000024 => x"00044863",
00000025 => x"34102473",
00000026 => x"00440413",
00000027 => x"34141073",
00000028 => x"00012403",
00000029 => x"00410113",
00000030 => x"30200073",
00000031 => x"fd010113",
00000032 => x"02112623",
00000033 => x"02812423",
00000034 => x"02912223",
00000035 => x"03212023",
00000036 => x"01312e23",
00000037 => x"01412c23",
00000038 => x"01512a23",
00000039 => x"01612823",
00000040 => x"01712623",
00000041 => x"01812423",
00000042 => x"f8002823",
00000043 => x"f8002a23",
00000044 => x"1c9000ef",
00000045 => x"4f5000ef",
00000046 => x"4c9000ef",
00000047 => x"431000ef",
00000048 => x"281000ef",
00000049 => x"4d1000ef",
00000050 => x"fe002403",
00000051 => x"026267b7",
00000052 => x"9ff78793",
00000053 => x"00000713",
00000054 => x"00000693",
00000055 => x"00000613",
00000056 => x"00000593",
00000057 => x"00200513",
00000058 => x"0087f463",
00000059 => x"00400513",
00000060 => x"3b1000ef",
00000061 => x"00005537",
00000062 => x"00000613",
00000063 => x"00000593",
00000064 => x"b0050513",
00000065 => x"299000ef",
00000066 => x"251000ef",
00000067 => x"00245793",
00000068 => x"00a78533",
00000069 => x"00f537b3",
00000070 => x"00b785b3",
00000071 => x"269000ef",
00000072 => x"ffff07b7",
00000073 => x"41878793",
00000074 => x"30579073",
00000075 => x"08000793",
00000076 => x"30479073",
00000077 => x"30046073",
00000078 => x"00100513",
00000079 => x"43d000ef",
00000080 => x"00000793",
00000081 => x"34079073",
00000082 => x"ffff1537",
00000083 => x"eec50513",
00000084 => x"2f9000ef",
00000085 => x"135000ef",
00000086 => x"ffff1537",
00000087 => x"f2450513",
00000088 => x"2e9000ef",
00000089 => x"fe002503",
00000090 => x"240000ef",
00000091 => x"ffff1537",
00000092 => x"f2c50513",
00000093 => x"2d5000ef",
00000094 => x"fe402503",
00000095 => x"22c000ef",
00000096 => x"ffff1537",
00000097 => x"f3850513",
00000098 => x"2c1000ef",
00000099 => x"30102573",
00000100 => x"218000ef",
00000101 => x"ffff1537",
00000102 => x"f4050513",
00000103 => x"2ad000ef",
00000104 => x"fe802503",
00000105 => x"ffff14b7",
00000106 => x"00341413",
00000107 => x"1fc000ef",
00000108 => x"ffff1537",
00000109 => x"f5050513",
00000110 => x"299000ef",
00000111 => x"fc602573",
00000112 => x"ffff14b7",
00000113 => x"200000ef",
00000114 => x"f5848513",
00000115 => x"285000ef",
00000116 => x"fc402573",
00000117 => x"1f0000ef",
00000109 => x"f4850513",
00000110 => x"291000ef",
00000111 => x"ff802503",
00000112 => x"ffff1937",
00000113 => x"1e4000ef",
00000114 => x"f5048513",
00000115 => x"27d000ef",
00000116 => x"ff002503",
00000117 => x"1d4000ef",
00000118 => x"ffff1537",
00000119 => x"f6450513",
00000120 => x"271000ef",
00000121 => x"fc702573",
00000122 => x"1dc000ef",
00000123 => x"f5848513",
00000124 => x"261000ef",
00000125 => x"fc502573",
00000126 => x"1cc000ef",
00000127 => x"ffff1537",
00000128 => x"f6c50513",
00000129 => x"24d000ef",
00000130 => x"00341413",
00000131 => x"00000493",
00000132 => x"ffff1937",
00000133 => x"fa402783",
00000134 => x"0607d063",
00000135 => x"ffff1537",
00000136 => x"f9850513",
00000137 => x"22d000ef",
00000138 => x"ffff1937",
00000139 => x"0f4000ef",
00000140 => x"ffff19b7",
00000141 => x"07200a13",
00000142 => x"06800a93",
00000143 => x"07500b13",
00000144 => x"07300b93",
00000145 => x"ffff14b7",
00000146 => x"ffff1c37",
00000147 => x"fa490513",
00000148 => x"201000ef",
00000149 => x"1ed000ef",
00000150 => x"00050413",
00000151 => x"1d5000ef",
00000152 => x"f9498513",
00000153 => x"1ed000ef",
00000154 => x"09440263",
00000155 => x"03541863",
00000156 => x"0b0000ef",
00000157 => x"fd9ff06f",
00000158 => x"109000ef",
00000159 => x"00b49463",
00000160 => x"f8856ae3",
00000161 => x"00100513",
00000162 => x"508000ef",
00000163 => x"f9490513",
00000164 => x"1c1000ef",
00000165 => x"098000ef",
00000166 => x"f7dff06f",
00000167 => x"00000513",
00000168 => x"01640e63",
00000169 => x"01741663",
00000170 => x"72c000ef",
00000171 => x"fa1ff06f",
00000172 => x"06c00793",
00000173 => x"00f41863",
00000174 => x"00100513",
00000175 => x"4d4000ef",
00000176 => x"f8dff06f",
00000177 => x"06500793",
00000178 => x"00f41663",
00000179 => x"060000ef",
00000180 => x"f7dff06f",
00000181 => x"03f00793",
00000182 => x"facc0513",
00000183 => x"00f40463",
00000184 => x"fc048513",
00000185 => x"16d000ef",
00000186 => x"f65ff06f",
00000187 => x"02c12083",
00000188 => x"02812403",
00000189 => x"02412483",
00000190 => x"02012903",
00000191 => x"01c12983",
00000192 => x"01812a03",
00000193 => x"01412a83",
00000194 => x"01012b03",
00000195 => x"00c12b83",
00000196 => x"00812c03",
00000197 => x"00000513",
00000198 => x"03010113",
00000199 => x"00008067",
00000200 => x"ffff1537",
00000201 => x"dc450513",
00000202 => x"1290006f",
00000203 => x"340027f3",
00000204 => x"00079863",
00000205 => x"ffff1537",
00000206 => x"e2850513",
00000207 => x"1150006f",
00000208 => x"ff010113",
00000209 => x"00112623",
00000210 => x"30047073",
00000211 => x"00000793",
00000212 => x"30479073",
00000213 => x"ffff1537",
00000214 => x"e4450513",
00000215 => x"0f5000ef",
00000216 => x"fa002783",
00000217 => x"fe07cee3",
00000218 => x"fc4027f3",
00000219 => x"00078067",
00000220 => x"ff9ff06f",
00000221 => x"ff010113",
00000222 => x"00812423",
00000223 => x"00050413",
00000224 => x"ffff1537",
00000225 => x"e5450513",
00000226 => x"00112623",
00000227 => x"0c5000ef",
00000228 => x"00500793",
00000229 => x"0287e063",
00000230 => x"03040513",
00000231 => x"0ff57513",
00000232 => x"091000ef",
00000233 => x"30047073",
00000234 => x"00100513",
00000235 => x"1d5000ef",
00000236 => x"0000006f",
00000119 => x"f5c50513",
00000120 => x"269000ef",
00000121 => x"ffc02503",
00000122 => x"1c0000ef",
00000123 => x"f5048513",
00000124 => x"259000ef",
00000125 => x"ff402503",
00000126 => x"00000493",
00000127 => x"1ac000ef",
00000128 => x"ffff1537",
00000129 => x"f6450513",
00000130 => x"241000ef",
00000131 => x"fa402783",
00000132 => x"0607d263",
00000133 => x"ffff1537",
00000134 => x"f9050513",
00000135 => x"22d000ef",
00000136 => x"ffff1937",
00000137 => x"0d0000ef",
00000138 => x"ffff19b7",
00000139 => x"07200a13",
00000140 => x"06800a93",
00000141 => x"07500b13",
00000142 => x"07300b93",
00000143 => x"ffff14b7",
00000144 => x"ffff1c37",
00000145 => x"f9c90513",
00000146 => x"201000ef",
00000147 => x"1ed000ef",
00000148 => x"00050413",
00000149 => x"1d5000ef",
00000150 => x"f8c98513",
00000151 => x"1ed000ef",
00000152 => x"03441c63",
00000153 => x"30047073",
00000154 => x"ffff02b7",
00000155 => x"00028067",
00000156 => x"0000006f",
00000157 => x"0e5000ef",
00000158 => x"00b49463",
00000159 => x"f88568e3",
00000160 => x"00100513",
00000161 => x"438000ef",
00000162 => x"f8c90513",
00000163 => x"1bd000ef",
00000164 => x"070000ef",
00000165 => x"f79ff06f",
00000166 => x"01541663",
00000167 => x"058000ef",
00000168 => x"fa5ff06f",
00000169 => x"00000513",
00000170 => x"01640e63",
00000171 => x"01741663",
00000172 => x"650000ef",
00000173 => x"f91ff06f",
00000174 => x"06c00793",
00000175 => x"00f41863",
00000176 => x"00100513",
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others => x"00000000"
);
 
/core/neorv32_busswitch.vhd
0,0 → 1,278
-- #################################################################################################
-- # << NEORV32 - Bus Switch >> #
-- # ********************************************************************************************* #
-- # Allows to access a single peripheral bus ("p_bus") by two controller busses. Controller port #
-- # A ("ca_bus") has priority over controller port B ("cb_bus"). #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_busswitch is
generic (
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
PORT_CB_READ_ONLY : boolean := false -- set if controller port B is read-only
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- controller interface a --
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
ca_bus_we_i : in std_ulogic; -- write enable
ca_bus_re_i : in std_ulogic; -- read enable
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
ca_bus_err_o : out std_ulogic; -- bus transfer error
-- controller interface b --
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
cb_bus_we_i : in std_ulogic; -- write enable
cb_bus_re_i : in std_ulogic; -- read enable
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
cb_bus_err_o : out std_ulogic; -- bus transfer error
-- peripheral bus --
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
p_bus_we_o : out std_ulogic; -- write enable
p_bus_re_o : out std_ulogic; -- read enable
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
p_bus_err_i : in std_ulogic -- bus transfer error
);
end neorv32_busswitch;
 
architecture neorv32_busswitch_rtl of neorv32_busswitch is
 
-- access buffer --
signal ca_rd_req_buf : std_ulogic;
signal ca_wr_req_buf : std_ulogic;
signal cb_rd_req_buf : std_ulogic;
signal cb_wr_req_buf : std_ulogic;
 
-- access requests --
signal ca_req_current : std_ulogic;
signal cb_req_current : std_ulogic;
signal ca_req_buffered : std_ulogic;
signal cb_req_buffered : std_ulogic;
 
-- internal bus lines --
signal ca_bus_ack : std_ulogic;
signal cb_bus_ack : std_ulogic;
signal ca_bus_err : std_ulogic;
signal cb_bus_err : std_ulogic;
signal p_bus_we : std_ulogic;
signal p_bus_re : std_ulogic;
 
-- access arbiter --
type arbiter_state_t is (IDLE, BUSY, RETIRE, BUSY_SWITCHED, RETIRE_SWITCHED);
type arbiter_t is record
state : arbiter_state_t;
state_nxt : arbiter_state_t;
bus_sel : std_ulogic;
re_trig : std_ulogic;
we_trig : std_ulogic;
end record;
signal arbiter : arbiter_t;
 
begin
 
-- Access Buffer --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
access_buffer: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ca_rd_req_buf <= '0';
ca_wr_req_buf <= '0';
cb_rd_req_buf <= '0';
cb_wr_req_buf <= '0';
elsif rising_edge(clk_i) then
 
-- controller A requests --
if (ca_rd_req_buf = '0') and (ca_wr_req_buf = '0') then -- idle
ca_rd_req_buf <= ca_bus_re_i;
ca_wr_req_buf <= ca_bus_we_i;
elsif (ca_bus_cancel_i = '1') or -- controller cancels access
(ca_bus_err = '1') or -- peripheral cancels access
(ca_bus_ack = '1') then -- normal termination
ca_rd_req_buf <= '0';
ca_wr_req_buf <= '0';
end if;
 
-- controller B requests --
if (cb_rd_req_buf = '0') and (cb_wr_req_buf = '0') then
cb_rd_req_buf <= cb_bus_re_i;
cb_wr_req_buf <= cb_bus_we_i;
elsif (cb_bus_cancel_i = '1') or -- controller cancels access
(cb_bus_err = '1') or -- peripheral cancels access
(cb_bus_ack = '1') then -- normal termination
cb_rd_req_buf <= '0';
cb_wr_req_buf <= '0';
end if;
 
end if;
end process access_buffer;
 
-- any current requests? --
ca_req_current <= (ca_bus_re_i or ca_bus_we_i) when (PORT_CA_READ_ONLY = false) else ca_bus_re_i;
cb_req_current <= (cb_bus_re_i or cb_bus_we_i) when (PORT_CB_READ_ONLY = false) else cb_bus_re_i;
 
-- any buffered requests? --
ca_req_buffered <= (ca_rd_req_buf or ca_wr_req_buf) when (PORT_CA_READ_ONLY = false) else ca_rd_req_buf;
cb_req_buffered <= (cb_rd_req_buf or cb_wr_req_buf) when (PORT_CB_READ_ONLY = false) else cb_rd_req_buf;
 
 
-- Access Arbiter Sync --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- for registers that require a specific reset state --
arbiter_sync: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
arbiter.state <= IDLE;
elsif rising_edge(clk_i) then
arbiter.state <= arbiter.state_nxt;
end if;
end process arbiter_sync;
 
 
-- Peripheral Bus Arbiter -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered,
ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf,
ca_bus_cancel_i, cb_bus_cancel_i, p_bus_ack_i, p_bus_err_i)
begin
-- arbiter defaults --
arbiter.state_nxt <= arbiter.state;
arbiter.bus_sel <= '0';
arbiter.we_trig <= '0';
arbiter.re_trig <= '0';
 
-- state machine --
case arbiter.state is
 
when IDLE => -- Controller a has full bus access
-- ------------------------------------------------------------
if (ca_req_current = '1') then -- current request?
arbiter.bus_sel <= '0';
arbiter.state_nxt <= BUSY;
elsif (ca_req_buffered = '1') then -- buffered request?
arbiter.bus_sel <= '0';
arbiter.state_nxt <= RETIRE;
elsif (cb_req_current = '1') then -- current request from controller b?
arbiter.bus_sel <= '1';
arbiter.state_nxt <= BUSY_SWITCHED;
elsif (cb_req_buffered = '1') then -- buffered request from controller b?
arbiter.bus_sel <= '1';
arbiter.state_nxt <= RETIRE_SWITCHED;
end if;
 
when BUSY => -- transaction in progress
-- ------------------------------------------------------------
arbiter.bus_sel <= '0';
if (ca_bus_cancel_i = '1') or -- controller cancels access
(p_bus_err_i = '1') or -- peripheral cancels access
(p_bus_ack_i = '1') then -- normal termination
arbiter.state_nxt <= IDLE;
end if;
 
when RETIRE => -- retire pending access
-- ------------------------------------------------------------
arbiter.bus_sel <= '0';
if (PORT_CA_READ_ONLY = false) then
arbiter.we_trig <= ca_wr_req_buf;
end if;
arbiter.re_trig <= ca_rd_req_buf;
arbiter.state_nxt <= BUSY;
 
when BUSY_SWITCHED => -- switched transaction in progress
-- ------------------------------------------------------------
arbiter.bus_sel <= '1';
if (cb_bus_cancel_i = '1') or -- controller cancels access
(p_bus_err_i = '1') or -- peripheral cancels access
(p_bus_ack_i = '1') then -- normal termination
arbiter.state_nxt <= IDLE;
end if;
 
when RETIRE_SWITCHED => -- retire pending switched access
-- ------------------------------------------------------------
arbiter.bus_sel <= '1';
if (PORT_CB_READ_ONLY = false) then
arbiter.we_trig <= cb_wr_req_buf;
end if;
arbiter.re_trig <= cb_rd_req_buf;
arbiter.state_nxt <= BUSY_SWITCHED;
 
end case;
end process arbiter_comb;
 
 
-- Peripheral Bus Switch ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
p_bus_addr_o <= ca_bus_addr_i when (arbiter.bus_sel = '0') else cb_bus_addr_i;
p_bus_wdata_o <= cb_bus_wdata_i when (PORT_CA_READ_ONLY = true) else ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else
ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i;
p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else
ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i;
p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
p_bus_cancel_o <= ca_bus_cancel_i when (arbiter.bus_sel = '0') else cb_bus_cancel_i;
p_bus_we_o <= (p_bus_we or arbiter.we_trig);
p_bus_re_o <= (p_bus_re or arbiter.re_trig);
 
ca_bus_rdata_o <= p_bus_rdata_i;
cb_bus_rdata_o <= p_bus_rdata_i;
 
ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel);
cb_bus_ack <= p_bus_ack_i and ( arbiter.bus_sel);
ca_bus_ack_o <= ca_bus_ack;
cb_bus_ack_o <= cb_bus_ack;
 
ca_bus_err <= p_bus_err_i and (not arbiter.bus_sel);
cb_bus_err <= p_bus_err_i and ( arbiter.bus_sel);
ca_bus_err_o <= ca_bus_err;
cb_bus_err_o <= cb_bus_err;
 
 
end neorv32_busswitch_rtl;
/core/neorv32_cpu.vhd
2,10 → 2,10
-- # << NEORV32 - CPU Top Entity >> #
-- # ********************************************************************************************* #
-- # Top NEORV32 CPU: #
-- # * neorv32_cpu_alu: Arithemtical/logical unit #
-- # * neorv32_cpu_alu: Arithemtic/logic unit #
-- # * neorv32_cpu_ctrl: CPU control and CSR system #
-- # * neorv32_cpu_decompressor: Compressed instructions decoder #
-- # * neorv32_cpu_bus: Memory/IO bus interface unit #
-- # * neorv32_cpu_bus: Instruction and data bus interface unit #
-- # * neorv32_cpu_cp_muldiv: MULDIV co-processor #
-- # * neorv32_cpu_regfile: Data register file #
-- # ********************************************************************************************* #
50,61 → 50,50
entity neorv32_cpu is
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- bus interface --
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic; -- bus transfer error
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
-- data bus interface --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- external interrupts --
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
msw_irq_i : in std_ulogic; -- software interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
);
end neorv32_cpu;
 
111,28 → 100,28
architecture neorv32_cpu_rtl of neorv32_cpu is
 
-- local signals --
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
signal bus_wait : std_ulogic; -- wait for bus to finish operation
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
signal ma_instr : std_ulogic; -- misaligned instruction address
signal ma_load : std_ulogic; -- misaligned load data address
signal ma_store : std_ulogic; -- misaligned store data address
signal be_instr : std_ulogic; -- bus error on instruction access
signal be_load : std_ulogic; -- bus error on load data access
signal be_store : std_ulogic; -- bus error on store data access
signal bus_busy : std_ulogic; -- bus unit is busy
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
signal bus_d_wait : std_ulogic; -- wait for current bus data access
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
signal ma_instr : std_ulogic; -- misaligned instruction address
signal ma_load : std_ulogic; -- misaligned load data address
signal ma_store : std_ulogic; -- misaligned store data address
signal be_instr : std_ulogic; -- bus error on instruction access
signal be_load : std_ulogic; -- bus error on load data access
signal be_store : std_ulogic; -- bus error on store data access
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
 
-- co-processor interface --
signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
145,40 → 134,15
neorv32_cpu_control_inst: neorv32_cpu_control
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
HART_ID => HART_ID, -- custom hardware thread ID
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Memory configuration: External memory interface --
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)?
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei -- implement instruction stream sync.?
)
port map (
-- global control --
187,7 → 151,8
ctrl_o => ctrl, -- main control bus
-- status input --
alu_wait_i => alu_wait, -- wait for ALU
bus_wait_i => bus_wait, -- wait for bus
bus_i_wait_i => bus_i_wait, -- wait for bus
bus_d_wait_i => bus_d_wait, -- wait for bus
-- data input --
instr_i => instr, -- instruction
cmp_i => alu_cmp, -- comparator status
201,6 → 166,7
csr_wdata_i => alu_res, -- CSR write data
csr_rdata_o => csr_rdata, -- CSR read data
-- external interrupt --
msw_irq_i => msw_irq_i, -- software interrupt
clic_irq_i => clic_irq_i, -- CLIC interrupt request
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
-- system time input from MTIME --
212,8 → 178,7
ma_store_i => ma_store, -- misaligned store data address
be_instr_i => be_instr, -- bus error on instruction access
be_load_i => be_load, -- bus error on load data access
be_store_i => be_store, -- bus error on store data access
bus_busy_i => bus_busy -- bus unit is busy
be_store_i => be_store -- bus error on store data access
);
 
 
301,7 → 266,7
cp1_valid <= '0';
 
 
-- Bus Unit -------------------------------------------------------------------------------
-- Bus Interface Unit ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_bus_inst: neorv32_cpu_bus
generic map (
310,36 → 275,49
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl, -- main control bus
-- data input --
wdata_i => rs2, -- write data
pc_i => fetch_pc, -- current PC for instruction fetch
alu_i => alu_res, -- ALU result
-- data output --
instr_o => instr, -- instruction
rdata_o => rdata, -- read data
-- status --
mar_o => mar, -- current memory address register
ma_instr_o => ma_instr, -- misaligned instruction address
ma_load_o => ma_load, -- misaligned load data address
ma_store_o => ma_store, -- misaligned store data address
be_instr_o => be_instr, -- bus error on instruction access
be_load_o => be_load, -- bus error on load data access
be_store_o => be_store, -- bus error on store data access
bus_wait_o => bus_wait, -- wait for bus operation to finish
bus_busy_o => bus_busy, -- bus unit is busy
-- bus system --
bus_addr_o => bus_addr_o, -- bus access address
bus_rdata_i => bus_rdata_i, -- bus read data
bus_wdata_o => bus_wdata_o, -- bus write data
bus_ben_o => bus_ben_o, -- byte enable
bus_we_o => bus_we_o, -- write enable
bus_re_o => bus_re_o, -- read enable
bus_cancel_o => bus_cancel_o, -- cancel current bus transaction
bus_ack_i => bus_ack_i, -- bus transfer acknowledge
bus_err_i => bus_err_i -- bus transfer error
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl, -- main control bus
-- cpu instruction fetch interface --
fetch_pc_i => fetch_pc, -- PC for instruction fetch
instr_o => instr, -- instruction
i_wait_o => bus_i_wait, -- wait for fetch to complete
--
ma_instr_o => ma_instr, -- misaligned instruction address
be_instr_o => be_instr, -- bus error on instruction access
-- cpu data access interface --
addr_i => alu_add, -- ALU.add result -> access address
wdata_i => rs2, -- write data
rdata_o => rdata, -- read data
mar_o => mar, -- current memory address register
d_wait_o => bus_d_wait, -- wait for access to complete
--
ma_load_o => ma_load, -- misaligned load data address
ma_store_o => ma_store, -- misaligned store data address
be_load_o => be_load, -- bus error on load data access
be_store_o => be_store, -- bus error on store data access
-- instruction bus --
i_bus_addr_o => i_bus_addr_o, -- bus access address
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
i_bus_ben_o => i_bus_ben_o, -- byte enable
i_bus_we_o => i_bus_we_o, -- write enable
i_bus_re_o => i_bus_re_o, -- read enable
i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
i_bus_err_i => i_bus_err_i, -- bus transfer error
i_bus_fence_o => i_bus_fence_o, -- fence operation
-- data bus --
d_bus_addr_o => d_bus_addr_o, -- bus access address
d_bus_rdata_i => d_bus_rdata_i, -- bus read data
d_bus_wdata_o => d_bus_wdata_o, -- bus write data
d_bus_ben_o => d_bus_ben_o, -- byte enable
d_bus_we_o => d_bus_we_o, -- write enable
d_bus_re_o => d_bus_re_o, -- read enable
d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
d_bus_err_i => d_bus_err_i, -- bus transfer error
d_bus_fence_o => d_bus_fence_o -- fence operation
);
 
 
/core/neorv32_cpu_alu.vhd
88,12 → 88,15
signal cmp_less : std_ulogic;
 
-- shifter --
signal shift_cmd : std_ulogic;
signal shift_cmd_ff : std_ulogic;
signal shift_start : std_ulogic;
signal shift_run : std_ulogic;
signal shift_cnt : std_ulogic_vector(4 downto 0);
signal shift_sreg : std_ulogic_vector(data_width_c-1 downto 0);
type shifter_t is record
cmd : std_ulogic;
cmd_ff : std_ulogic;
start : std_ulogic;
run : std_ulogic;
cnt : std_ulogic_vector(4 downto 0);
sreg : std_ulogic_vector(data_width_c-1 downto 0);
end record;
signal shifter : shifter_t;
 
-- co-processor interface --
signal cp_cmd_ff : std_ulogic;
110,25 → 113,17
input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
begin
-- opa (first ALU input operand) --
if (ctrl_i(ctrl_alu_opa_mux_msb_c) = '0') then
if (ctrl_i(ctrl_alu_opa_mux_lsb_c) = '0') then
opa <= rs1_i;
else
opa <= pc2_i;
end if;
else
opa <= csr_i;
end if;
case ctrl_i(ctrl_alu_opa_mux_msb_c downto ctrl_alu_opa_mux_lsb_c) is
when "00" => opa <= rs1_i;
when "01" => opa <= pc2_i;
when others => opa <= csr_i;
end case;
-- opb (second ALU input operand) --
if (ctrl_i(ctrl_alu_opb_mux_msb_c) = '0') then
if (ctrl_i(ctrl_alu_opb_mux_lsb_c) = '0') then
opb <= rs2_i;
else
opb <= imm_i;
end if;
else
opb <= rs1_i;
end if;
case ctrl_i(ctrl_alu_opb_mux_msb_c downto ctrl_alu_opb_mux_lsb_c) is
when "00" => opb <= rs2_i;
when "01" => opb <= imm_i;
when others => opb <= rs1_i;
end case;
-- opc (second operand for comparison (and SUB)) --
if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
opc <= imm_i;
166,20 → 161,34
shifter_unit: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
shift_sreg <= (others => '0');
shift_cnt <= (others => '0');
shift_cmd_ff <= '0';
shifter.sreg <= (others => '0');
shifter.cnt <= (others => '0');
shifter.cmd_ff <= '0';
elsif rising_edge(clk_i) then
shift_cmd_ff <= shift_cmd;
if (shift_start = '1') then -- trigger new shift
shift_sreg <= opa; -- shift operand
shift_cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
elsif (shift_run = '1') then -- running shift
shift_cnt <= std_ulogic_vector(unsigned(shift_cnt) - 1);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shift_sreg <= shift_sreg(shift_sreg'left-1 downto 0) & '0';
else -- SRL: shift right logical / SRA: shift right arithmetical
shift_sreg <= (shift_sreg(shift_sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shift_sreg(shift_sreg'left downto 1);
shifter.cmd_ff <= shifter.cmd;
if (shifter.start = '1') then -- trigger new shift
shifter.sreg <= opa; -- shift operand
shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
elsif (shifter.run = '1') then -- running shift
-- coarse shift -> multiples of 4 --
if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
else -- SRL: shift right logical / SRA: shift right arithmetical
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
end if;
-- fine shift -> 0..3 --
else
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
else -- SRL: shift right logical / SRA: shift right arithmetical
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
end if;
end if;
end if;
end if;
186,11 → 195,11
end process shifter_unit;
 
-- is shift operation? --
shift_cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0';
shift_start <= '1' when (shift_cmd = '1') and (shift_cmd_ff = '0') else '0';
shifter.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0';
shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
 
-- shift operation running? --
shift_run <= '1' when (or_all_f(shift_cnt) = '1') or (shift_start = '1') else '0';
shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
 
 
-- Coprocessor Interface ------------------------------------------------------------------
231,7 → 240,7
 
-- ALU Function Select --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shift_sreg)
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter)
begin
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modifications only)
240,7 → 249,7
when alu_cmd_and_c => alu_res <= opa and opb;
when alu_cmd_sub_c => alu_res <= sub_res;
when alu_cmd_add_c => alu_res <= add_res;
when alu_cmd_shift_c => alu_res <= shift_sreg;
when alu_cmd_shift_c => alu_res <= shifter.sreg;
when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less;
when others => alu_res <= (others => '0'); -- undefined
end case;
249,7 → 258,7
 
-- ALU Result -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
wait_o <= shift_run or cp_run; -- wait until iterative units have completed
wait_o <= shifter.run or cp_run; -- wait until iterative units have completed
res_o <= (cp0_data_i or cp1_data_i) when (cp_rb_ff1 = '1') else alu_res; -- FIXME
 
 
/core/neorv32_cpu_bus.vhd
1,7 → 1,7
-- #################################################################################################
-- # << NEORV32 - Bus Interface Unit >> #
-- # ********************************************************************************************* #
-- # This unit connects the CPU to the memory/IO system. #
-- # Instruction and data bus interfaces. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
48,81 → 48,112
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-- data input --
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
-- data output --
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
-- status --
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
ma_instr_o : out std_ulogic; -- misaligned instruction address
ma_load_o : out std_ulogic; -- misaligned load data address
ma_store_o : out std_ulogic; -- misaligned store data address
be_instr_o : out std_ulogic; -- bus error on instruction access
be_load_o : out std_ulogic; -- bus error on load data access
be_store_o : out std_ulogic; -- bus error on store data access
bus_wait_o : out std_ulogic; -- wait for bus operation to finish
bus_busy_o : out std_ulogic; -- bus unit is busy
-- bus system --
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic -- bus transfer error
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-- cpu instruction fetch interface --
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
i_wait_o : out std_ulogic; -- wait for fetch to complete
--
ma_instr_o : out std_ulogic; -- misaligned instruction address
be_instr_o : out std_ulogic; -- bus error on instruction access
-- cpu data access interface --
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
d_wait_o : out std_ulogic; -- wait for access to complete
--
ma_load_o : out std_ulogic; -- misaligned load data address
ma_store_o : out std_ulogic; -- misaligned store data address
be_load_o : out std_ulogic; -- bus error on load data access
be_store_o : out std_ulogic; -- bus error on store data access
-- instruction bus --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- fence operation
-- data bus --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_fence_o : out std_ulogic -- fence operation
);
end neorv32_cpu_bus;
 
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
 
-- interface registers --
-- data interface registers --
signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
 
-- bus request controller --
signal bus_busy : std_ulogic;
signal bus_if_req : std_ulogic;
signal bus_rd_req : std_ulogic;
signal bus_wr_req : std_ulogic;
signal access_err : std_ulogic;
signal align_err : std_ulogic;
signal bus_timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
-- data access --
signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable
 
-- misaligned access? --
signal misaligned_data, misaligned_instr : std_ulogic;
signal d_misaligned, i_misaligned : std_ulogic;
 
-- bus arbiter --
type bus_arbiter_t is record
rd_req : std_ulogic; -- read access in progress
wr_req : std_ulogic; -- write access in progress
err_align : std_ulogic; -- alignment error
err_bus : std_ulogic; -- bus access error
timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
end record;
signal i_arbiter, d_arbiter : bus_arbiter_t;
 
begin
 
-- Address and Control --------------------------------------------------------------------
-- Data Interface: Access Address ---------------------------------------------------------
-- -------------------------------------------------------------------------------------------
mem_adr_reg: process(rstn_i, clk_i)
begin
if rising_edge(clk_i) then
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
mar <= alu_i;
mar <= addr_i;
end if;
end if;
end process mem_adr_reg;
 
-- address output --
bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch? keep output at PC as long as IF request is active
mar_o <= mar;
-- read-back for exception controller --
mar_o <= mar;
 
-- write request output --
bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data);
-- alignment check --
misaligned_d_check: process(mar, ctrl_i)
begin
-- check data access --
d_misaligned <= '0'; -- default
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
when "00" => -- byte
d_misaligned <= '0';
when "01" => -- half-word
if (mar(0) /= '0') then
d_misaligned <= '1';
end if;
when others => -- word
if (mar(1 downto 0) /= "00") then
d_misaligned <= '1';
end if;
end case;
end process misaligned_d_check;
 
-- read request output (also used for instruction fetch) --
bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or (ctrl_i(ctrl_bus_if_c) and (not misaligned_instr)); -- FIXME i_reg and misaligned
 
 
-- Write Data -----------------------------------------------------------------------------
-- Data Interface: Write Data -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
mem_do_reg: process(clk_i)
begin
138,28 → 169,28
begin
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
when "00" => -- byte
bus_wdata_o(07 downto 00) <= mdo(07 downto 00);
bus_wdata_o(15 downto 08) <= mdo(07 downto 00);
bus_wdata_o(23 downto 16) <= mdo(07 downto 00);
bus_wdata_o(31 downto 24) <= mdo(07 downto 00);
bus_ben_o <= (others => '0');
bus_ben_o(to_integer(unsigned(mar(1 downto 0)))) <= '1';
d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
d_bus_ben <= (others => '0');
d_bus_ben(to_integer(unsigned(mar(1 downto 0)))) <= '1';
when "01" => -- half-word
bus_wdata_o(31 downto 16) <= mdo(15 downto 00);
bus_wdata_o(15 downto 00) <= mdo(15 downto 00);
d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
if (mar(1) = '0') then
bus_ben_o <= "0011"; -- low half-word
d_bus_ben <= "0011"; -- low half-word
else
bus_ben_o <= "1100"; -- high half-word
d_bus_ben <= "1100"; -- high half-word
end if;
when others => -- word
bus_wdata_o <= mdo;
bus_ben_o <= "1111"; -- full word
d_bus_wdata <= mdo;
d_bus_ben <= "1111"; -- full word
end case;
end process byte_enable;
 
 
-- Read Data ------------------------------------------------------------------------------
-- Data Interface: Read Data --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
mem_out_buf: process(clk_i)
begin
166,15 → 197,12
if rising_edge(clk_i) then
-- memory data in register (MDI) --
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
mdi <= bus_rdata_i;
mdi <= d_bus_rdata;
end if;
end if;
end process mem_out_buf;
 
-- instruction output --
instr_o <= bus_rdata_i;
 
-- input data align and sign extension --
-- input data alignment and sign extension --
read_align: process(mdi, mar, ctrl_i)
variable signed_v : std_ulogic;
begin
209,98 → 237,134
end process read_align;
 
 
-- Bus Status Controller ------------------------------------------------------------------
-- Instruction Interface: Check for Misaligned Access -------------------------------------
-- -------------------------------------------------------------------------------------------
bus_ctrl: process(rstn_i, clk_i)
misaligned_i_check: process(ctrl_i, fetch_pc_i)
begin
-- check instruction access --
i_misaligned <= '0'; -- default
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
i_misaligned <= '0'; -- no alignment exceptions possible
else -- 32-bit instruction accesses only
if (fetch_pc_i(1) = '1') then -- PC(0) is always zero
i_misaligned <= '1';
end if;
end if;
end process misaligned_i_check;
 
 
-- Instruction Fetch Arbiter --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ifetch_arbiter: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
bus_busy <= '0';
bus_if_req <= '0';
bus_rd_req <= '0';
bus_wr_req <= '0';
access_err <= '0';
align_err <= '0';
bus_timeout <= (others => '0');
i_arbiter.rd_req <= '0';
i_arbiter.wr_req <= '0';
i_arbiter.err_align <= '0';
i_arbiter.err_bus <= '0';
i_arbiter.timeout <= (others => '0');
elsif rising_edge(clk_i) then
if (bus_busy = '0') or (ctrl_i(ctrl_bus_reset_c) = '1') then -- wait for new request or reset
bus_busy <= ctrl_i(ctrl_bus_if_c) or ctrl_i(ctrl_bus_rd_c) or ctrl_i(ctrl_bus_wr_c); -- any request at all?
bus_if_req <= ctrl_i(ctrl_bus_if_c); -- instruction fetch
bus_rd_req <= ctrl_i(ctrl_bus_rd_c); -- store access
bus_wr_req <= ctrl_i(ctrl_bus_wr_c); -- load access
bus_timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
access_err <= '0';
align_err <= '0';
else -- bus transfer in progress
bus_timeout <= std_ulogic_vector(unsigned(bus_timeout) - 1);
align_err <= (align_err or misaligned_data or misaligned_instr) and (not ctrl_i(ctrl_bus_exc_ack_c));
access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not ctrl_i(ctrl_bus_exc_ack_c));
if (align_err = '1') or (access_err = '1') then
if (ctrl_i(ctrl_bus_exc_ack_c) = '1') then -- wait for controller to ack exception
bus_if_req <= '0';
bus_rd_req <= '0';
bus_wr_req <= '0';
bus_busy <= '0';
i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
 
-- instruction fetch request --
if (i_arbiter.rd_req = '0') then -- idle
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
i_arbiter.err_align <= i_misaligned;
i_arbiter.err_bus <= '0';
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
else -- in progress
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error?
if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error
i_arbiter.rd_req <= '0';
end if;
elsif (bus_ack_i = '1') then -- normal termination
bus_if_req <= '0';
bus_rd_req <= '0';
bus_wr_req <= '0';
bus_busy <= '0';
elsif (i_bus_ack_i = '1') then -- wait for normal termination
i_arbiter.rd_req <= '0';
end if;
end if;
 
-- cancel bus access --
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
end if;
end process bus_ctrl;
end process ifetch_arbiter;
 
-- output bus access error to controller --
be_instr_o <= bus_if_req and access_err;
be_load_o <= bus_rd_req and access_err;
be_store_o <= bus_wr_req and access_err;
 
-- output alignment error to controller --
ma_instr_o <= bus_if_req and align_err;
ma_load_o <= bus_rd_req and align_err;
ma_store_o <= bus_wr_req and align_err;
-- wait for bus transaction to finish --
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
 
-- terminate bus access --
bus_cancel_o <= (bus_busy and (align_err or access_err)) or ctrl_i(ctrl_bus_reset_c);
-- output instruction fetch error to controller --
ma_instr_o <= i_arbiter.err_align;
be_instr_o <= i_arbiter.err_bus;
 
-- wait for bus --
bus_busy_o <= bus_busy;
bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack
-- instruction bus (read-only) --
i_bus_addr_o <= fetch_pc_i;
i_bus_wdata_o <= (others => '0');
i_bus_ben_o <= (others => '0');
i_bus_we_o <= '0';
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned); -- no actual read when misaligned
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
instr_o <= i_bus_rdata_i;
 
 
-- Check for Misaligned Access ------------------------------------------------------------
-- Data Access Arbiter --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
misaligned_d_check: process(mar, ctrl_i)
data_access_arbiter: process(rstn_i, clk_i)
begin
-- check data access --
misaligned_data <= '0'; -- default
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
when "00" => -- byte
misaligned_data <= '0';
when "01" => -- half-word
if (mar(0) /= '0') then
misaligned_data <= '1';
if (rstn_i = '0') then
d_arbiter.rd_req <= '0';
d_arbiter.wr_req <= '0';
d_arbiter.err_align <= '0';
d_arbiter.err_bus <= '0';
d_arbiter.timeout <= (others => '0');
elsif rising_edge(clk_i) then
 
-- data access request --
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
d_arbiter.err_align <= d_misaligned;
d_arbiter.err_bus <= '0';
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
else -- in progress
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error?
if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error
d_arbiter.wr_req <= '0';
d_arbiter.rd_req <= '0';
end if;
elsif (d_bus_ack_i = '1') then -- wait for normal termination
d_arbiter.wr_req <= '0';
d_arbiter.rd_req <= '0';
end if;
when others => -- word
if (mar(1 downto 0) /= "00") then
misaligned_data <= '1';
end if;
end case;
end process misaligned_d_check;
end if;
 
misaligned_i_check: process(ctrl_i, pc_i)
begin
-- check instruction access --
misaligned_instr <= '0'; -- default
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
misaligned_instr <= '0'; -- no alignment exceptions possible
else -- 32-bit instruction accesses only
if (pc_i(1) = '1') then -- PC(0) is always zero
misaligned_instr <= '1';
end if;
-- cancel bus access --
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
end if;
end process misaligned_i_check;
end process data_access_arbiter;
 
 
-- wait for bus transaction to finish --
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
 
-- output data access error to controller --
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
 
-- data bus --
d_bus_addr_o <= mar;
d_bus_wdata_o <= d_bus_wdata;
d_bus_ben_o <= d_bus_ben;
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned); -- no actual write when misaligned
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned); -- no actual read when misaligned
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
d_bus_rdata <= d_bus_rdata_i;
 
 
end neorv32_cpu_bus_rtl;
/core/neorv32_cpu_control.vhd
46,40 → 46,15
entity neorv32_cpu_control is
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
-- Memory configuration: External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.?
);
port (
-- global control --
88,7 → 63,8
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-- status input --
alu_wait_i : in std_ulogic; -- wait for ALU
bus_wait_i : in std_ulogic; -- wait for bus
bus_i_wait_i : in std_ulogic; -- wait for bus
bus_d_wait_i : in std_ulogic; -- wait for bus
-- data input --
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
102,6 → 78,7
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
-- external interrupt --
msw_irq_i : in std_ulogic; -- software interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic; -- machine timer interrupt
-- system time input from MTIME --
113,8 → 90,7
ma_store_i : in std_ulogic; -- misaligned store data address
be_instr_i : in std_ulogic; -- bus error on instruction access
be_load_i : in std_ulogic; -- bus error on load data access
be_store_i : in std_ulogic; -- bus error on store data access
bus_busy_i : in std_ulogic -- bus unit is busy
be_store_i : in std_ulogic -- bus error on store data access
);
end neorv32_cpu_control;
 
141,7 → 117,6
ci_return_nxt : std_ulogic;
reset : std_ulogic;
bus_err_ack : std_ulogic;
bus_reset : std_ulogic;
end record;
signal fetch_engine : fetch_engine_t;
 
165,11 → 140,10
signal ipb : ipb_t;
 
-- instruction execution engine --
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, STORE, LOAD, LOADSTORE_0, LOADSTORE_1, CSR_ACCESS);
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS);
type execute_engine_t is record
state : execute_engine_state_t;
state_nxt : execute_engine_state_t;
state_prev : execute_engine_state_t;
i_reg : std_ulogic_vector(31 downto 0);
i_reg_nxt : std_ulogic_vector(31 downto 0);
is_ci : std_ulogic; -- current instruction is de-compressed instruction
186,6 → 160,8
end record;
signal execute_engine : execute_engine_t;
 
signal next_pc_tmp : std_ulogic_vector(data_width_c-1 downto 0);
 
-- trap controller --
type trap_ctrl_t is record
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
195,9 → 171,8
exc_ack : std_ulogic; -- acknowledge all exceptions
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
cause : std_ulogic_vector(data_width_c-1 downto 0); -- trap ID (for "mcause")
cause_nxt : std_ulogic_vector(data_width_c-1 downto 0);
exc_src : std_ulogic_vector(exception_width_c-1 downto 0);
cause : std_ulogic_vector(4 downto 0); -- trap ID (for "mcause"), only for hw
cause_nxt : std_ulogic_vector(4 downto 0);
--
env_start : std_ulogic; -- start trap handler env
env_start_ack : std_ulogic; -- start of trap handler acknowledged
225,24 → 200,24
re_nxt : std_ulogic;
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)
mip_msip : std_ulogic; -- mip.MSIP: machine software interrupt pending (R/W)
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W)
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
mcycleh : std_ulogic_vector(19 downto 0); -- mcycleh (R/W) - REDUCED BIT-WIDTH!
minstreth : std_ulogic_vector(19 downto 0); -- minstreth (R/W) - REDUCED BIT-WIDTH!
end record;
signal csr : csr_t;
 
signal mcycle_msb : std_ulogic;
signal minstret_msb : std_ulogic;
signal systime : std_ulogic_vector(63 downto 0);
 
-- illegal instruction check --
signal illegal_instruction : std_ulogic;
314,10 → 289,13
end if;
end process fetch_engine_fsm_sync;
 
-- PC output --
fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0';
 
 
-- Fetch Engine FSM Comb ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
fetch_engine_fsm_comb: process(fetch_engine, execute_engine, csr, ipb, instr_i, bus_wait_i, bus_busy_i, ci_instr32, be_instr_i, ma_instr_i)
fetch_engine_fsm_comb: process(fetch_engine, csr, ipb, instr_i, bus_i_wait_i, ci_instr32, be_instr_i, ma_instr_i)
begin
-- arbiter defaults --
fetch_engine.state_nxt <= fetch_engine.state;
330,7 → 308,6
fetch_engine.ci_reg_nxt <= fetch_engine.ci_reg;
fetch_engine.ci_return_nxt <= fetch_engine.ci_return;
fetch_engine.bus_err_ack <= '0';
fetch_engine.bus_reset <= '0';
 
-- instruction prefetch buffer interface --
ipb.we <= '0';
345,82 → 322,71
-- ------------------------------------------------------------
fetch_engine.i_buf_state_nxt <= (others => '0');
fetch_engine.ci_return_nxt <= '0';
fetch_engine.bus_reset <= '1'; -- reset bus unit
ipb.clear <= '1'; -- clear instruction prefetch buffer
fetch_engine.state_nxt <= IFETCH_0;
 
when IFETCH_0 => -- output current PC to bus system, request 32-bit word
-- ------------------------------------------------------------
if (bus_busy_i = '0') and (execute_engine.state /= LOAD) and (execute_engine.state /= STORE) and
(execute_engine.state /= LOADSTORE_0) and (execute_engine.state /= LOADSTORE_1) then -- wait if execute engine is using bus unit
bus_fast_ir <= '1'; -- fast instruction fetch request (output PC to bus.address)
fetch_engine.state_nxt <= IFETCH_1;
end if;
bus_fast_ir <= '1'; -- fast instruction fetch request
fetch_engine.state_nxt <= IFETCH_1;
 
when IFETCH_1 => -- store data from memory to buffer(s)
-- ------------------------------------------------------------
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
if (bus_wait_i = '0') then -- wait for bus response
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
fetch_engine.i_buf_state_nxt(1) <= fetch_engine.i_buf_state(0);
fetch_engine.state_nxt <= IFETCH_2;
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1';
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them
if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled?
fetch_engine.state_nxt <= IFETCH_2;
else
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.state_nxt <= IFETCH_0; -- get another instruction word
end if;
end if;
 
fetch_engine.i_buf_state_nxt(0) <= '1';
if (be_instr_i = '1') or (ma_instr_i = '1') then -- any fetch exception?
fetch_engine.bus_err_ack <= '1'; -- ack bus errors, the execute engine has to take care of them
end if;
 
when IFETCH_2 => -- construct instruction and issue
when IFETCH_2 => -- construct instruction word and issue
-- ------------------------------------------------------------
if (fetch_engine.i_buf_state(1) = '1') then
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00);
ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
if (ipb.free = '1') then -- free entry in buffer?
ipb.we <= '1';
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.state_nxt <= IFETCH_0;
end if;
else -- compressed
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
fetch_engine.ci_return_nxt <= '1'; -- come back here after issueing
fetch_engine.state_nxt <= IFETCH_3;
end if;
else -- 16-bit aligned
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(31 downto 16);
ipb.wdata <= fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16);
if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed
if (ipb.free = '1') then -- free entry in buffer?
ipb.we <= '1';
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.state_nxt <= IFETCH_0;
end if;
else -- compressed
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
fetch_engine.ci_return_nxt <= '0'; -- start next fetch after issueing
fetch_engine.state_nxt <= IFETCH_3;
end if;
end if;
else
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.state_nxt <= IFETCH_0;
end if;
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00);
ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
 
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
if (ipb.free = '1') then -- free entry in buffer?
ipb.we <= '1';
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.state_nxt <= IFETCH_0;
end if;
else -- compressed
fetch_engine.ci_return_nxt <= '1'; -- come back here after issueing
fetch_engine.state_nxt <= IFETCH_3;
end if;
else -- 16-bit aligned
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(31 downto 16);
ipb.wdata <= fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16);
 
if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed
if (ipb.free = '1') then -- free entry in buffer?
ipb.we <= '1';
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
fetch_engine.state_nxt <= IFETCH_0;
end if;
else -- compressed
fetch_engine.ci_return_nxt <= '0'; -- start next fetch after issueing
fetch_engine.state_nxt <= IFETCH_3;
end if;
end if;
 
when IFETCH_3 => -- additional cycle for issueing decompressed instructions
-- ------------------------------------------------------------
if (ipb.free = '1') then -- free entry in buffer?
ipb.we <= '1';
ipb.wdata <= fetch_engine.ci_reg(17 downto 16) & '1' & ci_instr32;
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
ipb.we <= '1';
ipb.wdata <= fetch_engine.ci_reg(17 downto 16) & '1' & ci_instr32;
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
if (fetch_engine.ci_return = '0') then
fetch_engine.state_nxt <= IFETCH_0;
else
536,19 → 502,13
 
-- Execute Engine FSM Sync ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- for registers that require a specific reset state --
-- for registers that DO require a specific reset state --
execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
if (BOOTLOADER_USE = true) then -- boot from bootloader ROM
execute_engine.pc <= boot_base_c(data_width_c-1 downto 1) & '0';
execute_engine.last_pc <= boot_base_c(data_width_c-1 downto 1) & '0';
else -- boot from IMEM
execute_engine.pc <= MEM_ISPACE_BASE(data_width_c-1 downto 1) & '0';
execute_engine.last_pc <= MEM_ISPACE_BASE(data_width_c-1 downto 1) & '0';
end if;
execute_engine.state <= SYS_WAIT;
execute_engine.state_prev <= SYS_WAIT;
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
execute_engine.state <= SYS_WAIT;
--
execute_engine.sleep <= '0';
elsif rising_edge(clk_i) then
556,8 → 516,7
if (execute_engine.state = EXECUTE) then
execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0';
end if;
execute_engine.state <= execute_engine.state_nxt;
execute_engine.state_prev <= execute_engine.state;
execute_engine.state <= execute_engine.state_nxt;
--
execute_engine.sleep <= execute_engine.sleep_nxt;
end if;
564,7 → 523,7
end process execute_engine_fsm_sync_rst;
 
 
-- for registers that DO NOT require a specific reset state --
-- for registers that do NOT require a specific reset state --
execute_engine_fsm_sync: process(clk_i)
begin
if rising_edge(clk_i) then
576,13 → 535,11
end if;
end process execute_engine_fsm_sync;
 
 
-- PC output --
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc(data_width_c-1 downto 1) & '0') + 2) when (execute_engine.is_ci = '1') else
std_ulogic_vector(unsigned(execute_engine.pc(data_width_c-1 downto 1) & '0') + 4);
fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0';
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0';
next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0';
next_pc_tmp <= std_ulogic_vector(unsigned(execute_engine.pc) + 2) when (execute_engine.is_ci = '1') else std_ulogic_vector(unsigned(execute_engine.pc) + 4);
execute_engine.next_pc <= next_pc_tmp(data_width_c-1 downto 1) & '0';
next_pc_o <= next_pc_tmp(data_width_c-1 downto 1) & '0';
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0';
 
 
-- CPU Control Bus Output -----------------------------------------------------------------
594,11 → 551,11
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
-- bus access requests --
-- fast bus access requests --
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir;
-- bus control --
ctrl_o(ctrl_bus_exc_ack_c) <= trap_ctrl.env_start_ack or fetch_engine.bus_err_ack;
ctrl_o(ctrl_bus_reset_c) <= fetch_engine.bus_reset;
-- bus error control --
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;
end process ctrl_output;
 
 
605,10 → 562,9
-- Execute Engine FSM Comb ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
execute_engine_fsm_comb: process(execute_engine, fetch_engine, ipb, trap_ctrl, csr, ctrl,
alu_add_i, alu_wait_i, bus_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
alu_add_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
variable alu_immediate_v : std_ulogic;
variable alu_operation_v : std_ulogic_vector(2 downto 0);
variable rd_is_r0_v : std_ulogic;
variable rs1_is_r0_v : std_ulogic;
begin
-- arbiter defaults --
639,19 → 595,18
 
-- control defaults --
ctrl_nxt <= (others => '0'); -- all off at first
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation (SLTIU, SLTU)
else -- branches
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches (BLTU, BGEU)
end if;
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- arithmetic shift
ctrl_nxt(ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- transfer size lsb (00=byte, 01=half-word)
ctrl_nxt(ctrl_bus_size_msb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- transfer size msb (10=word, 11=?)
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = add
ctrl_nxt(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); -- CP operation
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 implemented yet
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 (MULDIV) implemented yet
 
-- is immediate operation? --
alu_immediate_v := '0';
677,12 → 632,6
when others => alu_operation_v := (others => '0'); -- undefined
end case;
 
-- is rd = r0? --
rd_is_r0_v := '0';
if (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") then
rd_is_r0_v := '1';
end if;
 
-- is rs1 = r0? --
rs1_is_r0_v := '0';
if (execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
722,7 → 671,7
if (trap_ctrl.env_start = '1') then
trap_ctrl.env_start_ack <= '1';
execute_engine.sleep_nxt <= '0'; -- waky waky
execute_engine.pc_nxt <= csr.mtvec(data_width_c-1 downto 1) & '0';
execute_engine.pc_nxt <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- has to be here for wfi to work
execute_engine.state_nxt <= SYS_WAIT;
end if;
 
740,7 → 689,7
-- multi cycle alu operation? --
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001")) then -- MULDIV?
(execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
execute_engine.state_nxt <= ALU_WAIT;
else
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
748,15 → 697,14
end if;
-- cp access? --
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV?
(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- muldiv CP
end if;
 
 
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 (only relevant for LUI)
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_auipc_c) then -- AUIPC
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
else -- LUI
775,13 → 723,7
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation
ctrl_nxt(ctrl_bus_mar_we_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_bus_mdo_we_c) <= '1'; -- write to MDO (only relevant for stores)
if (fetch_engine.state /= IFETCH_0) then
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD
execute_engine.state_nxt <= LOAD;
else -- STORE
execute_engine.state_nxt <= STORE;
end if;
end if;
execute_engine.state_nxt <= LOADSTORE_0;
 
when opcode_branch_c => -- branch instruction
-- ------------------------------------------------------------
808,22 → 750,19
 
when opcode_fence_c => -- fence operations
-- ------------------------------------------------------------
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
fetch_engine.reset <= '1';
execute_engine.pc_nxt <= execute_engine.next_pc;
execute_engine.state_nxt <= SYS_WAIT;
else
execute_engine.state_nxt <= DISPATCH;
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction (only relevant for fencei)
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCEI
fetch_engine.reset <= '1';
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
end if;
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
ctrl_nxt(ctrl_bus_fence_c) <= '1';
end if;
execute_engine.state_nxt <= SYS_WAIT;
 
when opcode_syscsr_c => -- system/csr access
-- ------------------------------------------------------------
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
csr.re_nxt <= not rd_is_r0_v; -- only read CSR if not writing to zero_reg
else
csr.re_nxt <= '1'; -- always read CSR
end if;
csr.re_nxt <= '1'; -- always read CSR
--
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
841,10 → 780,12
NULL;
end case;
execute_engine.state_nxt <= SYS_WAIT;
elsif (CPU_EXTENSION_RISCV_Zicsr = true) then -- CSR access
execute_engine.state_nxt <= CSR_ACCESS;
else
execute_engine.state_nxt <= DISPATCH;
if (CPU_EXTENSION_RISCV_Zicsr = true) then -- CSR access
execute_engine.state_nxt <= CSR_ACCESS;
else -- undefined
execute_engine.state_nxt <= DISPATCH;
end if;
end if;
 
when others => -- undefined
859,6 → 800,7
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- default
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '0'; -- default
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- default
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- default ALU operation = OR
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
-- register operations --
when funct3_csrrw_c => -- CSRRW
865,11 → 807,11
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- OPB = rs2
ctrl_nxt(ctrl_rf_clear_rs2_c) <= '1'; -- rs2 = 0
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = ADD
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
csr.we_nxt <= '1'; -- always write CSR
when funct3_csrrs_c => -- CSRRS
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = crs1
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if rs1 is not zero_reg
when funct3_csrrc_c => -- CSRRC
882,7 → 824,7
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- rs1 = 0
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = ADD
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
csr.we_nxt <= '1'; -- always write CSR
when funct3_csrrsi_c => -- CSRRSI
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
898,7 → 840,7
NULL;
end case;
-- RF write back --
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output register
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
 
906,9 → 848,9
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (write back all the time)
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
if (alu_wait_i = '0') then
execute_engine.state_nxt <= DISPATCH;
execute_engine.state_nxt <= DISPATCH;
end if;
 
when BRANCH => -- update PC for taken branches and jumps
921,28 → 863,27
execute_engine.state_nxt <= DISPATCH;
end if;
 
when LOAD => -- trigger memory read request
when LOADSTORE_0 => -- trigger memory request
-- ------------------------------------------------------------
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- fast read request
execute_engine.state_nxt <= LOADSTORE_0;
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
else -- STORE
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
end if;
execute_engine.state_nxt <= LOADSTORE_1;
 
when STORE => -- trigger memory write request
when LOADSTORE_1 => -- memory latency
-- ------------------------------------------------------------
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- fast write request
execute_engine.state_nxt <= LOADSTORE_0;
 
when LOADSTORE_0 => -- memory latency
-- ------------------------------------------------------------
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
execute_engine.state_nxt <= LOADSTORE_1;
execute_engine.state_nxt <= LOADSTORE_2;
 
when LOADSTORE_1 => -- wait for bus transaction to finish
when LOADSTORE_2 => -- wait for bus transaction to finish
-- ------------------------------------------------------------
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD)
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD)
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception
execute_engine.state_nxt <= SYS_WAIT;
elsif (bus_wait_i = '0') then -- wait here for bus to finish transaction
elsif (bus_d_wait_i = '0') then -- wait here for bus to finish transaction
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD?
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
end if;
1075,27 → 1016,22
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"343") or -- mtval
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"344") or -- mip
--
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycle
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (IO_MTIME_USE = true)) or -- time
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instret
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycleh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (IO_MTIME_USE = true)) or -- timeh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instreth
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CSR_COUNTERS_USE = true)) or -- cycle
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (CSR_COUNTERS_USE = true)) or -- time
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CSR_COUNTERS_USE = true)) or -- instret
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CSR_COUNTERS_USE = true)) or -- cycleh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (CSR_COUNTERS_USE = true)) or -- timeh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CSR_COUNTERS_USE = true)) or -- instreth
--
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- mcycle
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b02") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- minstret
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b80") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- mcycleh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b82") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- minstreth
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CSR_COUNTERS_USE = true)) or -- mcycle
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b02") and (CSR_COUNTERS_USE = true)) or -- minstret
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b80") and (CSR_COUNTERS_USE = true)) or -- mcycleh
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b82") and (CSR_COUNTERS_USE = true)) or -- minstreth
--
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f11") or -- mvendorid
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f12") or -- marchid
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f13") or -- mimpid
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f14") or -- mhartid
--
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc0") or -- mfeatures
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc1") or -- mclock
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc4") or -- mispacebase
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc5") or -- mispacesize
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc6") or -- mdspacebase
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc7") then -- mdspacesize
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f14") then -- mhartid
illegal_instruction <= '0';
else
illegal_instruction <= '1';
1119,7 → 1055,7
when others => -- compressed instruction or undefined instruction
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode
illegal_instruction <= '1';
else -- compressed instruction: illegal or disabled / not implemented
else -- compressed instruction: illegal or not implemented
illegal_compressed <= ci_illegal;
end if;
 
1150,7 → 1086,6
trap_ctrl.exc_ack <= '0';
trap_ctrl.irq_ack <= (others => '0');
trap_ctrl.cause <= (others => '0');
trap_ctrl.exc_src <= (others => '0');
trap_ctrl.env_start <= '0';
elsif rising_edge(clk_i) then
if (CPU_EXTENSION_RISCV_Zicsr = true) then
1167,7 → 1102,7
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
-- interrupt buffer: machine software/external/timer interrupt
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or csr.mip_msip) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or clic_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
 
1176,7 → 1111,6
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program
trap_ctrl.exc_src <= trap_ctrl.exc_buf; -- capture exception source for hardware
trap_ctrl.exc_ack <= '1'; -- clear execption
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
trap_ctrl.env_start <= '1'; -- now we want to start the trap handler
1206,77 → 1140,65
trap_ctrl.irq_ack_nxt <= (others => '0');
 
-- the following traps are caused by asynchronous exceptions (-> interrupts)
-- here we do need an acknowledge mask since several sources can trigger at once
-- here we do need a specific acknowledge mask since several sources can trigger at once
 
-- interrupt: 1.11 machine external interrupt --
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '1';
trap_ctrl.cause_nxt(3 downto 0) <= "1011";
trap_ctrl.cause_nxt <= trap_mei_c;
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
 
-- interrupt: 1.7 machine timer interrupt --
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '1';
trap_ctrl.cause_nxt(3 downto 0) <= "0111";
trap_ctrl.cause_nxt <= trap_mti_c;
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
 
-- interrupt: 1.3 machine SW interrupt --
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '1';
trap_ctrl.cause_nxt(3 downto 0) <= "0011";
trap_ctrl.cause_nxt <= trap_msi_c;
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
 
 
-- the following traps are caused by synchronous exceptions
-- here we do not need an acknowledge mask since only one exception (the one
-- here we do not need a specific acknowledge mask since only one exception (the one
-- with highest priority) can trigger at once
 
-- trap/fault: 0.0 instruction address misaligned --
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "0000";
 
-- trap/fault: 0.1 instruction access fault --
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "0001";
trap_ctrl.cause_nxt <= trap_iba_c;
 
-- trap/fault: 0.2 illegal instruction --
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "0010";
trap_ctrl.cause_nxt <= trap_iil_c;
 
-- trap/fault: 0.0 instruction address misaligned --
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
trap_ctrl.cause_nxt <= trap_ima_c;
 
 
-- trap/fault: 0.11 environment call from M-mode --
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "1011";
trap_ctrl.cause_nxt <= trap_env_c;
 
-- trap/fault: 0.3 breakpoint --
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "0011";
trap_ctrl.cause_nxt <= trap_brk_c;
 
 
-- trap/fault: 0.6 store address misaligned -
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "0110";
trap_ctrl.cause_nxt <= trap_sma_c;
 
-- trap/fault: 0.4 load address misaligned --
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "0100";
trap_ctrl.cause_nxt <= trap_lma_c;
 
-- trap/fault: 0.7 store access fault --
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "0111";
trap_ctrl.cause_nxt <= trap_sbe_c;
 
-- trap/fault: 0.5 load access fault --
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
trap_ctrl.cause_nxt(3 downto 0) <= "0101";
trap_ctrl.cause_nxt <= trap_lbe_c;
 
-- undefined / not implemented --
else
1304,9 → 1226,10
csr.mie_meie <= '0';
csr.mie_mtie <= '0';
csr.mtvec <= (others => '0');
csr.mscratch <= (others => '0');
csr.mepc <= (others => '0');
csr.mcause <= (others => '0');
csr.mtval <= (others => '0');
csr.mepc <= (others => '0');
csr.mip_msip <= '0';
elsif rising_edge(clk_i) then
if (CPU_EXTENSION_RISCV_Zicsr = true) then
-- access --
1313,9 → 1236,6
csr.we <= csr.we_nxt;
csr.re <= csr.re_nxt;
 
-- defaults --
csr.mip_msip <= '0';
 
-- registers that can be modified by user --
if (csr.we = '1') then -- manual update
 
1324,17 → 1244,17
-- machine trap setup --
if (execute_engine.i_reg(27 downto 24) = x"0") then
case execute_engine.i_reg(23 downto 20) is
when x"0" => -- R/W: mstatus - machine status register
csr.mstatus_mie <= csr_wdata_i(03);
csr.mstatus_mpie <= csr_wdata_i(07);
when x"4" => -- R/W: mie - machine interrupt-enable register
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.mtvec <= csr_wdata_i;
when others =>
NULL;
when x"0" => -- R/W: mstatus - machine status register
csr.mstatus_mie <= csr_wdata_i(03);
csr.mstatus_mpie <= csr_wdata_i(07);
when x"4" => -- R/W: mie - machine interrupt-enable register
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.mtvec <= csr_wdata_i(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
when others =>
NULL;
end case;
end if;
-- machine trap handling --
1343,13 → 1263,11
when x"0" => -- R/W: mscratch - machine scratch register
csr.mscratch <= csr_wdata_i;
when x"1" => -- R/W: mepc - machine exception program counter
csr.mepc <= csr_wdata_i;
csr.mepc <= csr_wdata_i(data_width_c-1 downto 1) & '0';
when x"2" => -- R/W: mcause - machine trap cause
csr.mcause <= csr_wdata_i;
when x"3" => -- R/W: mtval - machine bad address or instruction
csr.mtval <= csr_wdata_i;
when x"4" => -- R/W: mip - machine interrupt pending
csr.mip_msip <= csr_wdata_i(03); -- manual SW IRQ trigger
when others =>
NULL;
end case;
1359,19 → 1277,22
-- automatic update by hardware --
else
 
-- machine exception PC & exception value register --
if (trap_ctrl.env_start_ack = '1') then -- trap handler started?
csr.mcause <= trap_ctrl.cause;
if (csr.mcause(data_width_c-1) = '1') then -- for INTERRUPTS only
-- machine exception PC & trap value register --
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
csr.mcause <= trap_ctrl.cause(4) & "000" & x"000000" & trap_ctrl.cause(3 downto 0);
if (trap_ctrl.cause(4) = '1') then -- for INTERRUPTS only
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
csr.mtval <= (others => '0'); -- mtval not defined for interrupts
csr.mtval <= (others => '0'); -- mtval is zero for interrupts
else -- for EXCEPTIONS (according to their priority)
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
if ((trap_ctrl.exc_src(exception_iaccess_c) or trap_ctrl.exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction
if (trap_ctrl.cause(3 downto 0) = trap_iba_c(3 downto 0)) or -- instr access error OR
(trap_ctrl.cause(3 downto 0) = trap_ima_c(3 downto 0)) or -- misaligned instruction OR
(trap_ctrl.cause(3 downto 0) = trap_brk_c(3 downto 0)) or -- breakpoint OR
(trap_ctrl.cause(3 downto 0) = trap_env_c(3 downto 0)) then -- env call OR
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
elsif (trap_ctrl.exc_src(exception_iillegal_c) = '1') then -- illegal instruction
csr.mtval <= execute_engine.i_reg; -- the faulting instruction itself
else -- load/store msialignments/access errors
elsif (trap_ctrl.cause(3 downto 0) = trap_iil_c(3 downto 0)) then -- illegal instruction
csr.mtval <= execute_engine.i_reg; -- faulting instruction itself
else -- load/store misalignments/access errors
csr.mtval <= mar_i; -- faulting data access address
end if;
end if;
1378,7 → 1299,7
end if;
 
-- context switch in mstatus --
if (trap_ctrl.env_start_ack = '1') then -- actually entering trap
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
csr.mstatus_mie <= '0';
if (csr.mstatus_mpie = '0') then -- prevent loosing the prev MIE state in nested traps
csr.mstatus_mpie <= csr.mstatus_mie;
1406,8 → 1327,8
when x"300" => -- R/W: mstatus - machine status register
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE
csr_rdata_o(11) <= '1'; -- MPP low
csr_rdata_o(12) <= '1'; -- MPP high
csr_rdata_o(11) <= '1'; -- MPP low - M-mode
csr_rdata_o(12) <= '1'; -- MPP high - M-mode
when x"301" => -- R/-: misa - ISA and extensions
csr_rdata_o(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
1421,13 → 1342,13
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr_rdata_o <= csr.mtvec;
csr_rdata_o <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
 
-- machine trap handling --
when x"340" => -- R/W: mscratch - machine scratch register
csr_rdata_o <= csr.mscratch;
when x"341" => -- R/W: mepc - machine exception program counter
csr_rdata_o <= csr.mepc;
csr_rdata_o <= csr.mepc(data_width_c-1 downto 1) & '0';
when x"342" => -- R/W: mcause - machine trap cause
csr_rdata_o <= csr.mcause;
when x"343" => -- R/W: mtval - machine bad address or instruction
1440,64 → 1361,42
-- counter and timers --
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
csr_rdata_o <= csr.mcycle(31 downto 0);
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
csr_rdata_o <= systime(31 downto 0);
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW
csr_rdata_o <= csr.minstret(31 downto 0);
when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH
csr_rdata_o <= csr.mcycleh;
csr_rdata_o <= x"000" & csr.mcycleh(19 downto 0); -- only the lowest 20 bit!
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
csr_rdata_o <= systime(63 downto 32);
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
csr_rdata_o <= csr.minstreth;
csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit!
 
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
csr_rdata_o <= time_i(31 downto 0);
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
csr_rdata_o <= time_i(63 downto 32);
 
-- machine information registers --
when x"f13" => -- R/-: mimpid - implementation ID / version
when x"f11" => -- R/-: mvendorid
csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32
when x"f12" => -- R/-: marchid
csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32
when x"f13" => -- R/-: mimpid - implementation ID / NEORV32: version
csr_rdata_o <= hw_version_c;
when x"f14" => -- R/-: mhartid - hardware thread ID
csr_rdata_o <= HART_ID;
csr_rdata_o <= HW_THREAD_ID;
 
-- CUSTOM read-only machine CSRs --
when x"fc0" => -- R/-: mfeatures - implemented processor devices/features
csr_rdata_o(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader?
csr_rdata_o(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface?
csr_rdata_o(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory?
csr_rdata_o(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM?
csr_rdata_o(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory?
csr_rdata_o(05) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- implement RISC-V (performance) counter?
--
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)?
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)?
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)?
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)?
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)?
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)?
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)?
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)?
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)?
csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)?
when x"fc1" => -- R/-: mclock - processor clock speed
csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space
csr_rdata_o <= MEM_ISPACE_BASE;
when x"fc5" => -- R/-: mdspacebase - Base address of data memory space
csr_rdata_o <= MEM_DSPACE_BASE;
when x"fc6" => -- R/-: mispacesize - Total size of instruction memory space in byte
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32));
when x"fc7" => -- R/-: mdspacesize - Total size of data memory space in byte
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32));
 
-- undefined/unavailable --
when others =>
csr_rdata_o <= (others => '0'); -- not implemented
 
end case;
else
csr_rdata_o <= (others => '0');
end if;
end if;
end process csr_read_access;
 
-- time[h] CSR --
systime <= time_i when (CSR_COUNTERS_USE = true) else (others => '0');
 
 
-- RISC-V Counter CSRs --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_counters: process(rstn_i, clk_i)
1510,7 → 1409,7
mcycle_msb <= '0';
minstret_msb <= '0';
elsif rising_edge(clk_i) then
if (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true) then
if (CSR_COUNTERS_USE = true) then
 
-- mcycle (cycle) --
mcycle_msb <= csr.mcycle(csr.mcycle'left);
1523,7 → 1422,7
 
-- mcycleh (cycleh) --
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
csr.mcycleh <= csr_wdata_i;
csr.mcycleh <= csr_wdata_i(19 downto 0);
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
end if;
1533,17 → 1432,24
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
csr.minstret(31 downto 0) <= csr_wdata_i;
csr.minstret(32) <= '0';
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
elsif (execute_engine.state_nxt /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
end if;
 
-- minstreth (instreth) --
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
csr.minstreth <= csr_wdata_i;
csr.minstreth <= csr_wdata_i(19 downto 0);
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
end if;
 
else -- if not implemented
csr.mcycle <= (others => '0');
csr.minstret <= (others => '0');
csr.mcycleh <= (others => '0');
csr.minstreth <= (others => '0');
mcycle_msb <= '0';
minstret_msb <= '0';
end if;
end if;
end process csr_counters;
/core/neorv32_cpu_cp_muldiv.vhd
60,8 → 60,8
 
architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
 
-- constants --
constant all_zero_c : std_ulogic_vector(data_width_c-1 downto 0) := (others => '0');
-- configuration - still experimental --
constant FAST_MUL_EN : boolean := false; -- use DSPs for faster multiplication
 
-- controller --
type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
86,9 → 86,13
 
-- multiplier core --
signal mul_product : std_ulogic_vector(63 downto 0);
signal mul_do_add : std_ulogic_vector(32 downto 0);
signal mul_do_add : std_ulogic_vector(data_width_c downto 0);
signal mul_sign_cycle : std_ulogic;
signal mul_p_sext : std_ulogic;
signal mul_op_x : std_ulogic_vector(32 downto 0);
signal mul_op_y : std_ulogic_vector(32 downto 0);
signal mul_buf_ff0 : std_ulogic_vector(65 downto 0);
signal mul_buf_ff1 : std_ulogic_vector(65 downto 0);
 
begin
 
122,7 → 126,7
end if;
 
when DECODE =>
cnt <= "11111";
--
if (cp_op = cp_op_div_c) then -- result sign compensation for div?
div_res_corr <= opx(opx'left) xor opy(opy'left);
elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
130,15 → 134,22
else
div_res_corr <= '0';
end if;
-- if (cp_op = cp_op_div_c) and (opy = all_zero_c) then -- *divide* by 0?
if (opy = all_zero_c) then -- *divide* by 0?
--
if (or_all_f(opy) = '0') then -- *divide* by 0?
opy_is_zero <= '1';
else
opy_is_zero <= '0';
end if;
--
if (operation = '1') then -- division
cnt <= "11111";
state <= INIT_OPX;
else -- multiplication
if (FAST_MUL_EN = false) then
cnt <= "11111";
else
cnt <= "00101"; -- FIXME
end if;
start <= '1';
state <= PROCESSING;
end if;
182,17 → 193,27
opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
 
 
-- Multiplier Core ------------------------------------------------------------------------
-- Multiplier Core (signed) ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
multiplier_core: process(clk_i)
begin
if rising_edge(clk_i) then
if (start = '1') then -- start new multiplication
mul_product(63 downto 32) <= (others => '0');
mul_product(31 downto 00) <= opy;
elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
mul_product(63 downto 31) <= mul_do_add(32 downto 0);
mul_product(30 downto 00) <= mul_product(31 downto 1);
if (FAST_MUL_EN = false) then -- use small iterative computation
if (start = '1') then -- start new multiplication
mul_product(63 downto 32) <= (others => '0');
mul_product(31 downto 00) <= opy;
elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
mul_product(63 downto 31) <= mul_do_add(32 downto 0);
mul_product(30 downto 00) <= mul_product(31 downto 1);
end if;
else -- use direct approach using (several!) DSP blocks
if (start = '1') then
mul_op_x <= (opx(opx'left) and opx_is_signed) & opx;
mul_op_y <= (opy(opy'left) and opy_is_signed) & opy;
end if;
mul_buf_ff0 <= std_ulogic_vector(signed(mul_op_x) * signed(mul_op_y));
mul_buf_ff1 <= mul_buf_ff0;
mul_product <= mul_buf_ff1(63 downto 0); -- let the register balancing do the magic here
end if;
end if;
end process multiplier_core;
200,13 → 221,14
-- MUL: do another addition --
mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx)
begin
if (mul_product(0) = '1') then
if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB
-- current bit of opy to take care of --
if (mul_product(0) = '1') then -- multiply with 1
if (mul_sign_cycle = '1') then -- for signed operations only: take care of negative weighted MSB -> multiply with -1
mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opx'left) and opx_is_signed) & opx));
else
else -- multiply with +1
mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opx'left) and opx_is_signed) & opx));
end if;
else
else -- multiply with 0
mul_do_add <= mul_p_sext & mul_product(63 downto 32);
end if;
end process mul_update;
216,7 → 238,7
mul_p_sext <= mul_product(mul_product'left) and opx_is_signed;
 
 
-- Divider Core ---------------------------------------------------------------------------
-- Divider Core (unsigned) ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
divider_core: process(clk_i)
begin
/core/neorv32_cpu_regfile.vhd
75,6 → 75,20
-- reading from r0? --
signal rs1_clear, rs2_clear : std_ulogic;
 
 
-- attributes - these are *NOT mandatory*; just for footprint / timing optimization --
-- -------------------------------------------------------------------------------- --
 
-- lattice radiant --
attribute syn_ramstyle : string;
attribute syn_ramstyle of reg_file : signal is "no_rw_check";
attribute syn_ramstyle of reg_file_emb : signal is "no_rw_check";
 
-- intel quartus prime --
attribute ramstyle : string;
attribute ramstyle of reg_file : signal is "no_rw_check";
attribute ramstyle of reg_file_emb : signal is "no_rw_check";
 
begin
 
-- Input mux ------------------------------------------------------------------------------
/core/neorv32_dmem.vhd
71,7 → 71,18
signal dmem_file_hl : dmem_file_t;
signal dmem_file_hh : dmem_file_t;
 
-- RAM attribute to inhibit bypass-logic - Intel only! --
 
-- attributes - these are *NOT mandatory*; just for footprint / timing optimization --
-- -------------------------------------------------------------------------------- --
 
-- lattice radiant --
attribute syn_ramstyle : string;
attribute syn_ramstyle of dmem_file_ll : signal is "no_rw_check";
attribute syn_ramstyle of dmem_file_lh : signal is "no_rw_check";
attribute syn_ramstyle of dmem_file_hl : signal is "no_rw_check";
attribute syn_ramstyle of dmem_file_hh : signal is "no_rw_check";
 
-- intel quartus prime --
attribute ramstyle : string;
attribute ramstyle of dmem_file_ll : signal is "no_rw_check";
attribute ramstyle of dmem_file_lh : signal is "no_rw_check";
/core/neorv32_imem.vhd
112,16 → 112,31
signal imem_file_ram_hl : imem_file8_t;
signal imem_file_ram_hh : imem_file8_t;
 
-- RAM attribute to inhibit bypass-logic - Intel only! --
 
-- attributes - these are *NOT mandatory*; just for footprint / timing optimization --
-- -------------------------------------------------------------------------------- --
 
-- lattice radiant --
attribute syn_ramstyle : string;
attribute syn_ramstyle of imem_file_ram_ll : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_lh : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_hl : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_hh : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_init_ram_ll : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_init_ram_lh : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_init_ram_hl : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_init_ram_hh : signal is "no_rw_check";
 
-- intel quartus prime --
attribute ramstyle : string;
attribute ramstyle of imem_file_ram_ll : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_lh : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_hl : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_hh : signal is "no_rw_check";
attribute ramstyle of imem_file_init_ram_ll : signal is "no_rw_check";
attribute ramstyle of imem_file_init_ram_lh : signal is "no_rw_check";
attribute ramstyle of imem_file_init_ram_hl : signal is "no_rw_check";
attribute ramstyle of imem_file_init_ram_hh : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_ll : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_lh : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_hl : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_hh : signal is "no_rw_check";
 
begin
 
/core/neorv32_package.vhd
41,9 → 41,9
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - FIXED!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000600"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01020005"; -- no touchy!
 
-- Internal Functions ---------------------------------------------------------------------
-- Helper Functions -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function index_size_f(input : natural) return natural;
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
124,15 → 124,19
constant trng_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000");
constant trng_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000004");
 
-- RESERVED --
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed!
--constant ???_size_c : natural := 13*4; -- bytes, fixed!
 
-- Dummy Device (with SIM output) (DEVNULL) --
constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFFC"; -- base address, fixed!
-- Dummy Device (with SIMULATION output) (DEVNULL) --
constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed!
constant devnull_size_c : natural := 1*4; -- bytes, fixed!
constant devnull_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(devnull_base_c) + x"00000000");
 
-- RESERVED --
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC"; -- base address, fixed!
--constant ???_size_c : natural := 5*4; -- bytes, fixed!
 
-- System Information Memory (with SIMULATION output) (SYSINFO) --
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
constant sysinfo_size_c : natural := 8*4; -- bytes, fixed!
 
-- Main Control Bus -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- register file --
161,9 → 165,9
constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (10=CSR, 11=?)
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (1-=CSR)
constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM)
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (10=rs1, 11=?)
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (1-=rs1)
constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
173,22 → 177,24
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
constant ctrl_bus_rd_c : natural := 33; -- read data request
constant ctrl_bus_wr_c : natural := 34; -- write data request
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
constant ctrl_bus_exc_ack_c : natural := 40; -- acknowledge bus exception
constant ctrl_bus_reset_c : natural := 41; -- reset bus unit, terminate all actions
constant ctrl_bus_ierr_ack_c : natural := 40; -- acknowledge instruction fetch bus exception
constant ctrl_bus_derr_ack_c : natural := 41; -- acknowledge data access bus exception
constant ctrl_bus_fence_c : natural := 42; -- executed fence operation
constant ctrl_bus_fencei_c : natural := 43; -- executed fencei operation
-- co-processor --
constant ctrl_cp_use_c : natural := 42; -- is cp operation
constant ctrl_cp_id_lsb_c : natural := 43; -- cp select lsb
constant ctrl_cp_id_msb_c : natural := 44; -- cp select msb
constant ctrl_cp_cmd0_c : natural := 45; -- cp command bit 0
constant ctrl_cp_cmd1_c : natural := 46; -- cp command bit 1
constant ctrl_cp_cmd2_c : natural := 47; -- cp command bit 2
constant ctrl_cp_use_c : natural := 44; -- is cp operation
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select lsb
constant ctrl_cp_id_msb_c : natural := 46; -- cp select msb
constant ctrl_cp_cmd0_c : natural := 47; -- cp command bit 0
constant ctrl_cp_cmd1_c : natural := 48; -- cp command bit 1
constant ctrl_cp_cmd2_c : natural := 49; -- cp command bit 2
-- control bus size --
constant ctrl_width_c : natural := 48; -- control bus size
constant ctrl_width_c : natural := 50; -- control bus size
 
-- ALU Comparator Bus ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
309,6 → 315,21
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
 
-- Trap ID Codes --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant trap_ima_c : std_ulogic_vector(4 downto 0) := "00000"; -- 0.0: instruction misaligned
constant trap_iba_c : std_ulogic_vector(4 downto 0) := "00001"; -- 0.1: instruction access fault
constant trap_iil_c : std_ulogic_vector(4 downto 0) := "00010"; -- 0.2: illegal instruction
constant trap_brk_c : std_ulogic_vector(4 downto 0) := "00011"; -- 0.3: breakpoint
constant trap_lma_c : std_ulogic_vector(4 downto 0) := "00100"; -- 0.4: load address misaligned
constant trap_lbe_c : std_ulogic_vector(4 downto 0) := "00101"; -- 0.5: load access fault
constant trap_sma_c : std_ulogic_vector(4 downto 0) := "00110"; -- 0.6: store address misaligned
constant trap_sbe_c : std_ulogic_vector(4 downto 0) := "00111"; -- 0.7: store access fault
constant trap_env_c : std_ulogic_vector(4 downto 0) := "01011"; -- 0.11: environment call from m-mode
constant trap_msi_c : std_ulogic_vector(4 downto 0) := "10011"; -- 1.3: machine software interrupt
constant trap_mti_c : std_ulogic_vector(4 downto 0) := "10111"; -- 1.7: machine timer interrupt
constant trap_mei_c : std_ulogic_vector(4 downto 0) := "11011"; -- 1.11: machine external interrupt
 
-- CPU Control Exception System -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- exception source bits --
323,8 → 344,8
constant exception_laccess_c : natural := 8; -- load access fault
constant exception_width_c : natural := 9; -- length of this list in bits
-- interrupt source bits --
constant interrupt_mtime_irq_c : natural := 0; -- machine timer interrupt
constant interrupt_msw_irq_c : natural := 1; -- machine sw interrupt
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
constant interrupt_width_c : natural := 3; -- length of this list in bits
 
344,10 → 365,10
component neorv32_top
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
395,6 → 416,9
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- GPIO --
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
422,61 → 446,50
component neorv32_cpu
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- bus interface --
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic; -- bus transfer error
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
-- data bus interface --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- external interrupts --
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
msw_irq_i : in std_ulogic; -- software interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic -- machine timer interrupt
);
end component;
 
485,40 → 498,15
component neorv32_cpu_control
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
-- Memory configuration: External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.?
);
port (
-- global control --
527,7 → 515,8
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-- status input --
alu_wait_i : in std_ulogic; -- wait for ALU
bus_wait_i : in std_ulogic; -- wait for bus
bus_i_wait_i : in std_ulogic; -- wait for bus
bus_d_wait_i : in std_ulogic; -- wait for bus
-- data input --
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
541,6 → 530,7
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
-- external interrupt --
msw_irq_i : in std_ulogic; -- software interrupt
clic_irq_i : in std_ulogic; -- CLIC interrupt request
mtime_irq_i : in std_ulogic; -- machine timer interrupt
-- system time input from MTIME --
552,8 → 542,7
ma_store_i : in std_ulogic; -- misaligned store data address
be_instr_i : in std_ulogic; -- bus error on instruction access
be_load_i : in std_ulogic; -- bus error on load data access
be_store_i : in std_ulogic; -- bus error on store data access
bus_busy_i : in std_ulogic -- bus unit is busy
be_store_i : in std_ulogic -- bus error on store data access
);
end component;
 
635,39 → 624,96
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-- data input --
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
-- data output --
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
-- status --
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
ma_instr_o : out std_ulogic; -- misaligned instruction address
ma_load_o : out std_ulogic; -- misaligned load data address
ma_store_o : out std_ulogic; -- misaligned store data address
be_instr_o : out std_ulogic; -- bus error on instruction access
be_load_o : out std_ulogic; -- bus error on load data access
be_store_o : out std_ulogic; -- bus error on store data
bus_wait_o : out std_ulogic; -- wait for bus operation to finish
bus_busy_o : out std_ulogic; -- bus unit is busy
-- bus system --
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
bus_we_o : out std_ulogic; -- write enable
bus_re_o : out std_ulogic; -- read enable
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
bus_err_i : in std_ulogic -- bus transfer error
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-- cpu instruction fetch interface --
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
i_wait_o : out std_ulogic; -- wait for fetch to complete
--
ma_instr_o : out std_ulogic; -- misaligned instruction address
be_instr_o : out std_ulogic; -- bus error on instruction access
-- cpu data access interface --
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
d_wait_o : out std_ulogic; -- wait for access to complete
--
ma_load_o : out std_ulogic; -- misaligned load data address
ma_store_o : out std_ulogic; -- misaligned store data address
be_load_o : out std_ulogic; -- bus error on load data access
be_store_o : out std_ulogic; -- bus error on store data access
-- instruction bus --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- fence operation
-- data bus --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_fence_o : out std_ulogic -- fence operation
);
end component;
 
-- Component: CPU Bus Switch --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_busswitch
generic (
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
PORT_CB_READ_ONLY : boolean := false -- set if controller port B is read-only
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- controller interface a --
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
ca_bus_we_i : in std_ulogic; -- write enable
ca_bus_re_i : in std_ulogic; -- read enable
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
ca_bus_err_o : out std_ulogic; -- bus transfer error
-- controller interface b --
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
cb_bus_we_i : in std_ulogic; -- write enable
cb_bus_re_i : in std_ulogic; -- read enable
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
cb_bus_err_o : out std_ulogic; -- bus transfer error
-- peripheral bus --
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
p_bus_we_o : out std_ulogic; -- write enable
p_bus_re_o : out std_ulogic; -- read enable
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
p_bus_err_i : in std_ulogic -- bus transfer error
);
end component;
 
-- Component: CPU Compressed Instructions Decompressor ------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_decompressor
989,6 → 1035,49
);
end component;
 
---- Component: System Configuration Information Memory (SYSINFO) ---------------------------
---- -------------------------------------------------------------------------------------------
component neorv32_sysinfo
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
-- Memory configuration: External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
);
end component;
 
end neorv32_package;
 
package body neorv32_package is
/core/neorv32_sysinfo.vhd
0,0 → 1,171
-- #################################################################################################
-- # << NEORV32 - System/Processor Configuration Information Memory (SYSINFO) >> #
-- # ********************************************************************************************* #
-- # This unit provides information regarding the 'system' configuration - mostly derived from the #
-- # top's configuration generics. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_sysinfo is
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
-- Memory configuration: External memory interface --
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
);
end neorv32_sysinfo;
 
architecture neorv32_sysinfo_rtl of neorv32_sysinfo is
 
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(sysinfo_size_c); -- low address boundary bit
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
signal info_addr : std_ulogic_vector(02 downto 0);
 
-- system information ROM --
type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
signal sysinfo_mem : info_mem_t;
 
begin
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0';
rden <= acc_en and rden_i; -- valid read access
addr <= sysinfo_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
info_addr <= addr(index_size_f(sysinfo_size_c)-1 downto 2);
 
 
-- Construct Info ROM ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
 
-- SYSINFO(0): Processor (primary) clock frequency --
sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
 
-- SYSINFO(1): Custom user code --
sysinfo_mem(1) <= USER_CODE;
 
-- SYSINFO(2): Implemented processor devices/features --
-- Memory
sysinfo_mem(2)(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader?
sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface?
sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory?
sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM?
sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory?
-- IO
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)?
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)?
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)?
sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)?
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)?
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)?
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)?
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)?
 
-- SYSINFO(3): reserved --
sysinfo_mem(3) <= (others => '0'); -- reserved - maybe for technology-specific configuration options?
 
-- SYSINFO(4): Base address of instruction memory space --
sysinfo_mem(4) <= MEM_ISPACE_BASE;
 
-- SYSINFO(5): Base address of data memory space --
sysinfo_mem(5) <= MEM_DSPACE_BASE;
 
-- SYSINFO(6): Total size of instruction memory space in bytes --
sysinfo_mem(6) <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32));
 
-- SYSINFO(7): Total size of data memory space in bytes --
sysinfo_mem(7) <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32));
 
 
-- Read Access ----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
read_access: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= rden;
if (rden = '1') then
data_o <= sysinfo_mem(to_integer(unsigned(info_addr)));
else
data_o <= (others => '0');
end if;
end if;
end process read_access;
 
 
end neorv32_sysinfo_rtl;
/core/neorv32_top.vhd
47,10 → 47,10
entity neorv32_top is
generic (
-- General --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
98,6 → 98,9
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
wb_err_i : in std_ulogic := '0'; -- transfer error
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- GPIO (available if IO_GPIO_USE = true) --
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
122,6 → 125,9
 
architecture neorv32_top_rtl of neorv32_top is
 
-- CPU boot address --
constant boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_USE, boot_base_c, MEM_ISPACE_BASE);
 
-- reset generator --
signal rstn_i_sync0 : std_ulogic;
signal rstn_i_sync1 : std_ulogic;
141,8 → 147,8
signal twi_cg_en : std_ulogic;
signal pwm_cg_en : std_ulogic;
 
-- cpu bus --
type cpu_bus_t is record
-- bus interface --
type bus_interface_t is record
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
152,8 → 158,9
cancel : std_ulogic; -- cancel current transfer
ack : std_ulogic; -- bus transfer acknowledge
err : std_ulogic; -- bus transfer error
fence : std_ulogic; -- fence(i) instruction executed
end record;
signal cpu : cpu_bus_t;
signal cpu_i, cpu_d, p_bus : bus_interface_t;
 
-- io space access --
signal io_acc : std_ulogic;
190,6 → 197,8
signal trng_ack : std_ulogic;
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal devnull_ack : std_ulogic;
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
signal sysinfo_ack : std_ulogic;
 
-- IRQs --
signal mtime_irq : std_ulogic;
227,7 → 236,7
end if;
end if;
 
-- memory system - address space --
-- memory system --
if (MEM_INT_IMEM_USE = true) and (MEM_INT_IMEM_SIZE > MEM_ISPACE_SIZE) then
assert false report "NEORV32 CONFIG ERROR! Internal instruction memory (IMEM) cannot be greater than total instruction address space." severity error;
end if;
234,8 → 243,8
if (MEM_INT_DMEM_USE = true) and (MEM_INT_DMEM_SIZE > MEM_DSPACE_SIZE) then
assert false report "NEORV32 CONFIG ERROR! Internal data memory (DMEM) cannot be greater than total data address space." severity error;
end if;
if (MEM_EXT_TIMEOUT <= 1) then
assert false report "NEORV32 CONFIG ERROR! Invalid bus timeout. Internal components require 1 cycle delay." severity error;
if (MEM_EXT_TIMEOUT < 1) then
assert false report "NEORV32 CONFIG ERROR! Invalid bus timeout. Processor-internal components have 1 cycle delay." severity error;
end if;
 
-- clock --
245,7 → 254,7
 
-- CSR system not implemented --
if (CPU_EXTENSION_RISCV_Zicsr = false) then
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine status features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
end if;
-- core local interrupt controller --
if (CPU_EXTENSION_RISCV_Zicsr = false) and (IO_CLIC_USE = true) then
254,10 → 263,10
 
-- memory layout notifier --
if (MEM_ISPACE_BASE /= x"00000000") then
assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the linker script." severity warning;
assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framwork." severity warning;
end if;
if (MEM_DSPACE_BASE /= x"80000000") then
assert false report "NEORV32 CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the linker script." severity warning;
assert false report "NEORV32 CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framwork." severity warning;
end if;
end if;
end process sanity_check;
321,10 → 330,9
neorv32_cpu_inst: neorv32_cpu
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
HART_ID => HART_ID, -- custom hardware thread ID
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID => (others => '0'), -- hardware thread id
CPU_BOOT_ADDR => boot_addr_c, -- cpu boot address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
331,65 → 339,103
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Memory configuration: External memory interface --
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface?
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after which a valid bus access will timeout
-- Processor peripherals --
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)?
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => sys_rstn, -- global reset, low-active, async
-- bus interface --
bus_addr_o => cpu.addr, -- bus access address
bus_rdata_i => cpu.rdata, -- bus read data
bus_wdata_o => cpu.wdata, -- bus write data
bus_ben_o => cpu.ben, -- byte enable
bus_we_o => cpu.we, -- write enable
bus_re_o => cpu.re, -- read enable
bus_cancel_o => cpu.cancel, -- cancel current bus transaction
bus_ack_i => cpu.ack, -- bus transfer acknowledge
bus_err_i => cpu.err, -- bus transfer error
clk_i => clk_i, -- global clock, rising edge
rstn_i => sys_rstn, -- global reset, low-active, async
-- instruction bus interface --
i_bus_addr_o => cpu_i.addr, -- bus access address
i_bus_rdata_i => cpu_i.rdata, -- bus read data
i_bus_wdata_o => cpu_i.wdata, -- bus write data
i_bus_ben_o => cpu_i.ben, -- byte enable
i_bus_we_o => cpu_i.we, -- write enable
i_bus_re_o => cpu_i.re, -- read enable
i_bus_cancel_o => cpu_i.cancel, -- cancel current bus transaction
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge
i_bus_err_i => cpu_i.err, -- bus transfer error
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation
-- data bus interface --
d_bus_addr_o => cpu_d.addr, -- bus access address
d_bus_rdata_i => cpu_d.rdata, -- bus read data
d_bus_wdata_o => cpu_d.wdata, -- bus write data
d_bus_ben_o => cpu_d.ben, -- byte enable
d_bus_we_o => cpu_d.we, -- write enable
d_bus_re_o => cpu_d.re, -- read enable
d_bus_cancel_o => cpu_d.cancel, -- cancel current bus transaction
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
d_bus_err_i => cpu_d.err, -- bus transfer error
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
-- system time input from MTIME --
time_i => mtime_time, -- current system time
time_i => mtime_time, -- current system time
-- external interrupts --
clic_irq_i => clic_irq, -- CLIC interrupt request
mtime_irq_i => mtime_irq -- machine timer interrupt
msw_irq_i => '0', -- software interrupt
clic_irq_i => clic_irq, -- CLIC interrupt request
mtime_irq_i => mtime_irq -- machine timer interrupt
);
 
-- CPU data input --
cpu.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata);
 
-- CPU ACK input --
cpu.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack);
-- CPU Crossbar Switch --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_busswitch_inst: neorv32_busswitch
generic map (
PORT_CA_READ_ONLY => false, -- set if controller port A is read-only
PORT_CB_READ_ONLY => true -- set if controller port B is read-only
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => sys_rstn, -- global reset, low-active, async
-- controller interface a --
ca_bus_addr_i => cpu_d.addr, -- bus access address
ca_bus_rdata_o => cpu_d.rdata, -- bus read data
ca_bus_wdata_i => cpu_d.wdata, -- bus write data
ca_bus_ben_i => cpu_d.ben, -- byte enable
ca_bus_we_i => cpu_d.we, -- write enable
ca_bus_re_i => cpu_d.re, -- read enable
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge
ca_bus_err_o => cpu_d.err, -- bus transfer error
-- controller interface b --
cb_bus_addr_i => cpu_i.addr, -- bus access address
cb_bus_rdata_o => cpu_i.rdata, -- bus read data
cb_bus_wdata_i => cpu_i.wdata, -- bus write data
cb_bus_ben_i => cpu_i.ben, -- byte enable
cb_bus_we_i => cpu_i.we, -- write enable
cb_bus_re_i => cpu_i.re, -- read enable
cb_bus_cancel_i => cpu_i.cancel, -- cancel current bus transaction
cb_bus_ack_o => cpu_i.ack, -- bus transfer acknowledge
cb_bus_err_o => cpu_i.err, -- bus transfer error
-- peripheral bus --
p_bus_addr_o => p_bus.addr, -- bus access address
p_bus_rdata_i => p_bus.rdata, -- bus read data
p_bus_wdata_o => p_bus.wdata, -- bus write data
p_bus_ben_o => p_bus.ben, -- byte enable
p_bus_we_o => p_bus.we, -- write enable
p_bus_re_o => p_bus.re, -- read enable
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
p_bus_err_i => p_bus.err -- bus transfer error
);
 
-- CPU bus error input --
cpu.err <= wishbone_err;
-- advanced memory control --
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
 
-- process bus: CPU data input --
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata or sysinfo_rdata);
 
-- process bus: CPU data ACK input --
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or
spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack or sysinfo_ack);
 
-- process bus: CPU data bus error input --
p_bus.err <= wishbone_err;
 
 
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_int_imem_inst_true:
402,15 → 448,15
BOOTLOADER_USE => BOOTLOADER_USE -- implement and use bootloader?
)
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu.re, -- read enable
wren_i => cpu.we, -- write enable
ben_i => cpu.ben, -- byte write enable
upen_i => '1', -- update enable
addr_i => cpu.addr, -- address
data_i => cpu.wdata, -- data in
data_o => imem_rdata, -- data out
ack_o => imem_ack -- transfer acknowledge
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
upen_i => '1', -- update enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => imem_rdata, -- data out
ack_o => imem_ack -- transfer acknowledge
);
end generate;
 
431,14 → 477,14
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
)
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu.re, -- read enable
wren_i => cpu.we, -- write enable
ben_i => cpu.ben, -- byte write enable
addr_i => cpu.addr, -- address
data_i => cpu.wdata, -- data in
data_o => dmem_rdata, -- data out
ack_o => dmem_ack -- transfer acknowledge
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => dmem_rdata, -- data out
ack_o => dmem_ack -- transfer acknowledge
);
end generate;
 
456,8 → 502,8
neorv32_boot_rom_inst: neorv32_boot_rom
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu.re, -- read enable
addr_i => cpu.addr, -- address
rden_i => p_bus.re, -- read enable
addr_i => p_bus.addr, -- address
data_o => bootrom_rdata, -- data out
ack_o => bootrom_ack -- transfer acknowledge
);
478,15 → 524,15
generic map (
INTERFACE_REG_STAGES => MEM_EXT_REG_STAGES, -- number of interface register stages (0,1,2)
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
-- Memory configuration: Data memory --
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE -- size of processor-internal data memory in bytes
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE -- size of processor-internal data memory in bytes
)
port map (
-- global control --
493,13 → 539,13
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset line, low-active
-- host access --
addr_i => cpu.addr, -- address
rden_i => cpu.re, -- read enable
wren_i => cpu.we, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
addr_i => p_bus.addr, -- address
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => wishbone_rdata, -- data out
cancel_i => cpu.cancel, -- cancel current transaction
cancel_i => p_bus.cancel, -- cancel current transaction
ack_o => wishbone_ack, -- transfer acknowledge
err_o => wishbone_err, -- transfer error
-- wishbone interface --
532,9 → 578,9
 
-- IO Access? -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
io_acc <= '1' when (cpu.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
io_rden <= io_acc and cpu.re;
io_wren <= io_acc and cpu.we;
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
io_rden <= io_acc and p_bus.re;
io_wren <= io_acc and p_bus.we;
 
 
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
544,19 → 590,19
neorv32_gpio_inst: neorv32_gpio
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => gpio_rdata, -- data out
ack_o => gpio_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => gpio_rdata, -- data out
ack_o => gpio_ack, -- transfer acknowledge
-- parallel io --
gpio_o => gpio_o,
gpio_i => gpio_i,
-- interrupt --
irq_o => gpio_irq -- pin-change interrupt
irq_o => gpio_irq -- pin-change interrupt
);
end generate;
 
576,19 → 622,19
neorv32_clic_inst: neorv32_clic
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
addr_i => cpu.addr, -- address
data_i => cpu.wdata, -- data in
data_o => clic_rdata, -- data out
ack_o => clic_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => clic_rdata, -- data out
ack_o => clic_ack, -- transfer acknowledge
-- cpu interrupt --
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ
-- external interrupt lines --
ext_irq_i => clic_xirq, -- IRQ, triggering on HIGH level
ext_ack_o => clic_xack -- acknowledge
ext_irq_i => clic_xirq, -- IRQ, triggering on HIGH level
ext_ack_o => clic_xack -- acknowledge
);
end generate;
 
622,21 → 668,21
neorv32_wdt_inst: neorv32_wdt
port map (
-- host access --
clk_i => clk_i, -- global clock line
rstn_i => ext_rstn, -- global reset line, low-active
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
addr_i => cpu.addr, -- address
data_i => cpu.wdata, -- data in
data_o => wdt_rdata, -- data out
ack_o => wdt_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
rstn_i => ext_rstn, -- global reset line, low-active
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => wdt_rdata, -- data out
ack_o => wdt_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => wdt_cg_en, -- enable clock generator
clkgen_en_o => wdt_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- timeout event --
irq_o => wdt_irq, -- timeout IRQ
rstn_o => wdt_rstn -- timeout reset, low_active, use it as async!
irq_o => wdt_irq, -- timeout IRQ
rstn_o => wdt_rstn -- timeout reset, low_active, use it as async!
);
end generate;
 
657,19 → 703,19
neorv32_mtime_inst: neorv32_mtime
port map (
-- host access --
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset, low-active, async
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => mtime_rdata, -- data out
ack_o => mtime_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
rstn_i => sys_rstn, -- global reset, low-active, async
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => mtime_rdata, -- data out
ack_o => mtime_ack, -- transfer acknowledge
-- time output for CPU --
time_o => mtime_time, -- current system time
time_o => mtime_time, -- current system time
-- interrupt --
irq_o => mtime_irq -- interrupt request
irq_o => mtime_irq -- interrupt request
);
end generate;
 
689,22 → 735,22
neorv32_uart_inst: neorv32_uart
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => uart_rdata, -- data out
ack_o => uart_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => uart_rdata, -- data out
ack_o => uart_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => uart_cg_en, -- enable clock generator
clkgen_en_o => uart_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
-- interrupts --
uart_irq_o => uart_irq -- uart rx/tx interrupt
uart_irq_o => uart_irq -- uart rx/tx interrupt
);
end generate;
 
725,24 → 771,24
neorv32_spi_inst: neorv32_spi
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => spi_rdata, -- data out
ack_o => spi_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => spi_rdata, -- data out
ack_o => spi_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => spi_cg_en, -- enable clock generator
clkgen_en_o => spi_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
spi_sck_o => spi_sck_o, -- SPI serial clock
spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out
spi_csn_o => spi_csn_o, -- SPI CS
spi_sck_o => spi_sck_o, -- SPI serial clock
spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out
spi_csn_o => spi_csn_o, -- SPI CS
-- interrupt --
spi_irq_o => spi_irq -- transmission done interrupt
spi_irq_o => spi_irq -- transmission done interrupt
);
end generate;
 
765,22 → 811,22
neorv32_twi_inst: neorv32_twi
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => twi_rdata, -- data out
ack_o => twi_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => twi_rdata, -- data out
ack_o => twi_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => twi_cg_en, -- enable clock generator
clkgen_en_o => twi_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
twi_sda_io => twi_sda_io, -- serial data line
twi_scl_io => twi_scl_io, -- serial clock line
twi_sda_io => twi_sda_io, -- serial data line
twi_scl_io => twi_scl_io, -- serial clock line
-- interrupt --
twi_irq_o => twi_irq -- transfer done IRQ
twi_irq_o => twi_irq -- transfer done IRQ
);
end generate;
 
802,16 → 848,16
neorv32_pwm_inst: neorv32_pwm
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => pwm_rdata, -- data out
ack_o => pwm_ack, -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => pwm_rdata, -- data out
ack_o => pwm_ack, -- transfer acknowledge
-- clock generator --
clkgen_en_o => pwm_cg_en, -- enable clock generator
clkgen_en_o => pwm_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- pwm output channels --
pwm_o => pwm_o
834,14 → 880,14
neorv32_trng_inst: neorv32_trng
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
data_o => trng_rdata, -- data out
ack_o => trng_ack -- transfer acknowledge
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => trng_rdata, -- data out
ack_o => trng_ack -- transfer acknowledge
);
end generate;
 
860,16 → 906,16
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => cpu.addr, -- address
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- write enable
ben_i => cpu.ben, -- byte write enable
data_i => cpu.wdata, -- data in
ben_i => p_bus.ben, -- byte write enable
data_i => p_bus.wdata, -- data in
data_o => devnull_rdata, -- data out
ack_o => devnull_ack -- transfer acknowledge
);
end generate;
 
neorv32_devnull_inst_false:
if (IO_DEVNULL_USE = false) generate
devnull_rdata <= (others => '0');
877,4 → 923,47
end generate;
 
 
-- System Configuration Information Memory (SYSINFO) --------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_sysinfo_inst: neorv32_sysinfo
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
USER_CODE => USER_CODE, -- custom user code
-- Memory configuration: Instruction memory --
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
-- Memory configuration: Data memory --
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Memory configuration: External memory interface --
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)?
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
data_o => sysinfo_rdata, -- data out
ack_o => sysinfo_ack -- transfer acknowledge
);
 
 
end neorv32_top_rtl;
/top_templates/neorv32_test_setup.vhd
70,9 → 70,9
generic map (
-- General --
CLOCK_FREQUENCY => 100000000, -- clock frequency of clk_i in Hz
HART_ID => x"00000000", -- hardware thread ID
BOOTLOADER_USE => true, -- implement processor-internal bootloader?
CSR_COUNTERS_USE => true, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
USER_CODE => x"00000000", -- custom user code
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C => false, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
120,6 → 120,9
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
wb_err_i => '0', -- transfer error
-- Advanced memory control signals --
fence_o => open, -- indicates an executed FENCE operation
fencei_o => open, -- indicates an executed FENCEI operation
-- GPIO --
gpio_o => gpio_out, -- parallel output
gpio_i => (others => '0'), -- parallel input

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