URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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- This comparison shows the changes necessary to convert path
/neorv32/trunk/rtl
- from Rev 27 to Rev 28
- ↔ Reverse comparison
Rev 27 → Rev 28
/core/neorv32_cpu_bus.vhd
319,20 → 319,19
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1); |
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error? |
if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error |
i_arbiter.rd_req <= '0'; |
end if; |
elsif (i_bus_ack_i = '1') then -- wait for normal termination |
--if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error? |
-- if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error |
-- i_arbiter.rd_req <= '0'; |
-- end if; |
if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort |
i_arbiter.rd_req <= '0'; |
end if; |
end if; |
|
-- cancel bus access -- |
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c); |
end if; |
end process ifetch_arbiter; |
|
-- cancel bus access -- |
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c); |
|
-- wait for bus transaction to finish -- |
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i); |
374,22 → 373,21
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1); |
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error? |
if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
end if; |
elsif (d_bus_ack_i = '1') then -- wait for normal termination |
--if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error? |
-- if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error |
-- d_arbiter.wr_req <= '0'; |
-- d_arbiter.rd_req <= '0'; |
-- end if; |
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
end if; |
end if; |
|
-- cancel bus access -- |
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c); |
end if; |
end process data_access_arbiter; |
|
-- cancel bus access -- |
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c); |
|
-- wait for bus transaction to finish -- |
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i); |
/core/neorv32_cpu_control.vhd
319,6 → 319,7
fetch_engine.i_buf_state_nxt <= (others => '0'); |
ipb.clear <= '1'; -- clear instruction prefetch buffer |
fetch_engine.state_nxt <= IFETCH_0; |
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer |
|
when IFETCH_0 => -- output current PC to bus system, request 32-bit word |
-- ------------------------------------------------------------ |
331,7 → 332,6
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info |
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf; |
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1'; |
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them |
if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled? |
fetch_engine.state_nxt <= IFETCH_2; |
else |
342,6 → 342,7
|
when IFETCH_2 => -- construct instruction word and issue |
-- ------------------------------------------------------------ |
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer |
if (fetch_engine.pc(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned |
fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00); |
|
/core/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040309"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040400"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
|
-- Architecture Configuration ------------------------------------------------------------- |