OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/rtl
    from Rev 68 to Rev 69
    ↔ Reverse comparison
  •

Rev 68 → Rev 69

/core/neorv32_bootloader_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for BOOTLOADER) from source file <bootloader/main.bin>
-- Size: 4068 bytes
-- Size: 4040 bytes
 
library ieee;
use ieee.std_logic_1164.all;
51,7 → 51,7
00000037 => x"00158593",
00000038 => x"ff5ff06f",
00000039 => x"00001597",
00000040 => x"f4858593",
00000040 => x"f2c58593",
00000041 => x"80010617",
00000042 => x"f5c60613",
00000043 => x"80010697",
105,929 → 105,922
00000091 => x"0007a023",
00000092 => x"8001a223",
00000093 => x"ffff07b7",
00000094 => x"4c478793",
00000094 => x"4ac78793",
00000095 => x"30579073",
00000096 => x"00000693",
00000097 => x"00000613",
00000098 => x"00000593",
00000099 => x"00200513",
00000100 => x"385000ef",
00000101 => x"419000ef",
00000100 => x"369000ef",
00000101 => x"3fd000ef",
00000102 => x"00048493",
00000103 => x"00050863",
00000104 => x"00100513",
00000105 => x"00000593",
00000106 => x"445000ef",
00000106 => x"429000ef",
00000107 => x"00005537",
00000108 => x"00000613",
00000109 => x"00000593",
00000110 => x"b0050513",
00000111 => x"1f5000ef",
00000112 => x"1b9000ef",
00000113 => x"02050a63",
00000114 => x"321000ef",
00000111 => x"1d9000ef",
00000112 => x"19d000ef",
00000113 => x"02050663",
00000114 => x"305000ef",
00000115 => x"fe002783",
00000116 => x"0027d793",
00000117 => x"00a78533",
00000118 => x"00f537b3",
00000119 => x"00b785b3",
00000120 => x"1a9000ef",
00000120 => x"18d000ef",
00000121 => x"08000793",
00000122 => x"30479073",
00000123 => x"30046073",
00000124 => x"00000013",
00000125 => x"00000013",
00000126 => x"ffff1537",
00000127 => x"f1450513",
00000128 => x"291000ef",
00000129 => x"f1302573",
00000130 => x"24c000ef",
00000131 => x"ffff1537",
00000132 => x"f4c50513",
00000133 => x"27d000ef",
00000134 => x"fe002503",
00000135 => x"238000ef",
00000136 => x"ffff1537",
00000137 => x"f5450513",
00000138 => x"269000ef",
00000139 => x"30102573",
00000140 => x"224000ef",
00000141 => x"ffff1537",
00000142 => x"f5c50513",
00000143 => x"255000ef",
00000144 => x"fe402503",
00000145 => x"ffff1437",
00000146 => x"20c000ef",
00000147 => x"ffff1537",
00000148 => x"f6450513",
00000149 => x"23d000ef",
00000150 => x"fe802503",
00000151 => x"1f8000ef",
00000152 => x"ffff1537",
00000153 => x"f6c50513",
00000154 => x"229000ef",
00000155 => x"ff802503",
00000156 => x"1e4000ef",
00000157 => x"f7440513",
00000158 => x"219000ef",
00000159 => x"ff002503",
00000160 => x"1d4000ef",
00000161 => x"ffff1537",
00000162 => x"f8050513",
00000163 => x"205000ef",
00000164 => x"ffc02503",
00000165 => x"1c0000ef",
00000166 => x"f7440513",
00000167 => x"1f5000ef",
00000168 => x"ff402503",
00000169 => x"1b0000ef",
00000170 => x"0d1000ef",
00000171 => x"06050663",
00000172 => x"ffff1537",
00000173 => x"f8850513",
00000174 => x"1d9000ef",
00000175 => x"22d000ef",
00000176 => x"fe002403",
00000177 => x"00341413",
00000178 => x"00a40933",
00000179 => x"00893433",
00000180 => x"00b40433",
00000181 => x"0cd000ef",
00000182 => x"02051663",
00000183 => x"20d000ef",
00000184 => x"fe85eae3",
00000185 => x"00b41463",
00000186 => x"ff2566e3",
00000187 => x"00100513",
00000188 => x"4dc000ef",
00000189 => x"ffff1537",
00000190 => x"fb050513",
00000191 => x"195000ef",
00000192 => x"0d4000ef",
00000193 => x"181000ef",
00000194 => x"fc050ae3",
00000195 => x"ffff1537",
00000196 => x"fb450513",
00000197 => x"17d000ef",
00000198 => x"0b0000ef",
00000199 => x"ffff19b7",
00000200 => x"ffff1a37",
00000201 => x"07200a93",
00000202 => x"06800b13",
00000203 => x"07500b93",
00000204 => x"07300c13",
00000205 => x"ffff1937",
00000206 => x"ffff1cb7",
00000207 => x"fc098513",
00000208 => x"151000ef",
00000209 => x"131000ef",
00000210 => x"00050413",
00000211 => x"0f5000ef",
00000212 => x"fb0a0513",
00000213 => x"13d000ef",
00000214 => x"101000ef",
00000215 => x"fe051ee3",
00000216 => x"01541863",
00000217 => x"ffff02b7",
00000218 => x"00028067",
00000219 => x"fd1ff06f",
00000220 => x"01641663",
00000221 => x"054000ef",
00000222 => x"fc5ff06f",
00000223 => x"01741663",
00000224 => x"44c000ef",
00000225 => x"fb9ff06f",
00000226 => x"01841663",
00000227 => x"670000ef",
00000228 => x"fadff06f",
00000229 => x"06c00793",
00000230 => x"00f41663",
00000231 => x"00100513",
00000232 => x"fe1ff06f",
00000233 => x"06500793",
00000234 => x"00f41c63",
00000235 => x"0004a783",
00000236 => x"f40798e3",
00000237 => x"ebcc8513",
00000238 => x"0d9000ef",
00000239 => x"f81ff06f",
00000240 => x"fc890513",
00000241 => x"ff5ff06f",
00000242 => x"ffff1537",
00000243 => x"dfc50513",
00000244 => x"0c10006f",
00000245 => x"ff010113",
00000246 => x"00112623",
00000247 => x"30047073",
00000248 => x"00000013",
00000249 => x"00000013",
00000250 => x"ffff1537",
00000251 => x"e6050513",
00000252 => x"0a1000ef",
00000253 => x"065000ef",
00000254 => x"fe051ee3",
00000255 => x"ff002783",
00000256 => x"00078067",
00000257 => x"0000006f",
00000258 => x"ff010113",
00000259 => x"00812423",
00000260 => x"00050413",
00000261 => x"ffff1537",
00000262 => x"e7050513",
00000263 => x"00112623",
00000264 => x"071000ef",
00000265 => x"03040513",
00000266 => x"0ff57513",
00000267 => x"015000ef",
00000268 => x"30047073",
00000269 => x"00000013",
00000270 => x"00000013",
00000271 => x"171000ef",
00000272 => x"00050863",
00000273 => x"00100513",
00000274 => x"00000593",
00000275 => x"1a1000ef",
00000276 => x"0000006f",
00000277 => x"fe010113",
00000278 => x"01212823",
00000279 => x"00050913",
00000280 => x"ffff1537",
00000281 => x"00912a23",
00000282 => x"e7c50513",
00000283 => x"ffff14b7",
00000284 => x"00812c23",
00000285 => x"01312623",
00000286 => x"00112e23",
00000287 => x"01c00413",
00000288 => x"011000ef",
00000289 => x"fd448493",
00000290 => x"ffc00993",
00000291 => x"008957b3",
00000292 => x"00f7f793",
00000293 => x"00f487b3",
00000294 => x"0007c503",
00000295 => x"ffc40413",
00000296 => x"7a0000ef",
00000297 => x"ff3414e3",
00000298 => x"01c12083",
00000299 => x"01812403",
00000300 => x"01412483",
00000301 => x"01012903",
00000302 => x"00c12983",
00000303 => x"02010113",
00000304 => x"00008067",
00000305 => x"fb010113",
00000306 => x"04112623",
00000307 => x"04512423",
00000308 => x"04612223",
00000309 => x"04712023",
00000310 => x"02812e23",
00000311 => x"02912c23",
00000312 => x"02a12a23",
00000313 => x"02b12823",
00000314 => x"02c12623",
00000315 => x"02d12423",
00000316 => x"02e12223",
00000317 => x"02f12023",
00000318 => x"01012e23",
00000319 => x"01112c23",
00000320 => x"01c12a23",
00000321 => x"01d12823",
00000322 => x"01e12623",
00000323 => x"01f12423",
00000324 => x"342024f3",
00000325 => x"800007b7",
00000326 => x"00778793",
00000327 => x"08f49463",
00000328 => x"08d000ef",
00000329 => x"00050663",
00000330 => x"00000513",
00000331 => x"091000ef",
00000332 => x"648000ef",
00000333 => x"02050063",
00000334 => x"7b0000ef",
00000335 => x"fe002783",
00000336 => x"0027d793",
00000337 => x"00a78533",
00000338 => x"00f537b3",
00000339 => x"00b785b3",
00000340 => x"638000ef",
00000341 => x"03c12403",
00000342 => x"04c12083",
00000343 => x"04812283",
00000344 => x"04412303",
00000345 => x"04012383",
00000346 => x"03812483",
00000347 => x"03412503",
00000348 => x"03012583",
00000349 => x"02c12603",
00000350 => x"02812683",
00000351 => x"02412703",
00000352 => x"02012783",
00000353 => x"01c12803",
00000354 => x"01812883",
00000355 => x"01412e03",
00000356 => x"01012e83",
00000357 => x"00c12f03",
00000358 => x"00812f83",
00000359 => x"05010113",
00000360 => x"30200073",
00000361 => x"00700793",
00000362 => x"00f49a63",
00000363 => x"8041a783",
00000364 => x"00078663",
00000365 => x"00100513",
00000366 => x"e51ff0ef",
00000367 => x"34102473",
00000368 => x"5e0000ef",
00000369 => x"04050263",
00000370 => x"ffff1537",
00000371 => x"e8050513",
00000372 => x"6c0000ef",
00000373 => x"00048513",
00000374 => x"e7dff0ef",
00000375 => x"02000513",
00000376 => x"660000ef",
00000377 => x"00040513",
00000378 => x"e6dff0ef",
00000379 => x"02000513",
00000380 => x"650000ef",
00000381 => x"34302573",
00000382 => x"e5dff0ef",
00000383 => x"ffff1537",
00000384 => x"e8850513",
00000385 => x"68c000ef",
00000386 => x"00440413",
00000387 => x"34141073",
00000388 => x"f45ff06f",
00000389 => x"ff010113",
00000124 => x"ffff1537",
00000125 => x"ef850513",
00000126 => x"27d000ef",
00000127 => x"f1302573",
00000128 => x"23c000ef",
00000129 => x"ffff1537",
00000130 => x"f3050513",
00000131 => x"269000ef",
00000132 => x"fe002503",
00000133 => x"228000ef",
00000134 => x"ffff1537",
00000135 => x"f3850513",
00000136 => x"255000ef",
00000137 => x"30102573",
00000138 => x"214000ef",
00000139 => x"ffff1537",
00000140 => x"f4050513",
00000141 => x"241000ef",
00000142 => x"fe402503",
00000143 => x"ffff1437",
00000144 => x"1fc000ef",
00000145 => x"ffff1537",
00000146 => x"f4850513",
00000147 => x"229000ef",
00000148 => x"fe802503",
00000149 => x"1e8000ef",
00000150 => x"ffff1537",
00000151 => x"f5050513",
00000152 => x"215000ef",
00000153 => x"ff802503",
00000154 => x"1d4000ef",
00000155 => x"f5840513",
00000156 => x"205000ef",
00000157 => x"ff002503",
00000158 => x"1c4000ef",
00000159 => x"ffff1537",
00000160 => x"f6450513",
00000161 => x"1f1000ef",
00000162 => x"ffc02503",
00000163 => x"1b0000ef",
00000164 => x"f5840513",
00000165 => x"1e1000ef",
00000166 => x"ff402503",
00000167 => x"1a0000ef",
00000168 => x"0bd000ef",
00000169 => x"06050663",
00000170 => x"ffff1537",
00000171 => x"f6c50513",
00000172 => x"1c5000ef",
00000173 => x"219000ef",
00000174 => x"fe002403",
00000175 => x"00341413",
00000176 => x"00a40933",
00000177 => x"00893433",
00000178 => x"00b40433",
00000179 => x"0b9000ef",
00000180 => x"02051663",
00000181 => x"1f9000ef",
00000182 => x"fe85eae3",
00000183 => x"00b41463",
00000184 => x"ff2566e3",
00000185 => x"00100513",
00000186 => x"4c8000ef",
00000187 => x"ffff1537",
00000188 => x"f9450513",
00000189 => x"181000ef",
00000190 => x"0d4000ef",
00000191 => x"16d000ef",
00000192 => x"fc050ae3",
00000193 => x"ffff1537",
00000194 => x"f9850513",
00000195 => x"169000ef",
00000196 => x"0b0000ef",
00000197 => x"ffff19b7",
00000198 => x"ffff1a37",
00000199 => x"07200a93",
00000200 => x"06800b13",
00000201 => x"07500b93",
00000202 => x"07300c13",
00000203 => x"ffff1937",
00000204 => x"ffff1cb7",
00000205 => x"fa498513",
00000206 => x"13d000ef",
00000207 => x"11d000ef",
00000208 => x"00050413",
00000209 => x"0e1000ef",
00000210 => x"f94a0513",
00000211 => x"129000ef",
00000212 => x"0ed000ef",
00000213 => x"fe051ee3",
00000214 => x"01541863",
00000215 => x"ffff02b7",
00000216 => x"00028067",
00000217 => x"fd1ff06f",
00000218 => x"01641663",
00000219 => x"054000ef",
00000220 => x"fc5ff06f",
00000221 => x"01741663",
00000222 => x"438000ef",
00000223 => x"fb9ff06f",
00000224 => x"01841663",
00000225 => x"65c000ef",
00000226 => x"fadff06f",
00000227 => x"06c00793",
00000228 => x"00f41663",
00000229 => x"00100513",
00000230 => x"fe1ff06f",
00000231 => x"06500793",
00000232 => x"00f41c63",
00000233 => x"0004a783",
00000234 => x"f40798e3",
00000235 => x"ea0c8513",
00000236 => x"0c5000ef",
00000237 => x"f81ff06f",
00000238 => x"fac90513",
00000239 => x"ff5ff06f",
00000240 => x"ffff1537",
00000241 => x"de050513",
00000242 => x"0ad0006f",
00000243 => x"ff010113",
00000244 => x"00112623",
00000245 => x"30047073",
00000246 => x"ffff1537",
00000247 => x"e4450513",
00000248 => x"095000ef",
00000249 => x"059000ef",
00000250 => x"fe051ee3",
00000251 => x"ff002783",
00000252 => x"00078067",
00000253 => x"0000006f",
00000254 => x"ff010113",
00000255 => x"00812423",
00000256 => x"00050413",
00000257 => x"ffff1537",
00000258 => x"e5450513",
00000259 => x"00112623",
00000260 => x"065000ef",
00000261 => x"03040513",
00000262 => x"0ff57513",
00000263 => x"009000ef",
00000264 => x"30047073",
00000265 => x"16d000ef",
00000266 => x"00050863",
00000267 => x"00100513",
00000268 => x"00000593",
00000269 => x"19d000ef",
00000270 => x"0000006f",
00000271 => x"fe010113",
00000272 => x"01212823",
00000273 => x"00050913",
00000274 => x"ffff1537",
00000275 => x"00912a23",
00000276 => x"e6050513",
00000277 => x"ffff14b7",
00000278 => x"00812c23",
00000279 => x"01312623",
00000280 => x"00112e23",
00000281 => x"01c00413",
00000282 => x"00d000ef",
00000283 => x"fb848493",
00000284 => x"ffc00993",
00000285 => x"008957b3",
00000286 => x"00f7f793",
00000287 => x"00f487b3",
00000288 => x"0007c503",
00000289 => x"ffc40413",
00000290 => x"79c000ef",
00000291 => x"ff3414e3",
00000292 => x"01c12083",
00000293 => x"01812403",
00000294 => x"01412483",
00000295 => x"01012903",
00000296 => x"00c12983",
00000297 => x"02010113",
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00000304 => x"02812e23",
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00000317 => x"01f12423",
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00000320 => x"00778793",
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00000325 => x"08d000ef",
00000326 => x"644000ef",
00000327 => x"02050063",
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00001005 => x"00444d43",
00001006 => x"33323130",
00001007 => x"37363534",
00001008 => x"62613938",
00001009 => x"66656463"
);
 
end neorv32_bootloader_image;
/core/neorv32_bus_keeper.vhd
87,7 → 87,7
-- controller --
type control_t is record
pending : std_ulogic;
timeout : std_ulogic_vector(index_size_f(max_proc_int_response_time_c)-1 downto 0);
timeout : std_ulogic_vector(index_size_f(max_proc_int_response_time_c) downto 0);
err_type : std_ulogic;
bus_err : std_ulogic;
end record;
148,7 → 148,7
 
-- access monitor: IDLE --
if (control.pending = '0') then
control.timeout <= std_ulogic_vector(to_unsigned(max_proc_int_response_time_c, index_size_f(max_proc_int_response_time_c)));
control.timeout <= std_ulogic_vector(to_unsigned(max_proc_int_response_time_c, index_size_f(max_proc_int_response_time_c)+1));
if (bus_rden_i = '1') or (bus_wren_i = '1') then
control.pending <= '1';
end if;
/core/neorv32_cfs.vhd
174,10 → 174,10
-- Interrupt ------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1.
-- The interrupt is high-level-active. When set, the interrupt appears as "pending" in the CPU's mie register
-- ready to trigger execution of the according interrupt handler.
-- Once set, the irq_o signal **has to stay set** until explicitly acknowledged by the CPU
-- (for example by reading/writing from/to a specific CFS interface register address).
-- The interrupt is triggered by a one-shot rising edge. After triggering, the interrupt appears as "pending" in the CPU's mie register
-- ready to trigger execution of the according interrupt handler. The interrupt request signal should be triggered
-- whenever an interrupt condition is fulfilled. It is the task of the application to programmer to enable/clear the CFS interrupt
-- using the CPU's mie and mip registers when reuqired.
 
irq_o <= '0'; -- not used for this minimal example
 
/core/neorv32_cpu.vhd
94,6 → 94,7
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
debug_o : out std_ulogic; -- cpu is in debug mode when set
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
316,7 → 317,10
-- CPU is sleeping? --
sleep_o <= ctrl(ctrl_sleep_c); -- set when CPU is sleeping (after WFI)
 
-- CPU is in debug mode? --
debug_o <= ctrl(ctrl_debug_running_c);
 
 
-- Register File --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_regfile_inst: neorv32_cpu_regfile
/core/neorv32_cpu_control.vhd
287,6 → 287,8
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
mie_firqe : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
--
mip_clr : std_ulogic_vector(15 downto 0); -- clear pending FIRQ
--
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
392,7 → 394,7
elsif rising_edge(clk_i) then
fetch_engine.state <= fetch_engine.state_nxt;
fetch_engine.state_prev <= fetch_engine.state;
fetch_engine.restart <= fetch_engine.restart_nxt;
fetch_engine.restart <= fetch_engine.restart_nxt or fetch_engine.reset;
if (fetch_engine.restart = '1') then
fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
else
414,9 → 416,9
fetch_engine.state_nxt <= fetch_engine.state;
fetch_engine.pc_nxt <= fetch_engine.pc;
fetch_engine.bus_err_ack <= '0';
fetch_engine.restart_nxt <= fetch_engine.restart or fetch_engine.reset;
fetch_engine.restart_nxt <= fetch_engine.restart;
 
-- instruction prefetch buffer interface --
-- instruction prefetch buffer defaults --
ipb.we <= '0';
ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
ipb.clear <= fetch_engine.restart;
430,20 → 432,16
bus_fast_ir <= '1'; -- fast instruction fetch request
fetch_engine.state_nxt <= IFETCH_ISSUE;
end if;
if (fetch_engine.restart = '1') then -- reset request?
fetch_engine.restart_nxt <= '0';
end if;
fetch_engine.restart_nxt <= '0';
 
when IFETCH_ISSUE => -- store instruction data to prefetch buffer
-- ------------------------------------------------------------
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
if (fetch_engine.restart = '1') then -- reset request?
fetch_engine.restart_nxt <= '0';
end if;
fetch_engine.state_nxt <= IFETCH_REQUEST;
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
fetch_engine.restart_nxt <= '0';
fetch_engine.state_nxt <= IFETCH_REQUEST;
end if;
 
when others => -- undefined
504,7 → 502,7
issue_engine.align <= '1'; -- aligned on 16-bit boundary
else
issue_engine.state <= issue_engine.state_nxt;
issue_engine.align <= '0'; -- always aligned on 32-bit boundaries
issue_engine.align <= '0'; -- aligned on 32-bit boundary
end if;
else
issue_engine.state <= issue_engine.state_nxt;
541,14 → 539,13
 
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
ipb.re <= '1';
cmd_issue.valid <= '1';
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"
ipb.re <= '1';
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
else -- compressed
ipb.re <= '1';
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
issue_engine.align_nxt <= '1';
end if;
end if;
558,11 → 555,11
cmd_issue.valid <= '1';
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"
ipb.re <= '1';
ipb.re <= '1';
cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
else -- compressed
-- do not read from ipb here!
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
issue_engine.align_nxt <= '0';
end if;
end if;
573,7 → 570,7
-- ------------------------------------------------------------
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
if (ipb.avail = '1') then -- instructions available?
ipb.re <= '1';
ipb.re <= '1';
issue_engine.state_nxt <= ISSUE_ACTIVE;
end if;
 
787,7 → 784,7
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
-- fast bus access requests --
-- instruction fetch request --
ctrl_o(ctrl_bus_if_c) <= bus_fast_ir;
-- bus error control --
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack; -- instruction fetch bus access error ACK
1040,14 → 1037,13
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_and_c;
end case;
 
-- Check if single-cycle or multi-cycle (co-processor) operation --
-- co-processor MULDIV operation? --
-- co-processor MULDIV operation (multi-cycle)? --
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
execute_engine.state_nxt <= ALU_WAIT;
-- co-processor BIT-MANIPULATION operation? --
-- co-processor BIT-MANIPULATION operation (multi-cycle)? --
elsif (CPU_EXTENSION_RISCV_B = true) and
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- register operation
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation
1054,13 → 1050,13
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
execute_engine.state_nxt <= ALU_WAIT;
-- co-processor SHIFT operation? --
-- co-processor SHIFT operation (multi-cycle)? --
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- use SHIFTER CP (only relevant for shift operations)
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
execute_engine.state_nxt <= ALU_WAIT;
-- ALU core operations (single-cycle) --
-- ALU CORE operation (single-cycle) --
else
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_core_c;
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
1152,7 → 1148,7
when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ECALL
when funct12_ebreak_c => trap_ctrl.break_point <= '1'; -- EBREAK
when funct12_mret_c => execute_engine.state_nxt <= TRAP_EXIT; -- MRET
when funct12_dret_c => -- DRET
when funct12_dret_c => -- DRET
if (CPU_EXTENSION_RISCV_DEBUG = true) then
execute_engine.state_nxt <= TRAP_EXIT;
debug_ctrl.dret <= '1';
1177,7 → 1173,7
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then -- CSRRW(I)
csr.we_nxt <= '1'; -- always write CSR
else -- CSRRS(I) / CSRRC(I) [invalid CSR instruction are already checked by the illegal instruction logic]
else -- CSRRS(I) / CSRRC(I) [invalid CSR instructions are already checked by the illegal instruction logic]
csr.we_nxt <= not decode_aux.rs1_zero; -- write CSR if rs1/imm is not zero
end if;
-- register file write back --
1294,7 → 1290,7
-- machine trap setup/handling & counters --
when csr_mstatus_c | csr_mstatush_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mip_c | csr_mtval_c |
csr_mcycle_c | csr_mcycleh_c | csr_minstret_c | csr_minstreth_c | csr_mcountinhibit_c =>
-- NOTE: MISA, MIP and MTVAL are read-only in the NEORV32 but we do not cause an exception here for compatibility.
-- NOTE: MISA and MTVAL are read-only in the NEORV32 but we do not cause an exception here for compatibility.
-- Machine-level code should read-back those CSRs after writing them to realize they are read-only.
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
 
1632,8 → 1628,8
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and mext_irq_i;
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and mtime_irq_i;
 
-- interrupt buffer: NEORV32-specific fast interrupts (FIRQ) --
trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) <= csr.mie_firqe(15 downto 0) and firq_i(15 downto 0);
-- interrupt queue: NEORV32-specific fast interrupts (FIRQ) --
trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) <= (trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) or (csr.mie_firqe and firq_i)) and (not csr.mip_clr);
 
-- trap environment control --
if (trap_ctrl.env_start = '0') then -- no started trap handler
1722,7 → 1718,7
 
 
-- ----------------------------------------------------------------------------------------
-- (re-)enter debug mode requests; basically, these are standard traps that have some
-- (re-)enter debug mode requests: basically, these are standard traps that have some
-- special handling - they have the highest INTERRUPT priority in order to go to debug when requested
-- even if other IRQs are pending right now
-- ----------------------------------------------------------------------------------------
1878,6 → 1874,7
csr.mepc <= (others => def_rst_val_c);
csr.mcause <= (others => def_rst_val_c);
csr.mtval <= (others => def_rst_val_c);
csr.mip_clr <= (others => def_rst_val_c);
--
csr.pmpcfg <= (others => (others => '0'));
csr.pmpaddr <= (others => (others => def_rst_val_c));
1907,6 → 1904,9
-- write access? --
csr.we <= csr.we_nxt;
 
-- defaults --
csr.mip_clr <= (others => '0');
 
if (CPU_EXTENSION_RISCV_Zicsr = true) then
-- --------------------------------------------------------------------------------
-- CSR access by application software
1965,20 → 1965,24
 
-- machine trap handling --
-- --------------------------------------------------------------------
if (csr.addr(11 downto 3) = csr_class_trap_c) then -- machine trap handling CSR class
if (csr.addr(11 downto 4) = csr_class_trap_c) then -- machine trap handling CSR class
-- R/W: mscratch - machine scratch register --
if (csr.addr(2 downto 0) = csr_mscratch_c(2 downto 0)) then
if (csr.addr(3 downto 0) = csr_mscratch_c(3 downto 0)) then
csr.mscratch <= csr.wdata;
end if;
-- R/W: mepc - machine exception program counter --
if (csr.addr(2 downto 0) = csr_mepc_c(2 downto 0)) then
if (csr.addr(3 downto 0) = csr_mepc_c(3 downto 0)) then
csr.mepc <= csr.wdata;
end if;
-- R/W: mcause - machine trap cause --
if (csr.addr(2 downto 0) = csr_mcause_c(2 downto 0)) then
if (csr.addr(3 downto 0) = csr_mcause_c(3 downto 0)) then
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: async/interrupt, 0: sync/exception
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
end if;
-- R/W: mip - machine interrupt pending --
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
csr.mip_clr <= csr.wdata(31 downto 16);
end if;
end if;
 
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
2491,7 → 2495,7
csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0);
when csr_mtval_c => -- mtval (r/-): machine bad address or instruction
csr.rdata <= csr.mtval;
when csr_mip_c => -- mip (r/-): machine interrupt pending
when csr_mip_c => -- mip (r/w): machine interrupt pending
csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
/core/neorv32_cpu_cp_muldiv.vhd
79,7 → 79,7
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
 
-- controller --
type state_t is (IDLE, DIV_PREPROCESS, PROCESSING, FINALIZE, COMPLETED);
type state_t is (IDLE, DIV_PREPROCESS, PROCESSING, FINALIZE);
signal state : state_t;
signal cnt : std_ulogic_vector(4 downto 0);
signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
87,13 → 87,12
signal start_div : std_ulogic;
signal start_mul : std_ulogic;
signal operation : std_ulogic;
signal div_opx : std_ulogic_vector(data_width_c-1 downto 0);
signal div_opy : std_ulogic_vector(data_width_c-1 downto 0);
signal rs1_is_signed : std_ulogic;
signal rs2_is_signed : std_ulogic;
signal opy_is_zero : std_ulogic;
signal div_res_corr : std_ulogic;
signal valid : std_ulogic;
signal out_en : std_ulogic;
 
-- divider core --
signal remainder : std_ulogic_vector(data_width_c-1 downto 0);
110,7 → 109,6
signal mul_p_sext : std_ulogic;
signal mul_op_x : signed(32 downto 0); -- for using DSPs
signal mul_op_y : signed(32 downto 0); -- for using DSPs
signal mul_buf_ff : signed(65 downto 0); -- for using DSPs
 
begin
 
120,31 → 118,34
begin
if (rstn_i = '0') then
state <= IDLE;
div_opx <= (others => def_rst_val_c);
div_opy <= (others => def_rst_val_c);
cnt <= (others => def_rst_val_c);
cp_op_ff <= (others => def_rst_val_c);
start_div <= '0';
valid <= '0';
out_en <= '0';
valid_o <= '0';
div_res_corr <= def_rst_val_c;
opy_is_zero <= def_rst_val_c;
elsif rising_edge(clk_i) then
-- defaults --
start_div <= '0';
valid <= '0';
out_en <= '0';
valid_o <= '0';
 
-- FSM --
case state is
 
when IDLE =>
cp_op_ff <= cp_op;
cnt <= "11110";
if (start_i = '1') then
if (operation = '1') and (DIVISION_EN = true) then -- division
cnt <= "11111";
state <= DIV_PREPROCESS;
else
cnt <= "11110";
start_div <= '1';
state <= DIV_PREPROCESS;
else -- multiplication
if (FAST_MUL_EN = true) then
state <= FINALIZE;
valid_o <= '1';
state <= FINALIZE;
else
state <= PROCESSING;
end if;
152,47 → 153,37
end if;
 
when DIV_PREPROCESS =>
if (DIVISION_EN = true) then
-- check rlevatn input signs --
if (cp_op = cp_op_div_c) then -- result sign compensation for div?
div_res_corr <= rs1_i(rs1_i'left) xor rs2_i(rs2_i'left);
elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
div_res_corr <= rs1_i(rs1_i'left);
else
div_res_corr <= '0';
end if;
-- divide by zero? --
opy_is_zero <= not or_reduce_f(rs2_i); -- set if rs2 = 0
-- abs(rs1) --
if ((rs1_i(rs1_i'left) and rs1_is_signed) = '1') then -- signed division?
div_opx <= std_ulogic_vector(0 - unsigned(rs1_i)); -- make positive
else
div_opx <= rs1_i;
end if;
-- abs(rs2) --
if ((rs2_i(rs2_i'left) and rs2_is_signed) = '1') then -- signed division?
div_opy <= std_ulogic_vector(0 - unsigned(rs2_i)); -- make positive
else
div_opy <= rs2_i;
end if;
--
start_div <= '1';
state <= PROCESSING;
-- check relevant input signs --
if (cp_op = cp_op_div_c) then -- result sign compensation for div?
div_res_corr <= rs1_i(rs1_i'left) xor rs2_i(rs2_i'left);
elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
div_res_corr <= rs1_i(rs1_i'left);
else
state <= IDLE;
div_res_corr <= '0';
end if;
-- divide by zero? --
opy_is_zero <= not or_reduce_f(rs2_i); -- set if rs2 = 0
-- abs(rs2) --
if ((rs2_i(rs2_i'left) and rs2_is_signed) = '1') then -- signed division?
div_opy <= std_ulogic_vector(0 - unsigned(rs2_i)); -- make positive
else
div_opy <= rs2_i;
end if;
--
state <= PROCESSING;
 
when PROCESSING =>
cnt <= std_ulogic_vector(unsigned(cnt) - 1);
if (cnt = "00000") then
state <= FINALIZE;
valid_o <= '1';
state <= FINALIZE;
end if;
 
when FINALIZE =>
state <= COMPLETED;
out_en <= '1';
state <= IDLE;
 
when COMPLETED =>
valid <= '1';
when others =>
state <= IDLE;
end case;
end if;
235,10 → 226,11
end process multiplier_core;
end generate;
 
-- parallel multiplication --
-- parallel multiplication (using DSP blocks) --
multiplier_core_dsp:
if (FAST_MUL_EN = true) generate
multiplier_core: process(clk_i)
variable tmp_v : signed(65 downto 0);
begin
if rising_edge(clk_i) then
if (start_mul = '1') then
245,8 → 237,10
mul_op_x <= signed((rs1_i(rs1_i'left) and rs1_is_signed) & rs1_i);
mul_op_y <= signed((rs2_i(rs2_i'left) and rs2_is_signed) & rs2_i);
end if;
mul_buf_ff <= mul_op_x * mul_op_y;
mul_product <= std_ulogic_vector(mul_buf_ff(63 downto 0)); -- let the register balancing do the magic here
tmp_v := mul_op_x * mul_op_y;
mul_product <= std_ulogic_vector(tmp_v(63 downto 0));
--mul_buf_ff <= mul_op_x * mul_op_y;
--mul_product <= std_ulogic_vector(mul_buf_ff(63 downto 0)); -- let the register balancing do the magic here
end if;
end process multiplier_core;
end generate;
282,7 → 276,11
remainder <= (others => def_rst_val_c);
elsif rising_edge(clk_i) then
if (start_div = '1') then -- start new division
quotient <= div_opx;
if ((rs1_i(rs1_i'left) and rs1_is_signed) = '1') then -- signed division?
quotient <= std_ulogic_vector(0 - unsigned(rs1_i)); -- make positive
else
quotient <= rs1_i;
end if;
remainder <= (others => '0');
elsif (state = PROCESSING) or (state = FINALIZE) then -- running?
quotient <= quotient(30 downto 0) & (not div_sub(32));
307,49 → 305,39
-- no divider --
divider_core_serial_none:
if (DIVISION_EN = false) generate
remainder <= (others => '-');
quotient <= (others => '-');
div_res <= (others => '-');
remainder <= (others => '0');
quotient <= (others => '0');
div_res <= (others => '0');
end generate;
 
 
-- Data Output ----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
operation_result: process(rstn_i, clk_i)
operation_result: process(out_en, cp_op_ff, mul_product, div_res, quotient, opy_is_zero, rs1_i, remainder)
begin
if (rstn_i = '0') then
res_o <= (others => def_rst_val_c);
elsif rising_edge(clk_i) then
if (out_en = '1') then
case cp_op_ff is
when cp_op_mul_c =>
res_o <= mul_product(31 downto 00);
when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
res_o <= mul_product(63 downto 32);
when cp_op_div_c =>
res_o <= div_res;
when cp_op_divu_c =>
res_o <= quotient;
when cp_op_rem_c =>
if (opy_is_zero = '0') then
res_o <= div_res;
else
res_o <= rs1_i;
end if;
when others => -- cp_op_remu_c
res_o <= remainder;
end case;
else
res_o <= (others => '0');
if (valid = '1') then
case cp_op_ff is
when cp_op_mul_c =>
res_o <= mul_product(31 downto 00);
when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
res_o <= mul_product(63 downto 32);
when cp_op_div_c =>
if (DIVISION_EN = true) then res_o <= div_res; else NULL; end if;
when cp_op_divu_c =>
if (DIVISION_EN = true) then res_o <= quotient; else NULL; end if;
when cp_op_rem_c =>
if (DIVISION_EN = true) then
if (opy_is_zero = '0') then
res_o <= div_res;
else
res_o <= rs1_i;
end if;
else
NULL;
end if;
when others => -- cp_op_remu_c
if (DIVISION_EN = true) then res_o <= remainder; else NULL; end if;
end case;
end if;
end if;
end process operation_result;
 
-- status output --
valid_o <= valid;
 
 
end neorv32_cpu_cp_muldiv_rtl;
/core/neorv32_gptmr.vhd
74,7 → 74,6
constant ctrl_prsc1_c : natural := 2; -- r/w: clock prescaler select bit 1
constant ctrl_prsc2_c : natural := 3; -- r/w: clock prescaler select bit 2
constant ctrl_mode_c : natural := 4; -- r/w: mode (0=single-shot, 1=continuous)
constant ctrl_alarm_c : natural := 5; -- r/c: alarm flag (interrupt), cleared by writing zero
--
signal ctrl : std_ulogic_vector(4 downto 0);
 
96,13 → 95,8
end record;
signal timer : timer_t;
 
-- interrupt generator --
type irq_t is record
pending : std_ulogic; -- pending interrupt request
detect : std_ulogic_vector(1 downto 0); -- rising-edge detector
clearn : std_ulogic; -- clear/ack IRQ request, active-low
end record;
signal irq : irq_t;
-- interrupt detector --
signal irq_detect : std_ulogic_vector(1 downto 0);
 
begin
 
123,7 → 117,6
ack_o <= rden or wren;
 
-- write access --
irq.clearn <= '1';
timer.cnt_we <= '0';
if (wren = '1') then
if (addr = gptmr_ctrl_addr_c) then -- control register
132,7 → 125,6
ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c);
ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c);
ctrl(ctrl_mode_c) <= data_i(ctrl_mode_c);
irq.clearn <= data_i(ctrl_alarm_c);
end if;
if (addr = gptmr_thres_addr_c) then -- threshold register
timer.thres <= data_i;
152,7 → 144,6
data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
data_o(ctrl_mode_c) <= ctrl(ctrl_mode_c);
data_o(ctrl_alarm_c) <= irq.pending;
when "01" => -- threshold register
data_o <= timer.thres;
when others => -- counter register
198,21 → 189,15
begin
if rising_edge(clk_i) then
if (ctrl(ctrl_en_c) = '0') then
irq.detect <= "00";
irq.pending <= '0';
irq_detect <= "00";
else
irq.detect <= irq.detect(0) & timer.match;
if (irq.detect = "01") then -- rising edge
irq.pending <= '1';
elsif (irq.clearn = '0') then
irq.pending <= '0';
end if;
irq_detect <= irq_detect(0) & timer.match;
end if;
end if;
end process irq_generator;
 
-- IRQ request to CPU --
irq_o <= irq.pending;
irq_o <= '1' when (irq_detect = "01") else '0';
 
 
end neorv32_gptmr_rtl;
/core/neorv32_neoled.vhd
155,9 → 155,8
 
-- interrupt generator --
type irq_t is record
pending : std_ulogic; -- pending interrupt request
set : std_ulogic;
clr : std_ulogic;
set : std_ulogic;
buf : std_ulogic_vector(1 downto 0);
end record;
signal irq : irq_t;
 
250,42 → 249,31
 
-- IRQ Generator --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
irq_select: process(ctrl, tx_buffer)
irq_select: process(ctrl, tx_buffer, serial.done)
begin
if (FIFO_DEPTH = 1) then
irq.set <= tx_buffer.free; -- fire IRQ if FIFO is empty
if (FIFO_DEPTH = 1) or (ctrl.irq_conf = '1') then
irq.set <= tx_buffer.free and serial.done; -- fire IRQ if FIFO is empty
else
if (ctrl.irq_conf = '0') then -- fire IRQ if FIFO is less than half-full
irq.set <= not tx_buffer.half;
else -- fire IRQ if FIFO is empty
irq.set <= tx_buffer.free;
end if;
irq.set <= not tx_buffer.half; -- fire IRQ if FIFO is less than half-full
end if;
end process irq_select;
 
-- Interrupt Arbiter --
irq_generator: process(clk_i)
-- Interrupt Edge Detector --
irq_detect: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl.enable = '0') then
irq.pending <= '0';
irq.buf <= "00";
else
if (irq.set = '1') and (serial.done = '1') then -- evaluate IRQ condition when transmitter is done again
irq.pending <= '1';
elsif (irq.clr = '1') then
irq.pending <= '0';
end if;
irq.buf <= irq.buf(0) & irq.set;
end if;
end if;
end process irq_generator;
end process irq_detect;
 
-- IRQ request to CPU --
irq_o <= irq.pending;
irq_o <= '1' when (irq.buf = "01") else '0';
 
-- IRQ acknowledge --
irq.clr <= '1' when (wren = '1') else '0'; -- write data or control register
 
 
-- TX Buffer (FIFO) -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
tx_data_fifo: neorv32_fifo
/core/neorv32_package.vhd
53,7 → 53,7
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
constant pmp_num_regions_critical_c : natural := 8; -- default=8
 
-- "response time window" for processor-internal memories and IO devices
-- "response time window" for processor-internal modules --
constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
 
-- jtag tap - identifier --
64,9 → 64,23
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060400"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060500"; -- no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
 
-- Check if we're inside the Matrix -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant is_simulation_c : boolean := false -- seems like we're on real hardware
-- pragma translate_off
-- synthesis translate_off
-- synthesis synthesis_off
-- RTL_SYNTHESIS OFF
or true -- this MIGHT be a simulation
-- RTL_SYNTHESIS ON
-- synthesis synthesis_on
-- synthesis translate_on
-- pragma translate_on
;
 
-- External Interface Types ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
575,7 → 589,7
constant csr_mhpmevent30_c : std_ulogic_vector(11 downto 0) := x"33e";
constant csr_mhpmevent31_c : std_ulogic_vector(11 downto 0) := x"33f";
-- machine trap handling --
constant csr_class_trap_c : std_ulogic_vector(08 downto 0) := x"34" & '0'; -- machine trap handling
constant csr_class_trap_c : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340";
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341";
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342";
1089,6 → 1103,7
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
debug_o : out std_ulogic; -- cpu is in debug mode when set
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1616,6 → 1631,9
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_wdt
generic (
DEBUG_EN : boolean -- CPU debug mode implemented?
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
1626,6 → 1644,8
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- CPU in debug mode? --
cpu_debug_i : in std_ulogic;
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
2090,7 → 2110,7
 
package body neorv32_package is
 
-- Function: Minimal required number of bits to represent input number --------------------
-- Function: Minimal required number of bits to represent <input> numbers -----------------
-- -------------------------------------------------------------------------------------------
function index_size_f(input : natural) return natural is
begin
/core/neorv32_slink.vhd
153,11 → 153,9
-- interrupt generator --
type detect_t is array (0 to 7) of std_ulogic_vector(1 downto 0);
type irq_t is record
pending : std_ulogic; -- pending interrupt request
detect : detect_t; -- rising-edge detector
trigger : std_ulogic_vector(7 downto 0);
set : std_ulogic_vector(7 downto 0);
clr : std_ulogic;
end record;
signal rx_irq, tx_irq : irq_t;
 
261,65 → 259,59
 
-- Interrupt Generator --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
irq_type: process(irq_rx_mode, rx_fifo_avail, rx_fifo_half,
irq_tx_mode, tx_fifo_free, tx_fifo_half)
-- interrupt trigger type / condition --
irq_type: process(irq_rx_mode, rx_fifo_avail, rx_fifo_half, irq_tx_mode, tx_fifo_free, tx_fifo_half, tx_fifo_we)
begin
-- RX interrupt --
rx_irq.trigger <= (others => '0');
for i in 0 to SLINK_NUM_RX-1 loop
if (SLINK_RX_FIFO = 1) then
rx_irq.trigger(i) <= rx_fifo_avail(i); -- fire if any RX_FIFO is not empty
if (SLINK_RX_FIFO = 1) or (irq_rx_mode(i) = '0') then
rx_irq.trigger(i) <= rx_fifo_avail(i); -- fire if any RX_FIFO is not empty (= data available)
else
if (irq_rx_mode(i) = '0') then -- fire if any RX_FIFO is at least half-full
rx_irq.trigger(i) <= rx_fifo_half(i);
else -- fire if any RX_FIFO is not empty (= data available)
rx_irq.trigger(i) <= rx_fifo_avail(i);
end if;
rx_irq.trigger(i) <= rx_fifo_half(i);
end if;
end loop;
-- TX interrupt --
tx_irq.trigger <= (others => '0');
for i in 0 to SLINK_NUM_TX-1 loop
if (SLINK_TX_FIFO = 1) then
tx_irq.trigger(i) <= tx_fifo_free(i); -- fire if any TX_FIFO is not full
if (SLINK_TX_FIFO = 1) or (irq_tx_mode(i) = '0') then
tx_irq.trigger(i) <= tx_fifo_free(i) and tx_fifo_we(i); -- fire if any TX_FIFO is not full (= free buffer space available)
else
if (irq_tx_mode(i) = '0') then -- fire if any TX_FIFO is less than half-full
tx_irq.trigger(i) <= not tx_fifo_half(i);
else -- fire if any TX_FIFO is not full (= free buffer space available)
tx_irq.trigger(i) <= tx_fifo_free(i);
end if;
tx_irq.trigger(i) <= not tx_fifo_half(i);
end if;
end loop;
end process irq_type;
 
-- interrupt trigger --
irq_trigger_sync: process(clk_i)
-- edge detector - sync --
irq_edge_detect_sync: process(clk_i)
begin
if rising_edge(clk_i) then
-- RX --
rx_irq.detect <= (others => (others => '0')); -- default
if (enable = '1') then
for i in 0 to SLINK_NUM_RX-1 loop
for i in 0 to SLINK_NUM_RX-1 loop
if (enable = '1') and (irq_rx_en(i) = '1') then
rx_irq.detect(i) <= rx_irq.detect(i)(0) & rx_irq.trigger(i);
end loop;
end if;
else
rx_irq.detect(i) <= "00";
end if;
end loop;
-- TX --
tx_irq.detect <= (others => (others => '0')); -- default
if (enable = '1') then
for i in 0 to SLINK_NUM_TX-1 loop
for i in 0 to SLINK_NUM_TX-1 loop
if (enable = '1') and (irq_tx_en(i) = '1') then
tx_irq.detect(i) <= tx_irq.detect(i)(0) & tx_irq.trigger(i);
end loop;
end if;
else
tx_irq.detect(i) <= "00";
end if;
end loop;
end if;
end process irq_trigger_sync;
end process irq_edge_detect_sync;
 
-- interrupt trigger --
irq_trigger_comb: process(rx_irq, irq_rx_en, tx_irq, irq_tx_en)
-- edge detector - sync --
irq_edge_detect_comb: process(rx_irq, irq_rx_en, tx_irq, irq_tx_en)
begin
-- RX --
rx_irq.set <= (others => '0');
for i in 0 to SLINK_NUM_RX-1 loop
if (rx_irq.detect(i) = "01") and (irq_rx_en(i) = '1') then -- rising-edge
if (rx_irq.detect(i) = "01") then -- rising-edge
rx_irq.set(i) <= '1';
end if;
end loop;
326,45 → 318,22
-- TX --
tx_irq.set <= (others => '0');
for i in 0 to SLINK_NUM_TX-1 loop
if (tx_irq.detect(i) = "01") and (irq_tx_en(i) = '1') then -- rising-edge
if (tx_irq.detect(i) = "01") then -- rising-edge
tx_irq.set(i) <= '1';
end if;
end loop;
end process irq_trigger_comb;
end process irq_edge_detect_comb;
 
-- interrupt arbiter --
irq_generator: process(clk_i)
begin
if rising_edge(clk_i) then
if (enable = '0') then
rx_irq.pending <= '0';
tx_irq.pending <= '0';
else
-- RX --
if (or_reduce_f(rx_irq.set) = '1') then
rx_irq.pending <= '1';
elsif (rx_irq.clr = '1') then
rx_irq.pending <= '0';
end if;
-- TX --
if (or_reduce_f(tx_irq.set) = '1') then
tx_irq.pending <= '1';
elsif (tx_irq.clr = '1') then
tx_irq.pending <= '0';
end if;
end if;
irq_rx_o <= or_reduce_f(rx_irq.set);
irq_tx_o <= or_reduce_f(tx_irq.set);
end if;
end process irq_generator;
 
-- IRQ requests to CPU --
irq_rx_o <= rx_irq.pending;
irq_tx_o <= tx_irq.pending;
 
-- IRQ acknowledge --
rx_irq.clr <= '1' when ((rden = '1') and (addr(5) = '1')) or ((wren = '1') and (addr(5 downto 3) = "000")) else '0'; -- read from data FIFO OR write to control register
tx_irq.clr <= '1' when ((wren = '1') and (addr(5) = '1')) or ((wren = '1') and (addr(5 downto 3) = "000")) else '0'; -- write to data FIFO OR write to control register
 
 
-- Link Select ----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
link_select: process(addr)
/core/neorv32_spi.vhd
116,14 → 116,6
end record;
signal rtx_engine : rtx_engine_t;
 
-- interrupt generator --
type irq_t is record
pending : std_ulogic; -- pending interrupt request
set : std_ulogic;
clr : std_ulogic;
end record;
signal irq : irq_t;
 
begin
 
-- Access Control -------------------------------------------------------------------------
239,7 → 231,7
 
-- defaults --
spi_sck_o <= ctrl(ctrl_cpol_c);
irq.set <= '0';
irq_o <= '0';
 
-- serial engine --
rtx_engine.state(2) <= ctrl(ctrl_en_c);
273,7 → 265,7
if (spi_clk_en = '1') then
rtx_engine.sreg <= rtx_engine.sreg(30 downto 0) & rtx_engine.sdi_sync(rtx_engine.sdi_sync'left);
if (rtx_engine.bitcnt(5 downto 3) = rtx_engine.bytecnt) then -- all bits transferred?
irq.set <= '1'; -- interrupt!
irq_o <= '1'; -- interrupt!
rtx_engine.state(1 downto 0) <= "00"; -- transmission done
else
rtx_engine.state(1 downto 0) <= "10";
292,28 → 284,4
rtx_engine.busy <= '0' when (rtx_engine.state(1 downto 0) = "00") else '1';
 
 
-- Interrupt Generator --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
irq_generator: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl(ctrl_en_c) = '0') then
irq.pending <= '0';
else
if (irq.set = '1') then
irq.pending <= '1';
elsif (irq.clr = '1') then
irq.pending <= '0';
end if;
end if;
end if;
end process irq_generator;
 
-- IRQ request to CPU --
irq_o <= irq.pending;
 
-- IRQ acknowledge --
irq.clr <= '1' when ((rden = '1') and (addr = spi_rtx_addr_c)) or (wren = '1') else '0'; -- read data register OR write data/control register
 
 
end neorv32_spi_rtl;
/core/neorv32_sysinfo.vhd
163,8 → 163,9
sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_EXT_BIG_ENDIAN); -- is external memory bus interface using BIG-endian byte-order?
sysinfo_mem(2)(05) <= bool_to_ulogic_f(ICACHE_EN); -- processor-internal instruction cache implemented?
--
sysinfo_mem(2)(13 downto 06) <= (others => '0'); -- reserved
sysinfo_mem(2)(12 downto 06) <= (others => '0'); -- reserved
-- Misc --
sysinfo_mem(2)(13) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
sysinfo_mem(2)(14) <= bool_to_ulogic_f(ON_CHIP_DEBUGGER_EN); -- on-chip debugger implemented?
sysinfo_mem(2)(15) <= bool_to_ulogic_f(dedicated_reset_c); -- dedicated hardware reset of all core registers?
-- IO --
/core/neorv32_top.vhd
340,6 → 340,7
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
signal ext_timeout : std_ulogic;
signal ext_access : std_ulogic;
signal debug_mode : std_ulogic;
 
begin
 
492,6 → 493,7
clk_i => clk_i, -- global clock, rising edge
rstn_i => sys_rstn, -- global reset, low-active, async
sleep_o => open, -- cpu is in sleep mode when set
debug_o => debug_mode, -- cpu is in debug mode when set
-- instruction bus interface --
i_bus_addr_o => cpu_i.addr, -- bus access address
i_bus_rdata_i => cpu_i.rdata, -- bus read data
537,7 → 539,7
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
 
-- fast interrupt requests (FIRQs) --
-- these stay asserted until explicitly acknowledged --
-- these signals are single-shot --
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog
fast_irq(01) <= cfs_irq; -- custom functions subsystem
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX
937,6 → 939,9
neorv32_wdt_inst_true:
if (IO_WDT_EN = true) generate
neorv32_wdt_inst: neorv32_wdt
generic map(
DEBUG_EN => ON_CHIP_DEBUGGER_EN -- CPU debug mode implemented?
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
947,6 → 952,8
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_WDT).rdata, -- data out
ack_o => resp_bus(RESP_WDT).ack, -- transfer acknowledge
-- CPU in debug mode? --
cpu_debug_i => debug_mode,
-- clock generator --
clkgen_en_o => wdt_cg_en, -- enable clock generator
clkgen_i => clk_gen,
/core/neorv32_twi.vhd
111,14 → 111,6
signal twi_sda_out : std_ulogic;
signal twi_scl_out : std_ulogic;
 
-- interrupt generator --
type irq_t is record
pending : std_ulogic; -- pending interrupt request
set : std_ulogic;
clr : std_ulogic;
end record;
signal irq : irq_t;
 
begin
 
-- Access Control -------------------------------------------------------------------------
198,7 → 190,7
twi_scl_in_ff <= twi_scl_in_ff(0) & twi_scl_in;
 
-- defaults --
irq.set <= '0';
irq_o <= '0';
 
-- serial engine --
arbiter(2) <= ctrl(ctrl_en_c); -- still activated?
232,7 → 224,7
twi_scl_out <= '1';
elsif (twi_clk_phase(3) = '1') then
twi_scl_out <= '0';
irq.set <= '1'; -- Interrupt!
irq_o <= '1'; -- Interrupt!
arbiter(1 downto 0) <= "00"; -- go back to IDLE
end if;
 
241,7 → 233,7
twi_sda_out <= '0';
elsif (twi_clk_phase(3) = '1') then
twi_sda_out <= '1';
irq.set <= '1'; -- Interrupt!
irq_o <= '1'; -- Interrupt!
arbiter(1 downto 0) <= "00"; -- go back to IDLE
end if;
--
264,7 → 256,7
end if;
--
if (bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
irq.set <= '1'; -- Interrupt!
irq_o <= '1'; -- Interrupt!
arbiter(1 downto 0) <= "00"; -- go back to IDLE
end if;
 
295,28 → 287,4
twi_scl_in <= std_ulogic(twi_scl_io);
 
 
-- Interrupt Generator --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
irq_generator: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl(ctrl_en_c) = '0') then
irq.pending <= '0';
else
if (irq.set = '1') then
irq.pending <= '1';
elsif (irq.clr = '1') then
irq.pending <= '0';
end if;
end if;
end if;
end process irq_generator;
 
-- IRQ request to CPU --
irq_o <= irq.pending;
 
-- IRQ acknowledge --
irq.clr <= '1' when ((rden = '1') and (addr = twi_rtx_addr_c)) or (wren = '1') else '0'; -- read data register OR write data/control register
 
 
end neorv32_twi_rtl;
/core/neorv32_uart.vhd
231,9 → 231,8
 
-- interrupt generator --
type irq_t is record
pending : std_ulogic; -- pending interrupt request
set : std_ulogic;
clr : std_ulogic;
set : std_ulogic;
buf : std_ulogic_vector(1 downto 0);
end record;
signal rx_irq, tx_irq : irq_t;
 
490,9 → 489,9
 
-- overrun flag --
if (rden = '1') and (addr = uart_id_rtx_addr_c) then -- clear when reading data register
rx_engine.overr <= '0';
elsif (rx_buffer.we = '1') and (rx_buffer.free = '0') then -- write to full FIFO
rx_engine.overr <= '1';
elsif (rx_buffer.we = '1') and (rx_buffer.free = '0') then -- write to full FIFO
rx_engine.overr <= '0';
end if;
end if;
end if;
556,64 → 555,41
 
-- Interrupt Generator --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
irq_type: process(ctrl, tx_buffer, rx_buffer)
irq_type: process(ctrl, tx_buffer, rx_buffer, tx_engine.done)
begin
-- TX interrupt --
if (UART_TX_FIFO = 1) then
tx_irq.set <= tx_buffer.free; -- fire IRQ if FIFO is not full
if (UART_TX_FIFO = 1) or (ctrl(ctrl_tx_irq_c) = '0') then
tx_irq.set <= tx_buffer.free and tx_engine.done; -- fire IRQ if FIFO is not full
else
if (ctrl(ctrl_tx_irq_c) = '1') then
tx_irq.set <= not tx_buffer.half; -- fire IRQ if FIFO is less than half-full
else
tx_irq.set <= tx_buffer.free; -- fire IRQ if FIFO is not full
end if;
tx_irq.set <= (not tx_buffer.half) and tx_engine.done; -- fire IRQ if FIFO is less than half-full
end if;
 
-- RX interrupt --
if (UART_RX_FIFO = 1) then
if (UART_RX_FIFO = 1) or (ctrl(ctrl_rx_irq_c) = '0') then
rx_irq.set <= rx_buffer.avail; -- fire IRQ if FIFO is not empty
else
if (ctrl(ctrl_rx_irq_c) = '1') then
rx_irq.set <= rx_buffer.half; -- fire IRQ if FIFO is at least half-full
else
rx_irq.set <= rx_buffer.avail; -- fire IRQ is FIFO is not empty
end if;
rx_irq.set <= rx_buffer.half; -- fire IRQ if FIFO is at least half-full
end if;
end process irq_type;
 
-- interrupt arbiter --
irq_generator: process(clk_i)
-- interrupt edge detector --
irq_detect: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl(ctrl_en_c) = '0') then
rx_irq.pending <= '0';
tx_irq.pending <= '0';
tx_irq.buf <= "00";
rx_irq.buf <= "00";
else
-- TX --
if (tx_irq.set = '1') and (tx_engine.done = '1') then -- evaluate IRQ condition when TX is done with current sending
tx_irq.pending <= '1';
elsif (tx_irq.clr = '1') then
tx_irq.pending <= '0';
end if;
-- RX --
if (rx_irq.set = '1') and (rx_engine.done = '1') then -- evaluate IRQ condition when RX is done with current receiving
rx_irq.pending <= '1';
elsif (rx_irq.clr = '1') then
rx_irq.pending <= '0';
end if;
tx_irq.buf <= tx_irq.buf(0) & tx_irq.set;
rx_irq.buf <= rx_irq.buf(0) & rx_irq.set;
end if;
end if;
end process irq_generator;
end process irq_detect;
 
-- IRQ requests to CPU --
irq_txd_o <= tx_irq.pending;
irq_rxd_o <= rx_irq.pending;
irq_txd_o <= '1' when (tx_irq.buf = "01") else '0';
irq_rxd_o <= '1' when (rx_irq.buf = "01") else '0';
 
-- IRQ acknowledge --
tx_irq.clr <= '1' when (tx_buffer.we = '1') or ((wren = '1') and (addr = uart_id_ctrl_addr_c)) else '0'; -- write to data reg OR write to control reg
rx_irq.clr <= '1' when (rx_buffer.re = '1') or ((wren = '1') and (addr = uart_id_ctrl_addr_c)) else '0'; -- read from data reg OR write to control reg
 
 
-- SIMULATION Transmitter -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- pragma translate_off
/core/neorv32_wdt.vhd
48,6 → 48,9
use neorv32.neorv32_package.all;
 
entity neorv32_wdt is
generic (
DEBUG_EN : boolean -- CPU debug mode implemented?
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
58,6 → 61,8
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- CPU in debug mode? --
cpu_debug_i : in std_ulogic;
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
74,15 → 79,17
constant lo_abb_c : natural := index_size_f(wdt_size_c); -- low address boundary bit
 
-- Control register bits --
constant ctrl_enable_c : natural := 0; -- r/w: WDT enable
constant ctrl_clksel0_c : natural := 1; -- r/w: prescaler select bit 0
constant ctrl_clksel1_c : natural := 2; -- r/w: prescaler select bit 1
constant ctrl_clksel2_c : natural := 3; -- r/w: prescaler select bit 2
constant ctrl_mode_c : natural := 4; -- r/w: 0: WDT timeout triggers interrupt, 1: WDT timeout triggers hard reset
constant ctrl_rcause_c : natural := 5; -- r/-: cause of last action (reset/IRQ): 0=external reset, 1=watchdog overflow
constant ctrl_reset_c : natural := 6; -- -/w: reset WDT if set
constant ctrl_force_c : natural := 7; -- -/w: force WDT action
constant ctrl_lock_c : natural := 8; -- r/w: lock access to control register when set
constant ctrl_enable_c : natural := 0; -- r/w: WDT enable
constant ctrl_clksel0_c : natural := 1; -- r/w: prescaler select bit 0
constant ctrl_clksel1_c : natural := 2; -- r/w: prescaler select bit 1
constant ctrl_clksel2_c : natural := 3; -- r/w: prescaler select bit 2
constant ctrl_mode_c : natural := 4; -- r/w: 0: WDT timeout triggers interrupt, 1: WDT timeout triggers hard reset
constant ctrl_rcause_c : natural := 5; -- r/-: cause of last action (reset/IRQ): 0=external reset, 1=watchdog overflow
constant ctrl_reset_c : natural := 6; -- -/w: reset WDT if set
constant ctrl_force_c : natural := 7; -- -/w: force WDT action
constant ctrl_lock_c : natural := 8; -- r/w: lock access to control register when set
constant ctrl_dben_c : natural := 9; -- r/w: allow WDT to continue operation even when in debug mode
constant ctrl_half_c : natural := 10; -- r/-: set if at least half of the max. timeout counter value has been reached
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
90,7 → 97,7
signal rden : std_ulogic;
 
-- control register --
type ctrl_reg_t is record
type ctrl_t is record
enable : std_ulogic; -- 1=WDT enabled
clk_sel : std_ulogic_vector(2 downto 0);
mode : std_ulogic; -- 0=trigger IRQ on overflow; 1=trigger hard reset on overflow
98,8 → 105,9
reset : std_ulogic; -- reset WDT
enforce : std_ulogic; -- force action
lock : std_ulogic; -- lock control register
dben : std_ulogic; -- allow operation also in debug mode
end record;
signal ctrl_reg : ctrl_reg_t;
signal ctrl : ctrl_t;
 
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
108,18 → 116,11
signal wdt_cnt : std_ulogic_vector(20 downto 0);
signal hw_rst : std_ulogic;
signal rst_gen : std_ulogic_vector(03 downto 0);
signal cnt_en : std_ulogic;
 
-- internal reset (sync, low-active) --
signal rstn_sync : std_ulogic;
 
-- cpu interrupt --
type cpu_irq_t is record
pending : std_ulogic;
set : std_ulogic;
clr : std_ulogic;
end record;
signal cpu_irq : cpu_irq_t;
 
begin
 
-- Access Control -------------------------------------------------------------------------
134,34 → 135,36
write_access: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl_reg.reset <= '0';
ctrl_reg.enforce <= '0';
ctrl_reg.enable <= '0'; -- disable WDT
ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
ctrl_reg.lock <= '0';
ctrl.reset <= '1'; -- reset counter on start-up
ctrl.enforce <= '0';
ctrl.enable <= '0'; -- disable WDT
ctrl.mode <= '0';
ctrl.clk_sel <= (others => '0');
ctrl.lock <= '0';
ctrl.dben <= '0';
elsif rising_edge(clk_i) then
-- acknowledge interrupt when resetting WDT --
if (rstn_sync = '0') then -- internal reset
ctrl_reg.reset <= '0';
ctrl_reg.enforce <= '0';
ctrl_reg.enable <= '0'; -- disable WDT
ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
ctrl_reg.lock <= '0';
ctrl.reset <= '1'; -- reset counter on start-up
ctrl.enforce <= '0';
ctrl.enable <= '0'; -- disable WDT
ctrl.mode <= '0';
ctrl.clk_sel <= (others => '0');
ctrl.lock <= '0';
ctrl.dben <= '0';
else
-- auto-clear WDT reset and WDT force flags --
ctrl_reg.reset <= '0';
ctrl_reg.enforce <= '0';
ctrl.reset <= '0';
ctrl.enforce <= '0';
-- actual write access --
if (wren = '1') then
ctrl_reg.reset <= data_i(ctrl_reset_c);
ctrl_reg.enforce <= data_i(ctrl_force_c);
if (ctrl_reg.lock = '0') then -- update configuration only if unlocked
ctrl_reg.enable <= data_i(ctrl_enable_c);
ctrl_reg.mode <= data_i(ctrl_mode_c);
ctrl_reg.clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
ctrl_reg.lock <= data_i(ctrl_lock_c);
ctrl.reset <= data_i(ctrl_reset_c);
ctrl.enforce <= data_i(ctrl_force_c);
if (ctrl.lock = '0') then -- update configuration only if not locked
ctrl.enable <= data_i(ctrl_enable_c);
ctrl.mode <= data_i(ctrl_mode_c);
ctrl.clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
ctrl.lock <= data_i(ctrl_lock_c);
ctrl.dben <= data_i(ctrl_dben_c) and bool_to_ulogic_f(DEBUG_EN);
end if;
end if;
end if;
169,8 → 172,8
end process write_access;
 
-- clock generator --
clkgen_en_o <= ctrl_reg.enable; -- enable clock generator
prsc_tick <= clkgen_i(to_integer(unsigned(ctrl_reg.clk_sel))); -- clock enable tick
clkgen_en_o <= ctrl.enable; -- enable clock generator
prsc_tick <= clkgen_i(to_integer(unsigned(ctrl.clk_sel))); -- clock enable tick
 
 
-- Watchdog Counter -----------------------------------------------------------------------
178,53 → 181,32
wdt_counter: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl_reg.reset = '1') then -- watchdog reset
if (ctrl.reset = '1') then -- watchdog reset
wdt_cnt <= (others => '0');
elsif (ctrl_reg.enable = '1') and (prsc_tick = '1') then
wdt_cnt <= std_ulogic_vector(unsigned(wdt_cnt) + 1);
elsif (cnt_en = '1') then
wdt_cnt <= std_ulogic_vector(unsigned('0' & wdt_cnt(wdt_cnt'left-1 downto 0)) + 1);
end if;
end if;
end process wdt_counter;
 
-- WDT counter enable --
cnt_en <= ctrl.enable and prsc_tick and ((not cpu_debug_i) or ctrl.dben);
 
-- action trigger --
cpu_irq.set <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and (not ctrl_reg.mode); -- mode 0: IRQ
cpu_irq.clr <= ctrl_reg.reset; -- ack IRQ on WDT reset
hw_rst <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and ( ctrl_reg.mode); -- mode 1: RESET
irq_o <= ctrl.enable and (wdt_cnt(wdt_cnt'left) or ctrl.enforce) and (not ctrl.mode); -- mode 0: IRQ
hw_rst <= ctrl.enable and (wdt_cnt(wdt_cnt'left) or ctrl.enforce) and ( ctrl.mode); -- mode 1: RESET
 
 
-- Interrupt ------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
irq_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl_reg.enable = '0') then
cpu_irq.pending <= '0';
else
if (cpu_irq.set = '1') then
cpu_irq.pending <= '1';
elsif(cpu_irq.clr = '1') then
cpu_irq.pending <= '0';
else
cpu_irq.pending <= cpu_irq.pending;
end if;
end if;
end if;
end process irq_gen;
 
-- CPU IRQ --
irq_o <= cpu_irq.pending;
 
 
-- Reset Generator & Action Cause Indicator -----------------------------------------------
-- -------------------------------------------------------------------------------------------
reset_generator: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl_reg.rcause <= '0';
rst_gen <= (others => '1'); -- do NOT fire on reset!
rstn_sync <= '1';
ctrl.rcause <= '0';
rst_gen <= (others => '1'); -- do NOT fire on reset!
rstn_sync <= '1';
elsif rising_edge(clk_i) then
ctrl_reg.rcause <= ctrl_reg.rcause or hw_rst; -- sticky-set on WDT timeout/force
ctrl.rcause <= ctrl.rcause or hw_rst; -- sticky-set on WDT timeout/force
if (hw_rst = '1') then
rst_gen <= (others => '0');
else
243,13 → 225,15
read_access: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= rden or wren;
ack_o <= rden or wren;
if (rden = '1') then
data_o(ctrl_enable_c) <= ctrl_reg.enable;
data_o(ctrl_mode_c) <= ctrl_reg.mode;
data_o(ctrl_rcause_c) <= ctrl_reg.rcause;
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl_reg.clk_sel;
data_o(ctrl_lock_c) <= ctrl_reg.lock;
data_o(ctrl_enable_c) <= ctrl.enable;
data_o(ctrl_mode_c) <= ctrl.mode;
data_o(ctrl_rcause_c) <= ctrl.rcause;
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_sel;
data_o(ctrl_lock_c) <= ctrl.lock;
data_o(ctrl_dben_c) <= ctrl.dben;
data_o(ctrl_half_c) <= wdt_cnt(wdt_cnt'left-1);
else
data_o <= (others => '0');
end if;
/core/neorv32_wishbone.vhd
118,7 → 118,7
ack : std_ulogic;
err : std_ulogic;
tmo : std_ulogic;
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT) downto 0);
src : std_ulogic;
lock : std_ulogic;
priv : std_ulogic_vector(01 downto 0);
142,7 → 142,7
 
-- bus timeout --
assert not (BUS_TIMEOUT /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing auto-timeout (" & integer'image(BUS_TIMEOUT) & " cycles)." severity note;
assert not (BUS_TIMEOUT = 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing no auto-timeout (can cause permanent CPU stall!)." severity note;
assert not (BUS_TIMEOUT = 0) report "NEORV32 PROCESSOR CONFIG WARNING: External Bus Interface - Implementing NO auto-timeout (can cause permanent CPU stall!)." severity warning;
 
-- endianness --
assert not (BIG_ENDIAN = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing LITTLE-endian byte order." severity note;
190,7 → 190,7
ctrl.ack <= '0';
ctrl.err <= '0';
ctrl.tmo <= '0';
ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)+1));
 
-- state machine --
case ctrl.state is
/core/neorv32_xirq.vhd
210,10 → 210,12
irq_arbiter: process(clk_i)
begin
if rising_edge(clk_i) then
cpu_irq_o <= '0';
if (irq_run = '0') then -- no active IRQ
if (irq_fire = '1') then
irq_run <= '1';
irq_src <= irq_src_nxt;
cpu_irq_o <= '1';
irq_run <= '1';
irq_src <= irq_src_nxt;
end if;
else -- active IRQ, wait for CPU to acknowledge
if (wren = '1') and (addr = xirq_source_addr_c) then -- write _any_ value to acknowledge
223,8 → 225,5
end if;
end process irq_arbiter;
 
-- interrupt request --
cpu_irq_o <= irq_run;
 
 
end neorv32_xirq_rtl;
/processor_templates/README.md
1,3 → 1,35
# SoC Templates
# SoC/Processor Templates
 
:construction: Work in Progress :construction:
This folder provides exemplary templates that wrap the processor top entity and provide a simplified
set of configuration generics and IOs. These setups are intended to allow beginner an easy start by
hiding much of the processor's configuration complexity. Furthermore, these setups are used by many
of the provided [example setups](https://github.com/stnolting/neorv32/tree/master/setups).
 
Alternatively, you can directly instantiate the processor's top entity
[`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd)
to have full access to _all_ features.
 
### [`neorv32_ProcessorTop_Minimal.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd)
 
This setup used the ["Direct Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration).
Application software is installed directly into the processor-internal instruction memory (IMEM) during
synthesis. This memory is implemented as ROM and these is no bootloader available. Hence, the executable
remains unchangeable is executed right after reset.
 
The setup only provides 3 PWM channels as IO.
 
### [`neorv32_ProcessorTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd)
 
This setup used the ["Indirect Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration).
The NEORV32 bootloader is enabled in this setup allowing to upload new application software at any time
via a UART connection.
 
The setup provides 8 GPIO outputs and the UART communication lines as IO.
 
### [`neorv32_ProcessorTop_UP5KDemo.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd)
 
This is a more complex template that implements a small microcontroller-like NEORV32.
It was originally designed for _UPDuino V3_ board, which features a Lattice iCE40up5k FPGA, but has
also been ported to other boards that provide the same FPGA.
 
This setup provides a rich set of IOs including GPIO, SPI, TWI and PWM.
/system_integration/neorv32_SystemTop_axi4lite.vhd
103,7 → 103,7
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
IO_CFS_CONFIG : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
/test_setups/README.md
3,8 → 3,7
This folder contains very simple test setups that are intended for project beginners
to setup a minimal NEORV32 SoC. These setups are used in the :books:
[NEORV32 User Guide](https://stnolting.github.io/neorv32/ug/).
 
:information_source: Note that these setups provides a minimalistic configuration to keep
Note that these setups provides a minimalistic configuration to keep
things at a simple level at first. Additional CPU ISA extensions, performance options and
optional peripheral modules can be enabled by specifying the according :book:
[configuration generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics).
33,7 → 32,7
This setup configures a `rv32imc_Zicsr` CPU with 16kB IMEM (as pre-initialized ROM),
8kB DMEM and includes the GPIO module to drive 8 external signals (`gpio_o`)
and the MTIME module for generating timer interrupts.
The setup uses the [indidrect boot](https://stnolting.github.io/neorv32/#_indirect_boot)
The setup uses the ["indirect boot"](https://stnolting.github.io/neorv32/#_indirect_boot)
configuration, so software applications are "installed" directly into the
processor-internal IMEM during synthesis.
 
46,7 → 45,7
and includes the GPIO module to drive 8 external signals (`gpio_o`), the MTIME
module for generating timer interrupts and UART0 to interface with the bootloader
(via `uart0_txd_o` and `uart0_rxd_i`) via a serial terminal.
The setup uses the [direct boot](https://stnolting.github.io/neorv32/#_direct_boot)
The setup uses the ["direct boot"](https://stnolting.github.io/neorv32/#_direct_boot)
configuration, so software applications can be uploaded and run at any timer via a serial terminal.
 
:books: See User Guide section

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