URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sim/simple
- from Rev 70 to Rev 72
- ↔ Reverse comparison
Rev 70 → Rev 72
/neorv32_imem.iram.simple.vhd
6,7 → 6,7
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
125,6 → 125,7
begin |
if rising_edge(clk_i) then |
rden <= acc_en and rden_i; |
err_o <= '0'; |
ack_o <= acc_en and (rden_i or wren_i); |
end if; |
end process bus_feedback; |
/neorv32_imem.simple.vhd
78,7 → 78,8
begin |
if rising_edge(clk_i) then |
rden <= acc_en and rden_i; |
ack_o <= acc_en and (rden_i or wren_i); |
ack_o <= acc_en and rden_i; |
err_o <= acc_en and wren_i; |
addr_v := to_integer(unsigned(addr)); |
-- |
rdata <= (others => '0'); |
/neorv32_tb.simple.vhd
187,6 → 187,7
CPU_EXTENSION_RISCV_Zihpm => true, -- implement hardware performance monitors? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension? |
CPU_EXTENSION_RISCV_Zxcfu => true, -- implement custom (instr.) functions unit? |
-- Extension Options -- |
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations |