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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/example/processor_check
    from Rev 67 to Rev 68
    ↔ Reverse comparison
  •

Rev 67 → Rev 68

/main.c
483,26 → 483,26
}
 
 
// ----------------------------------------------------------
// No "real" CSR write access (because rs1 = r0)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] Read-only CSR 'no-write' (rs1=0) access: ", cnt_test);
//// ----------------------------------------------------------
//// No "real" CSR write access (because rs1 = r0)
//// ----------------------------------------------------------
//neorv32_cpu_csr_write(CSR_MCAUSE, 0);
//PRINT_STANDARD("[%i] Read-only CSR 'no-write' (rs1=0) access: ", cnt_test);
//
//cnt_test++;
//
//// time CSR is read-only, but no actual write is performed because rs1=r0
//// -> should cause no exception
//asm volatile("csrrs zero, time, zero");
//
//if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
// test_ok();
//}
//else {
// test_fail();
//}
 
cnt_test++;
 
// time CSR is read-only, but no actual write is performed because rs1=r0
// -> should cause no exception
asm volatile("csrrs zero, time, zero");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
test_ok();
}
else {
test_fail();
}
 
 
// ----------------------------------------------------------
// Unaligned instruction address
// ----------------------------------------------------------
1124,10 → 1124,11
// configure SPI
neorv32_spi_setup(CLK_PRSC_2, 0, 0, 0);
 
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
 
// trigger SPI IRQ
neorv32_spi_trans(0);
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
while(neorv32_spi_busy()); // wait for current transfer to finish
 
// wait some time for the IRQ to arrive the CPU
1155,14 → 1156,14
 
cnt_test++;
 
// configure TWI, fastest clock, no peripheral clock stretching
neorv32_twi_setup(CLK_PRSC_2, 0);
// configure TWI, fastest clock
neorv32_twi_setup(CLK_PRSC_2);
 
// enable TWI FIRQ
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
 
// trigger TWI IRQ
neorv32_twi_generate_start();
neorv32_twi_trans(0);
neorv32_twi_generate_stop();
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
1224,9 → 1225,37
// ----------------------------------------------------------
// Fast interrupt channel 9 (NEOLED)
// ----------------------------------------------------------
PRINT_STANDARD("[%i] FIRQ9 (NEOLED): skipped\n", cnt_test);
if (neorv32_neoled_available()) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] FIRQ9 (NEOLED): ", cnt_test);
 
cnt_test++;
 
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ9E);
 
// configure NEOLED
neorv32_neoled_setup(CLK_PRSC_2, 0, 0, 0);
 
// send dummy data
neorv32_neoled_write_nonblocking(0);
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
neorv32_cpu_irq_disable(CSR_MIE_FIRQ9E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_9) {
test_ok();
}
else {
test_fail();
}
 
// no more NEOLED interrupts
neorv32_neoled_disable();
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 10 & 11 (SLINK)
// ----------------------------------------------------------
1236,13 → 1265,13
 
cnt_test++;
 
// enable SLINK
neorv32_slink_enable();
 
// configure SLINK IRQs
neorv32_slink_tx_irq_config(0, SLINK_IRQ_ENABLE, SLINK_IRQ_TX_NOT_FULL);
neorv32_slink_rx_irq_config(0, SLINK_IRQ_ENABLE, SLINK_IRQ_RX_NOT_EMPTY);
 
// enable SLINK
neorv32_slink_enable();
 
// enable SLINK FIRQs
neorv32_cpu_irq_enable(CSR_MIE_FIRQ10E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ11E);
1306,8 → 1335,8
// enable GPTMR FIRQ
neorv32_cpu_irq_enable(CSR_MIE_FIRQ12E);
 
// configure timer IRQ for one-shot mode after 2*4 clock cycles
neorv32_gptmr_setup(CLK_PRSC_2, 0, 4);
// configure timer IRQ for one-shot mode after 2*3 clock cycles
neorv32_gptmr_setup(CLK_PRSC_2, 0, 3);
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
/makefile
34,6 → 34,7
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
#################################################################################################
 
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../../..
 
include ../../common/common.mk
include $(NEORV32_HOME)/sw/common/common.mk

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