OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/example
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/coremark/core_portme.c
71,7 → 71,9
or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
*/
void start_time(void) {
elapsed_cycles = neorv32_mtime_get_time();
elapsed_cycles = 0; // this is time zero
neorv32_cpu_set_mcycle(0);
neorv32_cpu_set_minstret(0);
//GETMYTIME(&start_time_val );
}
/* Function : stop_time
93,7 → 95,7
and the resolution is controlled by <TIMER_RES_DIVIDER>
*/
CORE_TICKS get_time(void) {
CORE_TICKS elapsed = ((CORE_TICKS)neorv32_mtime_get_time()) - elapsed_cycles;
CORE_TICKS elapsed = ((CORE_TICKS)neorv32_cpu_get_cycle()) - elapsed_cycles;
elapsed_cycles = elapsed;
//CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
return elapsed;
106,7 → 108,7
*/
secs_ret time_in_secs(CORE_TICKS ticks) {
//secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
secs_ret retval=(secs_ret)(ticks / neorv32_cpu_csr_read(CSR_MCLOCK));
secs_ret retval=(secs_ret)(ticks / SYSINFO_CLK);
return retval;
}
 
127,13 → 129,7
// setup neorv32 UART
neorv32_uart_setup(BAUD_RATE, 0, 0);
 
// check if MTIME unit was synthesized
if (!neorv32_mtime_available()) {
neorv32_uart_printf("NEORV32: Error! No MTIME unit synthesized!");
while(1);
}
 
neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)neorv32_cpu_csr_read(CSR_MCLOCK));
neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)SYSINFO_CLK);
neorv32_uart_printf("NEORV32: Executing coremark (%u iterations). This may take some time...\n\n", (uint32_t)ITERATIONS);
 
if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
155,23 → 151,14
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} exe_cycles;
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} exe_instructions, exe_time;
 
exe_time.uint64 = (uint64_t)elapsed_cycles;
exe_cycles.uint32[0] = neorv32_cpu_csr_read(CSR_TIME);
exe_cycles.uint32[1] = neorv32_cpu_csr_read(CSR_TIMEH);
exe_instructions.uint32[0] = neorv32_cpu_csr_read(CSR_INSTRET);
exe_instructions.uint32[1] = neorv32_cpu_csr_read(CSR_INSTRETH);
exe_instructions.uint64 = neorv32_cpu_get_instret();
 
neorv32_uart_printf("\nNEORV32: Executed instructions 0x%x_%x\n", (uint32_t)exe_instructions.uint32[1], (uint32_t)exe_instructions.uint32[0]);
neorv32_uart_printf("NEORV32: Total required clock cycles 0x%x_%x\n", (uint32_t)exe_cycles.uint32[1], (uint32_t)exe_cycles.uint32[0]);
neorv32_uart_printf("NEORV32: CoreMark core clock cycles 0x%x_%x\n", (uint32_t)exe_time.uint32[1], (uint32_t)exe_time.uint32[0]);
neorv32_uart_printf("\nNEORV32: Executed instructions 0x%x_%x\n", (uint32_t)exe_instructions.uint32[1], (uint32_t)exe_instructions.uint32[0]);
neorv32_uart_printf("NEORV32: CoreMark core clock cycles 0x%x_%x\n", (uint32_t)exe_time.uint32[1], (uint32_t)exe_time.uint32[0]);
 
uint64_t average_cpi = exe_cycles.uint64 / exe_instructions.uint64;
uint64_t average_cpi = exe_time.uint64 / exe_instructions.uint64;
neorv32_uart_printf("NEORV32: Average CPI (integer part only): %u cycles/instruction\n", (uint32_t)average_cpi);
}
/cpu_test/main.c
36,7 → 36,7
/**********************************************************************//**
* @file cpu_test/main.c
* @author Stephan Nolting
* @brief Simple CPU interrupts and exceptions test program.
* @brief Simple CPU (interrupts and exceptions) test program.
**************************************************************************/
 
#include <neorv32.h>
50,6 → 50,8
#define BAUD_RATE 19200
//** Set 1 for detailed exception debug information */
#define DETAILED_EXCEPTION_DEBUG 0
//** Set 1 to run memory tests */
#define PROBING_MEM_TEST 0
//** Reachable unaligned address */
#define ADDR_UNALIGNED 0x00000002
//** Unreachable aligned address */
61,39 → 63,13
* @name Exception handler acknowledges
**************************************************************************/
/**@{*/
/** Exception handler answers / identifiers */
enum EXC_HANDLER_ANSWERS {
ANSWER_I_MISALIGN = 0x12345678, /**< Answer for misaligned instruction address excetion */
ANSWER_I_ACCESS = 0xAABB1133, /**< Answer for instruction access fault excetion */
ANSWER_I_ILLEGAL = 0x0199203B, /**< Answer for illegal instruction excetion */
ANSWER_BREAKPOINT = 0x12322330, /**< Answer for breakpoint excetion */
ANSWER_L_MISALIGN = 0xBABCCCCC, /**< Answer for misaligned load address excetion */
ANSWER_L_ACCESS = 0xDEF728AA, /**< Answer for load access fault excetion */
ANSWER_S_MISALIGN = 0xFF0927DD, /**< Answer for misaligned store address excetion */
ANSWER_S_ACCESS = 0x20091777, /**< Answer for store access fault excetion */
ANSWER_ENVCALL = 0x55662244, /**< Answer for environment call excetion */
ANSWER_MSI = 0xCDECDEA9, /**< Answer for machine software interrupt */
ANSWER_MTI = 0x0012FA53, /**< Answer for machine timer interrupt */
ANSWER_CLIC = 0xEEF33088 /**< Answer for machine external interrupt */
};
/** Gloabl volatile variable to store exception handler answer */
/** Global volatile variable to store exception handler answer */
volatile uint32_t exception_handler_answer;
/**@}*/
 
 
// Prototypes
void exc_handler_i_misalign(void);
void exc_handler_i_access(void);
void exc_handler_i_illegal(void);
void exc_handler_breakpoint(void);
void exc_handler_l_misalign(void);
void exc_handler_l_access(void);
void exc_handler_s_misalign(void);
void exc_handler_s_access(void);
void exc_handler_envcall(void);
void exc_handler_msi(void);
void exc_handler_mti(void);
void irq_handler_clic_ch0();
void global_trap_handler(void);
 
 
/**********************************************************************//**
164,27 → 140,26
 
// install exception handler functions
int install_err = 0;
install_err += neorv32_rte_exception_install(EXCID_I_MISALIGNED, exc_handler_i_misalign);
install_err += neorv32_rte_exception_install(EXCID_I_ACCESS, exc_handler_i_access);
install_err += neorv32_rte_exception_install(EXCID_I_ILLEGAL, exc_handler_i_illegal);
install_err += neorv32_rte_exception_install(EXCID_BREAKPOINT, exc_handler_breakpoint);
install_err += neorv32_rte_exception_install(EXCID_L_MISALIGNED, exc_handler_l_misalign);
install_err += neorv32_rte_exception_install(EXCID_L_ACCESS, exc_handler_l_access);
install_err += neorv32_rte_exception_install(EXCID_S_MISALIGNED, exc_handler_s_misalign);
install_err += neorv32_rte_exception_install(EXCID_S_ACCESS, exc_handler_s_access);
install_err += neorv32_rte_exception_install(EXCID_MENV_CALL, exc_handler_envcall);
install_err += neorv32_rte_exception_install(EXCID_MSI, exc_handler_msi);
install_err += neorv32_rte_exception_install(EXCID_MTI, exc_handler_mti);
install_err += neorv32_rte_exception_install(EXCID_I_MISALIGNED, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_I_ACCESS, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_I_ILLEGAL, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_BREAKPOINT, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_L_MISALIGNED, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_L_ACCESS, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_S_MISALIGNED, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_S_ACCESS, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_MENV_CALL, global_trap_handler);
install_err += neorv32_rte_exception_install(EXCID_MTI, global_trap_handler);
//install_err += neorv32_rte_exception_install(EXCID_MEI, -); done by neorv32_clic_handler_install
 
if (install_err) {
neorv32_uart_printf("install error!\n");
neorv32_uart_printf("RTE install error!\n");
return 0;
}
 
 
// install interrupt handler for clic WDT channel
install_err += neorv32_clic_handler_install(CLIC_CH_WDT, irq_handler_clic_ch0);
install_err += neorv32_clic_handler_install(CLIC_CH_WDT, global_trap_handler);
 
if (install_err) {
neorv32_uart_printf("CLIC install error!\n");
203,10 → 178,79
// enable global interrupts
neorv32_cpu_eint();
 
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
 
 
// ----------------------------------------------------------
// Instruction memory test
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("IMEM_TEST: ");
#if (PROBING_MEM_TEST == 1)
cnt_test++;
 
register uint32_t dmem_probe_addr = neorv32_cpu_csr_read(CSR_MISPACEBASE);
uint32_t dmem_probe_cnt = 0;
 
while(1) {
asm volatile ("lb zero, 0(%[input_j])" : : [input_j] "r" (dmem_probe_addr));
if (exception_handler_answer == EXCCODE_L_ACCESS) {
break;
}
dmem_probe_addr++;
dmem_probe_cnt++;
}
neorv32_uart_printf("%u bytes (should be %u bytes) ", dmem_probe_cnt, neorv32_cpu_csr_read(CSR_MISPACESIZE));
neorv32_uart_printf("@ 0x%x ", neorv32_cpu_csr_read(CSR_MISPACEBASE));
if (dmem_probe_cnt == neorv32_cpu_csr_read(CSR_MISPACESIZE)) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
else {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
#else
neorv32_uart_printf("skipped (disabled)\n");
#endif
 
// ----------------------------------------------------------
// Data memory test
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("DMEM_TEST: ");
#if (PROBING_MEM_TEST == 1)
cnt_test++;
 
register uint32_t imem_probe_addr = neorv32_cpu_csr_read(CSR_MDSPACEBASE);
uint32_t imem_probe_cnt = 0;
 
while(1) {
asm volatile ("lb zero, 0(%[input_j])" : : [input_j] "r" (imem_probe_addr));
if (exception_handler_answer == EXCCODE_L_ACCESS) {
break;
}
imem_probe_addr++;
imem_probe_cnt++;
}
neorv32_uart_printf("%u bytes (should be %u bytes) ", imem_probe_cnt, neorv32_cpu_csr_read(CSR_MDSPACESIZE));
neorv32_uart_printf("@ 0x%x ", neorv32_cpu_csr_read(CSR_MDSPACEBASE));
if (imem_probe_cnt == neorv32_cpu_csr_read(CSR_MDSPACESIZE)) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
else {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
#else
neorv32_uart_printf("skipped (disabled)\n");
#endif
 
 
// ----------------------------------------------------------
// Test counter CSR access for mcycle[h]
// ----------------------------------------------------------
neorv32_uart_printf("MCYCLE[H]: ");
213,10 → 257,10
cnt_test++;
 
neorv32_cpu_csr_write(CSR_MCYCLE, 0x1BCD1234);
neorv32_cpu_csr_write(CSR_MCYCLEH, 0x22334455);
neorv32_cpu_csr_write(CSR_MCYCLEH, 0x00034455);
 
if (((neorv32_cpu_csr_read(CSR_MCYCLE) & 0xffff0000L) == 0x1BCD0000) &&
(neorv32_cpu_csr_read(CSR_MCYCLEH) == 0x22334455)) {
(neorv32_cpu_csr_read(CSR_MCYCLEH) == 0x00034455)) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
233,10 → 277,10
cnt_test++;
 
neorv32_cpu_csr_write(CSR_MINSTRET, 0x11224499);
neorv32_cpu_csr_write(CSR_MINSTRETH, 0x00110011);
neorv32_cpu_csr_write(CSR_MINSTRETH, 0x00090011);
 
if (((neorv32_cpu_csr_read(CSR_MINSTRET) & 0xffff0000L) == 0x11220000) &&
(neorv32_cpu_csr_read(CSR_MINSTRETH) == 0x00110011)) {
(neorv32_cpu_csr_read(CSR_MINSTRETH) == 0x00090011)) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
272,13 → 316,13
// Test fence instructions - make sure CPU does not crash here and throws no exception
// a more complex test is provided by the RISC-V compliance test
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("FENCE(.I): ");
cnt_test++;
asm volatile ("fence");
asm volatile ("fence.i");
 
if (exception_handler_answer != 0) {
if (exception_handler_answer != 0xFFFFFFFF) {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
291,7 → 335,7
// ----------------------------------------------------------
// Unaligned instruction address
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC I_ALIGN: ");
 
// skip if C-mode is not implemented
303,7 → 347,7
((void (*)(void))ADDR_UNALIGNED)();
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_I_MISALIGN) {
if (exception_handler_answer == EXCCODE_I_MISALIGNED) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
321,7 → 365,7
// ----------------------------------------------------------
// Instruction access fault
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC I_ACC: ");
cnt_test++;
 
329,7 → 373,7
((void (*)(void))ADDR_UNREACHABLE)();
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_I_ACCESS) {
if (exception_handler_answer == EXCCODE_I_ACCESS) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
343,7 → 387,7
// ----------------------------------------------------------
// Illegal instruction
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC I_ILLEG: ");
cnt_test++;
 
357,7 → 401,7
asm volatile ( "jalr ra, %0 " : "=r" (tmp_a) : "r" (tmp_a));
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_I_ILLEGAL) {
if (exception_handler_answer == EXCCODE_I_ILLEGAL) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
371,7 → 415,7
// ----------------------------------------------------------
// Breakpoint instruction
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC BREAK: ");
cnt_test++;
 
378,7 → 422,7
asm volatile("EBREAK");
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_BREAKPOINT) {
if (exception_handler_answer == EXCCODE_BREAKPOINT) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
392,7 → 436,7
// ----------------------------------------------------------
// Unaligned load address
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC L_ALIGN: ");
cnt_test++;
 
400,7 → 444,7
asm volatile ("lw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED));
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_L_MISALIGN) {
if (exception_handler_answer == EXCCODE_L_MISALIGNED) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
414,7 → 458,7
// ----------------------------------------------------------
// Load access fault
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC L_ACC: ");
cnt_test++;
 
422,7 → 466,7
dummy_dst = MMR_UNREACHABLE;
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_L_ACCESS) {
if (exception_handler_answer == EXCCODE_L_ACCESS) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
436,7 → 480,7
// ----------------------------------------------------------
// Unaligned store address
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC S_ALIGN: ");
cnt_test++;
 
444,7 → 488,7
asm volatile ("sw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED));
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_S_MISALIGN) {
if (exception_handler_answer == EXCCODE_S_MISALIGNED) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
458,7 → 502,7
// ----------------------------------------------------------
// Store access fault
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC S_ACC: ");
cnt_test++;
 
466,7 → 510,7
MMR_UNREACHABLE = 0;
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_S_ACCESS) {
if (exception_handler_answer == EXCCODE_S_ACCESS) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
480,7 → 524,7
// ----------------------------------------------------------
// Environment call
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXC ENVCALL: ");
cnt_test++;
 
487,7 → 531,7
asm volatile("ECALL");
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_ENVCALL) {
if (exception_handler_answer == EXCCODE_MENV_CALL) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
499,31 → 543,9
 
 
// ----------------------------------------------------------
// Machine software interrupt
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("IRQ MSI: ");
cnt_test++;
 
// trigger machine software interrupt
neorv32_cpu_sw_irq();
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_MSI) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
else {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
#endif
 
 
// ----------------------------------------------------------
// Machine timer interrupt (MTIME)
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("IRQ MTI: ");
cnt_test++;
 
537,7 → 559,7
asm volatile("nop");
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_MTI) {
if (exception_handler_answer == EXCCODE_MTI) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
554,7 → 576,7
// ----------------------------------------------------------
// Machine external interrupt (via CLIC)
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("IRQ MEI: ");
cnt_test++;
 
568,7 → 590,7
asm volatile("nop");
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_CLIC) {
if (exception_handler_answer == EXCCODE_MEI) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
582,7 → 604,7
// ----------------------------------------------------------
// Test WFI ("sleep") instructions
// ----------------------------------------------------------
exception_handler_answer = 0;
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("WFI: ");
cnt_test++;
 
592,7 → 614,7
// put CPU into sleep mode
asm volatile ("wfi");
 
if (exception_handler_answer != ANSWER_MTI) {
if (exception_handler_answer != EXCCODE_MTI) {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
603,9 → 625,6
 
 
 
 
 
 
// error report
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail);
 
622,88 → 641,8
 
 
/**********************************************************************//**
* Misaligned instruction address exception handler.
* Trap handler for ALL exceptions/interrupts.
**************************************************************************/
void exc_handler_i_misalign(void) {
exception_handler_answer = ANSWER_I_MISALIGN;
void global_trap_handler(void) {
exception_handler_answer = neorv32_cpu_csr_read(CSR_MCAUSE);
}
 
/**********************************************************************//**
* Instruction access fault exception handler.
**************************************************************************/
void exc_handler_i_access(void) {
exception_handler_answer = ANSWER_I_ACCESS;
}
 
/**********************************************************************//**
* Illegal instruction exception handler.
**************************************************************************/
void exc_handler_i_illegal(void) {
exception_handler_answer = ANSWER_I_ILLEGAL;
}
 
/**********************************************************************//**
* Breakpoint exception handler.
**************************************************************************/
void exc_handler_breakpoint(void) {
exception_handler_answer = ANSWER_BREAKPOINT;
}
 
/**********************************************************************//**
* Misaligned load address exception handler.
**************************************************************************/
void exc_handler_l_misalign(void) {
exception_handler_answer = ANSWER_L_MISALIGN;
}
 
/**********************************************************************//**
* Load instruction access fault exception handler.
**************************************************************************/
void exc_handler_l_access(void) {
exception_handler_answer = ANSWER_L_ACCESS;
}
 
/**********************************************************************//**
* Misaligned store address exception handler.
**************************************************************************/
void exc_handler_s_misalign(void) {
exception_handler_answer = ANSWER_S_MISALIGN;
}
 
/**********************************************************************//**
* Store address access fault exception handler.
**************************************************************************/
void exc_handler_s_access(void) {
exception_handler_answer = ANSWER_S_ACCESS;
}
 
/**********************************************************************//**
* Environment call exception handler.
**************************************************************************/
void exc_handler_envcall(void) {
exception_handler_answer = ANSWER_ENVCALL;
}
 
/**********************************************************************//**
* Machine software interrupt exception handler.
**************************************************************************/
void exc_handler_msi(void) {
exception_handler_answer = ANSWER_MSI;
}
 
/**********************************************************************//**
* Machine timer interrupt exception handler.
**************************************************************************/
void exc_handler_mti(void) {
exception_handler_answer = ANSWER_MTI;
// set CMP of machine system timer MTIME to max to prevent an IRQ
neorv32_mtime_set_timecmp(-1);
}
 
/**********************************************************************//**
* CLIC interrupt handler for channel 0.
**************************************************************************/
void irq_handler_clic_ch0(void) {
exception_handler_answer = ANSWER_CLIC;
}
 
/demo_twi/main.c
185,7 → 185,7
}
 
// print new clock frequency
uint32_t clock = neorv32_cpu_csr_read(CSR_MCLOCK);
uint32_t clock = SYSINFO_CLK;
switch (prsc) {
case 0: clock = clock / 2; break;
case 1: clock = clock / 4; break;

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