OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/example
    from Rev 41 to Rev 42
    ↔ Reverse comparison
  •

Rev 41 → Rev 42

/blink_led/main.c
73,8 → 73,8
**************************************************************************/
int main() {
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// check if GPIO unit is implemented at all
if (neorv32_gpio_available() == 0) {
/coremark/core_portme.c
81,6 → 81,7
void
start_time(void)
{
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // start all counters
GETMYTIME(&start_time_val);
}
/* Function : stop_time
94,6 → 95,7
void
stop_time(void)
{
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
GETMYTIME(&stop_time_val);
}
/* Function : get_time
123,12 → 125,16
time_in_secs(CORE_TICKS ticks)
{
/* NEORV32-specific */
secs_ret retval = ((secs_ret)ticks) / (secs_ret)SYSINFO_CLK;
secs_ret retval = (secs_ret)(((CORE_TICKS)ticks) / ((CORE_TICKS)SYSINFO_CLK));
return retval;
}
 
ee_u32 default_num_contexts = 1;
 
/* Number of available hardware performance monitors */
uint32_t num_hpm_cnts_global = 0;
 
 
/* Function : portable_init
Target specific initialization code
Test for some common mistakes.
145,7 → 151,7
/* NEORV32-specific */
neorv32_cpu_dint(); // no interrupt, thanks
neorv32_rte_setup(); // capture all exceptions and give debug information
neorv32_uart_setup(BAUD_RATE, 0, 0); // setup UART
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); // init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
 
 
// Disable coremark compilation by default
158,10 → 164,28
while(1);
#endif
 
num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();
 
// try to setup as many HPMs as possible
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT3, 1 << HPMCNT_EVENT_CIR);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT4, 1 << HPMCNT_EVENT_WAIT_IF);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT5, 1 << HPMCNT_EVENT_WAIT_II);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT6, 1 << HPMCNT_EVENT_LOAD);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT7, 1 << HPMCNT_EVENT_STORE);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT8, 1 << HPMCNT_EVENT_WAIT_LS);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT9, 1 << HPMCNT_EVENT_JUMP);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_BRANCH);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_TBRANCH);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_TRAP);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_ILLEGAL);
 
neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)SYSINFO_CLK);
neorv32_uart_printf("NEORV32: Executing coremark (%u iterations). This may take some time...\n\n", (uint32_t)ITERATIONS);
 
// clear cycle counter
neorv32_cpu_set_mcycle(0);
neorv32_cpu_csr_write(CSR_MCOUNTEREN, -1); // enable access to all counters
 
/*
#error \
"Call board initialization routines in portable init (if needed), in particular initialize UART!\n"
182,6 → 206,8
while(1);
#endif
}
 
 
/* Function : portable_fini
Target specific final code
*/
190,7 → 216,7
{
p->portable_id = 0;
 
/* NORV§"-specific */
/* NEORV32-specific */
 
// show executed instructions, required cycles and resulting average CPI
union {
201,8 → 227,23
exe_time.uint64 = (uint64_t)get_time();
exe_instructions.uint64 = neorv32_cpu_get_instret();
 
neorv32_uart_printf("\nNEORV32: All reported numbers only show the integer results.\n\n");
neorv32_uart_printf("\nNEORV32: All reported numbers only show the integer part of the results.\n\n");
 
neorv32_uart_printf("NEORV32: HPM results\n");
if (num_hpm_cnts_global == 0) {neorv32_uart_printf("no HPMs available\n"); }
if (num_hpm_cnts_global > 0) {neorv32_uart_printf("# Retired compr. instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3)); }
if (num_hpm_cnts_global > 1) {neorv32_uart_printf("# I-fetch wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4)); }
if (num_hpm_cnts_global > 2) {neorv32_uart_printf("# I-issue wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5)); }
if (num_hpm_cnts_global > 3) {neorv32_uart_printf("# Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6)); }
if (num_hpm_cnts_global > 4) {neorv32_uart_printf("# Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7)); }
if (num_hpm_cnts_global > 5) {neorv32_uart_printf("# Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8)); }
if (num_hpm_cnts_global > 6) {neorv32_uart_printf("# Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9)); }
if (num_hpm_cnts_global > 7) {neorv32_uart_printf("# Conditional branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10)); }
if (num_hpm_cnts_global > 8) {neorv32_uart_printf("# Conditional branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11)); }
if (num_hpm_cnts_global > 9) {neorv32_uart_printf("# Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12)); }
if (num_hpm_cnts_global > 10) {neorv32_uart_printf("# Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13)); }
neorv32_uart_printf("\n");
 
neorv32_uart_printf("NEORV32: Executed instructions 0x%x_%x\n", (uint32_t)exe_instructions.uint32[1], (uint32_t)exe_instructions.uint32[0]);
neorv32_uart_printf("NEORV32: CoreMark core clock cycles 0x%x_%x\n", (uint32_t)exe_time.uint32[1], (uint32_t)exe_time.uint32[0]);
 
/coremark/core_portme.h
98,15 → 98,15
ee_ptr_int needs to be the data type used to hold pointers, otherwise
coremark may fail!!!
*/
typedef signed short ee_s16;
typedef unsigned short ee_u16;
typedef signed int ee_s32;
typedef double ee_f32;
typedef unsigned char ee_u8;
typedef unsigned int ee_u32;
typedef unsigned long ee_u64;
typedef ee_u32 ee_ptr_int;
typedef size_t ee_size_t;
typedef int16_t ee_s16;
typedef uint16_t ee_u16;
typedef int32_t ee_s32;
typedef double ee_f32;
typedef unsigned char ee_u8;
typedef uint32_t ee_u32;
typedef uint64_t ee_u64;
typedef ee_u32 ee_ptr_int;
typedef size_t ee_size_t;
#define NULL ((void *)0)
/* align_mem :
This macro is used to align an offset to point to a 32b value. It is
/cpu_test/main.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
74,6 → 74,8
int cnt_test = 0;
/// Global timestamp for traps (stores mcycle.low on trap enter)
uint32_t trap_timestamp32 = 0;
/// Global numbe rof available HPMs
uint32_t num_hpm_cnts_global = 0;
 
 
/**********************************************************************//**
122,18 → 124,12
int main() {
 
register uint32_t tmp_a, tmp_b;
int i;
volatile uint32_t dummy_dst __attribute__((unused));
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cpu_systime;
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
 
// Disable cpu_test compilation by default
#ifndef RUN_CPUTEST
#warning cpu_test HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CPUTEST clean_all exe<< to compile it.
181,9 → 177,6
// show project credits
neorv32_rte_print_credits();
 
// show project license
neorv32_rte_print_license();
 
// show full HW config report
neorv32_rte_print_hw_config();
 
220,13 → 213,13
}
 
// enable interrupt sources
install_err = neorv32_cpu_irq_enable(CPU_MIE_MSIE); // activate software interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_MTIE); // activate timer interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_MEIE); // activate external interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ0E); // activate fast interrupt channel 0
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E); // activate fast interrupt channel 1
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ2E); // activate fast interrupt channel 2
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ3E); // activate fast interrupt channel 3
install_err = neorv32_cpu_irq_enable(CSR_MIE_MSIE); // activate software interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_MTIE); // activate timer interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_MEIE); // activate external interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E); // activate fast interrupt channel 0
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ1E); // activate fast interrupt channel 1
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E); // activate fast interrupt channel 2
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E); // activate fast interrupt channel 3
 
if (install_err) {
neorv32_uart_printf("IRQ enable error (%i)!\n", install_err);
241,63 → 234,6
 
 
// ----------------------------------------------------------
// List all accessible CSRs
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] List all accessible CSRs: ", cnt_test);
 
if ((UART_CT & (1 << UART_CT_SIM_MODE)) == 0) { // check if this is a simulation
 
cnt_test++;
i = 0;
 
neorv32_uart_printf("\n");
 
uint32_t csr_addr_cnt = 0;
 
// create test program in RAM
static const uint32_t csr_access_test_program[2] __attribute__((aligned(8))) = {
0x00006073, // csrrsi, 0x000, 0
0x00008067 // ret (32-bit)
};
 
// base address of program
tmp_a = (uint32_t)&csr_access_test_program;
uint32_t *csr_pnt = (uint32_t*)tmp_a;
 
// iterate through full 12-bit CSR address space
for (csr_addr_cnt=0x000; csr_addr_cnt<=0xfff; csr_addr_cnt++) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
// construct and store new CSR access instruction
// 0x00006073 = csrrsi, 0x000, 0
*csr_pnt = 0x00006073 | (csr_addr_cnt << 20); // insert current CSR address into most significant 12 bits
 
// sync instruction stream
asm volatile("fence.i");
 
// execute test program
asm volatile ("jalr ra, %[input_i]" : : [input_i] "r" (tmp_a));
 
// check for access exception
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) { // no exception -> access ok -> CSR exists
neorv32_uart_printf(" + 0x%x\n", csr_addr_cnt);
i++;
}
}
if (i != 0) { // at least one CSR was accessible
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (disabled for simulation)\n");
}
 
 
// ----------------------------------------------------------
// Test standard RISC-V performance counter [m]cycle[h]
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
357,7 → 293,7
 
// inhibit [m]cycle CSR
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
tmp_a |= (1<<CPU_MCOUNTINHIBIT_CY); // inhibit cycle counter auto-increment
tmp_a |= (1<<CSR_MCOUNTINHIBIT_CY); // inhibit cycle counter auto-increment
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a);
 
// get current cycle counter
379,7 → 315,7
 
// re-enable [m]cycle CSR
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
tmp_a &= ~(1<<CPU_MCOUNTINHIBIT_CY); // clear inhibit of cycle counter auto-increment
tmp_a &= ~(1<<CSR_MCOUNTINHIBIT_CY); // clear inhibit of cycle counter auto-increment
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a);
 
 
393,7 → 329,7
 
// do not allow user-level code to access cycle[h] CSRs
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
tmp_a &= ~(1<<CPU_MCOUNTEREN_CY); // clear access right
tmp_a &= ~(1<<CSR_MCOUNTEREN_CY); // clear access right
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
 
// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
420,11 → 356,49
 
// re-allow user-level code to access cycle[h] CSRs
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
tmp_a |= (1<<CPU_MCOUNTEREN_CY); // re-allow access right
tmp_a |= (1<<CSR_MCOUNTEREN_CY); // re-allow access right
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
 
 
// ----------------------------------------------------------
// Test performance counter: setup as many events and counter as feasible
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Initializing HPMs: ", cnt_test);
 
num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();
 
if (num_hpm_cnts_global != 0) {
cnt_test++;
 
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT3, 1 << HPMCNT_EVENT_CIR);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT4, 1 << HPMCNT_EVENT_WAIT_IF);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT5, 1 << HPMCNT_EVENT_WAIT_II);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT6, 1 << HPMCNT_EVENT_LOAD);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT7, 1 << HPMCNT_EVENT_STORE);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT8, 1 << HPMCNT_EVENT_WAIT_LS);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT9, 1 << HPMCNT_EVENT_JUMP);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_BRANCH);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_TBRANCH);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_TRAP);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT13, 1 << HPMCNT_EVENT_ILLEGAL);
 
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable all counters
 
// make sure there was no exception
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
 
 
// ----------------------------------------------------------
// Bus timeout latency estimation
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
435,9 → 409,9
neorv32_cpu_csr_write(CSR_MCYCLE, 0);
 
// this store access will timeout
MMR_UNREACHABLE = 0; // trap handler will stor mcycle.low to "trap_timestamp32"
MMR_UNREACHABLE = 0; // trap handler will store mcycle.low to "trap_timestamp32"
 
// make sure there was a time-out
// make sure there was a timeout
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) {
neorv32_uart_printf("~%u cycles ", trap_timestamp32-178); // remove trap handler overhead - empiric value ;)
test_ok();
496,66 → 470,6
 
 
// ----------------------------------------------------------
// Test time (must be == MTIME.TIME)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] Time (MTIME.time vs CSR.time) sync: ", cnt_test);
cnt_test++;
 
cpu_systime.uint64 = neorv32_cpu_get_systime();
uint64_t mtime_systime = neorv32_mtime_get_time();
 
// compute difference
mtime_systime = mtime_systime - cpu_systime.uint64;
 
if (mtime_systime < 4096) { // diff should be pretty small depending on bus latency
test_ok();
}
else {
test_fail();
}
 
 
// ----------------------------------------------------------
// Test fence instructions - make sure CPU does not crash here and throws no exception
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FENCE instruction test: ", cnt_test);
cnt_test++;
asm volatile ("fence");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) != 0) {
test_fail();
}
else {
test_ok();
}
 
 
// ----------------------------------------------------------
// Test fencei instructions - make sure CPU does not crash here and throws no exception
// a more complex test is provided by the RISC-V compliance test
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FENCE.I instruction test: ", cnt_test);
asm volatile ("fence.i");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
neorv32_uart_printf("skipped (not implemented)\n");
}
else {
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
asm volatile ("fence.i");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
test_ok();
}
else {
test_fail();
}
}
 
 
// ----------------------------------------------------------
// Illegal CSR access (CSR not implemented)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
672,7 → 586,7
neorv32_mtime_set_timecmp(-1);
 
 
if (neorv32_cpu_csr_read(CSR_MIP) & (1 << CPU_MIP_MTIP)) { // make sure MTIP is pending
if (neorv32_cpu_csr_read(CSR_MIP) & (1 << CSR_MIP_MTIP)) { // make sure MTIP is pending
 
neorv32_cpu_csr_write(CSR_MIP, 0); // just clear all pending IRQs
neorv32_cpu_eint(); // re-enable global interrupts
704,7 → 618,7
neorv32_uart_printf("[%i] I_ALIGN (instruction alignment) exception test: ", cnt_test);
 
// skip if C-mode is implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_C_EXT)) == 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) == 0) {
 
cnt_test++;
 
776,7 → 690,7
neorv32_uart_printf("[%i] CI_ILLEG (illegal compressed instruction) exception test: ", cnt_test);
 
// skip if C-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_C_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) != 0) {
 
cnt_test++;
 
914,7 → 828,7
neorv32_uart_printf("[%i] ENVCALL (ecall instruction) from U-mode exception test: ", cnt_test);
 
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_U_EXT)) {
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
 
cnt_test++;
 
1261,7 → 1175,7
neorv32_uart_printf("[%i] Invalid CSR access (mstatus) from user mode test: ", cnt_test);
 
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_U_EXT)) {
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
 
cnt_test++;
 
1324,7 → 1238,7
neorv32_uart_printf("[%i] Physical memory protection (PMP): ", cnt_test);
 
// check if PMP is implemented
if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) {
if (neorv32_cpu_pmp_get_num_regions() != 0) {
 
// Test access to protected region
// ---------------------------------------------
1476,7 → 1390,7
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
 
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
 
cnt_test++;
 
1513,7 → 1427,7
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
 
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
 
cnt_test++;
 
1547,7 → 1461,7
 
#ifdef __riscv_atomic
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
 
cnt_test++;
 
1572,6 → 1486,26
 
 
// ----------------------------------------------------------
// HPM reports
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
neorv32_uart_printf("\n\nHPM results:\n");
if (num_hpm_cnts_global == 0) {neorv32_uart_printf("no HPMs available\n"); }
if (num_hpm_cnts_global > 0) {neorv32_uart_printf("# Retired compr. instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3)); }
if (num_hpm_cnts_global > 1) {neorv32_uart_printf("# I-fetch wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4)); }
if (num_hpm_cnts_global > 2) {neorv32_uart_printf("# I-issue wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5)); }
if (num_hpm_cnts_global > 3) {neorv32_uart_printf("# Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6)); }
if (num_hpm_cnts_global > 4) {neorv32_uart_printf("# Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7)); }
if (num_hpm_cnts_global > 5) {neorv32_uart_printf("# Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8)); }
if (num_hpm_cnts_global > 6) {neorv32_uart_printf("# Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9)); }
if (num_hpm_cnts_global > 7) {neorv32_uart_printf("# Conditional branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10)); }
if (num_hpm_cnts_global > 8) {neorv32_uart_printf("# Conditional branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11)); }
if (num_hpm_cnts_global > 9) {neorv32_uart_printf("# Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12)); }
if (num_hpm_cnts_global > 10) {neorv32_uart_printf("# Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13)); }
neorv32_uart_printf("\n");
 
 
// ----------------------------------------------------------
// Final test reports
// ----------------------------------------------------------
neorv32_uart_printf("\nExecuted instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET));
1600,7 → 1534,7
trap_timestamp32 = neorv32_cpu_csr_read(CSR_MCYCLE);
 
// hack: always come back in MACHINE MODE
register uint32_t mask = (1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L);
register uint32_t mask = (1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L);
asm volatile ("csrrs zero, mstatus, %[input_j]" : : [input_j] "r" (mask));
}
 
/demo_freeRTOS/main.c
46,6 → 46,9
* Modified for the NEORV32 processor by Stephan Nolting.
*/
 
/* UART hardware constants. */
#define BAUD_RATE 19200
 
#ifdef RUN_FREERTOS_DEMO
 
#include <stdint.h>
66,9 → 69,6
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1
 
/* UART hardware constants. */
#define BAUD_RATE 19200
 
/*-----------------------------------------------------------*/
 
/*
127,8 → 127,8
// clear GPIO.out port
neorv32_gpio_port_set(0);
 
// configure UART for default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
}
 
/*-----------------------------------------------------------*/
228,7 → 228,8
#include <neorv32.h>
int main() {
 
neorv32_uart_setup(19200, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
neorv32_uart_print("ERROR! FreeRTOS has not been compiled. Use >>make USER_FLAGS+=-DRUN_FREERTOS_DEMO clean_all exe<< to compile it.\n");
return 0;
}
/demo_gpio_irq/main.c
72,8 → 72,8
// setup run-time environment for interrupts and exceptions
neorv32_rte_setup();
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
 
// check if GPIO unit is implemented at all
115,7 → 115,7
}
 
// activate fast interrupt channel 1 (which is GPIO_PIN_CHANGE)
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E);
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ1E);
 
// activate GPIO pin-change irq only for input pins 0 to 7
neorv32_gpio_pin_change_config(0x000000ff);
/demo_pwm/main.c
73,8 → 73,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// say hello
neorv32_uart_print("PWM demo program\n");
/demo_trng/main.c
79,8 → 79,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// intro
neorv32_uart_printf("\n--- TRNG Demo ---\n\n");
/demo_twi/main.c
83,8 → 83,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// intro
neorv32_uart_printf("\n--- TWI Bus Explorer ---\n\n");
/demo_wdt/main.c
76,8 → 76,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// simple text output via UART (strings only)
neorv32_uart_print("\nWatchdog system reset demo program\n\n");
/game_of_life/main.c
97,8 → 97,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
 
while (1) {
/hello_world/main.c
61,13 → 61,13
**************************************************************************/
int main() {
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
 
// capture all exceptions and give debug info via UART
// this is not required, but keeps us safe
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// print project logo via UART
neorv32_rte_print_logo();
 
/hex_viewer/main.c
82,8 → 82,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// intro
neorv32_uart_printf("\n--- Hex Viewer ---\n\n");
208,7 → 208,7
char terminal_buffer[16];
uint32_t mem_address, cas_expected, cas_desired;
 
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
 
// enter memory address
neorv32_uart_printf("Enter memory address (8 hex chars): 0x");

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